1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
49 #define BEGIN_LP_RING(n) \
50 intel_ring_begin(LP_RING(dev_priv), (n))
53 intel_ring_emit(LP_RING(dev_priv), x)
55 #define ADVANCE_LP_RING() \
56 intel_ring_advance(LP_RING(dev_priv))
59 * Lock test for when it's just for synchronization of ring access.
61 * In that case, we don't need to do it when GEM is initialized as nobody else
62 * has access to the ring.
64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
65 if (LP_RING(dev->dev_private)->obj == NULL) \
66 LOCK_TEST_WITH_RETURN(dev, file); \
70 intel_read_legacy_status_page(struct drm_i915_private
*dev_priv
, int reg
)
72 if (I915_NEED_GFX_HWS(dev_priv
->dev
))
73 return ioread32(dev_priv
->dri1
.gfx_hws_cpu_addr
+ reg
);
75 return intel_read_status_page(LP_RING(dev_priv
), reg
);
78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
80 #define I915_BREADCRUMB_INDEX 0x21
82 void i915_update_dri1_breadcrumb(struct drm_device
*dev
)
84 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
85 struct drm_i915_master_private
*master_priv
;
87 if (dev
->primary
->master
) {
88 master_priv
= dev
->primary
->master
->driver_priv
;
89 if (master_priv
->sarea_priv
)
90 master_priv
->sarea_priv
->last_dispatch
=
91 READ_BREADCRUMB(dev_priv
);
95 static void i915_write_hws_pga(struct drm_device
*dev
)
97 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
100 addr
= dev_priv
->status_page_dmah
->busaddr
;
101 if (INTEL_INFO(dev
)->gen
>= 4)
102 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
103 I915_WRITE(HWS_PGA
, addr
);
107 * Sets up the hardware status page for devices that need a physical address
110 static int i915_init_phys_hws(struct drm_device
*dev
)
112 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
114 /* Program Hardware Status Page */
115 dev_priv
->status_page_dmah
=
116 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
);
118 if (!dev_priv
->status_page_dmah
) {
119 DRM_ERROR("Can not allocate hardware status page\n");
123 memset_io((void __force __iomem
*)dev_priv
->status_page_dmah
->vaddr
,
126 i915_write_hws_pga(dev
);
128 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
133 * Frees the hardware status page, whether it's a physical address or a virtual
134 * address set up by the X Server.
136 static void i915_free_hws(struct drm_device
*dev
)
138 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
139 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
141 if (dev_priv
->status_page_dmah
) {
142 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
143 dev_priv
->status_page_dmah
= NULL
;
146 if (ring
->status_page
.gfx_addr
) {
147 ring
->status_page
.gfx_addr
= 0;
148 iounmap(dev_priv
->dri1
.gfx_hws_cpu_addr
);
151 /* Need to rewrite hardware status page */
152 I915_WRITE(HWS_PGA
, 0x1ffff000);
155 void i915_kernel_lost_context(struct drm_device
* dev
)
157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
158 struct drm_i915_master_private
*master_priv
;
159 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
162 * We should never lose context on the ring with modesetting
163 * as we don't expose it to userspace
165 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
168 ring
->head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
169 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
170 ring
->space
= ring
->head
- (ring
->tail
+ 8);
172 ring
->space
+= ring
->size
;
174 if (!dev
->primary
->master
)
177 master_priv
= dev
->primary
->master
->driver_priv
;
178 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
179 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
182 static int i915_dma_cleanup(struct drm_device
* dev
)
184 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
187 /* Make sure interrupts are disabled here because the uninstall ioctl
188 * may not have been called from userspace and after dev_private
189 * is freed, it's too late.
191 if (dev
->irq_enabled
)
192 drm_irq_uninstall(dev
);
194 mutex_lock(&dev
->struct_mutex
);
195 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
196 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
197 mutex_unlock(&dev
->struct_mutex
);
199 /* Clear the HWS virtual address at teardown */
200 if (I915_NEED_GFX_HWS(dev
))
206 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
208 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
209 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
212 master_priv
->sarea
= drm_getsarea(dev
);
213 if (master_priv
->sarea
) {
214 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
215 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
217 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
220 if (init
->ring_size
!= 0) {
221 if (LP_RING(dev_priv
)->obj
!= NULL
) {
222 i915_dma_cleanup(dev
);
223 DRM_ERROR("Client tried to initialize ringbuffer in "
228 ret
= intel_render_ring_init_dri(dev
,
232 i915_dma_cleanup(dev
);
237 dev_priv
->cpp
= init
->cpp
;
238 dev_priv
->back_offset
= init
->back_offset
;
239 dev_priv
->front_offset
= init
->front_offset
;
240 dev_priv
->current_page
= 0;
241 if (master_priv
->sarea_priv
)
242 master_priv
->sarea_priv
->pf_current_page
= 0;
244 /* Allow hardware batchbuffers unless told otherwise.
246 dev_priv
->dri1
.allow_batchbuffer
= 1;
251 static int i915_dma_resume(struct drm_device
* dev
)
253 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
254 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
256 DRM_DEBUG_DRIVER("%s\n", __func__
);
258 if (ring
->virtual_start
== NULL
) {
259 DRM_ERROR("can not ioremap virtual address for"
264 /* Program Hardware Status Page */
265 if (!ring
->status_page
.page_addr
) {
266 DRM_ERROR("Can not find hardware status page\n");
269 DRM_DEBUG_DRIVER("hw status page @ %p\n",
270 ring
->status_page
.page_addr
);
271 if (ring
->status_page
.gfx_addr
!= 0)
272 intel_ring_setup_status_page(ring
);
274 i915_write_hws_pga(dev
);
276 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
281 static int i915_dma_init(struct drm_device
*dev
, void *data
,
282 struct drm_file
*file_priv
)
284 drm_i915_init_t
*init
= data
;
287 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
290 switch (init
->func
) {
292 retcode
= i915_initialize(dev
, init
);
294 case I915_CLEANUP_DMA
:
295 retcode
= i915_dma_cleanup(dev
);
297 case I915_RESUME_DMA
:
298 retcode
= i915_dma_resume(dev
);
308 /* Implement basically the same security restrictions as hardware does
309 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
311 * Most of the calculations below involve calculating the size of a
312 * particular instruction. It's important to get the size right as
313 * that tells us where the next instruction to check is. Any illegal
314 * instruction detected will be given a size of zero, which is a
315 * signal to abort the rest of the buffer.
317 static int validate_cmd(int cmd
)
319 switch (((cmd
>> 29) & 0x7)) {
321 switch ((cmd
>> 23) & 0x3f) {
323 return 1; /* MI_NOOP */
325 return 1; /* MI_FLUSH */
327 return 0; /* disallow everything else */
331 return 0; /* reserved */
333 return (cmd
& 0xff) + 2; /* 2d commands */
335 if (((cmd
>> 24) & 0x1f) <= 0x18)
338 switch ((cmd
>> 24) & 0x1f) {
342 switch ((cmd
>> 16) & 0xff) {
344 return (cmd
& 0x1f) + 2;
346 return (cmd
& 0xf) + 2;
348 return (cmd
& 0xffff) + 2;
352 return (cmd
& 0xffff) + 1;
356 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
357 return (cmd
& 0x1ffff) + 2;
358 else if (cmd
& (1 << 17)) /* indirect random */
359 if ((cmd
& 0xffff) == 0)
360 return 0; /* unknown length, too hard */
362 return (((cmd
& 0xffff) + 1) / 2) + 1;
364 return 2; /* indirect sequential */
375 static int i915_emit_cmds(struct drm_device
* dev
, int *buffer
, int dwords
)
377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
380 if ((dwords
+1) * sizeof(int) >= LP_RING(dev_priv
)->size
- 8)
383 for (i
= 0; i
< dwords
;) {
384 int sz
= validate_cmd(buffer
[i
]);
385 if (sz
== 0 || i
+ sz
> dwords
)
390 ret
= BEGIN_LP_RING((dwords
+1)&~1);
394 for (i
= 0; i
< dwords
; i
++)
405 i915_emit_box(struct drm_device
*dev
,
406 struct drm_clip_rect
*box
,
409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
412 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
413 box
->y2
<= 0 || box
->x2
<= 0) {
414 DRM_ERROR("Bad box %d,%d..%d,%d\n",
415 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
419 if (INTEL_INFO(dev
)->gen
>= 4) {
420 ret
= BEGIN_LP_RING(4);
424 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
425 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
426 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
429 ret
= BEGIN_LP_RING(6);
433 OUT_RING(GFX_OP_DRAWRECT_INFO
);
435 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
436 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
445 /* XXX: Emitting the counter should really be moved to part of the IRQ
446 * emit. For now, do it in both places:
449 static void i915_emit_breadcrumb(struct drm_device
*dev
)
451 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
452 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
455 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
456 dev_priv
->counter
= 0;
457 if (master_priv
->sarea_priv
)
458 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
460 if (BEGIN_LP_RING(4) == 0) {
461 OUT_RING(MI_STORE_DWORD_INDEX
);
462 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
463 OUT_RING(dev_priv
->counter
);
469 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
470 drm_i915_cmdbuffer_t
*cmd
,
471 struct drm_clip_rect
*cliprects
,
474 int nbox
= cmd
->num_cliprects
;
475 int i
= 0, count
, ret
;
478 DRM_ERROR("alignment");
482 i915_kernel_lost_context(dev
);
484 count
= nbox
? nbox
: 1;
486 for (i
= 0; i
< count
; i
++) {
488 ret
= i915_emit_box(dev
, &cliprects
[i
],
494 ret
= i915_emit_cmds(dev
, cmdbuf
, cmd
->sz
/ 4);
499 i915_emit_breadcrumb(dev
);
503 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
504 drm_i915_batchbuffer_t
* batch
,
505 struct drm_clip_rect
*cliprects
)
507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 int nbox
= batch
->num_cliprects
;
511 if ((batch
->start
| batch
->used
) & 0x7) {
512 DRM_ERROR("alignment");
516 i915_kernel_lost_context(dev
);
518 count
= nbox
? nbox
: 1;
519 for (i
= 0; i
< count
; i
++) {
521 ret
= i915_emit_box(dev
, &cliprects
[i
],
522 batch
->DR1
, batch
->DR4
);
527 if (!IS_I830(dev
) && !IS_845G(dev
)) {
528 ret
= BEGIN_LP_RING(2);
532 if (INTEL_INFO(dev
)->gen
>= 4) {
533 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
534 OUT_RING(batch
->start
);
536 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
537 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
540 ret
= BEGIN_LP_RING(4);
544 OUT_RING(MI_BATCH_BUFFER
);
545 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
546 OUT_RING(batch
->start
+ batch
->used
- 4);
553 if (IS_G4X(dev
) || IS_GEN5(dev
)) {
554 if (BEGIN_LP_RING(2) == 0) {
555 OUT_RING(MI_FLUSH
| MI_NO_WRITE_FLUSH
| MI_INVALIDATE_ISP
);
561 i915_emit_breadcrumb(dev
);
565 static int i915_dispatch_flip(struct drm_device
* dev
)
567 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
568 struct drm_i915_master_private
*master_priv
=
569 dev
->primary
->master
->driver_priv
;
572 if (!master_priv
->sarea_priv
)
575 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
577 dev_priv
->current_page
,
578 master_priv
->sarea_priv
->pf_current_page
);
580 i915_kernel_lost_context(dev
);
582 ret
= BEGIN_LP_RING(10);
586 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
589 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
591 if (dev_priv
->current_page
== 0) {
592 OUT_RING(dev_priv
->back_offset
);
593 dev_priv
->current_page
= 1;
595 OUT_RING(dev_priv
->front_offset
);
596 dev_priv
->current_page
= 0;
600 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
605 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
607 if (BEGIN_LP_RING(4) == 0) {
608 OUT_RING(MI_STORE_DWORD_INDEX
);
609 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
610 OUT_RING(dev_priv
->counter
);
615 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
619 static int i915_quiescent(struct drm_device
*dev
)
621 struct intel_ring_buffer
*ring
= LP_RING(dev
->dev_private
);
623 i915_kernel_lost_context(dev
);
624 return intel_wait_ring_idle(ring
);
627 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
628 struct drm_file
*file_priv
)
632 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
635 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
637 mutex_lock(&dev
->struct_mutex
);
638 ret
= i915_quiescent(dev
);
639 mutex_unlock(&dev
->struct_mutex
);
644 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
645 struct drm_file
*file_priv
)
647 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
648 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
649 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
650 master_priv
->sarea_priv
;
651 drm_i915_batchbuffer_t
*batch
= data
;
653 struct drm_clip_rect
*cliprects
= NULL
;
655 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
658 if (!dev_priv
->dri1
.allow_batchbuffer
) {
659 DRM_ERROR("Batchbuffer ioctl disabled\n");
663 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
664 batch
->start
, batch
->used
, batch
->num_cliprects
);
666 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
668 if (batch
->num_cliprects
< 0)
671 if (batch
->num_cliprects
) {
672 cliprects
= kcalloc(batch
->num_cliprects
,
673 sizeof(struct drm_clip_rect
),
675 if (cliprects
== NULL
)
678 ret
= copy_from_user(cliprects
, batch
->cliprects
,
679 batch
->num_cliprects
*
680 sizeof(struct drm_clip_rect
));
687 mutex_lock(&dev
->struct_mutex
);
688 ret
= i915_dispatch_batchbuffer(dev
, batch
, cliprects
);
689 mutex_unlock(&dev
->struct_mutex
);
692 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
700 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
701 struct drm_file
*file_priv
)
703 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
704 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
705 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
706 master_priv
->sarea_priv
;
707 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
708 struct drm_clip_rect
*cliprects
= NULL
;
712 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
713 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
715 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
718 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
720 if (cmdbuf
->num_cliprects
< 0)
723 batch_data
= kmalloc(cmdbuf
->sz
, GFP_KERNEL
);
724 if (batch_data
== NULL
)
727 ret
= copy_from_user(batch_data
, cmdbuf
->buf
, cmdbuf
->sz
);
730 goto fail_batch_free
;
733 if (cmdbuf
->num_cliprects
) {
734 cliprects
= kcalloc(cmdbuf
->num_cliprects
,
735 sizeof(struct drm_clip_rect
), GFP_KERNEL
);
736 if (cliprects
== NULL
) {
738 goto fail_batch_free
;
741 ret
= copy_from_user(cliprects
, cmdbuf
->cliprects
,
742 cmdbuf
->num_cliprects
*
743 sizeof(struct drm_clip_rect
));
750 mutex_lock(&dev
->struct_mutex
);
751 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
, cliprects
, batch_data
);
752 mutex_unlock(&dev
->struct_mutex
);
754 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
759 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
769 static int i915_emit_irq(struct drm_device
* dev
)
771 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
772 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
774 i915_kernel_lost_context(dev
);
776 DRM_DEBUG_DRIVER("\n");
779 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
780 dev_priv
->counter
= 1;
781 if (master_priv
->sarea_priv
)
782 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
784 if (BEGIN_LP_RING(4) == 0) {
785 OUT_RING(MI_STORE_DWORD_INDEX
);
786 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
787 OUT_RING(dev_priv
->counter
);
788 OUT_RING(MI_USER_INTERRUPT
);
792 return dev_priv
->counter
;
795 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
797 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
798 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
800 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
802 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr
,
803 READ_BREADCRUMB(dev_priv
));
805 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
806 if (master_priv
->sarea_priv
)
807 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
811 if (master_priv
->sarea_priv
)
812 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
814 if (ring
->irq_get(ring
)) {
815 DRM_WAIT_ON(ret
, ring
->irq_queue
, 3 * DRM_HZ
,
816 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
818 } else if (wait_for(READ_BREADCRUMB(dev_priv
) >= irq_nr
, 3000))
822 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
823 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
829 /* Needs the lock as it touches the ring.
831 static int i915_irq_emit(struct drm_device
*dev
, void *data
,
832 struct drm_file
*file_priv
)
834 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
835 drm_i915_irq_emit_t
*emit
= data
;
838 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
841 if (!dev_priv
|| !LP_RING(dev_priv
)->virtual_start
) {
842 DRM_ERROR("called with no initialization\n");
846 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
848 mutex_lock(&dev
->struct_mutex
);
849 result
= i915_emit_irq(dev
);
850 mutex_unlock(&dev
->struct_mutex
);
852 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
853 DRM_ERROR("copy_to_user\n");
860 /* Doesn't need the hardware lock.
862 static int i915_irq_wait(struct drm_device
*dev
, void *data
,
863 struct drm_file
*file_priv
)
865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
866 drm_i915_irq_wait_t
*irqwait
= data
;
868 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
872 DRM_ERROR("called with no initialization\n");
876 return i915_wait_irq(dev
, irqwait
->irq_seq
);
879 static int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
880 struct drm_file
*file_priv
)
882 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
883 drm_i915_vblank_pipe_t
*pipe
= data
;
885 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
889 DRM_ERROR("called with no initialization\n");
893 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
899 * Schedule buffer swap at given vertical blank.
901 static int i915_vblank_swap(struct drm_device
*dev
, void *data
,
902 struct drm_file
*file_priv
)
904 /* The delayed swap mechanism was fundamentally racy, and has been
905 * removed. The model was that the client requested a delayed flip/swap
906 * from the kernel, then waited for vblank before continuing to perform
907 * rendering. The problem was that the kernel might wake the client
908 * up before it dispatched the vblank swap (since the lock has to be
909 * held while touching the ringbuffer), in which case the client would
910 * clear and start the next frame before the swap occurred, and
911 * flicker would occur in addition to likely missing the vblank.
913 * In the absence of this ioctl, userland falls back to a correct path
914 * of waiting for a vblank, then dispatching the swap on its own.
915 * Context switching to userland and back is plenty fast enough for
916 * meeting the requirements of vblank swapping.
921 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
922 struct drm_file
*file_priv
)
926 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
929 DRM_DEBUG_DRIVER("%s\n", __func__
);
931 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
933 mutex_lock(&dev
->struct_mutex
);
934 ret
= i915_dispatch_flip(dev
);
935 mutex_unlock(&dev
->struct_mutex
);
940 static int i915_getparam(struct drm_device
*dev
, void *data
,
941 struct drm_file
*file_priv
)
943 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
944 drm_i915_getparam_t
*param
= data
;
948 DRM_ERROR("called with no initialization\n");
952 switch (param
->param
) {
953 case I915_PARAM_IRQ_ACTIVE
:
954 value
= dev
->pdev
->irq
? 1 : 0;
956 case I915_PARAM_ALLOW_BATCHBUFFER
:
957 value
= dev_priv
->dri1
.allow_batchbuffer
? 1 : 0;
959 case I915_PARAM_LAST_DISPATCH
:
960 value
= READ_BREADCRUMB(dev_priv
);
962 case I915_PARAM_CHIPSET_ID
:
963 value
= dev
->pci_device
;
965 case I915_PARAM_HAS_GEM
:
968 case I915_PARAM_NUM_FENCES_AVAIL
:
969 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
971 case I915_PARAM_HAS_OVERLAY
:
972 value
= dev_priv
->overlay
? 1 : 0;
974 case I915_PARAM_HAS_PAGEFLIPPING
:
977 case I915_PARAM_HAS_EXECBUF2
:
981 case I915_PARAM_HAS_BSD
:
982 value
= intel_ring_initialized(&dev_priv
->ring
[VCS
]);
984 case I915_PARAM_HAS_BLT
:
985 value
= intel_ring_initialized(&dev_priv
->ring
[BCS
]);
987 case I915_PARAM_HAS_RELAXED_FENCING
:
990 case I915_PARAM_HAS_COHERENT_RINGS
:
993 case I915_PARAM_HAS_EXEC_CONSTANTS
:
994 value
= INTEL_INFO(dev
)->gen
>= 4;
996 case I915_PARAM_HAS_RELAXED_DELTA
:
999 case I915_PARAM_HAS_GEN7_SOL_RESET
:
1002 case I915_PARAM_HAS_LLC
:
1003 value
= HAS_LLC(dev
);
1005 case I915_PARAM_HAS_ALIASING_PPGTT
:
1006 value
= dev_priv
->mm
.aliasing_ppgtt
? 1 : 0;
1008 case I915_PARAM_HAS_WAIT_TIMEOUT
:
1012 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1017 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
1018 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1025 static int i915_setparam(struct drm_device
*dev
, void *data
,
1026 struct drm_file
*file_priv
)
1028 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1029 drm_i915_setparam_t
*param
= data
;
1032 DRM_ERROR("called with no initialization\n");
1036 switch (param
->param
) {
1037 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
1039 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
1041 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
1042 dev_priv
->dri1
.allow_batchbuffer
= param
->value
? 1 : 0;
1044 case I915_SETPARAM_NUM_USED_FENCES
:
1045 if (param
->value
> dev_priv
->num_fence_regs
||
1048 /* Userspace can use first N regs */
1049 dev_priv
->fence_reg_start
= param
->value
;
1052 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1060 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
1061 struct drm_file
*file_priv
)
1063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1064 drm_i915_hws_addr_t
*hws
= data
;
1065 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
1067 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1070 if (!I915_NEED_GFX_HWS(dev
))
1074 DRM_ERROR("called with no initialization\n");
1078 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1079 WARN(1, "tried to set status page when mode setting active\n");
1083 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32
)hws
->addr
);
1085 ring
->status_page
.gfx_addr
= hws
->addr
& (0x1ffff<<12);
1087 dev_priv
->dri1
.gfx_hws_cpu_addr
=
1088 ioremap_wc(dev_priv
->mm
.gtt_base_addr
+ hws
->addr
, 4096);
1089 if (dev_priv
->dri1
.gfx_hws_cpu_addr
== NULL
) {
1090 i915_dma_cleanup(dev
);
1091 ring
->status_page
.gfx_addr
= 0;
1092 DRM_ERROR("can not ioremap virtual address for"
1093 " G33 hw status page\n");
1097 memset_io(dev_priv
->dri1
.gfx_hws_cpu_addr
, 0, PAGE_SIZE
);
1098 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
1100 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1101 ring
->status_page
.gfx_addr
);
1102 DRM_DEBUG_DRIVER("load hws at %p\n",
1103 ring
->status_page
.page_addr
);
1107 static int i915_get_bridge_dev(struct drm_device
*dev
)
1109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1112 if (!dev_priv
->bridge_dev
) {
1113 DRM_ERROR("bridge device not found\n");
1119 #define MCHBAR_I915 0x44
1120 #define MCHBAR_I965 0x48
1121 #define MCHBAR_SIZE (4*4096)
1123 #define DEVEN_REG 0x54
1124 #define DEVEN_MCHBAR_EN (1 << 28)
1126 /* Allocate space for the MCH regs if needed, return nonzero on error */
1128 intel_alloc_mchbar_resource(struct drm_device
*dev
)
1130 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1131 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1132 u32 temp_lo
, temp_hi
= 0;
1136 if (INTEL_INFO(dev
)->gen
>= 4)
1137 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
1138 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
1139 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
1141 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1144 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
1148 /* Get some space for it */
1149 dev_priv
->mch_res
.name
= "i915 MCHBAR";
1150 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
1151 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
1153 MCHBAR_SIZE
, MCHBAR_SIZE
,
1155 0, pcibios_align_resource
,
1156 dev_priv
->bridge_dev
);
1158 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
1159 dev_priv
->mch_res
.start
= 0;
1163 if (INTEL_INFO(dev
)->gen
>= 4)
1164 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
1165 upper_32_bits(dev_priv
->mch_res
.start
));
1167 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
1168 lower_32_bits(dev_priv
->mch_res
.start
));
1172 /* Setup MCHBAR if possible, return true if we should disable it again */
1174 intel_setup_mchbar(struct drm_device
*dev
)
1176 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1177 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1181 dev_priv
->mchbar_need_disable
= false;
1183 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1184 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1185 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
1187 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1191 /* If it's already enabled, don't have to do anything */
1195 if (intel_alloc_mchbar_resource(dev
))
1198 dev_priv
->mchbar_need_disable
= true;
1200 /* Space is allocated or reserved, so enable it. */
1201 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1202 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
1203 temp
| DEVEN_MCHBAR_EN
);
1205 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1206 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
1211 intel_teardown_mchbar(struct drm_device
*dev
)
1213 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1214 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1217 if (dev_priv
->mchbar_need_disable
) {
1218 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1219 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1220 temp
&= ~DEVEN_MCHBAR_EN
;
1221 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
1223 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1225 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
1229 if (dev_priv
->mch_res
.start
)
1230 release_resource(&dev_priv
->mch_res
);
1233 /* true = enable decode, false = disable decoder */
1234 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
1236 struct drm_device
*dev
= cookie
;
1238 intel_modeset_vga_set_state(dev
, state
);
1240 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1241 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1243 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1246 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1248 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1249 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
1250 if (state
== VGA_SWITCHEROO_ON
) {
1251 pr_info("switched on\n");
1252 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1253 /* i915 resume handler doesn't set to D0 */
1254 pci_set_power_state(dev
->pdev
, PCI_D0
);
1256 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1258 pr_err("switched off\n");
1259 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1260 i915_suspend(dev
, pmm
);
1261 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1265 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
1267 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1270 spin_lock(&dev
->count_lock
);
1271 can_switch
= (dev
->open_count
== 0);
1272 spin_unlock(&dev
->count_lock
);
1276 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
1277 .set_gpu_state
= i915_switcheroo_set_state
,
1279 .can_switch
= i915_switcheroo_can_switch
,
1282 static int i915_load_modeset_init(struct drm_device
*dev
)
1284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1287 ret
= intel_parse_bios(dev
);
1289 DRM_INFO("failed to find VBIOS tables\n");
1291 /* If we have > 1 VGA cards, then we need to arbitrate access
1292 * to the common VGA resources.
1294 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1295 * then we do not take part in VGA arbitration and the
1296 * vga_client_register() fails with -ENODEV.
1298 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
1299 if (ret
&& ret
!= -ENODEV
)
1302 intel_register_dsm_handler();
1304 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
);
1306 goto cleanup_vga_client
;
1308 /* Initialise stolen first so that we may reserve preallocated
1309 * objects for the BIOS to KMS transition.
1311 ret
= i915_gem_init_stolen(dev
);
1313 goto cleanup_vga_switcheroo
;
1315 intel_modeset_init(dev
);
1317 ret
= i915_gem_init(dev
);
1319 goto cleanup_gem_stolen
;
1321 intel_modeset_gem_init(dev
);
1323 ret
= drm_irq_install(dev
);
1327 /* Always safe in the mode setting case. */
1328 /* FIXME: do pre/post-mode set stuff in core KMS code */
1329 dev
->vblank_disable_allowed
= 1;
1331 ret
= intel_fbdev_init(dev
);
1335 drm_kms_helper_poll_init(dev
);
1337 /* We're off and running w/KMS */
1338 dev_priv
->mm
.suspended
= 0;
1343 drm_irq_uninstall(dev
);
1345 mutex_lock(&dev
->struct_mutex
);
1346 i915_gem_cleanup_ringbuffer(dev
);
1347 mutex_unlock(&dev
->struct_mutex
);
1348 i915_gem_cleanup_aliasing_ppgtt(dev
);
1350 i915_gem_cleanup_stolen(dev
);
1351 cleanup_vga_switcheroo
:
1352 vga_switcheroo_unregister_client(dev
->pdev
);
1354 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1359 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1361 struct drm_i915_master_private
*master_priv
;
1363 master_priv
= kzalloc(sizeof(*master_priv
), GFP_KERNEL
);
1367 master
->driver_priv
= master_priv
;
1371 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1373 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1380 master
->driver_priv
= NULL
;
1384 i915_mtrr_setup(struct drm_i915_private
*dev_priv
, unsigned long base
,
1387 dev_priv
->mm
.gtt_mtrr
= -1;
1389 #if defined(CONFIG_X86_PAT)
1394 /* Set up a WC MTRR for non-PAT systems. This is more common than
1395 * one would think, because the kernel disables PAT on first
1396 * generation Core chips because WC PAT gets overridden by a UC
1397 * MTRR if present. Even if a UC MTRR isn't present.
1399 dev_priv
->mm
.gtt_mtrr
= mtrr_add(base
, size
, MTRR_TYPE_WRCOMB
, 1);
1400 if (dev_priv
->mm
.gtt_mtrr
< 0) {
1401 DRM_INFO("MTRR allocation failed. Graphics "
1402 "performance may suffer.\n");
1406 static void i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
1408 struct apertures_struct
*ap
;
1409 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
1412 ap
= alloc_apertures(1);
1416 ap
->ranges
[0].base
= dev_priv
->mm
.gtt
->gma_bus_addr
;
1417 ap
->ranges
[0].size
=
1418 dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
1420 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
1422 remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
1428 * i915_driver_load - setup chip and create an initial config
1430 * @flags: startup flags
1432 * The driver load routine has to do several things:
1433 * - drive output discovery via intel_modeset_init()
1434 * - initialize the memory manager
1435 * - allocate initial config memory
1436 * - setup the DRM framebuffer with the allocated memory
1438 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
1440 struct drm_i915_private
*dev_priv
;
1441 struct intel_device_info
*info
;
1442 int ret
= 0, mmio_bar
;
1443 uint32_t aperture_size
;
1445 info
= (struct intel_device_info
*) flags
;
1447 /* Refuse to load on gen6+ without kms enabled. */
1448 if (info
->gen
>= 6 && !drm_core_check_feature(dev
, DRIVER_MODESET
))
1452 /* i915 has 4 more counters */
1454 dev
->types
[6] = _DRM_STAT_IRQ
;
1455 dev
->types
[7] = _DRM_STAT_PRIMARY
;
1456 dev
->types
[8] = _DRM_STAT_SECONDARY
;
1457 dev
->types
[9] = _DRM_STAT_DMA
;
1459 dev_priv
= kzalloc(sizeof(drm_i915_private_t
), GFP_KERNEL
);
1460 if (dev_priv
== NULL
)
1463 dev
->dev_private
= (void *)dev_priv
;
1464 dev_priv
->dev
= dev
;
1465 dev_priv
->info
= info
;
1467 if (i915_get_bridge_dev(dev
)) {
1472 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev
->pdev
, NULL
);
1474 DRM_ERROR("failed to set up gmch\n");
1479 dev_priv
->mm
.gtt
= intel_gtt_get();
1480 if (!dev_priv
->mm
.gtt
) {
1481 DRM_ERROR("Failed to initialize GTT\n");
1486 i915_kick_out_firmware_fb(dev_priv
);
1488 pci_set_master(dev
->pdev
);
1490 /* overlay on gen2 is broken and can't address above 1G */
1492 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
1494 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1495 * using 32bit addressing, overwriting memory if HWS is located
1498 * The documentation also mentions an issue with undefined
1499 * behaviour if any general state is accessed within a page above 4GB,
1500 * which also needs to be handled carefully.
1502 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1503 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
1505 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
1506 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, 0);
1507 if (!dev_priv
->regs
) {
1508 DRM_ERROR("failed to map registers\n");
1513 aperture_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
1514 dev_priv
->mm
.gtt_base_addr
= dev_priv
->mm
.gtt
->gma_bus_addr
;
1516 dev_priv
->mm
.gtt_mapping
=
1517 io_mapping_create_wc(dev_priv
->mm
.gtt_base_addr
,
1519 if (dev_priv
->mm
.gtt_mapping
== NULL
) {
1524 i915_mtrr_setup(dev_priv
, dev_priv
->mm
.gtt_base_addr
,
1527 /* The i915 workqueue is primarily used for batched retirement of
1528 * requests (and thus managing bo) once the task has been completed
1529 * by the GPU. i915_gem_retire_requests() is called directly when we
1530 * need high-priority retirement, such as waiting for an explicit
1533 * It is also used for periodic low-priority events, such as
1534 * idle-timers and recording error state.
1536 * All tasks on the workqueue are expected to acquire the dev mutex
1537 * so there is no point in running more than one instance of the
1538 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1540 dev_priv
->wq
= alloc_workqueue("i915",
1541 WQ_UNBOUND
| WQ_NON_REENTRANT
,
1543 if (dev_priv
->wq
== NULL
) {
1544 DRM_ERROR("Failed to create our workqueue.\n");
1549 /* This must be called before any calls to HAS_PCH_* */
1550 intel_detect_pch(dev
);
1552 intel_irq_init(dev
);
1555 /* Try to make sure MCHBAR is enabled before poking at it */
1556 intel_setup_mchbar(dev
);
1557 intel_setup_gmbus(dev
);
1558 intel_opregion_setup(dev
);
1560 /* Make sure the bios did its job and set up vital registers */
1561 intel_setup_bios(dev
);
1566 if (!I915_NEED_GFX_HWS(dev
)) {
1567 ret
= i915_init_phys_hws(dev
);
1569 goto out_gem_unload
;
1572 /* On the 945G/GM, the chipset reports the MSI capability on the
1573 * integrated graphics even though the support isn't actually there
1574 * according to the published specs. It doesn't appear to function
1575 * correctly in testing on 945G.
1576 * This may be a side effect of MSI having been made available for PEG
1577 * and the registers being closely associated.
1579 * According to chipset errata, on the 965GM, MSI interrupts may
1580 * be lost or delayed, but we use them anyways to avoid
1581 * stuck interrupts on some machines.
1583 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1584 pci_enable_msi(dev
->pdev
);
1586 spin_lock_init(&dev_priv
->irq_lock
);
1587 spin_lock_init(&dev_priv
->error_lock
);
1588 spin_lock_init(&dev_priv
->rps_lock
);
1589 spin_lock_init(&dev_priv
->dpio_lock
);
1591 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1592 dev_priv
->num_pipe
= 3;
1593 else if (IS_MOBILE(dev
) || !IS_GEN2(dev
))
1594 dev_priv
->num_pipe
= 2;
1596 dev_priv
->num_pipe
= 1;
1598 ret
= drm_vblank_init(dev
, dev_priv
->num_pipe
);
1600 goto out_gem_unload
;
1602 /* Start out suspended */
1603 dev_priv
->mm
.suspended
= 1;
1605 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1606 ret
= i915_load_modeset_init(dev
);
1608 DRM_ERROR("failed to init modeset\n");
1609 goto out_gem_unload
;
1613 i915_setup_sysfs(dev
);
1615 /* Must be done after probing outputs */
1616 intel_opregion_init(dev
);
1617 acpi_video_register();
1619 setup_timer(&dev_priv
->hangcheck_timer
, i915_hangcheck_elapsed
,
1620 (unsigned long) dev
);
1623 intel_gpu_ips_init(dev_priv
);
1628 if (dev_priv
->mm
.inactive_shrinker
.shrink
)
1629 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1631 if (dev
->pdev
->msi_enabled
)
1632 pci_disable_msi(dev
->pdev
);
1634 intel_teardown_gmbus(dev
);
1635 intel_teardown_mchbar(dev
);
1636 destroy_workqueue(dev_priv
->wq
);
1638 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1639 mtrr_del(dev_priv
->mm
.gtt_mtrr
,
1640 dev_priv
->mm
.gtt_base_addr
,
1642 dev_priv
->mm
.gtt_mtrr
= -1;
1644 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1646 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1648 intel_gmch_remove();
1650 pci_dev_put(dev_priv
->bridge_dev
);
1656 int i915_driver_unload(struct drm_device
*dev
)
1658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 intel_gpu_ips_teardown();
1663 i915_teardown_sysfs(dev
);
1665 if (dev_priv
->mm
.inactive_shrinker
.shrink
)
1666 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1668 mutex_lock(&dev
->struct_mutex
);
1669 ret
= i915_gpu_idle(dev
);
1671 DRM_ERROR("failed to idle hardware: %d\n", ret
);
1672 i915_gem_retire_requests(dev
);
1673 mutex_unlock(&dev
->struct_mutex
);
1675 /* Cancel the retire work handler, which should be idle now. */
1676 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
1678 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1679 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1680 mtrr_del(dev_priv
->mm
.gtt_mtrr
,
1681 dev_priv
->mm
.gtt_base_addr
,
1682 dev_priv
->mm
.gtt
->gtt_mappable_entries
* PAGE_SIZE
);
1683 dev_priv
->mm
.gtt_mtrr
= -1;
1686 acpi_video_unregister();
1688 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1689 intel_fbdev_fini(dev
);
1690 intel_modeset_cleanup(dev
);
1693 * free the memory space allocated for the child device
1694 * config parsed from VBT
1696 if (dev_priv
->child_dev
&& dev_priv
->child_dev_num
) {
1697 kfree(dev_priv
->child_dev
);
1698 dev_priv
->child_dev
= NULL
;
1699 dev_priv
->child_dev_num
= 0;
1702 vga_switcheroo_unregister_client(dev
->pdev
);
1703 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1706 /* Free error state after interrupts are fully disabled. */
1707 del_timer_sync(&dev_priv
->hangcheck_timer
);
1708 cancel_work_sync(&dev_priv
->error_work
);
1709 i915_destroy_error_state(dev
);
1711 if (dev
->pdev
->msi_enabled
)
1712 pci_disable_msi(dev
->pdev
);
1714 intel_opregion_fini(dev
);
1716 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1717 /* Flush any outstanding unpin_work. */
1718 flush_workqueue(dev_priv
->wq
);
1720 mutex_lock(&dev
->struct_mutex
);
1721 i915_gem_free_all_phys_object(dev
);
1722 i915_gem_cleanup_ringbuffer(dev
);
1723 i915_gem_context_fini(dev
);
1724 mutex_unlock(&dev
->struct_mutex
);
1725 i915_gem_cleanup_aliasing_ppgtt(dev
);
1726 i915_gem_cleanup_stolen(dev
);
1727 drm_mm_takedown(&dev_priv
->mm
.stolen
);
1729 intel_cleanup_overlay(dev
);
1731 if (!I915_NEED_GFX_HWS(dev
))
1735 if (dev_priv
->regs
!= NULL
)
1736 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1738 intel_teardown_gmbus(dev
);
1739 intel_teardown_mchbar(dev
);
1741 destroy_workqueue(dev_priv
->wq
);
1743 pci_dev_put(dev_priv
->bridge_dev
);
1744 kfree(dev
->dev_private
);
1749 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1751 struct drm_i915_file_private
*file_priv
;
1753 DRM_DEBUG_DRIVER("\n");
1754 file_priv
= kmalloc(sizeof(*file_priv
), GFP_KERNEL
);
1758 file
->driver_priv
= file_priv
;
1760 spin_lock_init(&file_priv
->mm
.lock
);
1761 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
1763 idr_init(&file_priv
->context_idr
);
1769 * i915_driver_lastclose - clean up after all DRM clients have exited
1772 * Take care of cleaning up after all DRM clients have exited. In the
1773 * mode setting case, we want to restore the kernel's initial mode (just
1774 * in case the last client left us in a bad state).
1776 * Additionally, in the non-mode setting case, we'll tear down the GTT
1777 * and DMA structures, since the kernel won't be using them, and clea
1780 void i915_driver_lastclose(struct drm_device
* dev
)
1782 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1784 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1785 * goes right around and calls lastclose. Check for this and don't clean
1790 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1791 intel_fb_restore_mode(dev
);
1792 vga_switcheroo_process_delayed_switch();
1796 i915_gem_lastclose(dev
);
1798 i915_dma_cleanup(dev
);
1801 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
1803 i915_gem_context_close(dev
, file_priv
);
1804 i915_gem_release(dev
, file_priv
);
1807 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1809 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1814 struct drm_ioctl_desc i915_ioctls
[] = {
1815 DRM_IOCTL_DEF_DRV(I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1816 DRM_IOCTL_DEF_DRV(I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
1817 DRM_IOCTL_DEF_DRV(I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
1818 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
1819 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
1820 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
1821 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
1822 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1823 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1824 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1825 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1826 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
1827 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1828 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1829 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
1830 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
1831 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1832 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1833 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1834 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
),
1835 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1836 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1837 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
1838 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
1839 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1840 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1841 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
),
1842 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
),
1843 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
),
1844 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
),
1845 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
),
1846 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
),
1847 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
),
1848 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
),
1849 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
),
1850 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
),
1851 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1852 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
),
1853 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1854 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1855 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1856 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, intel_sprite_get_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1857 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
1858 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_UNLOCKED
),
1859 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_UNLOCKED
),
1862 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
1865 * This is really ugly: Because old userspace abused the linux agp interface to
1866 * manage the gtt, we need to claim that all intel devices are agp. For
1867 * otherwise the drm core refuses to initialize the agp support code.
1869 int i915_driver_device_is_agp(struct drm_device
* dev
)