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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45
46 static void i915_write_hws_pga(struct drm_device *dev)
47 {
48 drm_i915_private_t *dev_priv = dev->dev_private;
49 u32 addr;
50
51 addr = dev_priv->status_page_dmah->busaddr;
52 if (INTEL_INFO(dev)->gen >= 4)
53 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
54 I915_WRITE(HWS_PGA, addr);
55 }
56
57 /**
58 * Sets up the hardware status page for devices that need a physical address
59 * in the register.
60 */
61 static int i915_init_phys_hws(struct drm_device *dev)
62 {
63 drm_i915_private_t *dev_priv = dev->dev_private;
64 struct intel_ring_buffer *ring = LP_RING(dev_priv);
65
66 /* Program Hardware Status Page */
67 dev_priv->status_page_dmah =
68 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
69
70 if (!dev_priv->status_page_dmah) {
71 DRM_ERROR("Can not allocate hardware status page\n");
72 return -ENOMEM;
73 }
74 ring->status_page.page_addr =
75 (void __force __iomem *)dev_priv->status_page_dmah->vaddr;
76
77 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
78
79 i915_write_hws_pga(dev);
80
81 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
82 return 0;
83 }
84
85 /**
86 * Frees the hardware status page, whether it's a physical address or a virtual
87 * address set up by the X Server.
88 */
89 static void i915_free_hws(struct drm_device *dev)
90 {
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 struct intel_ring_buffer *ring = LP_RING(dev_priv);
93
94 if (dev_priv->status_page_dmah) {
95 drm_pci_free(dev, dev_priv->status_page_dmah);
96 dev_priv->status_page_dmah = NULL;
97 }
98
99 if (ring->status_page.gfx_addr) {
100 ring->status_page.gfx_addr = 0;
101 drm_core_ioremapfree(&dev_priv->hws_map, dev);
102 }
103
104 /* Need to rewrite hardware status page */
105 I915_WRITE(HWS_PGA, 0x1ffff000);
106 }
107
108 void i915_kernel_lost_context(struct drm_device * dev)
109 {
110 drm_i915_private_t *dev_priv = dev->dev_private;
111 struct drm_i915_master_private *master_priv;
112 struct intel_ring_buffer *ring = LP_RING(dev_priv);
113
114 /*
115 * We should never lose context on the ring with modesetting
116 * as we don't expose it to userspace
117 */
118 if (drm_core_check_feature(dev, DRIVER_MODESET))
119 return;
120
121 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
122 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
123 ring->space = ring->head - (ring->tail + 8);
124 if (ring->space < 0)
125 ring->space += ring->size;
126
127 if (!dev->primary->master)
128 return;
129
130 master_priv = dev->primary->master->driver_priv;
131 if (ring->head == ring->tail && master_priv->sarea_priv)
132 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
133 }
134
135 static int i915_dma_cleanup(struct drm_device * dev)
136 {
137 drm_i915_private_t *dev_priv = dev->dev_private;
138 int i;
139
140 /* Make sure interrupts are disabled here because the uninstall ioctl
141 * may not have been called from userspace and after dev_private
142 * is freed, it's too late.
143 */
144 if (dev->irq_enabled)
145 drm_irq_uninstall(dev);
146
147 mutex_lock(&dev->struct_mutex);
148 for (i = 0; i < I915_NUM_RINGS; i++)
149 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
150 mutex_unlock(&dev->struct_mutex);
151
152 /* Clear the HWS virtual address at teardown */
153 if (I915_NEED_GFX_HWS(dev))
154 i915_free_hws(dev);
155
156 return 0;
157 }
158
159 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
160 {
161 drm_i915_private_t *dev_priv = dev->dev_private;
162 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
163 int ret;
164
165 master_priv->sarea = drm_getsarea(dev);
166 if (master_priv->sarea) {
167 master_priv->sarea_priv = (drm_i915_sarea_t *)
168 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
169 } else {
170 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
171 }
172
173 if (init->ring_size != 0) {
174 if (LP_RING(dev_priv)->obj != NULL) {
175 i915_dma_cleanup(dev);
176 DRM_ERROR("Client tried to initialize ringbuffer in "
177 "GEM mode\n");
178 return -EINVAL;
179 }
180
181 ret = intel_render_ring_init_dri(dev,
182 init->ring_start,
183 init->ring_size);
184 if (ret) {
185 i915_dma_cleanup(dev);
186 return ret;
187 }
188 }
189
190 dev_priv->cpp = init->cpp;
191 dev_priv->back_offset = init->back_offset;
192 dev_priv->front_offset = init->front_offset;
193 dev_priv->current_page = 0;
194 if (master_priv->sarea_priv)
195 master_priv->sarea_priv->pf_current_page = 0;
196
197 /* Allow hardware batchbuffers unless told otherwise.
198 */
199 dev_priv->allow_batchbuffer = 1;
200
201 return 0;
202 }
203
204 static int i915_dma_resume(struct drm_device * dev)
205 {
206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
207 struct intel_ring_buffer *ring = LP_RING(dev_priv);
208
209 DRM_DEBUG_DRIVER("%s\n", __func__);
210
211 if (ring->map.handle == NULL) {
212 DRM_ERROR("can not ioremap virtual address for"
213 " ring buffer\n");
214 return -ENOMEM;
215 }
216
217 /* Program Hardware Status Page */
218 if (!ring->status_page.page_addr) {
219 DRM_ERROR("Can not find hardware status page\n");
220 return -EINVAL;
221 }
222 DRM_DEBUG_DRIVER("hw status page @ %p\n",
223 ring->status_page.page_addr);
224 if (ring->status_page.gfx_addr != 0)
225 intel_ring_setup_status_page(ring);
226 else
227 i915_write_hws_pga(dev);
228
229 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
230
231 return 0;
232 }
233
234 static int i915_dma_init(struct drm_device *dev, void *data,
235 struct drm_file *file_priv)
236 {
237 drm_i915_init_t *init = data;
238 int retcode = 0;
239
240 switch (init->func) {
241 case I915_INIT_DMA:
242 retcode = i915_initialize(dev, init);
243 break;
244 case I915_CLEANUP_DMA:
245 retcode = i915_dma_cleanup(dev);
246 break;
247 case I915_RESUME_DMA:
248 retcode = i915_dma_resume(dev);
249 break;
250 default:
251 retcode = -EINVAL;
252 break;
253 }
254
255 return retcode;
256 }
257
258 /* Implement basically the same security restrictions as hardware does
259 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
260 *
261 * Most of the calculations below involve calculating the size of a
262 * particular instruction. It's important to get the size right as
263 * that tells us where the next instruction to check is. Any illegal
264 * instruction detected will be given a size of zero, which is a
265 * signal to abort the rest of the buffer.
266 */
267 static int validate_cmd(int cmd)
268 {
269 switch (((cmd >> 29) & 0x7)) {
270 case 0x0:
271 switch ((cmd >> 23) & 0x3f) {
272 case 0x0:
273 return 1; /* MI_NOOP */
274 case 0x4:
275 return 1; /* MI_FLUSH */
276 default:
277 return 0; /* disallow everything else */
278 }
279 break;
280 case 0x1:
281 return 0; /* reserved */
282 case 0x2:
283 return (cmd & 0xff) + 2; /* 2d commands */
284 case 0x3:
285 if (((cmd >> 24) & 0x1f) <= 0x18)
286 return 1;
287
288 switch ((cmd >> 24) & 0x1f) {
289 case 0x1c:
290 return 1;
291 case 0x1d:
292 switch ((cmd >> 16) & 0xff) {
293 case 0x3:
294 return (cmd & 0x1f) + 2;
295 case 0x4:
296 return (cmd & 0xf) + 2;
297 default:
298 return (cmd & 0xffff) + 2;
299 }
300 case 0x1e:
301 if (cmd & (1 << 23))
302 return (cmd & 0xffff) + 1;
303 else
304 return 1;
305 case 0x1f:
306 if ((cmd & (1 << 23)) == 0) /* inline vertices */
307 return (cmd & 0x1ffff) + 2;
308 else if (cmd & (1 << 17)) /* indirect random */
309 if ((cmd & 0xffff) == 0)
310 return 0; /* unknown length, too hard */
311 else
312 return (((cmd & 0xffff) + 1) / 2) + 1;
313 else
314 return 2; /* indirect sequential */
315 default:
316 return 0;
317 }
318 default:
319 return 0;
320 }
321
322 return 0;
323 }
324
325 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
326 {
327 drm_i915_private_t *dev_priv = dev->dev_private;
328 int i, ret;
329
330 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
331 return -EINVAL;
332
333 for (i = 0; i < dwords;) {
334 int sz = validate_cmd(buffer[i]);
335 if (sz == 0 || i + sz > dwords)
336 return -EINVAL;
337 i += sz;
338 }
339
340 ret = BEGIN_LP_RING((dwords+1)&~1);
341 if (ret)
342 return ret;
343
344 for (i = 0; i < dwords; i++)
345 OUT_RING(buffer[i]);
346 if (dwords & 1)
347 OUT_RING(0);
348
349 ADVANCE_LP_RING();
350
351 return 0;
352 }
353
354 int
355 i915_emit_box(struct drm_device *dev,
356 struct drm_clip_rect *box,
357 int DR1, int DR4)
358 {
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 int ret;
361
362 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
363 box->y2 <= 0 || box->x2 <= 0) {
364 DRM_ERROR("Bad box %d,%d..%d,%d\n",
365 box->x1, box->y1, box->x2, box->y2);
366 return -EINVAL;
367 }
368
369 if (INTEL_INFO(dev)->gen >= 4) {
370 ret = BEGIN_LP_RING(4);
371 if (ret)
372 return ret;
373
374 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
375 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
376 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
377 OUT_RING(DR4);
378 } else {
379 ret = BEGIN_LP_RING(6);
380 if (ret)
381 return ret;
382
383 OUT_RING(GFX_OP_DRAWRECT_INFO);
384 OUT_RING(DR1);
385 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
386 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
387 OUT_RING(DR4);
388 OUT_RING(0);
389 }
390 ADVANCE_LP_RING();
391
392 return 0;
393 }
394
395 /* XXX: Emitting the counter should really be moved to part of the IRQ
396 * emit. For now, do it in both places:
397 */
398
399 static void i915_emit_breadcrumb(struct drm_device *dev)
400 {
401 drm_i915_private_t *dev_priv = dev->dev_private;
402 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
403
404 dev_priv->counter++;
405 if (dev_priv->counter > 0x7FFFFFFFUL)
406 dev_priv->counter = 0;
407 if (master_priv->sarea_priv)
408 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
409
410 if (BEGIN_LP_RING(4) == 0) {
411 OUT_RING(MI_STORE_DWORD_INDEX);
412 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
413 OUT_RING(dev_priv->counter);
414 OUT_RING(0);
415 ADVANCE_LP_RING();
416 }
417 }
418
419 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
420 drm_i915_cmdbuffer_t *cmd,
421 struct drm_clip_rect *cliprects,
422 void *cmdbuf)
423 {
424 int nbox = cmd->num_cliprects;
425 int i = 0, count, ret;
426
427 if (cmd->sz & 0x3) {
428 DRM_ERROR("alignment");
429 return -EINVAL;
430 }
431
432 i915_kernel_lost_context(dev);
433
434 count = nbox ? nbox : 1;
435
436 for (i = 0; i < count; i++) {
437 if (i < nbox) {
438 ret = i915_emit_box(dev, &cliprects[i],
439 cmd->DR1, cmd->DR4);
440 if (ret)
441 return ret;
442 }
443
444 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
445 if (ret)
446 return ret;
447 }
448
449 i915_emit_breadcrumb(dev);
450 return 0;
451 }
452
453 static int i915_dispatch_batchbuffer(struct drm_device * dev,
454 drm_i915_batchbuffer_t * batch,
455 struct drm_clip_rect *cliprects)
456 {
457 struct drm_i915_private *dev_priv = dev->dev_private;
458 int nbox = batch->num_cliprects;
459 int i, count, ret;
460
461 if ((batch->start | batch->used) & 0x7) {
462 DRM_ERROR("alignment");
463 return -EINVAL;
464 }
465
466 i915_kernel_lost_context(dev);
467
468 count = nbox ? nbox : 1;
469 for (i = 0; i < count; i++) {
470 if (i < nbox) {
471 ret = i915_emit_box(dev, &cliprects[i],
472 batch->DR1, batch->DR4);
473 if (ret)
474 return ret;
475 }
476
477 if (!IS_I830(dev) && !IS_845G(dev)) {
478 ret = BEGIN_LP_RING(2);
479 if (ret)
480 return ret;
481
482 if (INTEL_INFO(dev)->gen >= 4) {
483 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
484 OUT_RING(batch->start);
485 } else {
486 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
487 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
488 }
489 } else {
490 ret = BEGIN_LP_RING(4);
491 if (ret)
492 return ret;
493
494 OUT_RING(MI_BATCH_BUFFER);
495 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
496 OUT_RING(batch->start + batch->used - 4);
497 OUT_RING(0);
498 }
499 ADVANCE_LP_RING();
500 }
501
502
503 if (IS_G4X(dev) || IS_GEN5(dev)) {
504 if (BEGIN_LP_RING(2) == 0) {
505 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
506 OUT_RING(MI_NOOP);
507 ADVANCE_LP_RING();
508 }
509 }
510
511 i915_emit_breadcrumb(dev);
512 return 0;
513 }
514
515 static int i915_dispatch_flip(struct drm_device * dev)
516 {
517 drm_i915_private_t *dev_priv = dev->dev_private;
518 struct drm_i915_master_private *master_priv =
519 dev->primary->master->driver_priv;
520 int ret;
521
522 if (!master_priv->sarea_priv)
523 return -EINVAL;
524
525 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
526 __func__,
527 dev_priv->current_page,
528 master_priv->sarea_priv->pf_current_page);
529
530 i915_kernel_lost_context(dev);
531
532 ret = BEGIN_LP_RING(10);
533 if (ret)
534 return ret;
535
536 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
537 OUT_RING(0);
538
539 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
540 OUT_RING(0);
541 if (dev_priv->current_page == 0) {
542 OUT_RING(dev_priv->back_offset);
543 dev_priv->current_page = 1;
544 } else {
545 OUT_RING(dev_priv->front_offset);
546 dev_priv->current_page = 0;
547 }
548 OUT_RING(0);
549
550 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
551 OUT_RING(0);
552
553 ADVANCE_LP_RING();
554
555 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
556
557 if (BEGIN_LP_RING(4) == 0) {
558 OUT_RING(MI_STORE_DWORD_INDEX);
559 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
560 OUT_RING(dev_priv->counter);
561 OUT_RING(0);
562 ADVANCE_LP_RING();
563 }
564
565 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
566 return 0;
567 }
568
569 static int i915_quiescent(struct drm_device *dev)
570 {
571 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
572
573 i915_kernel_lost_context(dev);
574 return intel_wait_ring_buffer(ring, ring->size - 8);
575 }
576
577 static int i915_flush_ioctl(struct drm_device *dev, void *data,
578 struct drm_file *file_priv)
579 {
580 int ret;
581
582 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
583
584 mutex_lock(&dev->struct_mutex);
585 ret = i915_quiescent(dev);
586 mutex_unlock(&dev->struct_mutex);
587
588 return ret;
589 }
590
591 static int i915_batchbuffer(struct drm_device *dev, void *data,
592 struct drm_file *file_priv)
593 {
594 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
595 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
596 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
597 master_priv->sarea_priv;
598 drm_i915_batchbuffer_t *batch = data;
599 int ret;
600 struct drm_clip_rect *cliprects = NULL;
601
602 if (!dev_priv->allow_batchbuffer) {
603 DRM_ERROR("Batchbuffer ioctl disabled\n");
604 return -EINVAL;
605 }
606
607 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
608 batch->start, batch->used, batch->num_cliprects);
609
610 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
611
612 if (batch->num_cliprects < 0)
613 return -EINVAL;
614
615 if (batch->num_cliprects) {
616 cliprects = kcalloc(batch->num_cliprects,
617 sizeof(struct drm_clip_rect),
618 GFP_KERNEL);
619 if (cliprects == NULL)
620 return -ENOMEM;
621
622 ret = copy_from_user(cliprects, batch->cliprects,
623 batch->num_cliprects *
624 sizeof(struct drm_clip_rect));
625 if (ret != 0) {
626 ret = -EFAULT;
627 goto fail_free;
628 }
629 }
630
631 mutex_lock(&dev->struct_mutex);
632 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
633 mutex_unlock(&dev->struct_mutex);
634
635 if (sarea_priv)
636 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
637
638 fail_free:
639 kfree(cliprects);
640
641 return ret;
642 }
643
644 static int i915_cmdbuffer(struct drm_device *dev, void *data,
645 struct drm_file *file_priv)
646 {
647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
648 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
649 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
650 master_priv->sarea_priv;
651 drm_i915_cmdbuffer_t *cmdbuf = data;
652 struct drm_clip_rect *cliprects = NULL;
653 void *batch_data;
654 int ret;
655
656 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
657 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
658
659 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
660
661 if (cmdbuf->num_cliprects < 0)
662 return -EINVAL;
663
664 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
665 if (batch_data == NULL)
666 return -ENOMEM;
667
668 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
669 if (ret != 0) {
670 ret = -EFAULT;
671 goto fail_batch_free;
672 }
673
674 if (cmdbuf->num_cliprects) {
675 cliprects = kcalloc(cmdbuf->num_cliprects,
676 sizeof(struct drm_clip_rect), GFP_KERNEL);
677 if (cliprects == NULL) {
678 ret = -ENOMEM;
679 goto fail_batch_free;
680 }
681
682 ret = copy_from_user(cliprects, cmdbuf->cliprects,
683 cmdbuf->num_cliprects *
684 sizeof(struct drm_clip_rect));
685 if (ret != 0) {
686 ret = -EFAULT;
687 goto fail_clip_free;
688 }
689 }
690
691 mutex_lock(&dev->struct_mutex);
692 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
693 mutex_unlock(&dev->struct_mutex);
694 if (ret) {
695 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
696 goto fail_clip_free;
697 }
698
699 if (sarea_priv)
700 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
701
702 fail_clip_free:
703 kfree(cliprects);
704 fail_batch_free:
705 kfree(batch_data);
706
707 return ret;
708 }
709
710 static int i915_flip_bufs(struct drm_device *dev, void *data,
711 struct drm_file *file_priv)
712 {
713 int ret;
714
715 DRM_DEBUG_DRIVER("%s\n", __func__);
716
717 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
718
719 mutex_lock(&dev->struct_mutex);
720 ret = i915_dispatch_flip(dev);
721 mutex_unlock(&dev->struct_mutex);
722
723 return ret;
724 }
725
726 static int i915_getparam(struct drm_device *dev, void *data,
727 struct drm_file *file_priv)
728 {
729 drm_i915_private_t *dev_priv = dev->dev_private;
730 drm_i915_getparam_t *param = data;
731 int value;
732
733 if (!dev_priv) {
734 DRM_ERROR("called with no initialization\n");
735 return -EINVAL;
736 }
737
738 switch (param->param) {
739 case I915_PARAM_IRQ_ACTIVE:
740 value = dev->pdev->irq ? 1 : 0;
741 break;
742 case I915_PARAM_ALLOW_BATCHBUFFER:
743 value = dev_priv->allow_batchbuffer ? 1 : 0;
744 break;
745 case I915_PARAM_LAST_DISPATCH:
746 value = READ_BREADCRUMB(dev_priv);
747 break;
748 case I915_PARAM_CHIPSET_ID:
749 value = dev->pci_device;
750 break;
751 case I915_PARAM_HAS_GEM:
752 value = dev_priv->has_gem;
753 break;
754 case I915_PARAM_NUM_FENCES_AVAIL:
755 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
756 break;
757 case I915_PARAM_HAS_OVERLAY:
758 value = dev_priv->overlay ? 1 : 0;
759 break;
760 case I915_PARAM_HAS_PAGEFLIPPING:
761 value = 1;
762 break;
763 case I915_PARAM_HAS_EXECBUF2:
764 /* depends on GEM */
765 value = dev_priv->has_gem;
766 break;
767 case I915_PARAM_HAS_BSD:
768 value = HAS_BSD(dev);
769 break;
770 case I915_PARAM_HAS_BLT:
771 value = HAS_BLT(dev);
772 break;
773 case I915_PARAM_HAS_RELAXED_FENCING:
774 value = 1;
775 break;
776 case I915_PARAM_HAS_COHERENT_RINGS:
777 value = 1;
778 break;
779 case I915_PARAM_HAS_EXEC_CONSTANTS:
780 value = INTEL_INFO(dev)->gen >= 4;
781 break;
782 case I915_PARAM_HAS_RELAXED_DELTA:
783 value = 1;
784 break;
785 default:
786 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
787 param->param);
788 return -EINVAL;
789 }
790
791 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
792 DRM_ERROR("DRM_COPY_TO_USER failed\n");
793 return -EFAULT;
794 }
795
796 return 0;
797 }
798
799 static int i915_setparam(struct drm_device *dev, void *data,
800 struct drm_file *file_priv)
801 {
802 drm_i915_private_t *dev_priv = dev->dev_private;
803 drm_i915_setparam_t *param = data;
804
805 if (!dev_priv) {
806 DRM_ERROR("called with no initialization\n");
807 return -EINVAL;
808 }
809
810 switch (param->param) {
811 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
812 break;
813 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
814 dev_priv->tex_lru_log_granularity = param->value;
815 break;
816 case I915_SETPARAM_ALLOW_BATCHBUFFER:
817 dev_priv->allow_batchbuffer = param->value;
818 break;
819 case I915_SETPARAM_NUM_USED_FENCES:
820 if (param->value > dev_priv->num_fence_regs ||
821 param->value < 0)
822 return -EINVAL;
823 /* Userspace can use first N regs */
824 dev_priv->fence_reg_start = param->value;
825 break;
826 default:
827 DRM_DEBUG_DRIVER("unknown parameter %d\n",
828 param->param);
829 return -EINVAL;
830 }
831
832 return 0;
833 }
834
835 static int i915_set_status_page(struct drm_device *dev, void *data,
836 struct drm_file *file_priv)
837 {
838 drm_i915_private_t *dev_priv = dev->dev_private;
839 drm_i915_hws_addr_t *hws = data;
840 struct intel_ring_buffer *ring = LP_RING(dev_priv);
841
842 if (!I915_NEED_GFX_HWS(dev))
843 return -EINVAL;
844
845 if (!dev_priv) {
846 DRM_ERROR("called with no initialization\n");
847 return -EINVAL;
848 }
849
850 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
851 WARN(1, "tried to set status page when mode setting active\n");
852 return 0;
853 }
854
855 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
856
857 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
858
859 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
860 dev_priv->hws_map.size = 4*1024;
861 dev_priv->hws_map.type = 0;
862 dev_priv->hws_map.flags = 0;
863 dev_priv->hws_map.mtrr = 0;
864
865 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
866 if (dev_priv->hws_map.handle == NULL) {
867 i915_dma_cleanup(dev);
868 ring->status_page.gfx_addr = 0;
869 DRM_ERROR("can not ioremap virtual address for"
870 " G33 hw status page\n");
871 return -ENOMEM;
872 }
873 ring->status_page.page_addr =
874 (void __force __iomem *)dev_priv->hws_map.handle;
875 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
876 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
877
878 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
879 ring->status_page.gfx_addr);
880 DRM_DEBUG_DRIVER("load hws at %p\n",
881 ring->status_page.page_addr);
882 return 0;
883 }
884
885 static int i915_get_bridge_dev(struct drm_device *dev)
886 {
887 struct drm_i915_private *dev_priv = dev->dev_private;
888
889 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
890 if (!dev_priv->bridge_dev) {
891 DRM_ERROR("bridge device not found\n");
892 return -1;
893 }
894 return 0;
895 }
896
897 #define MCHBAR_I915 0x44
898 #define MCHBAR_I965 0x48
899 #define MCHBAR_SIZE (4*4096)
900
901 #define DEVEN_REG 0x54
902 #define DEVEN_MCHBAR_EN (1 << 28)
903
904 /* Allocate space for the MCH regs if needed, return nonzero on error */
905 static int
906 intel_alloc_mchbar_resource(struct drm_device *dev)
907 {
908 drm_i915_private_t *dev_priv = dev->dev_private;
909 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
910 u32 temp_lo, temp_hi = 0;
911 u64 mchbar_addr;
912 int ret;
913
914 if (INTEL_INFO(dev)->gen >= 4)
915 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
916 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
917 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
918
919 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
920 #ifdef CONFIG_PNP
921 if (mchbar_addr &&
922 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
923 return 0;
924 #endif
925
926 /* Get some space for it */
927 dev_priv->mch_res.name = "i915 MCHBAR";
928 dev_priv->mch_res.flags = IORESOURCE_MEM;
929 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
930 &dev_priv->mch_res,
931 MCHBAR_SIZE, MCHBAR_SIZE,
932 PCIBIOS_MIN_MEM,
933 0, pcibios_align_resource,
934 dev_priv->bridge_dev);
935 if (ret) {
936 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
937 dev_priv->mch_res.start = 0;
938 return ret;
939 }
940
941 if (INTEL_INFO(dev)->gen >= 4)
942 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
943 upper_32_bits(dev_priv->mch_res.start));
944
945 pci_write_config_dword(dev_priv->bridge_dev, reg,
946 lower_32_bits(dev_priv->mch_res.start));
947 return 0;
948 }
949
950 /* Setup MCHBAR if possible, return true if we should disable it again */
951 static void
952 intel_setup_mchbar(struct drm_device *dev)
953 {
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
956 u32 temp;
957 bool enabled;
958
959 dev_priv->mchbar_need_disable = false;
960
961 if (IS_I915G(dev) || IS_I915GM(dev)) {
962 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
963 enabled = !!(temp & DEVEN_MCHBAR_EN);
964 } else {
965 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
966 enabled = temp & 1;
967 }
968
969 /* If it's already enabled, don't have to do anything */
970 if (enabled)
971 return;
972
973 if (intel_alloc_mchbar_resource(dev))
974 return;
975
976 dev_priv->mchbar_need_disable = true;
977
978 /* Space is allocated or reserved, so enable it. */
979 if (IS_I915G(dev) || IS_I915GM(dev)) {
980 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
981 temp | DEVEN_MCHBAR_EN);
982 } else {
983 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
984 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
985 }
986 }
987
988 static void
989 intel_teardown_mchbar(struct drm_device *dev)
990 {
991 drm_i915_private_t *dev_priv = dev->dev_private;
992 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
993 u32 temp;
994
995 if (dev_priv->mchbar_need_disable) {
996 if (IS_I915G(dev) || IS_I915GM(dev)) {
997 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
998 temp &= ~DEVEN_MCHBAR_EN;
999 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1000 } else {
1001 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1002 temp &= ~1;
1003 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1004 }
1005 }
1006
1007 if (dev_priv->mch_res.start)
1008 release_resource(&dev_priv->mch_res);
1009 }
1010
1011 #define PTE_ADDRESS_MASK 0xfffff000
1012 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1013 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1014 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1015 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1016 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1017 #define PTE_VALID (1 << 0)
1018
1019 /**
1020 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1021 * a physical one
1022 * @dev: drm device
1023 * @offset: address to translate
1024 *
1025 * Some chip functions require allocations from stolen space and need the
1026 * physical address of the memory in question.
1027 */
1028 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1029 {
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct pci_dev *pdev = dev_priv->bridge_dev;
1032 u32 base;
1033
1034 #if 0
1035 /* On the machines I have tested the Graphics Base of Stolen Memory
1036 * is unreliable, so compute the base by subtracting the stolen memory
1037 * from the Top of Low Usable DRAM which is where the BIOS places
1038 * the graphics stolen memory.
1039 */
1040 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1041 /* top 32bits are reserved = 0 */
1042 pci_read_config_dword(pdev, 0xA4, &base);
1043 } else {
1044 /* XXX presume 8xx is the same as i915 */
1045 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1046 }
1047 #else
1048 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1049 u16 val;
1050 pci_read_config_word(pdev, 0xb0, &val);
1051 base = val >> 4 << 20;
1052 } else {
1053 u8 val;
1054 pci_read_config_byte(pdev, 0x9c, &val);
1055 base = val >> 3 << 27;
1056 }
1057 base -= dev_priv->mm.gtt->stolen_size;
1058 #endif
1059
1060 return base + offset;
1061 }
1062
1063 static void i915_warn_stolen(struct drm_device *dev)
1064 {
1065 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1066 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1067 }
1068
1069 static void i915_setup_compression(struct drm_device *dev, int size)
1070 {
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1073 unsigned long cfb_base;
1074 unsigned long ll_base = 0;
1075
1076 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1077 if (compressed_fb)
1078 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1079 if (!compressed_fb)
1080 goto err;
1081
1082 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1083 if (!cfb_base)
1084 goto err_fb;
1085
1086 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1087 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1088 4096, 4096, 0);
1089 if (compressed_llb)
1090 compressed_llb = drm_mm_get_block(compressed_llb,
1091 4096, 4096);
1092 if (!compressed_llb)
1093 goto err_fb;
1094
1095 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1096 if (!ll_base)
1097 goto err_llb;
1098 }
1099
1100 dev_priv->cfb_size = size;
1101
1102 intel_disable_fbc(dev);
1103 dev_priv->compressed_fb = compressed_fb;
1104 if (HAS_PCH_SPLIT(dev))
1105 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1106 else if (IS_GM45(dev)) {
1107 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1108 } else {
1109 I915_WRITE(FBC_CFB_BASE, cfb_base);
1110 I915_WRITE(FBC_LL_BASE, ll_base);
1111 dev_priv->compressed_llb = compressed_llb;
1112 }
1113
1114 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1115 cfb_base, ll_base, size >> 20);
1116 return;
1117
1118 err_llb:
1119 drm_mm_put_block(compressed_llb);
1120 err_fb:
1121 drm_mm_put_block(compressed_fb);
1122 err:
1123 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1124 i915_warn_stolen(dev);
1125 }
1126
1127 static void i915_cleanup_compression(struct drm_device *dev)
1128 {
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130
1131 drm_mm_put_block(dev_priv->compressed_fb);
1132 if (dev_priv->compressed_llb)
1133 drm_mm_put_block(dev_priv->compressed_llb);
1134 }
1135
1136 /* true = enable decode, false = disable decoder */
1137 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1138 {
1139 struct drm_device *dev = cookie;
1140
1141 intel_modeset_vga_set_state(dev, state);
1142 if (state)
1143 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1144 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1145 else
1146 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1147 }
1148
1149 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1150 {
1151 struct drm_device *dev = pci_get_drvdata(pdev);
1152 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1153 if (state == VGA_SWITCHEROO_ON) {
1154 printk(KERN_INFO "i915: switched on\n");
1155 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1156 /* i915 resume handler doesn't set to D0 */
1157 pci_set_power_state(dev->pdev, PCI_D0);
1158 i915_resume(dev);
1159 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1160 } else {
1161 printk(KERN_ERR "i915: switched off\n");
1162 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1163 i915_suspend(dev, pmm);
1164 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1165 }
1166 }
1167
1168 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1169 {
1170 struct drm_device *dev = pci_get_drvdata(pdev);
1171 bool can_switch;
1172
1173 spin_lock(&dev->count_lock);
1174 can_switch = (dev->open_count == 0);
1175 spin_unlock(&dev->count_lock);
1176 return can_switch;
1177 }
1178
1179 static int i915_load_modeset_init(struct drm_device *dev)
1180 {
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 unsigned long prealloc_size, gtt_size, mappable_size;
1183 int ret = 0;
1184
1185 prealloc_size = dev_priv->mm.gtt->stolen_size;
1186 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1187 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1188
1189 /* Basic memrange allocator for stolen space */
1190 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1191
1192 /* Let GEM Manage all of the aperture.
1193 *
1194 * However, leave one page at the end still bound to the scratch page.
1195 * There are a number of places where the hardware apparently
1196 * prefetches past the end of the object, and we've seen multiple
1197 * hangs with the GPU head pointer stuck in a batchbuffer bound
1198 * at the last page of the aperture. One page should be enough to
1199 * keep any prefetching inside of the aperture.
1200 */
1201 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1202
1203 mutex_lock(&dev->struct_mutex);
1204 ret = i915_gem_init_ringbuffer(dev);
1205 mutex_unlock(&dev->struct_mutex);
1206 if (ret)
1207 goto out;
1208
1209 /* Try to set up FBC with a reasonable compressed buffer size */
1210 if (I915_HAS_FBC(dev) && i915_powersave) {
1211 int cfb_size;
1212
1213 /* Leave 1M for line length buffer & misc. */
1214
1215 /* Try to get a 32M buffer... */
1216 if (prealloc_size > (36*1024*1024))
1217 cfb_size = 32*1024*1024;
1218 else /* fall back to 7/8 of the stolen space */
1219 cfb_size = prealloc_size * 7 / 8;
1220 i915_setup_compression(dev, cfb_size);
1221 }
1222
1223 /* Allow hardware batchbuffers unless told otherwise. */
1224 dev_priv->allow_batchbuffer = 1;
1225
1226 ret = intel_parse_bios(dev);
1227 if (ret)
1228 DRM_INFO("failed to find VBIOS tables\n");
1229
1230 /* If we have > 1 VGA cards, then we need to arbitrate access
1231 * to the common VGA resources.
1232 *
1233 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1234 * then we do not take part in VGA arbitration and the
1235 * vga_client_register() fails with -ENODEV.
1236 */
1237 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1238 if (ret && ret != -ENODEV)
1239 goto cleanup_ringbuffer;
1240
1241 intel_register_dsm_handler();
1242
1243 ret = vga_switcheroo_register_client(dev->pdev,
1244 i915_switcheroo_set_state,
1245 NULL,
1246 i915_switcheroo_can_switch);
1247 if (ret)
1248 goto cleanup_vga_client;
1249
1250 /* IIR "flip pending" bit means done if this bit is set */
1251 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1252 dev_priv->flip_pending_is_done = true;
1253
1254 intel_modeset_init(dev);
1255
1256 ret = drm_irq_install(dev);
1257 if (ret)
1258 goto cleanup_vga_switcheroo;
1259
1260 /* Always safe in the mode setting case. */
1261 /* FIXME: do pre/post-mode set stuff in core KMS code */
1262 dev->vblank_disable_allowed = 1;
1263
1264 ret = intel_fbdev_init(dev);
1265 if (ret)
1266 goto cleanup_irq;
1267
1268 drm_kms_helper_poll_init(dev);
1269
1270 /* We're off and running w/KMS */
1271 dev_priv->mm.suspended = 0;
1272
1273 return 0;
1274
1275 cleanup_irq:
1276 drm_irq_uninstall(dev);
1277 cleanup_vga_switcheroo:
1278 vga_switcheroo_unregister_client(dev->pdev);
1279 cleanup_vga_client:
1280 vga_client_register(dev->pdev, NULL, NULL, NULL);
1281 cleanup_ringbuffer:
1282 mutex_lock(&dev->struct_mutex);
1283 i915_gem_cleanup_ringbuffer(dev);
1284 mutex_unlock(&dev->struct_mutex);
1285 out:
1286 return ret;
1287 }
1288
1289 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1290 {
1291 struct drm_i915_master_private *master_priv;
1292
1293 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1294 if (!master_priv)
1295 return -ENOMEM;
1296
1297 master->driver_priv = master_priv;
1298 return 0;
1299 }
1300
1301 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1302 {
1303 struct drm_i915_master_private *master_priv = master->driver_priv;
1304
1305 if (!master_priv)
1306 return;
1307
1308 kfree(master_priv);
1309
1310 master->driver_priv = NULL;
1311 }
1312
1313 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1314 {
1315 drm_i915_private_t *dev_priv = dev->dev_private;
1316 u32 tmp;
1317
1318 tmp = I915_READ(CLKCFG);
1319
1320 switch (tmp & CLKCFG_FSB_MASK) {
1321 case CLKCFG_FSB_533:
1322 dev_priv->fsb_freq = 533; /* 133*4 */
1323 break;
1324 case CLKCFG_FSB_800:
1325 dev_priv->fsb_freq = 800; /* 200*4 */
1326 break;
1327 case CLKCFG_FSB_667:
1328 dev_priv->fsb_freq = 667; /* 167*4 */
1329 break;
1330 case CLKCFG_FSB_400:
1331 dev_priv->fsb_freq = 400; /* 100*4 */
1332 break;
1333 }
1334
1335 switch (tmp & CLKCFG_MEM_MASK) {
1336 case CLKCFG_MEM_533:
1337 dev_priv->mem_freq = 533;
1338 break;
1339 case CLKCFG_MEM_667:
1340 dev_priv->mem_freq = 667;
1341 break;
1342 case CLKCFG_MEM_800:
1343 dev_priv->mem_freq = 800;
1344 break;
1345 }
1346
1347 /* detect pineview DDR3 setting */
1348 tmp = I915_READ(CSHRDDR3CTL);
1349 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1350 }
1351
1352 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1353 {
1354 drm_i915_private_t *dev_priv = dev->dev_private;
1355 u16 ddrpll, csipll;
1356
1357 ddrpll = I915_READ16(DDRMPLL1);
1358 csipll = I915_READ16(CSIPLL0);
1359
1360 switch (ddrpll & 0xff) {
1361 case 0xc:
1362 dev_priv->mem_freq = 800;
1363 break;
1364 case 0x10:
1365 dev_priv->mem_freq = 1066;
1366 break;
1367 case 0x14:
1368 dev_priv->mem_freq = 1333;
1369 break;
1370 case 0x18:
1371 dev_priv->mem_freq = 1600;
1372 break;
1373 default:
1374 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1375 ddrpll & 0xff);
1376 dev_priv->mem_freq = 0;
1377 break;
1378 }
1379
1380 dev_priv->r_t = dev_priv->mem_freq;
1381
1382 switch (csipll & 0x3ff) {
1383 case 0x00c:
1384 dev_priv->fsb_freq = 3200;
1385 break;
1386 case 0x00e:
1387 dev_priv->fsb_freq = 3733;
1388 break;
1389 case 0x010:
1390 dev_priv->fsb_freq = 4266;
1391 break;
1392 case 0x012:
1393 dev_priv->fsb_freq = 4800;
1394 break;
1395 case 0x014:
1396 dev_priv->fsb_freq = 5333;
1397 break;
1398 case 0x016:
1399 dev_priv->fsb_freq = 5866;
1400 break;
1401 case 0x018:
1402 dev_priv->fsb_freq = 6400;
1403 break;
1404 default:
1405 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1406 csipll & 0x3ff);
1407 dev_priv->fsb_freq = 0;
1408 break;
1409 }
1410
1411 if (dev_priv->fsb_freq == 3200) {
1412 dev_priv->c_m = 0;
1413 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1414 dev_priv->c_m = 1;
1415 } else {
1416 dev_priv->c_m = 2;
1417 }
1418 }
1419
1420 static const struct cparams {
1421 u16 i;
1422 u16 t;
1423 u16 m;
1424 u16 c;
1425 } cparams[] = {
1426 { 1, 1333, 301, 28664 },
1427 { 1, 1066, 294, 24460 },
1428 { 1, 800, 294, 25192 },
1429 { 0, 1333, 276, 27605 },
1430 { 0, 1066, 276, 27605 },
1431 { 0, 800, 231, 23784 },
1432 };
1433
1434 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1435 {
1436 u64 total_count, diff, ret;
1437 u32 count1, count2, count3, m = 0, c = 0;
1438 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1439 int i;
1440
1441 diff1 = now - dev_priv->last_time1;
1442
1443 count1 = I915_READ(DMIEC);
1444 count2 = I915_READ(DDREC);
1445 count3 = I915_READ(CSIEC);
1446
1447 total_count = count1 + count2 + count3;
1448
1449 /* FIXME: handle per-counter overflow */
1450 if (total_count < dev_priv->last_count1) {
1451 diff = ~0UL - dev_priv->last_count1;
1452 diff += total_count;
1453 } else {
1454 diff = total_count - dev_priv->last_count1;
1455 }
1456
1457 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1458 if (cparams[i].i == dev_priv->c_m &&
1459 cparams[i].t == dev_priv->r_t) {
1460 m = cparams[i].m;
1461 c = cparams[i].c;
1462 break;
1463 }
1464 }
1465
1466 diff = div_u64(diff, diff1);
1467 ret = ((m * diff) + c);
1468 ret = div_u64(ret, 10);
1469
1470 dev_priv->last_count1 = total_count;
1471 dev_priv->last_time1 = now;
1472
1473 return ret;
1474 }
1475
1476 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1477 {
1478 unsigned long m, x, b;
1479 u32 tsfs;
1480
1481 tsfs = I915_READ(TSFS);
1482
1483 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1484 x = I915_READ8(TR1);
1485
1486 b = tsfs & TSFS_INTR_MASK;
1487
1488 return ((m * x) / 127) - b;
1489 }
1490
1491 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1492 {
1493 static const struct v_table {
1494 u16 vd; /* in .1 mil */
1495 u16 vm; /* in .1 mil */
1496 } v_table[] = {
1497 { 0, 0, },
1498 { 375, 0, },
1499 { 500, 0, },
1500 { 625, 0, },
1501 { 750, 0, },
1502 { 875, 0, },
1503 { 1000, 0, },
1504 { 1125, 0, },
1505 { 4125, 3000, },
1506 { 4125, 3000, },
1507 { 4125, 3000, },
1508 { 4125, 3000, },
1509 { 4125, 3000, },
1510 { 4125, 3000, },
1511 { 4125, 3000, },
1512 { 4125, 3000, },
1513 { 4125, 3000, },
1514 { 4125, 3000, },
1515 { 4125, 3000, },
1516 { 4125, 3000, },
1517 { 4125, 3000, },
1518 { 4125, 3000, },
1519 { 4125, 3000, },
1520 { 4125, 3000, },
1521 { 4125, 3000, },
1522 { 4125, 3000, },
1523 { 4125, 3000, },
1524 { 4125, 3000, },
1525 { 4125, 3000, },
1526 { 4125, 3000, },
1527 { 4125, 3000, },
1528 { 4125, 3000, },
1529 { 4250, 3125, },
1530 { 4375, 3250, },
1531 { 4500, 3375, },
1532 { 4625, 3500, },
1533 { 4750, 3625, },
1534 { 4875, 3750, },
1535 { 5000, 3875, },
1536 { 5125, 4000, },
1537 { 5250, 4125, },
1538 { 5375, 4250, },
1539 { 5500, 4375, },
1540 { 5625, 4500, },
1541 { 5750, 4625, },
1542 { 5875, 4750, },
1543 { 6000, 4875, },
1544 { 6125, 5000, },
1545 { 6250, 5125, },
1546 { 6375, 5250, },
1547 { 6500, 5375, },
1548 { 6625, 5500, },
1549 { 6750, 5625, },
1550 { 6875, 5750, },
1551 { 7000, 5875, },
1552 { 7125, 6000, },
1553 { 7250, 6125, },
1554 { 7375, 6250, },
1555 { 7500, 6375, },
1556 { 7625, 6500, },
1557 { 7750, 6625, },
1558 { 7875, 6750, },
1559 { 8000, 6875, },
1560 { 8125, 7000, },
1561 { 8250, 7125, },
1562 { 8375, 7250, },
1563 { 8500, 7375, },
1564 { 8625, 7500, },
1565 { 8750, 7625, },
1566 { 8875, 7750, },
1567 { 9000, 7875, },
1568 { 9125, 8000, },
1569 { 9250, 8125, },
1570 { 9375, 8250, },
1571 { 9500, 8375, },
1572 { 9625, 8500, },
1573 { 9750, 8625, },
1574 { 9875, 8750, },
1575 { 10000, 8875, },
1576 { 10125, 9000, },
1577 { 10250, 9125, },
1578 { 10375, 9250, },
1579 { 10500, 9375, },
1580 { 10625, 9500, },
1581 { 10750, 9625, },
1582 { 10875, 9750, },
1583 { 11000, 9875, },
1584 { 11125, 10000, },
1585 { 11250, 10125, },
1586 { 11375, 10250, },
1587 { 11500, 10375, },
1588 { 11625, 10500, },
1589 { 11750, 10625, },
1590 { 11875, 10750, },
1591 { 12000, 10875, },
1592 { 12125, 11000, },
1593 { 12250, 11125, },
1594 { 12375, 11250, },
1595 { 12500, 11375, },
1596 { 12625, 11500, },
1597 { 12750, 11625, },
1598 { 12875, 11750, },
1599 { 13000, 11875, },
1600 { 13125, 12000, },
1601 { 13250, 12125, },
1602 { 13375, 12250, },
1603 { 13500, 12375, },
1604 { 13625, 12500, },
1605 { 13750, 12625, },
1606 { 13875, 12750, },
1607 { 14000, 12875, },
1608 { 14125, 13000, },
1609 { 14250, 13125, },
1610 { 14375, 13250, },
1611 { 14500, 13375, },
1612 { 14625, 13500, },
1613 { 14750, 13625, },
1614 { 14875, 13750, },
1615 { 15000, 13875, },
1616 { 15125, 14000, },
1617 { 15250, 14125, },
1618 { 15375, 14250, },
1619 { 15500, 14375, },
1620 { 15625, 14500, },
1621 { 15750, 14625, },
1622 { 15875, 14750, },
1623 { 16000, 14875, },
1624 { 16125, 15000, },
1625 };
1626 if (dev_priv->info->is_mobile)
1627 return v_table[pxvid].vm;
1628 else
1629 return v_table[pxvid].vd;
1630 }
1631
1632 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1633 {
1634 struct timespec now, diff1;
1635 u64 diff;
1636 unsigned long diffms;
1637 u32 count;
1638
1639 getrawmonotonic(&now);
1640 diff1 = timespec_sub(now, dev_priv->last_time2);
1641
1642 /* Don't divide by 0 */
1643 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1644 if (!diffms)
1645 return;
1646
1647 count = I915_READ(GFXEC);
1648
1649 if (count < dev_priv->last_count2) {
1650 diff = ~0UL - dev_priv->last_count2;
1651 diff += count;
1652 } else {
1653 diff = count - dev_priv->last_count2;
1654 }
1655
1656 dev_priv->last_count2 = count;
1657 dev_priv->last_time2 = now;
1658
1659 /* More magic constants... */
1660 diff = diff * 1181;
1661 diff = div_u64(diff, diffms * 10);
1662 dev_priv->gfx_power = diff;
1663 }
1664
1665 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1666 {
1667 unsigned long t, corr, state1, corr2, state2;
1668 u32 pxvid, ext_v;
1669
1670 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1671 pxvid = (pxvid >> 24) & 0x7f;
1672 ext_v = pvid_to_extvid(dev_priv, pxvid);
1673
1674 state1 = ext_v;
1675
1676 t = i915_mch_val(dev_priv);
1677
1678 /* Revel in the empirically derived constants */
1679
1680 /* Correction factor in 1/100000 units */
1681 if (t > 80)
1682 corr = ((t * 2349) + 135940);
1683 else if (t >= 50)
1684 corr = ((t * 964) + 29317);
1685 else /* < 50 */
1686 corr = ((t * 301) + 1004);
1687
1688 corr = corr * ((150142 * state1) / 10000 - 78642);
1689 corr /= 100000;
1690 corr2 = (corr * dev_priv->corr);
1691
1692 state2 = (corr2 * state1) / 10000;
1693 state2 /= 100; /* convert to mW */
1694
1695 i915_update_gfx_val(dev_priv);
1696
1697 return dev_priv->gfx_power + state2;
1698 }
1699
1700 /* Global for IPS driver to get at the current i915 device */
1701 static struct drm_i915_private *i915_mch_dev;
1702 /*
1703 * Lock protecting IPS related data structures
1704 * - i915_mch_dev
1705 * - dev_priv->max_delay
1706 * - dev_priv->min_delay
1707 * - dev_priv->fmax
1708 * - dev_priv->gpu_busy
1709 */
1710 static DEFINE_SPINLOCK(mchdev_lock);
1711
1712 /**
1713 * i915_read_mch_val - return value for IPS use
1714 *
1715 * Calculate and return a value for the IPS driver to use when deciding whether
1716 * we have thermal and power headroom to increase CPU or GPU power budget.
1717 */
1718 unsigned long i915_read_mch_val(void)
1719 {
1720 struct drm_i915_private *dev_priv;
1721 unsigned long chipset_val, graphics_val, ret = 0;
1722
1723 spin_lock(&mchdev_lock);
1724 if (!i915_mch_dev)
1725 goto out_unlock;
1726 dev_priv = i915_mch_dev;
1727
1728 chipset_val = i915_chipset_val(dev_priv);
1729 graphics_val = i915_gfx_val(dev_priv);
1730
1731 ret = chipset_val + graphics_val;
1732
1733 out_unlock:
1734 spin_unlock(&mchdev_lock);
1735
1736 return ret;
1737 }
1738 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1739
1740 /**
1741 * i915_gpu_raise - raise GPU frequency limit
1742 *
1743 * Raise the limit; IPS indicates we have thermal headroom.
1744 */
1745 bool i915_gpu_raise(void)
1746 {
1747 struct drm_i915_private *dev_priv;
1748 bool ret = true;
1749
1750 spin_lock(&mchdev_lock);
1751 if (!i915_mch_dev) {
1752 ret = false;
1753 goto out_unlock;
1754 }
1755 dev_priv = i915_mch_dev;
1756
1757 if (dev_priv->max_delay > dev_priv->fmax)
1758 dev_priv->max_delay--;
1759
1760 out_unlock:
1761 spin_unlock(&mchdev_lock);
1762
1763 return ret;
1764 }
1765 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1766
1767 /**
1768 * i915_gpu_lower - lower GPU frequency limit
1769 *
1770 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1771 * frequency maximum.
1772 */
1773 bool i915_gpu_lower(void)
1774 {
1775 struct drm_i915_private *dev_priv;
1776 bool ret = true;
1777
1778 spin_lock(&mchdev_lock);
1779 if (!i915_mch_dev) {
1780 ret = false;
1781 goto out_unlock;
1782 }
1783 dev_priv = i915_mch_dev;
1784
1785 if (dev_priv->max_delay < dev_priv->min_delay)
1786 dev_priv->max_delay++;
1787
1788 out_unlock:
1789 spin_unlock(&mchdev_lock);
1790
1791 return ret;
1792 }
1793 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1794
1795 /**
1796 * i915_gpu_busy - indicate GPU business to IPS
1797 *
1798 * Tell the IPS driver whether or not the GPU is busy.
1799 */
1800 bool i915_gpu_busy(void)
1801 {
1802 struct drm_i915_private *dev_priv;
1803 bool ret = false;
1804
1805 spin_lock(&mchdev_lock);
1806 if (!i915_mch_dev)
1807 goto out_unlock;
1808 dev_priv = i915_mch_dev;
1809
1810 ret = dev_priv->busy;
1811
1812 out_unlock:
1813 spin_unlock(&mchdev_lock);
1814
1815 return ret;
1816 }
1817 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1818
1819 /**
1820 * i915_gpu_turbo_disable - disable graphics turbo
1821 *
1822 * Disable graphics turbo by resetting the max frequency and setting the
1823 * current frequency to the default.
1824 */
1825 bool i915_gpu_turbo_disable(void)
1826 {
1827 struct drm_i915_private *dev_priv;
1828 bool ret = true;
1829
1830 spin_lock(&mchdev_lock);
1831 if (!i915_mch_dev) {
1832 ret = false;
1833 goto out_unlock;
1834 }
1835 dev_priv = i915_mch_dev;
1836
1837 dev_priv->max_delay = dev_priv->fstart;
1838
1839 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1840 ret = false;
1841
1842 out_unlock:
1843 spin_unlock(&mchdev_lock);
1844
1845 return ret;
1846 }
1847 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1848
1849 /**
1850 * Tells the intel_ips driver that the i915 driver is now loaded, if
1851 * IPS got loaded first.
1852 *
1853 * This awkward dance is so that neither module has to depend on the
1854 * other in order for IPS to do the appropriate communication of
1855 * GPU turbo limits to i915.
1856 */
1857 static void
1858 ips_ping_for_i915_load(void)
1859 {
1860 void (*link)(void);
1861
1862 link = symbol_get(ips_link_to_i915_driver);
1863 if (link) {
1864 link();
1865 symbol_put(ips_link_to_i915_driver);
1866 }
1867 }
1868
1869 /**
1870 * i915_driver_load - setup chip and create an initial config
1871 * @dev: DRM device
1872 * @flags: startup flags
1873 *
1874 * The driver load routine has to do several things:
1875 * - drive output discovery via intel_modeset_init()
1876 * - initialize the memory manager
1877 * - allocate initial config memory
1878 * - setup the DRM framebuffer with the allocated memory
1879 */
1880 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1881 {
1882 struct drm_i915_private *dev_priv;
1883 int ret = 0, mmio_bar;
1884 uint32_t agp_size;
1885
1886 /* i915 has 4 more counters */
1887 dev->counters += 4;
1888 dev->types[6] = _DRM_STAT_IRQ;
1889 dev->types[7] = _DRM_STAT_PRIMARY;
1890 dev->types[8] = _DRM_STAT_SECONDARY;
1891 dev->types[9] = _DRM_STAT_DMA;
1892
1893 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1894 if (dev_priv == NULL)
1895 return -ENOMEM;
1896
1897 dev->dev_private = (void *)dev_priv;
1898 dev_priv->dev = dev;
1899 dev_priv->info = (struct intel_device_info *) flags;
1900
1901 if (i915_get_bridge_dev(dev)) {
1902 ret = -EIO;
1903 goto free_priv;
1904 }
1905
1906 /* overlay on gen2 is broken and can't address above 1G */
1907 if (IS_GEN2(dev))
1908 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1909
1910 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1911 * using 32bit addressing, overwriting memory if HWS is located
1912 * above 4GB.
1913 *
1914 * The documentation also mentions an issue with undefined
1915 * behaviour if any general state is accessed within a page above 4GB,
1916 * which also needs to be handled carefully.
1917 */
1918 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1919 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1920
1921 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1922 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1923 if (!dev_priv->regs) {
1924 DRM_ERROR("failed to map registers\n");
1925 ret = -EIO;
1926 goto put_bridge;
1927 }
1928
1929 dev_priv->mm.gtt = intel_gtt_get();
1930 if (!dev_priv->mm.gtt) {
1931 DRM_ERROR("Failed to initialize GTT\n");
1932 ret = -ENODEV;
1933 goto out_iomapfree;
1934 }
1935
1936 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1937
1938 dev_priv->mm.gtt_mapping =
1939 io_mapping_create_wc(dev->agp->base, agp_size);
1940 if (dev_priv->mm.gtt_mapping == NULL) {
1941 ret = -EIO;
1942 goto out_rmmap;
1943 }
1944
1945 /* Set up a WC MTRR for non-PAT systems. This is more common than
1946 * one would think, because the kernel disables PAT on first
1947 * generation Core chips because WC PAT gets overridden by a UC
1948 * MTRR if present. Even if a UC MTRR isn't present.
1949 */
1950 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1951 agp_size,
1952 MTRR_TYPE_WRCOMB, 1);
1953 if (dev_priv->mm.gtt_mtrr < 0) {
1954 DRM_INFO("MTRR allocation failed. Graphics "
1955 "performance may suffer.\n");
1956 }
1957
1958 /* The i915 workqueue is primarily used for batched retirement of
1959 * requests (and thus managing bo) once the task has been completed
1960 * by the GPU. i915_gem_retire_requests() is called directly when we
1961 * need high-priority retirement, such as waiting for an explicit
1962 * bo.
1963 *
1964 * It is also used for periodic low-priority events, such as
1965 * idle-timers and recording error state.
1966 *
1967 * All tasks on the workqueue are expected to acquire the dev mutex
1968 * so there is no point in running more than one instance of the
1969 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1970 */
1971 dev_priv->wq = alloc_workqueue("i915",
1972 WQ_UNBOUND | WQ_NON_REENTRANT,
1973 1);
1974 if (dev_priv->wq == NULL) {
1975 DRM_ERROR("Failed to create our workqueue.\n");
1976 ret = -ENOMEM;
1977 goto out_iomapfree;
1978 }
1979
1980 /* enable GEM by default */
1981 dev_priv->has_gem = 1;
1982
1983 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1984 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1985 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1986 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1987 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1988 }
1989
1990 /* Try to make sure MCHBAR is enabled before poking at it */
1991 intel_setup_mchbar(dev);
1992 intel_setup_gmbus(dev);
1993 intel_opregion_setup(dev);
1994
1995 /* Make sure the bios did its job and set up vital registers */
1996 intel_setup_bios(dev);
1997
1998 i915_gem_load(dev);
1999
2000 /* Init HWS */
2001 if (!I915_NEED_GFX_HWS(dev)) {
2002 ret = i915_init_phys_hws(dev);
2003 if (ret)
2004 goto out_gem_unload;
2005 }
2006
2007 if (IS_PINEVIEW(dev))
2008 i915_pineview_get_mem_freq(dev);
2009 else if (IS_GEN5(dev))
2010 i915_ironlake_get_mem_freq(dev);
2011
2012 /* On the 945G/GM, the chipset reports the MSI capability on the
2013 * integrated graphics even though the support isn't actually there
2014 * according to the published specs. It doesn't appear to function
2015 * correctly in testing on 945G.
2016 * This may be a side effect of MSI having been made available for PEG
2017 * and the registers being closely associated.
2018 *
2019 * According to chipset errata, on the 965GM, MSI interrupts may
2020 * be lost or delayed, but we use them anyways to avoid
2021 * stuck interrupts on some machines.
2022 */
2023 if (!IS_I945G(dev) && !IS_I945GM(dev))
2024 pci_enable_msi(dev->pdev);
2025
2026 spin_lock_init(&dev_priv->irq_lock);
2027 spin_lock_init(&dev_priv->error_lock);
2028
2029 if (IS_MOBILE(dev) || !IS_GEN2(dev))
2030 dev_priv->num_pipe = 2;
2031 else
2032 dev_priv->num_pipe = 1;
2033
2034 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2035 if (ret)
2036 goto out_gem_unload;
2037
2038 /* Start out suspended */
2039 dev_priv->mm.suspended = 1;
2040
2041 intel_detect_pch(dev);
2042
2043 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2044 ret = i915_load_modeset_init(dev);
2045 if (ret < 0) {
2046 DRM_ERROR("failed to init modeset\n");
2047 goto out_gem_unload;
2048 }
2049 }
2050
2051 /* Must be done after probing outputs */
2052 intel_opregion_init(dev);
2053 acpi_video_register();
2054
2055 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2056 (unsigned long) dev);
2057
2058 spin_lock(&mchdev_lock);
2059 i915_mch_dev = dev_priv;
2060 dev_priv->mchdev_lock = &mchdev_lock;
2061 spin_unlock(&mchdev_lock);
2062
2063 ips_ping_for_i915_load();
2064
2065 return 0;
2066
2067 out_gem_unload:
2068 if (dev->pdev->msi_enabled)
2069 pci_disable_msi(dev->pdev);
2070
2071 intel_teardown_gmbus(dev);
2072 intel_teardown_mchbar(dev);
2073 destroy_workqueue(dev_priv->wq);
2074 out_iomapfree:
2075 io_mapping_free(dev_priv->mm.gtt_mapping);
2076 out_rmmap:
2077 pci_iounmap(dev->pdev, dev_priv->regs);
2078 put_bridge:
2079 pci_dev_put(dev_priv->bridge_dev);
2080 free_priv:
2081 kfree(dev_priv);
2082 return ret;
2083 }
2084
2085 int i915_driver_unload(struct drm_device *dev)
2086 {
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 int ret;
2089
2090 spin_lock(&mchdev_lock);
2091 i915_mch_dev = NULL;
2092 spin_unlock(&mchdev_lock);
2093
2094 if (dev_priv->mm.inactive_shrinker.shrink)
2095 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2096
2097 mutex_lock(&dev->struct_mutex);
2098 ret = i915_gpu_idle(dev);
2099 if (ret)
2100 DRM_ERROR("failed to idle hardware: %d\n", ret);
2101 mutex_unlock(&dev->struct_mutex);
2102
2103 /* Cancel the retire work handler, which should be idle now. */
2104 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2105
2106 io_mapping_free(dev_priv->mm.gtt_mapping);
2107 if (dev_priv->mm.gtt_mtrr >= 0) {
2108 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2109 dev->agp->agp_info.aper_size * 1024 * 1024);
2110 dev_priv->mm.gtt_mtrr = -1;
2111 }
2112
2113 acpi_video_unregister();
2114
2115 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2116 intel_fbdev_fini(dev);
2117 intel_modeset_cleanup(dev);
2118
2119 /*
2120 * free the memory space allocated for the child device
2121 * config parsed from VBT
2122 */
2123 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2124 kfree(dev_priv->child_dev);
2125 dev_priv->child_dev = NULL;
2126 dev_priv->child_dev_num = 0;
2127 }
2128
2129 vga_switcheroo_unregister_client(dev->pdev);
2130 vga_client_register(dev->pdev, NULL, NULL, NULL);
2131 }
2132
2133 /* Free error state after interrupts are fully disabled. */
2134 del_timer_sync(&dev_priv->hangcheck_timer);
2135 cancel_work_sync(&dev_priv->error_work);
2136 i915_destroy_error_state(dev);
2137
2138 if (dev->pdev->msi_enabled)
2139 pci_disable_msi(dev->pdev);
2140
2141 intel_opregion_fini(dev);
2142
2143 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2144 /* Flush any outstanding unpin_work. */
2145 flush_workqueue(dev_priv->wq);
2146
2147 i915_gem_free_all_phys_object(dev);
2148
2149 mutex_lock(&dev->struct_mutex);
2150 i915_gem_cleanup_ringbuffer(dev);
2151 mutex_unlock(&dev->struct_mutex);
2152 if (I915_HAS_FBC(dev) && i915_powersave)
2153 i915_cleanup_compression(dev);
2154 drm_mm_takedown(&dev_priv->mm.stolen);
2155
2156 intel_cleanup_overlay(dev);
2157
2158 if (!I915_NEED_GFX_HWS(dev))
2159 i915_free_hws(dev);
2160 }
2161
2162 if (dev_priv->regs != NULL)
2163 pci_iounmap(dev->pdev, dev_priv->regs);
2164
2165 intel_teardown_gmbus(dev);
2166 intel_teardown_mchbar(dev);
2167
2168 destroy_workqueue(dev_priv->wq);
2169
2170 pci_dev_put(dev_priv->bridge_dev);
2171 kfree(dev->dev_private);
2172
2173 return 0;
2174 }
2175
2176 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2177 {
2178 struct drm_i915_file_private *file_priv;
2179
2180 DRM_DEBUG_DRIVER("\n");
2181 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2182 if (!file_priv)
2183 return -ENOMEM;
2184
2185 file->driver_priv = file_priv;
2186
2187 spin_lock_init(&file_priv->mm.lock);
2188 INIT_LIST_HEAD(&file_priv->mm.request_list);
2189
2190 return 0;
2191 }
2192
2193 /**
2194 * i915_driver_lastclose - clean up after all DRM clients have exited
2195 * @dev: DRM device
2196 *
2197 * Take care of cleaning up after all DRM clients have exited. In the
2198 * mode setting case, we want to restore the kernel's initial mode (just
2199 * in case the last client left us in a bad state).
2200 *
2201 * Additionally, in the non-mode setting case, we'll tear down the AGP
2202 * and DMA structures, since the kernel won't be using them, and clea
2203 * up any GEM state.
2204 */
2205 void i915_driver_lastclose(struct drm_device * dev)
2206 {
2207 drm_i915_private_t *dev_priv = dev->dev_private;
2208
2209 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2210 intel_fb_restore_mode(dev);
2211 vga_switcheroo_process_delayed_switch();
2212 return;
2213 }
2214
2215 i915_gem_lastclose(dev);
2216
2217 if (dev_priv->agp_heap)
2218 i915_mem_takedown(&(dev_priv->agp_heap));
2219
2220 i915_dma_cleanup(dev);
2221 }
2222
2223 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2224 {
2225 drm_i915_private_t *dev_priv = dev->dev_private;
2226 i915_gem_release(dev, file_priv);
2227 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2228 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2229 }
2230
2231 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2232 {
2233 struct drm_i915_file_private *file_priv = file->driver_priv;
2234
2235 kfree(file_priv);
2236 }
2237
2238 struct drm_ioctl_desc i915_ioctls[] = {
2239 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2240 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2241 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2242 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2243 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2244 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2245 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2246 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2247 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2248 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2249 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2250 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2251 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2252 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2253 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2254 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2255 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2256 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2257 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2258 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2259 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2260 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2261 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2262 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2263 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2264 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2265 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2266 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2267 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2268 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2269 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2270 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2271 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2272 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2273 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2274 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2275 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2276 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2277 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2278 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2279 };
2280
2281 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2282
2283 /**
2284 * Determine if the device really is AGP or not.
2285 *
2286 * All Intel graphics chipsets are treated as AGP, even if they are really
2287 * PCI-e.
2288 *
2289 * \param dev The device to be tested.
2290 *
2291 * \returns
2292 * A value of 1 is always retured to indictate every i9x5 is AGP.
2293 */
2294 int i915_driver_device_is_agp(struct drm_device * dev)
2295 {
2296 return 1;
2297 }
kernel source for telekom puls (alcatel/mediatek)