2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
53 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
54 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
55 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
57 #ifdef CONFIG_DRM_AMDGPU_CIK
58 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
59 MODULE_FIRMWARE(FIRMWARE_KABINI
);
60 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
61 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
62 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
64 MODULE_FIRMWARE(FIRMWARE_TONGA
);
65 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
66 MODULE_FIRMWARE(FIRMWARE_FIJI
);
67 MODULE_FIRMWARE(FIRMWARE_STONEY
);
68 MODULE_FIRMWARE(FIRMWARE_POLARIS10
);
69 MODULE_FIRMWARE(FIRMWARE_POLARIS11
);
70 MODULE_FIRMWARE(FIRMWARE_POLARIS12
);
72 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
);
75 * amdgpu_vce_init - allocate memory, load vce firmware
77 * @adev: amdgpu_device pointer
79 * First step to get VCE online, allocate memory and load the firmware
81 int amdgpu_vce_sw_init(struct amdgpu_device
*adev
, unsigned long size
)
83 struct amdgpu_ring
*ring
;
84 struct amd_sched_rq
*rq
;
86 const struct common_firmware_header
*hdr
;
87 unsigned ucode_version
, version_major
, version_minor
, binary_id
;
90 switch (adev
->asic_type
) {
91 #ifdef CONFIG_DRM_AMDGPU_CIK
93 fw_name
= FIRMWARE_BONAIRE
;
96 fw_name
= FIRMWARE_KAVERI
;
99 fw_name
= FIRMWARE_KABINI
;
102 fw_name
= FIRMWARE_HAWAII
;
105 fw_name
= FIRMWARE_MULLINS
;
109 fw_name
= FIRMWARE_TONGA
;
112 fw_name
= FIRMWARE_CARRIZO
;
115 fw_name
= FIRMWARE_FIJI
;
118 fw_name
= FIRMWARE_STONEY
;
121 fw_name
= FIRMWARE_POLARIS10
;
124 fw_name
= FIRMWARE_POLARIS11
;
127 fw_name
= FIRMWARE_POLARIS12
;
134 r
= request_firmware(&adev
->vce
.fw
, fw_name
, adev
->dev
);
136 dev_err(adev
->dev
, "amdgpu_vce: Can't load firmware \"%s\"\n",
141 r
= amdgpu_ucode_validate(adev
->vce
.fw
);
143 dev_err(adev
->dev
, "amdgpu_vce: Can't validate firmware \"%s\"\n",
145 release_firmware(adev
->vce
.fw
);
150 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
152 ucode_version
= le32_to_cpu(hdr
->ucode_version
);
153 version_major
= (ucode_version
>> 20) & 0xfff;
154 version_minor
= (ucode_version
>> 8) & 0xfff;
155 binary_id
= ucode_version
& 0xff;
156 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
157 version_major
, version_minor
, binary_id
);
158 adev
->vce
.fw_version
= ((version_major
<< 24) | (version_minor
<< 16) |
161 /* allocate firmware, stack and heap BO */
163 r
= amdgpu_bo_create(adev
, size
, PAGE_SIZE
, true,
164 AMDGPU_GEM_DOMAIN_VRAM
,
165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
|
166 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
,
167 NULL
, NULL
, &adev
->vce
.vcpu_bo
);
169 dev_err(adev
->dev
, "(%d) failed to allocate VCE bo\n", r
);
173 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
175 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
176 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
180 r
= amdgpu_bo_pin(adev
->vce
.vcpu_bo
, AMDGPU_GEM_DOMAIN_VRAM
,
181 &adev
->vce
.gpu_addr
);
182 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
184 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
185 dev_err(adev
->dev
, "(%d) VCE bo pin failed\n", r
);
190 ring
= &adev
->vce
.ring
[0];
191 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
192 r
= amd_sched_entity_init(&ring
->sched
, &adev
->vce
.entity
,
193 rq
, amdgpu_sched_jobs
);
195 DRM_ERROR("Failed setting up VCE run queue.\n");
199 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
200 atomic_set(&adev
->vce
.handles
[i
], 0);
201 adev
->vce
.filp
[i
] = NULL
;
204 INIT_DELAYED_WORK(&adev
->vce
.idle_work
, amdgpu_vce_idle_work_handler
);
205 mutex_init(&adev
->vce
.idle_mutex
);
211 * amdgpu_vce_fini - free memory
213 * @adev: amdgpu_device pointer
215 * Last step on VCE teardown, free firmware memory
217 int amdgpu_vce_sw_fini(struct amdgpu_device
*adev
)
221 if (adev
->vce
.vcpu_bo
== NULL
)
224 amd_sched_entity_fini(&adev
->vce
.ring
[0].sched
, &adev
->vce
.entity
);
226 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
228 for (i
= 0; i
< adev
->vce
.num_rings
; i
++)
229 amdgpu_ring_fini(&adev
->vce
.ring
[i
]);
231 release_firmware(adev
->vce
.fw
);
232 mutex_destroy(&adev
->vce
.idle_mutex
);
238 * amdgpu_vce_suspend - unpin VCE fw memory
240 * @adev: amdgpu_device pointer
243 int amdgpu_vce_suspend(struct amdgpu_device
*adev
)
247 if (adev
->vce
.vcpu_bo
== NULL
)
250 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
251 if (atomic_read(&adev
->vce
.handles
[i
]))
254 if (i
== AMDGPU_MAX_VCE_HANDLES
)
257 cancel_delayed_work_sync(&adev
->vce
.idle_work
);
258 /* TODO: suspending running encoding sessions isn't supported */
263 * amdgpu_vce_resume - pin VCE fw memory
265 * @adev: amdgpu_device pointer
268 int amdgpu_vce_resume(struct amdgpu_device
*adev
)
271 const struct common_firmware_header
*hdr
;
275 if (adev
->vce
.vcpu_bo
== NULL
)
278 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
280 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
284 r
= amdgpu_bo_kmap(adev
->vce
.vcpu_bo
, &cpu_addr
);
286 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
287 dev_err(adev
->dev
, "(%d) VCE map failed\n", r
);
291 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
292 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
293 memcpy_toio(cpu_addr
, adev
->vce
.fw
->data
+ offset
,
294 adev
->vce
.fw
->size
- offset
);
296 amdgpu_bo_kunmap(adev
->vce
.vcpu_bo
);
298 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
304 * amdgpu_vce_idle_work_handler - power off VCE
306 * @work: pointer to work structure
308 * power of VCE when it's not used any more
310 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
)
312 struct amdgpu_device
*adev
=
313 container_of(work
, struct amdgpu_device
, vce
.idle_work
.work
);
314 unsigned i
, count
= 0;
316 for (i
= 0; i
< adev
->vce
.num_rings
; i
++)
317 count
+= amdgpu_fence_count_emitted(&adev
->vce
.ring
[i
]);
320 if (adev
->pm
.dpm_enabled
) {
321 amdgpu_dpm_enable_vce(adev
, false);
323 amdgpu_asic_set_vce_clocks(adev
, 0, 0);
326 schedule_delayed_work(&adev
->vce
.idle_work
, VCE_IDLE_TIMEOUT
);
331 * amdgpu_vce_ring_begin_use - power up VCE
335 * Make sure VCE is powerd up when we want to use it
337 void amdgpu_vce_ring_begin_use(struct amdgpu_ring
*ring
)
339 struct amdgpu_device
*adev
= ring
->adev
;
342 mutex_lock(&adev
->vce
.idle_mutex
);
343 set_clocks
= !cancel_delayed_work_sync(&adev
->vce
.idle_work
);
345 if (adev
->pm
.dpm_enabled
) {
346 amdgpu_dpm_enable_vce(adev
, true);
348 amdgpu_asic_set_vce_clocks(adev
, 53300, 40000);
351 mutex_unlock(&adev
->vce
.idle_mutex
);
355 * amdgpu_vce_ring_end_use - power VCE down
359 * Schedule work to power VCE down again
361 void amdgpu_vce_ring_end_use(struct amdgpu_ring
*ring
)
363 schedule_delayed_work(&ring
->adev
->vce
.idle_work
, VCE_IDLE_TIMEOUT
);
367 * amdgpu_vce_free_handles - free still open VCE handles
369 * @adev: amdgpu_device pointer
370 * @filp: drm file pointer
372 * Close all VCE handles still open by this file pointer
374 void amdgpu_vce_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
376 struct amdgpu_ring
*ring
= &adev
->vce
.ring
[0];
378 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
379 uint32_t handle
= atomic_read(&adev
->vce
.handles
[i
]);
381 if (!handle
|| adev
->vce
.filp
[i
] != filp
)
384 r
= amdgpu_vce_get_destroy_msg(ring
, handle
, false, NULL
);
386 DRM_ERROR("Error destroying VCE handle (%d)!\n", r
);
388 adev
->vce
.filp
[i
] = NULL
;
389 atomic_set(&adev
->vce
.handles
[i
], 0);
394 * amdgpu_vce_get_create_msg - generate a VCE create msg
396 * @adev: amdgpu_device pointer
397 * @ring: ring we should submit the msg to
398 * @handle: VCE session handle to use
399 * @fence: optional fence to return
401 * Open up a stream for HW test
403 int amdgpu_vce_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
404 struct dma_fence
**fence
)
406 const unsigned ib_size_dw
= 1024;
407 struct amdgpu_job
*job
;
408 struct amdgpu_ib
*ib
;
409 struct dma_fence
*f
= NULL
;
413 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
419 dummy
= ib
->gpu_addr
+ 1024;
421 /* stitch together an VCE create msg */
423 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
424 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
425 ib
->ptr
[ib
->length_dw
++] = handle
;
427 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52)
428 ib
->ptr
[ib
->length_dw
++] = 0x00000040; /* len */
430 ib
->ptr
[ib
->length_dw
++] = 0x00000030; /* len */
431 ib
->ptr
[ib
->length_dw
++] = 0x01000001; /* create cmd */
432 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
433 ib
->ptr
[ib
->length_dw
++] = 0x00000042;
434 ib
->ptr
[ib
->length_dw
++] = 0x0000000a;
435 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
436 ib
->ptr
[ib
->length_dw
++] = 0x00000080;
437 ib
->ptr
[ib
->length_dw
++] = 0x00000060;
438 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
439 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
440 ib
->ptr
[ib
->length_dw
++] = 0x0000000c;
441 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
442 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52) {
443 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
444 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
445 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
446 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
449 ib
->ptr
[ib
->length_dw
++] = 0x00000014; /* len */
450 ib
->ptr
[ib
->length_dw
++] = 0x05000005; /* feedback buffer */
451 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dummy
);
452 ib
->ptr
[ib
->length_dw
++] = dummy
;
453 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
455 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
458 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, NULL
, &f
);
459 job
->fence
= dma_fence_get(f
);
463 amdgpu_job_free(job
);
465 *fence
= dma_fence_get(f
);
470 amdgpu_job_free(job
);
475 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
477 * @adev: amdgpu_device pointer
478 * @ring: ring we should submit the msg to
479 * @handle: VCE session handle to use
480 * @fence: optional fence to return
482 * Close up a stream for HW test or if userspace failed to do so
484 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
485 bool direct
, struct dma_fence
**fence
)
487 const unsigned ib_size_dw
= 1024;
488 struct amdgpu_job
*job
;
489 struct amdgpu_ib
*ib
;
490 struct dma_fence
*f
= NULL
;
493 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
499 /* stitch together an VCE destroy msg */
501 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
502 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
503 ib
->ptr
[ib
->length_dw
++] = handle
;
505 ib
->ptr
[ib
->length_dw
++] = 0x00000020; /* len */
506 ib
->ptr
[ib
->length_dw
++] = 0x00000002; /* task info */
507 ib
->ptr
[ib
->length_dw
++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
508 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* destroy session */
509 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
510 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
511 ib
->ptr
[ib
->length_dw
++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
512 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
514 ib
->ptr
[ib
->length_dw
++] = 0x00000008; /* len */
515 ib
->ptr
[ib
->length_dw
++] = 0x02000001; /* destroy cmd */
517 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
521 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, NULL
, &f
);
522 job
->fence
= dma_fence_get(f
);
526 amdgpu_job_free(job
);
528 r
= amdgpu_job_submit(job
, ring
, &ring
->adev
->vce
.entity
,
529 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
535 *fence
= dma_fence_get(f
);
540 amdgpu_job_free(job
);
545 * amdgpu_vce_cs_reloc - command submission relocation
548 * @lo: address of lower dword
549 * @hi: address of higher dword
550 * @size: minimum size
552 * Patch relocation inside command stream with real buffer address
554 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
,
555 int lo
, int hi
, unsigned size
, uint32_t index
)
557 struct amdgpu_bo_va_mapping
*mapping
;
558 struct amdgpu_bo
*bo
;
561 if (index
== 0xffffffff)
564 addr
= ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, lo
)) |
565 ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, hi
)) << 32;
566 addr
+= ((uint64_t)size
) * ((uint64_t)index
);
568 mapping
= amdgpu_cs_find_mapping(p
, addr
, &bo
);
569 if (mapping
== NULL
) {
570 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
571 addr
, lo
, hi
, size
, index
);
575 if ((addr
+ (uint64_t)size
) >
576 ((uint64_t)mapping
->it
.last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
577 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
582 addr
-= ((uint64_t)mapping
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
583 addr
+= amdgpu_bo_gpu_offset(bo
);
584 addr
-= ((uint64_t)size
) * ((uint64_t)index
);
586 amdgpu_set_ib_value(p
, ib_idx
, lo
, lower_32_bits(addr
));
587 amdgpu_set_ib_value(p
, ib_idx
, hi
, upper_32_bits(addr
));
593 * amdgpu_vce_validate_handle - validate stream handle
596 * @handle: handle to validate
597 * @allocated: allocated a new handle?
599 * Validates the handle and return the found session index or -EINVAL
600 * we we don't have another free session index.
602 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser
*p
,
603 uint32_t handle
, uint32_t *allocated
)
607 /* validate the handle */
608 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
609 if (atomic_read(&p
->adev
->vce
.handles
[i
]) == handle
) {
610 if (p
->adev
->vce
.filp
[i
] != p
->filp
) {
611 DRM_ERROR("VCE handle collision detected!\n");
618 /* handle not found try to alloc a new one */
619 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
620 if (!atomic_cmpxchg(&p
->adev
->vce
.handles
[i
], 0, handle
)) {
621 p
->adev
->vce
.filp
[i
] = p
->filp
;
622 p
->adev
->vce
.img_size
[i
] = 0;
623 *allocated
|= 1 << i
;
628 DRM_ERROR("No more free VCE handles!\n");
633 * amdgpu_vce_cs_parse - parse and validate the command stream
638 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
)
640 struct amdgpu_ib
*ib
= &p
->job
->ibs
[ib_idx
];
641 unsigned fb_idx
= 0, bs_idx
= 0;
642 int session_idx
= -1;
643 uint32_t destroyed
= 0;
644 uint32_t created
= 0;
645 uint32_t allocated
= 0;
646 uint32_t tmp
, handle
= 0;
647 uint32_t *size
= &tmp
;
651 ib
->gpu_addr
= amdgpu_sa_bo_gpu_addr(ib
->sa_bo
);
653 r
= amdgpu_cs_sysvm_access_required(p
);
657 while (idx
< ib
->length_dw
) {
658 uint32_t len
= amdgpu_get_ib_value(p
, ib_idx
, idx
);
659 uint32_t cmd
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 1);
661 if ((len
< 8) || (len
& 3)) {
662 DRM_ERROR("invalid VCE command length (%d)!\n", len
);
668 case 0x00000001: /* session */
669 handle
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 2);
670 session_idx
= amdgpu_vce_validate_handle(p
, handle
,
672 if (session_idx
< 0) {
676 size
= &p
->adev
->vce
.img_size
[session_idx
];
679 case 0x00000002: /* task info */
680 fb_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 6);
681 bs_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 7);
684 case 0x01000001: /* create */
685 created
|= 1 << session_idx
;
686 if (destroyed
& (1 << session_idx
)) {
687 destroyed
&= ~(1 << session_idx
);
688 allocated
|= 1 << session_idx
;
690 } else if (!(allocated
& (1 << session_idx
))) {
691 DRM_ERROR("Handle already in use!\n");
696 *size
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 8) *
697 amdgpu_get_ib_value(p
, ib_idx
, idx
+ 10) *
701 case 0x04000001: /* config extension */
702 case 0x04000002: /* pic control */
703 case 0x04000005: /* rate control */
704 case 0x04000007: /* motion estimation */
705 case 0x04000008: /* rdo */
706 case 0x04000009: /* vui */
707 case 0x05000002: /* auxiliary buffer */
708 case 0x05000009: /* clock table */
711 case 0x0500000c: /* hw config */
712 switch (p
->adev
->asic_type
) {
713 #ifdef CONFIG_DRM_AMDGPU_CIK
725 case 0x03000001: /* encode */
726 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 10, idx
+ 9,
731 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 12, idx
+ 11,
737 case 0x02000001: /* destroy */
738 destroyed
|= 1 << session_idx
;
741 case 0x05000001: /* context buffer */
742 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
748 case 0x05000004: /* video bitstream buffer */
749 tmp
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 4);
750 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
756 case 0x05000005: /* feedback buffer */
757 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
764 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd
);
769 if (session_idx
== -1) {
770 DRM_ERROR("no session command at start of IB\n");
778 if (allocated
& ~created
) {
779 DRM_ERROR("New session without create command!\n");
785 /* No error, free all destroyed handle slots */
788 /* Error during parsing, free all allocated handle slots */
792 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
794 atomic_set(&p
->adev
->vce
.handles
[i
], 0);
800 * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode
805 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
)
807 struct amdgpu_ib
*ib
= &p
->job
->ibs
[ib_idx
];
808 int session_idx
= -1;
809 uint32_t destroyed
= 0;
810 uint32_t created
= 0;
811 uint32_t allocated
= 0;
812 uint32_t tmp
, handle
= 0;
813 int i
, r
= 0, idx
= 0;
815 while (idx
< ib
->length_dw
) {
816 uint32_t len
= amdgpu_get_ib_value(p
, ib_idx
, idx
);
817 uint32_t cmd
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 1);
819 if ((len
< 8) || (len
& 3)) {
820 DRM_ERROR("invalid VCE command length (%d)!\n", len
);
826 case 0x00000001: /* session */
827 handle
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 2);
828 session_idx
= amdgpu_vce_validate_handle(p
, handle
,
830 if (session_idx
< 0) {
836 case 0x01000001: /* create */
837 created
|= 1 << session_idx
;
838 if (destroyed
& (1 << session_idx
)) {
839 destroyed
&= ~(1 << session_idx
);
840 allocated
|= 1 << session_idx
;
842 } else if (!(allocated
& (1 << session_idx
))) {
843 DRM_ERROR("Handle already in use!\n");
850 case 0x02000001: /* destroy */
851 destroyed
|= 1 << session_idx
;
858 if (session_idx
== -1) {
859 DRM_ERROR("no session command at start of IB\n");
867 if (allocated
& ~created
) {
868 DRM_ERROR("New session without create command!\n");
874 /* No error, free all destroyed handle slots */
876 amdgpu_ib_free(p
->adev
, ib
, NULL
);
878 /* Error during parsing, free all allocated handle slots */
882 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
884 atomic_set(&p
->adev
->vce
.handles
[i
], 0);
890 * amdgpu_vce_ring_emit_ib - execute indirect buffer
892 * @ring: engine to use
893 * @ib: the IB to execute
896 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
,
897 unsigned vm_id
, bool ctx_switch
)
899 amdgpu_ring_write(ring
, VCE_CMD_IB
);
900 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
));
901 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
902 amdgpu_ring_write(ring
, ib
->length_dw
);
906 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
908 * @ring: engine to use
912 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
915 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
917 amdgpu_ring_write(ring
, VCE_CMD_FENCE
);
918 amdgpu_ring_write(ring
, addr
);
919 amdgpu_ring_write(ring
, upper_32_bits(addr
));
920 amdgpu_ring_write(ring
, seq
);
921 amdgpu_ring_write(ring
, VCE_CMD_TRAP
);
922 amdgpu_ring_write(ring
, VCE_CMD_END
);
926 * amdgpu_vce_ring_test_ring - test if VCE ring is working
928 * @ring: the engine to test on
931 int amdgpu_vce_ring_test_ring(struct amdgpu_ring
*ring
)
933 struct amdgpu_device
*adev
= ring
->adev
;
934 uint32_t rptr
= amdgpu_ring_get_rptr(ring
);
938 r
= amdgpu_ring_alloc(ring
, 16);
940 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
944 amdgpu_ring_write(ring
, VCE_CMD_END
);
945 amdgpu_ring_commit(ring
);
947 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
948 if (amdgpu_ring_get_rptr(ring
) != rptr
)
953 if (i
< adev
->usec_timeout
) {
954 DRM_INFO("ring test on %d succeeded in %d usecs\n",
957 DRM_ERROR("amdgpu: ring %d test failed\n",
966 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
968 * @ring: the engine to test on
971 int amdgpu_vce_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
973 struct dma_fence
*fence
= NULL
;
976 /* skip vce ring1/2 ib test for now, since it's not reliable */
977 if (ring
!= &ring
->adev
->vce
.ring
[0])
980 r
= amdgpu_vce_get_create_msg(ring
, 1, NULL
);
982 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r
);
986 r
= amdgpu_vce_get_destroy_msg(ring
, 1, true, &fence
);
988 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r
);
992 r
= dma_fence_wait_timeout(fence
, false, timeout
);
994 DRM_ERROR("amdgpu: IB test timed out.\n");
997 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
999 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
1003 dma_fence_put(fence
);