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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
1 /**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8 /*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32 #include <drm/drmP.h>
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_gem.h>
35 #include "amdgpu_drv.h"
36
37 #include <drm/drm_pciids.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include <drm/drm_crtc_helper.h>
43
44 #include "amdgpu.h"
45 #include "amdgpu_irq.h"
46
47 #include "amdgpu_amdkfd.h"
48
49 /*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
55 * - 3.3.0 - Add VM support for UVD on supported hardware.
56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
57 * - 3.5.0 - Add support for new UVD_NO_OP register.
58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
59 * - 3.7.0 - Add support for VCE clock list packet
60 * - 3.8.0 - Add support raster config init in the kernel
61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
64 * - 3.12.0 - Add query for double offchip LDS buffers
65 * - 3.13.0 - Add PRT support
66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
67 * - 3.15.0 - Export more gpu info for gfx9
68 * - 3.16.0 - Add reserved vmid support
69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
70 * - 3.18.0 - Export gpu always on cu bitmap
71 * - 3.19.0 - Add support for UVD MJPEG decode
72 */
73 #define KMS_DRIVER_MAJOR 3
74 #define KMS_DRIVER_MINOR 19
75 #define KMS_DRIVER_PATCHLEVEL 0
76
77 int amdgpu_vram_limit = 0;
78 int amdgpu_vis_vram_limit = 0;
79 int amdgpu_gart_size = -1; /* auto */
80 int amdgpu_gtt_size = -1; /* auto */
81 int amdgpu_moverate = -1; /* auto */
82 int amdgpu_benchmarking = 0;
83 int amdgpu_testing = 0;
84 int amdgpu_audio = -1;
85 int amdgpu_disp_priority = 0;
86 int amdgpu_hw_i2c = 0;
87 int amdgpu_pcie_gen2 = -1;
88 int amdgpu_msi = -1;
89 int amdgpu_lockup_timeout = 0;
90 int amdgpu_dpm = -1;
91 int amdgpu_fw_load_type = -1;
92 int amdgpu_aspm = -1;
93 int amdgpu_runtime_pm = -1;
94 unsigned amdgpu_ip_block_mask = 0xffffffff;
95 int amdgpu_bapm = -1;
96 int amdgpu_deep_color = 0;
97 int amdgpu_vm_size = -1;
98 int amdgpu_vm_fragment_size = -1;
99 int amdgpu_vm_block_size = -1;
100 int amdgpu_vm_fault_stop = 0;
101 int amdgpu_vm_debug = 0;
102 int amdgpu_vram_page_split = 512;
103 int amdgpu_vm_update_mode = -1;
104 int amdgpu_exp_hw_support = 0;
105 int amdgpu_sched_jobs = 32;
106 int amdgpu_sched_hw_submission = 2;
107 int amdgpu_no_evict = 0;
108 int amdgpu_direct_gma_size = 0;
109 unsigned amdgpu_pcie_gen_cap = 0;
110 unsigned amdgpu_pcie_lane_cap = 0;
111 unsigned amdgpu_cg_mask = 0xffffffff;
112 unsigned amdgpu_pg_mask = 0xffffffff;
113 unsigned amdgpu_sdma_phase_quantum = 32;
114 char *amdgpu_disable_cu = NULL;
115 char *amdgpu_virtual_display = NULL;
116 unsigned amdgpu_pp_feature_mask = 0xffffffff;
117 int amdgpu_ngg = 0;
118 int amdgpu_prim_buf_per_se = 0;
119 int amdgpu_pos_buf_per_se = 0;
120 int amdgpu_cntl_sb_buf_per_se = 0;
121 int amdgpu_param_buf_per_se = 0;
122 int amdgpu_job_hang_limit = 0;
123 int amdgpu_lbpw = -1;
124
125 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
126 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
127
128 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
129 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
130
131 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
132 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
133
134 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
135 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
136
137 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
138 module_param_named(moverate, amdgpu_moverate, int, 0600);
139
140 MODULE_PARM_DESC(benchmark, "Run benchmark");
141 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
142
143 MODULE_PARM_DESC(test, "Run tests");
144 module_param_named(test, amdgpu_testing, int, 0444);
145
146 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
147 module_param_named(audio, amdgpu_audio, int, 0444);
148
149 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
150 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
151
152 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
153 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
154
155 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
156 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
157
158 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
159 module_param_named(msi, amdgpu_msi, int, 0444);
160
161 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
162 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
163
164 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
165 module_param_named(dpm, amdgpu_dpm, int, 0444);
166
167 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
168 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
169
170 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
171 module_param_named(aspm, amdgpu_aspm, int, 0444);
172
173 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
174 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
175
176 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
177 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
178
179 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
180 module_param_named(bapm, amdgpu_bapm, int, 0444);
181
182 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
183 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
184
185 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
186 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
187
188 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
189 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
190
191 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
192 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
193
194 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
195 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
196
197 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
198 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
199
200 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
201 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
202
203 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
204 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
205
206 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
207 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
208
209 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
210 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
211
212 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
213 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
214
215 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
216 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
217
218 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
219 module_param_named(no_evict, amdgpu_no_evict, int, 0444);
220
221 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
222 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
223
224 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
225 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
226
227 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
228 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
229
230 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
231 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
232
233 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
234 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
235
236 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
237 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
238
239 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
240 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
241
242 MODULE_PARM_DESC(virtual_display,
243 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
244 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
245
246 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
247 module_param_named(ngg, amdgpu_ngg, int, 0444);
248
249 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
250 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
251
252 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
253 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
254
255 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
256 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
257
258 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
259 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
260
261 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
262 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
263
264 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
265 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
266
267 #ifdef CONFIG_DRM_AMDGPU_SI
268
269 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
270 int amdgpu_si_support = 0;
271 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
272 #else
273 int amdgpu_si_support = 1;
274 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
275 #endif
276
277 module_param_named(si_support, amdgpu_si_support, int, 0444);
278 #endif
279
280 #ifdef CONFIG_DRM_AMDGPU_CIK
281
282 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
283 int amdgpu_cik_support = 0;
284 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
285 #else
286 int amdgpu_cik_support = 1;
287 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
288 #endif
289
290 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
291 #endif
292
293
294 static const struct pci_device_id pciidlist[] = {
295 #ifdef CONFIG_DRM_AMDGPU_SI
296 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
297 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
298 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
299 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
300 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
301 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
302 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
303 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
304 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
305 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
306 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
307 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
308 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
309 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
310 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
311 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
312 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
313 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
314 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
315 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
316 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
317 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
318 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
319 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
320 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
321 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
322 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
323 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
324 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
325 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
326 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
327 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
328 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
329 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
330 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
331 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
332 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
333 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
334 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
335 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
336 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
337 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
338 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
339 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
340 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
341 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
342 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
343 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
344 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
345 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
346 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
347 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
348 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
349 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
350 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
351 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
352 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
353 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
354 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
355 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
356 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
357 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
358 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
359 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
360 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
361 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
362 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
363 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
364 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
365 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
366 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
367 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
368 #endif
369 #ifdef CONFIG_DRM_AMDGPU_CIK
370 /* Kaveri */
371 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
372 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
373 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
374 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
375 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
376 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
377 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
378 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
379 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
380 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
381 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
382 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
383 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
384 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
385 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
386 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
387 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
388 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
389 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
390 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
391 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
392 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
393 /* Bonaire */
394 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
395 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
396 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
397 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
398 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
399 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
400 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
401 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
402 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
403 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
404 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
405 /* Hawaii */
406 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
407 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
408 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
409 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
410 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
411 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
412 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
413 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
414 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
415 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
416 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
417 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
418 /* Kabini */
419 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
420 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
421 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
422 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
423 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
424 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
425 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
426 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
427 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
428 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
429 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
430 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
431 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
432 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
433 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
434 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
435 /* mullins */
436 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
437 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
438 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
439 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
440 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
441 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
442 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
443 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
444 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
445 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
446 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
447 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
448 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
449 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
450 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
451 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
452 #endif
453 /* topaz */
454 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
455 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
456 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
457 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
458 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
459 /* tonga */
460 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
461 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
462 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
463 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
464 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
465 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
466 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
467 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
468 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
469 /* fiji */
470 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
471 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
472 /* carrizo */
473 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
474 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
475 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
476 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
477 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
478 /* stoney */
479 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
480 /* Polaris11 */
481 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
482 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
483 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
484 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
485 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
486 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
487 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
488 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
489 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
490 /* Polaris10 */
491 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
492 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
493 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
494 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
495 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
496 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
497 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
498 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
499 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
500 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
501 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
502 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
503 /* Polaris12 */
504 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
505 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
506 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
507 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
508 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
509 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
510 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
511 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
512 /* Vega 10 */
513 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
514 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
515 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
516 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
517 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
518 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
519 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
520 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
521 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
522 /* Raven */
523 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
524
525 {0, 0, 0}
526 };
527
528 MODULE_DEVICE_TABLE(pci, pciidlist);
529
530 static struct drm_driver kms_driver;
531
532 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
533 {
534 struct apertures_struct *ap;
535 bool primary = false;
536
537 ap = alloc_apertures(1);
538 if (!ap)
539 return -ENOMEM;
540
541 ap->ranges[0].base = pci_resource_start(pdev, 0);
542 ap->ranges[0].size = pci_resource_len(pdev, 0);
543
544 #ifdef CONFIG_X86
545 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
546 #endif
547 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
548 kfree(ap);
549
550 return 0;
551 }
552
553 static int amdgpu_pci_probe(struct pci_dev *pdev,
554 const struct pci_device_id *ent)
555 {
556 struct drm_device *dev;
557 unsigned long flags = ent->driver_data;
558 int ret;
559
560 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
561 DRM_INFO("This hardware requires experimental hardware support.\n"
562 "See modparam exp_hw_support\n");
563 return -ENODEV;
564 }
565
566 /*
567 * Initialize amdkfd before starting radeon. If it was not loaded yet,
568 * defer radeon probing
569 */
570 ret = amdgpu_amdkfd_init();
571 if (ret == -EPROBE_DEFER)
572 return ret;
573
574 /* Get rid of things like offb */
575 ret = amdgpu_kick_out_firmware_fb(pdev);
576 if (ret)
577 return ret;
578
579 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
580 if (IS_ERR(dev))
581 return PTR_ERR(dev);
582
583 ret = pci_enable_device(pdev);
584 if (ret)
585 goto err_free;
586
587 dev->pdev = pdev;
588
589 pci_set_drvdata(pdev, dev);
590
591 ret = drm_dev_register(dev, ent->driver_data);
592 if (ret)
593 goto err_pci;
594
595 return 0;
596
597 err_pci:
598 pci_disable_device(pdev);
599 err_free:
600 drm_dev_unref(dev);
601 return ret;
602 }
603
604 static void
605 amdgpu_pci_remove(struct pci_dev *pdev)
606 {
607 struct drm_device *dev = pci_get_drvdata(pdev);
608
609 drm_dev_unregister(dev);
610 drm_dev_unref(dev);
611 }
612
613 static void
614 amdgpu_pci_shutdown(struct pci_dev *pdev)
615 {
616 struct drm_device *dev = pci_get_drvdata(pdev);
617 struct amdgpu_device *adev = dev->dev_private;
618
619 /* if we are running in a VM, make sure the device
620 * torn down properly on reboot/shutdown.
621 * unfortunately we can't detect certain
622 * hypervisors so just do this all the time.
623 */
624 amdgpu_suspend(adev);
625 }
626
627 static int amdgpu_pmops_suspend(struct device *dev)
628 {
629 struct pci_dev *pdev = to_pci_dev(dev);
630
631 struct drm_device *drm_dev = pci_get_drvdata(pdev);
632 return amdgpu_device_suspend(drm_dev, true, true);
633 }
634
635 static int amdgpu_pmops_resume(struct device *dev)
636 {
637 struct pci_dev *pdev = to_pci_dev(dev);
638 struct drm_device *drm_dev = pci_get_drvdata(pdev);
639
640 /* GPU comes up enabled by the bios on resume */
641 if (amdgpu_device_is_px(drm_dev)) {
642 pm_runtime_disable(dev);
643 pm_runtime_set_active(dev);
644 pm_runtime_enable(dev);
645 }
646
647 return amdgpu_device_resume(drm_dev, true, true);
648 }
649
650 static int amdgpu_pmops_freeze(struct device *dev)
651 {
652 struct pci_dev *pdev = to_pci_dev(dev);
653
654 struct drm_device *drm_dev = pci_get_drvdata(pdev);
655 return amdgpu_device_suspend(drm_dev, false, true);
656 }
657
658 static int amdgpu_pmops_thaw(struct device *dev)
659 {
660 struct pci_dev *pdev = to_pci_dev(dev);
661
662 struct drm_device *drm_dev = pci_get_drvdata(pdev);
663 return amdgpu_device_resume(drm_dev, false, true);
664 }
665
666 static int amdgpu_pmops_poweroff(struct device *dev)
667 {
668 struct pci_dev *pdev = to_pci_dev(dev);
669
670 struct drm_device *drm_dev = pci_get_drvdata(pdev);
671 return amdgpu_device_suspend(drm_dev, true, true);
672 }
673
674 static int amdgpu_pmops_restore(struct device *dev)
675 {
676 struct pci_dev *pdev = to_pci_dev(dev);
677
678 struct drm_device *drm_dev = pci_get_drvdata(pdev);
679 return amdgpu_device_resume(drm_dev, false, true);
680 }
681
682 static int amdgpu_pmops_runtime_suspend(struct device *dev)
683 {
684 struct pci_dev *pdev = to_pci_dev(dev);
685 struct drm_device *drm_dev = pci_get_drvdata(pdev);
686 int ret;
687
688 if (!amdgpu_device_is_px(drm_dev)) {
689 pm_runtime_forbid(dev);
690 return -EBUSY;
691 }
692
693 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
694 drm_kms_helper_poll_disable(drm_dev);
695 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
696
697 ret = amdgpu_device_suspend(drm_dev, false, false);
698 pci_save_state(pdev);
699 pci_disable_device(pdev);
700 pci_ignore_hotplug(pdev);
701 if (amdgpu_is_atpx_hybrid())
702 pci_set_power_state(pdev, PCI_D3cold);
703 else if (!amdgpu_has_atpx_dgpu_power_cntl())
704 pci_set_power_state(pdev, PCI_D3hot);
705 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
706
707 return 0;
708 }
709
710 static int amdgpu_pmops_runtime_resume(struct device *dev)
711 {
712 struct pci_dev *pdev = to_pci_dev(dev);
713 struct drm_device *drm_dev = pci_get_drvdata(pdev);
714 int ret;
715
716 if (!amdgpu_device_is_px(drm_dev))
717 return -EINVAL;
718
719 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
720
721 if (amdgpu_is_atpx_hybrid() ||
722 !amdgpu_has_atpx_dgpu_power_cntl())
723 pci_set_power_state(pdev, PCI_D0);
724 pci_restore_state(pdev);
725 ret = pci_enable_device(pdev);
726 if (ret)
727 return ret;
728 pci_set_master(pdev);
729
730 ret = amdgpu_device_resume(drm_dev, false, false);
731 drm_kms_helper_poll_enable(drm_dev);
732 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
733 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
734 return 0;
735 }
736
737 static int amdgpu_pmops_runtime_idle(struct device *dev)
738 {
739 struct pci_dev *pdev = to_pci_dev(dev);
740 struct drm_device *drm_dev = pci_get_drvdata(pdev);
741 struct drm_crtc *crtc;
742
743 if (!amdgpu_device_is_px(drm_dev)) {
744 pm_runtime_forbid(dev);
745 return -EBUSY;
746 }
747
748 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
749 if (crtc->enabled) {
750 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
751 return -EBUSY;
752 }
753 }
754
755 pm_runtime_mark_last_busy(dev);
756 pm_runtime_autosuspend(dev);
757 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
758 return 1;
759 }
760
761 long amdgpu_drm_ioctl(struct file *filp,
762 unsigned int cmd, unsigned long arg)
763 {
764 struct drm_file *file_priv = filp->private_data;
765 struct drm_device *dev;
766 long ret;
767 dev = file_priv->minor->dev;
768 ret = pm_runtime_get_sync(dev->dev);
769 if (ret < 0)
770 return ret;
771
772 ret = drm_ioctl(filp, cmd, arg);
773
774 pm_runtime_mark_last_busy(dev->dev);
775 pm_runtime_put_autosuspend(dev->dev);
776 return ret;
777 }
778
779 static const struct dev_pm_ops amdgpu_pm_ops = {
780 .suspend = amdgpu_pmops_suspend,
781 .resume = amdgpu_pmops_resume,
782 .freeze = amdgpu_pmops_freeze,
783 .thaw = amdgpu_pmops_thaw,
784 .poweroff = amdgpu_pmops_poweroff,
785 .restore = amdgpu_pmops_restore,
786 .runtime_suspend = amdgpu_pmops_runtime_suspend,
787 .runtime_resume = amdgpu_pmops_runtime_resume,
788 .runtime_idle = amdgpu_pmops_runtime_idle,
789 };
790
791 static const struct file_operations amdgpu_driver_kms_fops = {
792 .owner = THIS_MODULE,
793 .open = drm_open,
794 .release = drm_release,
795 .unlocked_ioctl = amdgpu_drm_ioctl,
796 .mmap = amdgpu_mmap,
797 .poll = drm_poll,
798 .read = drm_read,
799 #ifdef CONFIG_COMPAT
800 .compat_ioctl = amdgpu_kms_compat_ioctl,
801 #endif
802 };
803
804 static bool
805 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
806 bool in_vblank_irq, int *vpos, int *hpos,
807 ktime_t *stime, ktime_t *etime,
808 const struct drm_display_mode *mode)
809 {
810 return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
811 stime, etime, mode);
812 }
813
814 static struct drm_driver kms_driver = {
815 .driver_features =
816 DRIVER_USE_AGP |
817 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
818 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
819 .load = amdgpu_driver_load_kms,
820 .open = amdgpu_driver_open_kms,
821 .postclose = amdgpu_driver_postclose_kms,
822 .lastclose = amdgpu_driver_lastclose_kms,
823 .unload = amdgpu_driver_unload_kms,
824 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
825 .enable_vblank = amdgpu_enable_vblank_kms,
826 .disable_vblank = amdgpu_disable_vblank_kms,
827 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
828 .get_scanout_position = amdgpu_get_crtc_scanout_position,
829 #if defined(CONFIG_DEBUG_FS)
830 .debugfs_init = amdgpu_debugfs_init,
831 #endif
832 .irq_preinstall = amdgpu_irq_preinstall,
833 .irq_postinstall = amdgpu_irq_postinstall,
834 .irq_uninstall = amdgpu_irq_uninstall,
835 .irq_handler = amdgpu_irq_handler,
836 .ioctls = amdgpu_ioctls_kms,
837 .gem_free_object_unlocked = amdgpu_gem_object_free,
838 .gem_open_object = amdgpu_gem_object_open,
839 .gem_close_object = amdgpu_gem_object_close,
840 .dumb_create = amdgpu_mode_dumb_create,
841 .dumb_map_offset = amdgpu_mode_dumb_mmap,
842 .fops = &amdgpu_driver_kms_fops,
843
844 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
845 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
846 .gem_prime_export = amdgpu_gem_prime_export,
847 .gem_prime_import = drm_gem_prime_import,
848 .gem_prime_pin = amdgpu_gem_prime_pin,
849 .gem_prime_unpin = amdgpu_gem_prime_unpin,
850 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
851 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
852 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
853 .gem_prime_vmap = amdgpu_gem_prime_vmap,
854 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
855
856 .name = DRIVER_NAME,
857 .desc = DRIVER_DESC,
858 .date = DRIVER_DATE,
859 .major = KMS_DRIVER_MAJOR,
860 .minor = KMS_DRIVER_MINOR,
861 .patchlevel = KMS_DRIVER_PATCHLEVEL,
862 };
863
864 static struct drm_driver *driver;
865 static struct pci_driver *pdriver;
866
867 static struct pci_driver amdgpu_kms_pci_driver = {
868 .name = DRIVER_NAME,
869 .id_table = pciidlist,
870 .probe = amdgpu_pci_probe,
871 .remove = amdgpu_pci_remove,
872 .shutdown = amdgpu_pci_shutdown,
873 .driver.pm = &amdgpu_pm_ops,
874 };
875
876
877
878 static int __init amdgpu_init(void)
879 {
880 int r;
881
882 r = amdgpu_sync_init();
883 if (r)
884 goto error_sync;
885
886 r = amdgpu_fence_slab_init();
887 if (r)
888 goto error_fence;
889
890 r = amd_sched_fence_slab_init();
891 if (r)
892 goto error_sched;
893
894 if (vgacon_text_force()) {
895 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
896 return -EINVAL;
897 }
898 DRM_INFO("amdgpu kernel modesetting enabled.\n");
899 driver = &kms_driver;
900 pdriver = &amdgpu_kms_pci_driver;
901 driver->num_ioctls = amdgpu_max_kms_ioctl;
902 amdgpu_register_atpx_handler();
903 /* let modprobe override vga console setting */
904 return pci_register_driver(pdriver);
905
906 error_sched:
907 amdgpu_fence_slab_fini();
908
909 error_fence:
910 amdgpu_sync_fini();
911
912 error_sync:
913 return r;
914 }
915
916 static void __exit amdgpu_exit(void)
917 {
918 amdgpu_amdkfd_fini();
919 pci_unregister_driver(pdriver);
920 amdgpu_unregister_atpx_handler();
921 amdgpu_sync_fini();
922 amd_sched_fence_slab_fini();
923 amdgpu_fence_slab_fini();
924 }
925
926 module_init(amdgpu_init);
927 module_exit(amdgpu_exit);
928
929 MODULE_AUTHOR(DRIVER_AUTHOR);
930 MODULE_DESCRIPTION(DRIVER_DESC);
931 MODULE_LICENSE("GPL and additional rights");