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Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55
56 #include "gpu_scheduler.h"
57
58 /*
59 * Modules parameters.
60 */
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_vm_fault_stop;
83 extern int amdgpu_vm_debug;
84 extern int amdgpu_enable_scheduler;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_enable_semaphores;
88
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
97
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
103
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
106
107 /* number of hw syncs before falling back on blocking */
108 #define AMDGPU_NUM_SYNCS 4
109
110 /* hardcode that limit for now */
111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112
113 /* hard reset data */
114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
115
116 /* reset flags */
117 #define AMDGPU_RESET_GFX (1 << 0)
118 #define AMDGPU_RESET_COMPUTE (1 << 1)
119 #define AMDGPU_RESET_DMA (1 << 2)
120 #define AMDGPU_RESET_CP (1 << 3)
121 #define AMDGPU_RESET_GRBM (1 << 4)
122 #define AMDGPU_RESET_DMA1 (1 << 5)
123 #define AMDGPU_RESET_RLC (1 << 6)
124 #define AMDGPU_RESET_SEM (1 << 7)
125 #define AMDGPU_RESET_IH (1 << 8)
126 #define AMDGPU_RESET_VMC (1 << 9)
127 #define AMDGPU_RESET_MC (1 << 10)
128 #define AMDGPU_RESET_DISPLAY (1 << 11)
129 #define AMDGPU_RESET_UVD (1 << 12)
130 #define AMDGPU_RESET_VCE (1 << 13)
131 #define AMDGPU_RESET_VCE1 (1 << 14)
132
133 /* CG block flags */
134 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
135 #define AMDGPU_CG_BLOCK_MC (1 << 1)
136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
138 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
139 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
140 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
141
142 /* CG flags */
143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
160
161 /* PG flags */
162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173
174 /* GFX current status */
175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181 /* max cursor sizes (in pixels) */
182 #define CIK_CURSOR_WIDTH 128
183 #define CIK_CURSOR_HEIGHT 128
184
185 struct amdgpu_device;
186 struct amdgpu_fence;
187 struct amdgpu_ib;
188 struct amdgpu_vm;
189 struct amdgpu_ring;
190 struct amdgpu_semaphore;
191 struct amdgpu_cs_parser;
192 struct amdgpu_job;
193 struct amdgpu_irq_src;
194 struct amdgpu_fpriv;
195
196 enum amdgpu_cp_irq {
197 AMDGPU_CP_IRQ_GFX_EOP = 0,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
206
207 AMDGPU_CP_IRQ_LAST
208 };
209
210 enum amdgpu_sdma_irq {
211 AMDGPU_SDMA_IRQ_TRAP0 = 0,
212 AMDGPU_SDMA_IRQ_TRAP1,
213
214 AMDGPU_SDMA_IRQ_LAST
215 };
216
217 enum amdgpu_thermal_irq {
218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
220
221 AMDGPU_THERMAL_IRQ_LAST
222 };
223
224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type,
226 enum amd_clockgating_state state);
227 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type,
229 enum amd_powergating_state state);
230
231 struct amdgpu_ip_block_version {
232 enum amd_ip_block_type type;
233 u32 major;
234 u32 minor;
235 u32 rev;
236 const struct amd_ip_funcs *funcs;
237 };
238
239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
240 enum amd_ip_block_type type,
241 u32 major, u32 minor);
242
243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
244 struct amdgpu_device *adev,
245 enum amd_ip_block_type type);
246
247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
248 struct amdgpu_buffer_funcs {
249 /* maximum bytes in a single operation */
250 uint32_t copy_max_bytes;
251
252 /* number of dw to reserve per operation */
253 unsigned copy_num_dw;
254
255 /* used for buffer migration */
256 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
257 /* src addr in bytes */
258 uint64_t src_offset,
259 /* dst addr in bytes */
260 uint64_t dst_offset,
261 /* number of byte to transfer */
262 uint32_t byte_count);
263
264 /* maximum bytes in a single operation */
265 uint32_t fill_max_bytes;
266
267 /* number of dw to reserve per operation */
268 unsigned fill_num_dw;
269
270 /* used for buffer clearing */
271 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
272 /* value to write to memory */
273 uint32_t src_data,
274 /* dst addr in bytes */
275 uint64_t dst_offset,
276 /* number of byte to fill */
277 uint32_t byte_count);
278 };
279
280 /* provided by hw blocks that can write ptes, e.g., sdma */
281 struct amdgpu_vm_pte_funcs {
282 /* copy pte entries from GART */
283 void (*copy_pte)(struct amdgpu_ib *ib,
284 uint64_t pe, uint64_t src,
285 unsigned count);
286 /* write pte one entry at a time with addr mapping */
287 void (*write_pte)(struct amdgpu_ib *ib,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
290 uint32_t incr, uint32_t flags);
291 /* for linear pte/pde updates without addr mapping */
292 void (*set_pte_pde)(struct amdgpu_ib *ib,
293 uint64_t pe,
294 uint64_t addr, unsigned count,
295 uint32_t incr, uint32_t flags);
296 /* pad the indirect buffer to the necessary number of dw */
297 void (*pad_ib)(struct amdgpu_ib *ib);
298 };
299
300 /* provided by the gmc block */
301 struct amdgpu_gart_funcs {
302 /* flush the vm tlb via mmio */
303 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
304 uint32_t vmid);
305 /* write pte/pde updates using the cpu */
306 int (*set_pte_pde)(struct amdgpu_device *adev,
307 void *cpu_pt_addr, /* cpu addr of page table */
308 uint32_t gpu_page_idx, /* pte/pde to update */
309 uint64_t addr, /* addr to write into pte/pde */
310 uint32_t flags); /* access flags */
311 };
312
313 /* provided by the ih block */
314 struct amdgpu_ih_funcs {
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr)(struct amdgpu_device *adev);
317 void (*decode_iv)(struct amdgpu_device *adev,
318 struct amdgpu_iv_entry *entry);
319 void (*set_rptr)(struct amdgpu_device *adev);
320 };
321
322 /* provided by hw blocks that expose a ring buffer for commands */
323 struct amdgpu_ring_funcs {
324 /* ring read/write ptr handling */
325 u32 (*get_rptr)(struct amdgpu_ring *ring);
326 u32 (*get_wptr)(struct amdgpu_ring *ring);
327 void (*set_wptr)(struct amdgpu_ring *ring);
328 /* validating and patching of IBs */
329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
330 /* command emit functions */
331 void (*emit_ib)(struct amdgpu_ring *ring,
332 struct amdgpu_ib *ib);
333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
334 uint64_t seq, unsigned flags);
335 bool (*emit_semaphore)(struct amdgpu_ring *ring,
336 struct amdgpu_semaphore *semaphore,
337 bool emit_wait);
338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
339 uint64_t pd_addr);
340 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
342 uint32_t gds_base, uint32_t gds_size,
343 uint32_t gws_base, uint32_t gws_size,
344 uint32_t oa_base, uint32_t oa_size);
345 /* testing functions */
346 int (*test_ring)(struct amdgpu_ring *ring);
347 int (*test_ib)(struct amdgpu_ring *ring);
348 /* insert NOP packets */
349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
350 };
351
352 /*
353 * BIOS.
354 */
355 bool amdgpu_get_bios(struct amdgpu_device *adev);
356 bool amdgpu_read_bios(struct amdgpu_device *adev);
357
358 /*
359 * Dummy page
360 */
361 struct amdgpu_dummy_page {
362 struct page *page;
363 dma_addr_t addr;
364 };
365 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
367
368
369 /*
370 * Clocks
371 */
372
373 #define AMDGPU_MAX_PPLL 3
374
375 struct amdgpu_clock {
376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
377 struct amdgpu_pll spll;
378 struct amdgpu_pll mpll;
379 /* 10 Khz units */
380 uint32_t default_mclk;
381 uint32_t default_sclk;
382 uint32_t default_dispclk;
383 uint32_t current_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386 };
387
388 /*
389 * Fences.
390 */
391 struct amdgpu_fence_driver {
392 struct amdgpu_ring *ring;
393 uint64_t gpu_addr;
394 volatile uint32_t *cpu_addr;
395 /* sync_seq is protected by ring emission lock */
396 uint64_t sync_seq[AMDGPU_MAX_RINGS];
397 atomic64_t last_seq;
398 bool initialized;
399 struct amdgpu_irq_src *irq_src;
400 unsigned irq_type;
401 struct delayed_work lockup_work;
402 wait_queue_head_t fence_queue;
403 };
404
405 /* some special values for the owner field */
406 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
407 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
408
409 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
410 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
411
412 struct amdgpu_fence {
413 struct fence base;
414
415 /* RB, DMA, etc. */
416 struct amdgpu_ring *ring;
417 uint64_t seq;
418
419 /* filp or special value for fence creator */
420 void *owner;
421
422 wait_queue_t fence_wake;
423 };
424
425 struct amdgpu_user_fence {
426 /* write-back bo */
427 struct amdgpu_bo *bo;
428 /* write-back address offset to bo start */
429 uint32_t offset;
430 };
431
432 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
433 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
434 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
435
436 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
437 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
438 struct amdgpu_irq_src *irq_src,
439 unsigned irq_type);
440 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
441 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
442 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
443 struct amdgpu_fence **fence);
444 void amdgpu_fence_process(struct amdgpu_ring *ring);
445 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
446 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
447 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
448
449 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
450 struct amdgpu_ring *ring);
451 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
452 struct amdgpu_ring *ring);
453
454 /*
455 * TTM.
456 */
457 struct amdgpu_mman {
458 struct ttm_bo_global_ref bo_global_ref;
459 struct drm_global_reference mem_global_ref;
460 struct ttm_bo_device bdev;
461 bool mem_global_referenced;
462 bool initialized;
463
464 #if defined(CONFIG_DEBUG_FS)
465 struct dentry *vram;
466 struct dentry *gtt;
467 #endif
468
469 /* buffer handling */
470 const struct amdgpu_buffer_funcs *buffer_funcs;
471 struct amdgpu_ring *buffer_funcs_ring;
472 };
473
474 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
475 uint64_t src_offset,
476 uint64_t dst_offset,
477 uint32_t byte_count,
478 struct reservation_object *resv,
479 struct fence **fence);
480 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
481
482 struct amdgpu_bo_list_entry {
483 struct amdgpu_bo *robj;
484 struct ttm_validate_buffer tv;
485 struct amdgpu_bo_va *bo_va;
486 unsigned prefered_domains;
487 unsigned allowed_domains;
488 uint32_t priority;
489 };
490
491 struct amdgpu_bo_va_mapping {
492 struct list_head list;
493 struct interval_tree_node it;
494 uint64_t offset;
495 uint32_t flags;
496 };
497
498 /* bo virtual addresses in a specific vm */
499 struct amdgpu_bo_va {
500 /* protected by bo being reserved */
501 struct list_head bo_list;
502 struct fence *last_pt_update;
503 unsigned ref_count;
504
505 /* protected by vm mutex and spinlock */
506 struct list_head vm_status;
507
508 /* mappings for this bo_va */
509 struct list_head invalids;
510 struct list_head valids;
511
512 /* constant after initialization */
513 struct amdgpu_vm *vm;
514 struct amdgpu_bo *bo;
515 };
516
517 #define AMDGPU_GEM_DOMAIN_MAX 0x3
518
519 struct amdgpu_bo {
520 /* Protected by gem.mutex */
521 struct list_head list;
522 /* Protected by tbo.reserved */
523 u32 initial_domain;
524 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
525 struct ttm_placement placement;
526 struct ttm_buffer_object tbo;
527 struct ttm_bo_kmap_obj kmap;
528 u64 flags;
529 unsigned pin_count;
530 void *kptr;
531 u64 tiling_flags;
532 u64 metadata_flags;
533 void *metadata;
534 u32 metadata_size;
535 /* list of all virtual address to which this bo
536 * is associated to
537 */
538 struct list_head va;
539 /* Constant after initialization */
540 struct amdgpu_device *adev;
541 struct drm_gem_object gem_base;
542
543 struct ttm_bo_kmap_obj dma_buf_vmap;
544 pid_t pid;
545 struct amdgpu_mn *mn;
546 struct list_head mn_list;
547 };
548 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
549
550 void amdgpu_gem_object_free(struct drm_gem_object *obj);
551 int amdgpu_gem_object_open(struct drm_gem_object *obj,
552 struct drm_file *file_priv);
553 void amdgpu_gem_object_close(struct drm_gem_object *obj,
554 struct drm_file *file_priv);
555 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
556 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
557 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
558 struct dma_buf_attachment *attach,
559 struct sg_table *sg);
560 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
561 struct drm_gem_object *gobj,
562 int flags);
563 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
564 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
565 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
566 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
567 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
568 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
569
570 /* sub-allocation manager, it has to be protected by another lock.
571 * By conception this is an helper for other part of the driver
572 * like the indirect buffer or semaphore, which both have their
573 * locking.
574 *
575 * Principe is simple, we keep a list of sub allocation in offset
576 * order (first entry has offset == 0, last entry has the highest
577 * offset).
578 *
579 * When allocating new object we first check if there is room at
580 * the end total_size - (last_object_offset + last_object_size) >=
581 * alloc_size. If so we allocate new object there.
582 *
583 * When there is not enough room at the end, we start waiting for
584 * each sub object until we reach object_offset+object_size >=
585 * alloc_size, this object then become the sub object we return.
586 *
587 * Alignment can't be bigger than page size.
588 *
589 * Hole are not considered for allocation to keep things simple.
590 * Assumption is that there won't be hole (all object on same
591 * alignment).
592 */
593 struct amdgpu_sa_manager {
594 wait_queue_head_t wq;
595 struct amdgpu_bo *bo;
596 struct list_head *hole;
597 struct list_head flist[AMDGPU_MAX_RINGS];
598 struct list_head olist;
599 unsigned size;
600 uint64_t gpu_addr;
601 void *cpu_ptr;
602 uint32_t domain;
603 uint32_t align;
604 };
605
606 struct amdgpu_sa_bo;
607
608 /* sub-allocation buffer */
609 struct amdgpu_sa_bo {
610 struct list_head olist;
611 struct list_head flist;
612 struct amdgpu_sa_manager *manager;
613 unsigned soffset;
614 unsigned eoffset;
615 struct fence *fence;
616 };
617
618 /*
619 * GEM objects.
620 */
621 struct amdgpu_gem {
622 struct mutex mutex;
623 struct list_head objects;
624 };
625
626 int amdgpu_gem_init(struct amdgpu_device *adev);
627 void amdgpu_gem_fini(struct amdgpu_device *adev);
628 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
629 int alignment, u32 initial_domain,
630 u64 flags, bool kernel,
631 struct drm_gem_object **obj);
632
633 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
634 struct drm_device *dev,
635 struct drm_mode_create_dumb *args);
636 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
637 struct drm_device *dev,
638 uint32_t handle, uint64_t *offset_p);
639
640 /*
641 * Semaphores.
642 */
643 struct amdgpu_semaphore {
644 struct amdgpu_sa_bo *sa_bo;
645 signed waiters;
646 uint64_t gpu_addr;
647 };
648
649 int amdgpu_semaphore_create(struct amdgpu_device *adev,
650 struct amdgpu_semaphore **semaphore);
651 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
652 struct amdgpu_semaphore *semaphore);
653 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
654 struct amdgpu_semaphore *semaphore);
655 void amdgpu_semaphore_free(struct amdgpu_device *adev,
656 struct amdgpu_semaphore **semaphore,
657 struct fence *fence);
658
659 /*
660 * Synchronization
661 */
662 struct amdgpu_sync {
663 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
664 struct fence *sync_to[AMDGPU_MAX_RINGS];
665 DECLARE_HASHTABLE(fences, 4);
666 struct fence *last_vm_update;
667 };
668
669 void amdgpu_sync_create(struct amdgpu_sync *sync);
670 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
671 struct fence *f);
672 int amdgpu_sync_resv(struct amdgpu_device *adev,
673 struct amdgpu_sync *sync,
674 struct reservation_object *resv,
675 void *owner);
676 int amdgpu_sync_rings(struct amdgpu_sync *sync,
677 struct amdgpu_ring *ring);
678 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
679 int amdgpu_sync_wait(struct amdgpu_sync *sync);
680 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
681 struct fence *fence);
682
683 /*
684 * GART structures, functions & helpers
685 */
686 struct amdgpu_mc;
687
688 #define AMDGPU_GPU_PAGE_SIZE 4096
689 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
690 #define AMDGPU_GPU_PAGE_SHIFT 12
691 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
692
693 struct amdgpu_gart {
694 dma_addr_t table_addr;
695 struct amdgpu_bo *robj;
696 void *ptr;
697 unsigned num_gpu_pages;
698 unsigned num_cpu_pages;
699 unsigned table_size;
700 struct page **pages;
701 dma_addr_t *pages_addr;
702 bool ready;
703 const struct amdgpu_gart_funcs *gart_funcs;
704 };
705
706 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
707 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
708 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
709 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
710 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
711 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
712 int amdgpu_gart_init(struct amdgpu_device *adev);
713 void amdgpu_gart_fini(struct amdgpu_device *adev);
714 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
715 int pages);
716 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
717 int pages, struct page **pagelist,
718 dma_addr_t *dma_addr, uint32_t flags);
719
720 /*
721 * GPU MC structures, functions & helpers
722 */
723 struct amdgpu_mc {
724 resource_size_t aper_size;
725 resource_size_t aper_base;
726 resource_size_t agp_base;
727 /* for some chips with <= 32MB we need to lie
728 * about vram size near mc fb location */
729 u64 mc_vram_size;
730 u64 visible_vram_size;
731 u64 gtt_size;
732 u64 gtt_start;
733 u64 gtt_end;
734 u64 vram_start;
735 u64 vram_end;
736 unsigned vram_width;
737 u64 real_vram_size;
738 int vram_mtrr;
739 u64 gtt_base_align;
740 u64 mc_mask;
741 const struct firmware *fw; /* MC firmware */
742 uint32_t fw_version;
743 struct amdgpu_irq_src vm_fault;
744 uint32_t vram_type;
745 };
746
747 /*
748 * GPU doorbell structures, functions & helpers
749 */
750 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
751 {
752 AMDGPU_DOORBELL_KIQ = 0x000,
753 AMDGPU_DOORBELL_HIQ = 0x001,
754 AMDGPU_DOORBELL_DIQ = 0x002,
755 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
756 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
757 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
758 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
759 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
760 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
761 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
762 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
763 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
764 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
765 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
766 AMDGPU_DOORBELL_IH = 0x1E8,
767 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
768 AMDGPU_DOORBELL_INVALID = 0xFFFF
769 } AMDGPU_DOORBELL_ASSIGNMENT;
770
771 struct amdgpu_doorbell {
772 /* doorbell mmio */
773 resource_size_t base;
774 resource_size_t size;
775 u32 __iomem *ptr;
776 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
777 };
778
779 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
780 phys_addr_t *aperture_base,
781 size_t *aperture_size,
782 size_t *start_offset);
783
784 /*
785 * IRQS.
786 */
787
788 struct amdgpu_flip_work {
789 struct work_struct flip_work;
790 struct work_struct unpin_work;
791 struct amdgpu_device *adev;
792 int crtc_id;
793 uint64_t base;
794 struct drm_pending_vblank_event *event;
795 struct amdgpu_bo *old_rbo;
796 struct fence *excl;
797 unsigned shared_count;
798 struct fence **shared;
799 };
800
801
802 /*
803 * CP & rings.
804 */
805
806 struct amdgpu_ib {
807 struct amdgpu_sa_bo *sa_bo;
808 uint32_t length_dw;
809 uint64_t gpu_addr;
810 uint32_t *ptr;
811 struct amdgpu_ring *ring;
812 struct amdgpu_fence *fence;
813 struct amdgpu_user_fence *user;
814 struct amdgpu_vm *vm;
815 struct amdgpu_ctx *ctx;
816 struct amdgpu_sync sync;
817 uint32_t gds_base, gds_size;
818 uint32_t gws_base, gws_size;
819 uint32_t oa_base, oa_size;
820 uint32_t flags;
821 /* resulting sequence number */
822 uint64_t sequence;
823 };
824
825 enum amdgpu_ring_type {
826 AMDGPU_RING_TYPE_GFX,
827 AMDGPU_RING_TYPE_COMPUTE,
828 AMDGPU_RING_TYPE_SDMA,
829 AMDGPU_RING_TYPE_UVD,
830 AMDGPU_RING_TYPE_VCE
831 };
832
833 extern struct amd_sched_backend_ops amdgpu_sched_ops;
834
835 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
836 struct amdgpu_ring *ring,
837 struct amdgpu_ib *ibs,
838 unsigned num_ibs,
839 int (*free_job)(struct amdgpu_job *),
840 void *owner,
841 struct fence **fence);
842
843 struct amdgpu_ring {
844 struct amdgpu_device *adev;
845 const struct amdgpu_ring_funcs *funcs;
846 struct amdgpu_fence_driver fence_drv;
847 struct amd_gpu_scheduler sched;
848
849 spinlock_t fence_lock;
850 struct mutex *ring_lock;
851 struct amdgpu_bo *ring_obj;
852 volatile uint32_t *ring;
853 unsigned rptr_offs;
854 u64 next_rptr_gpu_addr;
855 volatile u32 *next_rptr_cpu_addr;
856 unsigned wptr;
857 unsigned wptr_old;
858 unsigned ring_size;
859 unsigned ring_free_dw;
860 int count_dw;
861 uint64_t gpu_addr;
862 uint32_t align_mask;
863 uint32_t ptr_mask;
864 bool ready;
865 u32 nop;
866 u32 idx;
867 u64 last_semaphore_signal_addr;
868 u64 last_semaphore_wait_addr;
869 u32 me;
870 u32 pipe;
871 u32 queue;
872 struct amdgpu_bo *mqd_obj;
873 u32 doorbell_index;
874 bool use_doorbell;
875 unsigned wptr_offs;
876 unsigned next_rptr_offs;
877 unsigned fence_offs;
878 struct amdgpu_ctx *current_ctx;
879 enum amdgpu_ring_type type;
880 char name[16];
881 bool is_pte_ring;
882 };
883
884 /*
885 * VM
886 */
887
888 /* maximum number of VMIDs */
889 #define AMDGPU_NUM_VM 16
890
891 /* number of entries in page table */
892 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
893
894 /* PTBs (Page Table Blocks) need to be aligned to 32K */
895 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
896 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
897 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
898
899 #define AMDGPU_PTE_VALID (1 << 0)
900 #define AMDGPU_PTE_SYSTEM (1 << 1)
901 #define AMDGPU_PTE_SNOOPED (1 << 2)
902
903 /* VI only */
904 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
905
906 #define AMDGPU_PTE_READABLE (1 << 5)
907 #define AMDGPU_PTE_WRITEABLE (1 << 6)
908
909 /* PTE (Page Table Entry) fragment field for different page sizes */
910 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
911 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
912 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
913
914 /* How to programm VM fault handling */
915 #define AMDGPU_VM_FAULT_STOP_NEVER 0
916 #define AMDGPU_VM_FAULT_STOP_FIRST 1
917 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
918
919 struct amdgpu_vm_pt {
920 struct amdgpu_bo *bo;
921 uint64_t addr;
922 };
923
924 struct amdgpu_vm_id {
925 unsigned id;
926 uint64_t pd_gpu_addr;
927 /* last flushed PD/PT update */
928 struct fence *flushed_updates;
929 /* last use of vmid */
930 struct fence *last_id_use;
931 };
932
933 struct amdgpu_vm {
934 struct mutex mutex;
935
936 struct rb_root va;
937
938 /* protecting invalidated */
939 spinlock_t status_lock;
940
941 /* BOs moved, but not yet updated in the PT */
942 struct list_head invalidated;
943
944 /* BOs cleared in the PT because of a move */
945 struct list_head cleared;
946
947 /* BO mappings freed, but not yet updated in the PT */
948 struct list_head freed;
949
950 /* contains the page directory */
951 struct amdgpu_bo *page_directory;
952 unsigned max_pde_used;
953 struct fence *page_directory_fence;
954
955 /* array of page tables, one for each page directory entry */
956 struct amdgpu_vm_pt *page_tables;
957
958 /* for id and flush management per ring */
959 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
960 };
961
962 struct amdgpu_vm_manager {
963 struct fence *active[AMDGPU_NUM_VM];
964 uint32_t max_pfn;
965 /* number of VMIDs */
966 unsigned nvm;
967 /* vram base address for page table entry */
968 u64 vram_base_offset;
969 /* is vm enabled? */
970 bool enabled;
971 /* for hw to save the PD addr on suspend/resume */
972 uint32_t saved_table_addr[AMDGPU_NUM_VM];
973 /* vm pte handling */
974 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
975 struct amdgpu_ring *vm_pte_funcs_ring;
976 };
977
978 /*
979 * context related structures
980 */
981
982 #define AMDGPU_CTX_MAX_CS_PENDING 16
983
984 struct amdgpu_ctx_ring {
985 uint64_t sequence;
986 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
987 struct amd_sched_entity entity;
988 };
989
990 struct amdgpu_ctx {
991 struct kref refcount;
992 struct amdgpu_device *adev;
993 unsigned reset_counter;
994 spinlock_t ring_lock;
995 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
996 };
997
998 struct amdgpu_ctx_mgr {
999 struct amdgpu_device *adev;
1000 struct mutex lock;
1001 /* protected by lock */
1002 struct idr ctx_handles;
1003 };
1004
1005 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1006 struct amdgpu_ctx *ctx);
1007 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1008
1009 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1010 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1011
1012 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1013 struct fence *fence);
1014 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1015 struct amdgpu_ring *ring, uint64_t seq);
1016
1017 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1018 struct drm_file *filp);
1019
1020 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1021 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1022
1023 /*
1024 * file private structure
1025 */
1026
1027 struct amdgpu_fpriv {
1028 struct amdgpu_vm vm;
1029 struct mutex bo_list_lock;
1030 struct idr bo_list_handles;
1031 struct amdgpu_ctx_mgr ctx_mgr;
1032 };
1033
1034 /*
1035 * residency list
1036 */
1037
1038 struct amdgpu_bo_list {
1039 struct mutex lock;
1040 struct amdgpu_bo *gds_obj;
1041 struct amdgpu_bo *gws_obj;
1042 struct amdgpu_bo *oa_obj;
1043 bool has_userptr;
1044 unsigned num_entries;
1045 struct amdgpu_bo_list_entry *array;
1046 };
1047
1048 struct amdgpu_bo_list *
1049 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1050 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1051 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1052
1053 /*
1054 * GFX stuff
1055 */
1056 #include "clearstate_defs.h"
1057
1058 struct amdgpu_rlc {
1059 /* for power gating */
1060 struct amdgpu_bo *save_restore_obj;
1061 uint64_t save_restore_gpu_addr;
1062 volatile uint32_t *sr_ptr;
1063 const u32 *reg_list;
1064 u32 reg_list_size;
1065 /* for clear state */
1066 struct amdgpu_bo *clear_state_obj;
1067 uint64_t clear_state_gpu_addr;
1068 volatile uint32_t *cs_ptr;
1069 const struct cs_section_def *cs_data;
1070 u32 clear_state_size;
1071 /* for cp tables */
1072 struct amdgpu_bo *cp_table_obj;
1073 uint64_t cp_table_gpu_addr;
1074 volatile uint32_t *cp_table_ptr;
1075 u32 cp_table_size;
1076 };
1077
1078 struct amdgpu_mec {
1079 struct amdgpu_bo *hpd_eop_obj;
1080 u64 hpd_eop_gpu_addr;
1081 u32 num_pipe;
1082 u32 num_mec;
1083 u32 num_queue;
1084 };
1085
1086 /*
1087 * GPU scratch registers structures, functions & helpers
1088 */
1089 struct amdgpu_scratch {
1090 unsigned num_reg;
1091 uint32_t reg_base;
1092 bool free[32];
1093 uint32_t reg[32];
1094 };
1095
1096 /*
1097 * GFX configurations
1098 */
1099 struct amdgpu_gca_config {
1100 unsigned max_shader_engines;
1101 unsigned max_tile_pipes;
1102 unsigned max_cu_per_sh;
1103 unsigned max_sh_per_se;
1104 unsigned max_backends_per_se;
1105 unsigned max_texture_channel_caches;
1106 unsigned max_gprs;
1107 unsigned max_gs_threads;
1108 unsigned max_hw_contexts;
1109 unsigned sc_prim_fifo_size_frontend;
1110 unsigned sc_prim_fifo_size_backend;
1111 unsigned sc_hiz_tile_fifo_size;
1112 unsigned sc_earlyz_tile_fifo_size;
1113
1114 unsigned num_tile_pipes;
1115 unsigned backend_enable_mask;
1116 unsigned mem_max_burst_length_bytes;
1117 unsigned mem_row_size_in_kb;
1118 unsigned shader_engine_tile_size;
1119 unsigned num_gpus;
1120 unsigned multi_gpu_tile_size;
1121 unsigned mc_arb_ramcfg;
1122 unsigned gb_addr_config;
1123
1124 uint32_t tile_mode_array[32];
1125 uint32_t macrotile_mode_array[16];
1126 };
1127
1128 struct amdgpu_gfx {
1129 struct mutex gpu_clock_mutex;
1130 struct amdgpu_gca_config config;
1131 struct amdgpu_rlc rlc;
1132 struct amdgpu_mec mec;
1133 struct amdgpu_scratch scratch;
1134 const struct firmware *me_fw; /* ME firmware */
1135 uint32_t me_fw_version;
1136 const struct firmware *pfp_fw; /* PFP firmware */
1137 uint32_t pfp_fw_version;
1138 const struct firmware *ce_fw; /* CE firmware */
1139 uint32_t ce_fw_version;
1140 const struct firmware *rlc_fw; /* RLC firmware */
1141 uint32_t rlc_fw_version;
1142 const struct firmware *mec_fw; /* MEC firmware */
1143 uint32_t mec_fw_version;
1144 const struct firmware *mec2_fw; /* MEC2 firmware */
1145 uint32_t mec2_fw_version;
1146 uint32_t me_feature_version;
1147 uint32_t ce_feature_version;
1148 uint32_t pfp_feature_version;
1149 uint32_t rlc_feature_version;
1150 uint32_t mec_feature_version;
1151 uint32_t mec2_feature_version;
1152 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1153 unsigned num_gfx_rings;
1154 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1155 unsigned num_compute_rings;
1156 struct amdgpu_irq_src eop_irq;
1157 struct amdgpu_irq_src priv_reg_irq;
1158 struct amdgpu_irq_src priv_inst_irq;
1159 /* gfx status */
1160 uint32_t gfx_current_status;
1161 /* ce ram size*/
1162 unsigned ce_ram_size;
1163 };
1164
1165 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1166 unsigned size, struct amdgpu_ib *ib);
1167 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1168 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1169 struct amdgpu_ib *ib, void *owner);
1170 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1171 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1172 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1173 /* Ring access between begin & end cannot sleep */
1174 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1175 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1176 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1177 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1178 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1179 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1180 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1181 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1182 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1183 uint32_t **data);
1184 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1185 unsigned size, uint32_t *data);
1186 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1187 unsigned ring_size, u32 nop, u32 align_mask,
1188 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1189 enum amdgpu_ring_type ring_type);
1190 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1191 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1192
1193 /*
1194 * CS.
1195 */
1196 struct amdgpu_cs_chunk {
1197 uint32_t chunk_id;
1198 uint32_t length_dw;
1199 uint32_t *kdata;
1200 void __user *user_ptr;
1201 };
1202
1203 struct amdgpu_cs_parser {
1204 struct amdgpu_device *adev;
1205 struct drm_file *filp;
1206 struct amdgpu_ctx *ctx;
1207 struct amdgpu_bo_list *bo_list;
1208 /* chunks */
1209 unsigned nchunks;
1210 struct amdgpu_cs_chunk *chunks;
1211 /* relocations */
1212 struct amdgpu_bo_list_entry *vm_bos;
1213 struct list_head validated;
1214
1215 struct amdgpu_ib *ibs;
1216 uint32_t num_ibs;
1217
1218 struct ww_acquire_ctx ticket;
1219
1220 /* user fence */
1221 struct amdgpu_user_fence uf;
1222 };
1223
1224 struct amdgpu_job {
1225 struct amd_sched_job base;
1226 struct amdgpu_device *adev;
1227 struct amdgpu_ib *ibs;
1228 uint32_t num_ibs;
1229 struct mutex job_lock;
1230 struct amdgpu_user_fence uf;
1231 int (*free_job)(struct amdgpu_job *job);
1232 };
1233 #define to_amdgpu_job(sched_job) \
1234 container_of((sched_job), struct amdgpu_job, base)
1235
1236 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1237 {
1238 return p->ibs[ib_idx].ptr[idx];
1239 }
1240
1241 /*
1242 * Writeback
1243 */
1244 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1245
1246 struct amdgpu_wb {
1247 struct amdgpu_bo *wb_obj;
1248 volatile uint32_t *wb;
1249 uint64_t gpu_addr;
1250 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1251 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1252 };
1253
1254 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1255 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1256
1257 /**
1258 * struct amdgpu_pm - power management datas
1259 * It keeps track of various data needed to take powermanagement decision.
1260 */
1261
1262 enum amdgpu_pm_state_type {
1263 /* not used for dpm */
1264 POWER_STATE_TYPE_DEFAULT,
1265 POWER_STATE_TYPE_POWERSAVE,
1266 /* user selectable states */
1267 POWER_STATE_TYPE_BATTERY,
1268 POWER_STATE_TYPE_BALANCED,
1269 POWER_STATE_TYPE_PERFORMANCE,
1270 /* internal states */
1271 POWER_STATE_TYPE_INTERNAL_UVD,
1272 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1273 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1274 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1275 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1276 POWER_STATE_TYPE_INTERNAL_BOOT,
1277 POWER_STATE_TYPE_INTERNAL_THERMAL,
1278 POWER_STATE_TYPE_INTERNAL_ACPI,
1279 POWER_STATE_TYPE_INTERNAL_ULV,
1280 POWER_STATE_TYPE_INTERNAL_3DPERF,
1281 };
1282
1283 enum amdgpu_int_thermal_type {
1284 THERMAL_TYPE_NONE,
1285 THERMAL_TYPE_EXTERNAL,
1286 THERMAL_TYPE_EXTERNAL_GPIO,
1287 THERMAL_TYPE_RV6XX,
1288 THERMAL_TYPE_RV770,
1289 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1290 THERMAL_TYPE_EVERGREEN,
1291 THERMAL_TYPE_SUMO,
1292 THERMAL_TYPE_NI,
1293 THERMAL_TYPE_SI,
1294 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1295 THERMAL_TYPE_CI,
1296 THERMAL_TYPE_KV,
1297 };
1298
1299 enum amdgpu_dpm_auto_throttle_src {
1300 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1301 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1302 };
1303
1304 enum amdgpu_dpm_event_src {
1305 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1306 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1307 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1308 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1309 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1310 };
1311
1312 #define AMDGPU_MAX_VCE_LEVELS 6
1313
1314 enum amdgpu_vce_level {
1315 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1316 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1317 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1318 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1319 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1320 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1321 };
1322
1323 struct amdgpu_ps {
1324 u32 caps; /* vbios flags */
1325 u32 class; /* vbios flags */
1326 u32 class2; /* vbios flags */
1327 /* UVD clocks */
1328 u32 vclk;
1329 u32 dclk;
1330 /* VCE clocks */
1331 u32 evclk;
1332 u32 ecclk;
1333 bool vce_active;
1334 enum amdgpu_vce_level vce_level;
1335 /* asic priv */
1336 void *ps_priv;
1337 };
1338
1339 struct amdgpu_dpm_thermal {
1340 /* thermal interrupt work */
1341 struct work_struct work;
1342 /* low temperature threshold */
1343 int min_temp;
1344 /* high temperature threshold */
1345 int max_temp;
1346 /* was last interrupt low to high or high to low */
1347 bool high_to_low;
1348 /* interrupt source */
1349 struct amdgpu_irq_src irq;
1350 };
1351
1352 enum amdgpu_clk_action
1353 {
1354 AMDGPU_SCLK_UP = 1,
1355 AMDGPU_SCLK_DOWN
1356 };
1357
1358 struct amdgpu_blacklist_clocks
1359 {
1360 u32 sclk;
1361 u32 mclk;
1362 enum amdgpu_clk_action action;
1363 };
1364
1365 struct amdgpu_clock_and_voltage_limits {
1366 u32 sclk;
1367 u32 mclk;
1368 u16 vddc;
1369 u16 vddci;
1370 };
1371
1372 struct amdgpu_clock_array {
1373 u32 count;
1374 u32 *values;
1375 };
1376
1377 struct amdgpu_clock_voltage_dependency_entry {
1378 u32 clk;
1379 u16 v;
1380 };
1381
1382 struct amdgpu_clock_voltage_dependency_table {
1383 u32 count;
1384 struct amdgpu_clock_voltage_dependency_entry *entries;
1385 };
1386
1387 union amdgpu_cac_leakage_entry {
1388 struct {
1389 u16 vddc;
1390 u32 leakage;
1391 };
1392 struct {
1393 u16 vddc1;
1394 u16 vddc2;
1395 u16 vddc3;
1396 };
1397 };
1398
1399 struct amdgpu_cac_leakage_table {
1400 u32 count;
1401 union amdgpu_cac_leakage_entry *entries;
1402 };
1403
1404 struct amdgpu_phase_shedding_limits_entry {
1405 u16 voltage;
1406 u32 sclk;
1407 u32 mclk;
1408 };
1409
1410 struct amdgpu_phase_shedding_limits_table {
1411 u32 count;
1412 struct amdgpu_phase_shedding_limits_entry *entries;
1413 };
1414
1415 struct amdgpu_uvd_clock_voltage_dependency_entry {
1416 u32 vclk;
1417 u32 dclk;
1418 u16 v;
1419 };
1420
1421 struct amdgpu_uvd_clock_voltage_dependency_table {
1422 u8 count;
1423 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1424 };
1425
1426 struct amdgpu_vce_clock_voltage_dependency_entry {
1427 u32 ecclk;
1428 u32 evclk;
1429 u16 v;
1430 };
1431
1432 struct amdgpu_vce_clock_voltage_dependency_table {
1433 u8 count;
1434 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1435 };
1436
1437 struct amdgpu_ppm_table {
1438 u8 ppm_design;
1439 u16 cpu_core_number;
1440 u32 platform_tdp;
1441 u32 small_ac_platform_tdp;
1442 u32 platform_tdc;
1443 u32 small_ac_platform_tdc;
1444 u32 apu_tdp;
1445 u32 dgpu_tdp;
1446 u32 dgpu_ulv_power;
1447 u32 tj_max;
1448 };
1449
1450 struct amdgpu_cac_tdp_table {
1451 u16 tdp;
1452 u16 configurable_tdp;
1453 u16 tdc;
1454 u16 battery_power_limit;
1455 u16 small_power_limit;
1456 u16 low_cac_leakage;
1457 u16 high_cac_leakage;
1458 u16 maximum_power_delivery_limit;
1459 };
1460
1461 struct amdgpu_dpm_dynamic_state {
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1463 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1465 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1466 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1467 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1468 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1470 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1471 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1472 struct amdgpu_clock_array valid_sclk_values;
1473 struct amdgpu_clock_array valid_mclk_values;
1474 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1475 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1476 u32 mclk_sclk_ratio;
1477 u32 sclk_mclk_delta;
1478 u16 vddc_vddci_delta;
1479 u16 min_vddc_for_pcie_gen2;
1480 struct amdgpu_cac_leakage_table cac_leakage_table;
1481 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1482 struct amdgpu_ppm_table *ppm_table;
1483 struct amdgpu_cac_tdp_table *cac_tdp_table;
1484 };
1485
1486 struct amdgpu_dpm_fan {
1487 u16 t_min;
1488 u16 t_med;
1489 u16 t_high;
1490 u16 pwm_min;
1491 u16 pwm_med;
1492 u16 pwm_high;
1493 u8 t_hyst;
1494 u32 cycle_delay;
1495 u16 t_max;
1496 u8 control_mode;
1497 u16 default_max_fan_pwm;
1498 u16 default_fan_output_sensitivity;
1499 u16 fan_output_sensitivity;
1500 bool ucode_fan_control;
1501 };
1502
1503 enum amdgpu_pcie_gen {
1504 AMDGPU_PCIE_GEN1 = 0,
1505 AMDGPU_PCIE_GEN2 = 1,
1506 AMDGPU_PCIE_GEN3 = 2,
1507 AMDGPU_PCIE_GEN_INVALID = 0xffff
1508 };
1509
1510 enum amdgpu_dpm_forced_level {
1511 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1512 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1513 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1514 };
1515
1516 struct amdgpu_vce_state {
1517 /* vce clocks */
1518 u32 evclk;
1519 u32 ecclk;
1520 /* gpu clocks */
1521 u32 sclk;
1522 u32 mclk;
1523 u8 clk_idx;
1524 u8 pstate;
1525 };
1526
1527 struct amdgpu_dpm_funcs {
1528 int (*get_temperature)(struct amdgpu_device *adev);
1529 int (*pre_set_power_state)(struct amdgpu_device *adev);
1530 int (*set_power_state)(struct amdgpu_device *adev);
1531 void (*post_set_power_state)(struct amdgpu_device *adev);
1532 void (*display_configuration_changed)(struct amdgpu_device *adev);
1533 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1534 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1535 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1536 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1537 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1538 bool (*vblank_too_short)(struct amdgpu_device *adev);
1539 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1540 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1541 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1542 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1543 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1544 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1545 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1546 };
1547
1548 struct amdgpu_dpm {
1549 struct amdgpu_ps *ps;
1550 /* number of valid power states */
1551 int num_ps;
1552 /* current power state that is active */
1553 struct amdgpu_ps *current_ps;
1554 /* requested power state */
1555 struct amdgpu_ps *requested_ps;
1556 /* boot up power state */
1557 struct amdgpu_ps *boot_ps;
1558 /* default uvd power state */
1559 struct amdgpu_ps *uvd_ps;
1560 /* vce requirements */
1561 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1562 enum amdgpu_vce_level vce_level;
1563 enum amdgpu_pm_state_type state;
1564 enum amdgpu_pm_state_type user_state;
1565 u32 platform_caps;
1566 u32 voltage_response_time;
1567 u32 backbias_response_time;
1568 void *priv;
1569 u32 new_active_crtcs;
1570 int new_active_crtc_count;
1571 u32 current_active_crtcs;
1572 int current_active_crtc_count;
1573 struct amdgpu_dpm_dynamic_state dyn_state;
1574 struct amdgpu_dpm_fan fan;
1575 u32 tdp_limit;
1576 u32 near_tdp_limit;
1577 u32 near_tdp_limit_adjusted;
1578 u32 sq_ramping_threshold;
1579 u32 cac_leakage;
1580 u16 tdp_od_limit;
1581 u32 tdp_adjustment;
1582 u16 load_line_slope;
1583 bool power_control;
1584 bool ac_power;
1585 /* special states active */
1586 bool thermal_active;
1587 bool uvd_active;
1588 bool vce_active;
1589 /* thermal handling */
1590 struct amdgpu_dpm_thermal thermal;
1591 /* forced levels */
1592 enum amdgpu_dpm_forced_level forced_level;
1593 };
1594
1595 struct amdgpu_pm {
1596 struct mutex mutex;
1597 u32 current_sclk;
1598 u32 current_mclk;
1599 u32 default_sclk;
1600 u32 default_mclk;
1601 struct amdgpu_i2c_chan *i2c_bus;
1602 /* internal thermal controller on rv6xx+ */
1603 enum amdgpu_int_thermal_type int_thermal_type;
1604 struct device *int_hwmon_dev;
1605 /* fan control parameters */
1606 bool no_fan;
1607 u8 fan_pulses_per_revolution;
1608 u8 fan_min_rpm;
1609 u8 fan_max_rpm;
1610 /* dpm */
1611 bool dpm_enabled;
1612 bool sysfs_initialized;
1613 struct amdgpu_dpm dpm;
1614 const struct firmware *fw; /* SMC firmware */
1615 uint32_t fw_version;
1616 const struct amdgpu_dpm_funcs *funcs;
1617 };
1618
1619 /*
1620 * UVD
1621 */
1622 #define AMDGPU_MAX_UVD_HANDLES 10
1623 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1624 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1625 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1626
1627 struct amdgpu_uvd {
1628 struct amdgpu_bo *vcpu_bo;
1629 void *cpu_addr;
1630 uint64_t gpu_addr;
1631 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1632 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1633 struct delayed_work idle_work;
1634 const struct firmware *fw; /* UVD firmware */
1635 struct amdgpu_ring ring;
1636 struct amdgpu_irq_src irq;
1637 bool address_64_bit;
1638 };
1639
1640 /*
1641 * VCE
1642 */
1643 #define AMDGPU_MAX_VCE_HANDLES 16
1644 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1645
1646 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1647 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1648
1649 struct amdgpu_vce {
1650 struct amdgpu_bo *vcpu_bo;
1651 uint64_t gpu_addr;
1652 unsigned fw_version;
1653 unsigned fb_version;
1654 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1655 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1656 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1657 struct delayed_work idle_work;
1658 const struct firmware *fw; /* VCE firmware */
1659 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1660 struct amdgpu_irq_src irq;
1661 unsigned harvest_config;
1662 };
1663
1664 /*
1665 * SDMA
1666 */
1667 struct amdgpu_sdma_instance {
1668 /* SDMA firmware */
1669 const struct firmware *fw;
1670 uint32_t fw_version;
1671 uint32_t feature_version;
1672
1673 struct amdgpu_ring ring;
1674 bool burst_nop;
1675 };
1676
1677 struct amdgpu_sdma {
1678 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1679 struct amdgpu_irq_src trap_irq;
1680 struct amdgpu_irq_src illegal_inst_irq;
1681 int num_instances;
1682 };
1683
1684 /*
1685 * Firmware
1686 */
1687 struct amdgpu_firmware {
1688 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1689 bool smu_load;
1690 struct amdgpu_bo *fw_buf;
1691 unsigned int fw_size;
1692 };
1693
1694 /*
1695 * Benchmarking
1696 */
1697 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1698
1699
1700 /*
1701 * Testing
1702 */
1703 void amdgpu_test_moves(struct amdgpu_device *adev);
1704 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1705 struct amdgpu_ring *cpA,
1706 struct amdgpu_ring *cpB);
1707 void amdgpu_test_syncing(struct amdgpu_device *adev);
1708
1709 /*
1710 * MMU Notifier
1711 */
1712 #if defined(CONFIG_MMU_NOTIFIER)
1713 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1714 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1715 #else
1716 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1717 {
1718 return -ENODEV;
1719 }
1720 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1721 #endif
1722
1723 /*
1724 * Debugfs
1725 */
1726 struct amdgpu_debugfs {
1727 struct drm_info_list *files;
1728 unsigned num_files;
1729 };
1730
1731 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1732 struct drm_info_list *files,
1733 unsigned nfiles);
1734 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1735
1736 #if defined(CONFIG_DEBUG_FS)
1737 int amdgpu_debugfs_init(struct drm_minor *minor);
1738 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1739 #endif
1740
1741 /*
1742 * amdgpu smumgr functions
1743 */
1744 struct amdgpu_smumgr_funcs {
1745 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1746 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1747 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1748 };
1749
1750 /*
1751 * amdgpu smumgr
1752 */
1753 struct amdgpu_smumgr {
1754 struct amdgpu_bo *toc_buf;
1755 struct amdgpu_bo *smu_buf;
1756 /* asic priv smu data */
1757 void *priv;
1758 spinlock_t smu_lock;
1759 /* smumgr functions */
1760 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1761 /* ucode loading complete flag */
1762 uint32_t fw_flags;
1763 };
1764
1765 /*
1766 * ASIC specific register table accessible by UMD
1767 */
1768 struct amdgpu_allowed_register_entry {
1769 uint32_t reg_offset;
1770 bool untouched;
1771 bool grbm_indexed;
1772 };
1773
1774 struct amdgpu_cu_info {
1775 uint32_t number; /* total active CU number */
1776 uint32_t ao_cu_mask;
1777 uint32_t bitmap[4][4];
1778 };
1779
1780
1781 /*
1782 * ASIC specific functions.
1783 */
1784 struct amdgpu_asic_funcs {
1785 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1786 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1787 u32 sh_num, u32 reg_offset, u32 *value);
1788 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1789 int (*reset)(struct amdgpu_device *adev);
1790 /* wait for mc_idle */
1791 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1792 /* get the reference clock */
1793 u32 (*get_xclk)(struct amdgpu_device *adev);
1794 /* get the gpu clock counter */
1795 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1796 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1797 /* MM block clocks */
1798 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1799 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1800 };
1801
1802 /*
1803 * IOCTL.
1804 */
1805 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1806 struct drm_file *filp);
1807 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1808 struct drm_file *filp);
1809
1810 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1811 struct drm_file *filp);
1812 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1813 struct drm_file *filp);
1814 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1815 struct drm_file *filp);
1816 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1817 struct drm_file *filp);
1818 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1819 struct drm_file *filp);
1820 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1823 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1824
1825 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827
1828 /* VRAM scratch page for HDP bug, default vram page */
1829 struct amdgpu_vram_scratch {
1830 struct amdgpu_bo *robj;
1831 volatile uint32_t *ptr;
1832 u64 gpu_addr;
1833 };
1834
1835 /*
1836 * ACPI
1837 */
1838 struct amdgpu_atif_notification_cfg {
1839 bool enabled;
1840 int command_code;
1841 };
1842
1843 struct amdgpu_atif_notifications {
1844 bool display_switch;
1845 bool expansion_mode_change;
1846 bool thermal_state;
1847 bool forced_power_state;
1848 bool system_power_state;
1849 bool display_conf_change;
1850 bool px_gfx_switch;
1851 bool brightness_change;
1852 bool dgpu_display_event;
1853 };
1854
1855 struct amdgpu_atif_functions {
1856 bool system_params;
1857 bool sbios_requests;
1858 bool select_active_disp;
1859 bool lid_state;
1860 bool get_tv_standard;
1861 bool set_tv_standard;
1862 bool get_panel_expansion_mode;
1863 bool set_panel_expansion_mode;
1864 bool temperature_change;
1865 bool graphics_device_types;
1866 };
1867
1868 struct amdgpu_atif {
1869 struct amdgpu_atif_notifications notifications;
1870 struct amdgpu_atif_functions functions;
1871 struct amdgpu_atif_notification_cfg notification_cfg;
1872 struct amdgpu_encoder *encoder_for_bl;
1873 };
1874
1875 struct amdgpu_atcs_functions {
1876 bool get_ext_state;
1877 bool pcie_perf_req;
1878 bool pcie_dev_rdy;
1879 bool pcie_bus_width;
1880 };
1881
1882 struct amdgpu_atcs {
1883 struct amdgpu_atcs_functions functions;
1884 };
1885
1886 /*
1887 * CGS
1888 */
1889 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1890 void amdgpu_cgs_destroy_device(void *cgs_device);
1891
1892
1893 /*
1894 * Core structure, functions and helpers.
1895 */
1896 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1897 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1898
1899 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1900 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1901
1902 struct amdgpu_ip_block_status {
1903 bool valid;
1904 bool sw;
1905 bool hw;
1906 };
1907
1908 struct amdgpu_device {
1909 struct device *dev;
1910 struct drm_device *ddev;
1911 struct pci_dev *pdev;
1912
1913 /* ASIC */
1914 enum amd_asic_type asic_type;
1915 uint32_t family;
1916 uint32_t rev_id;
1917 uint32_t external_rev_id;
1918 unsigned long flags;
1919 int usec_timeout;
1920 const struct amdgpu_asic_funcs *asic_funcs;
1921 bool shutdown;
1922 bool suspend;
1923 bool need_dma32;
1924 bool accel_working;
1925 struct work_struct reset_work;
1926 struct notifier_block acpi_nb;
1927 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1928 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1929 unsigned debugfs_count;
1930 #if defined(CONFIG_DEBUG_FS)
1931 struct dentry *debugfs_regs;
1932 #endif
1933 struct amdgpu_atif atif;
1934 struct amdgpu_atcs atcs;
1935 struct mutex srbm_mutex;
1936 /* GRBM index mutex. Protects concurrent access to GRBM index */
1937 struct mutex grbm_idx_mutex;
1938 struct dev_pm_domain vga_pm_domain;
1939 bool have_disp_power_ref;
1940
1941 /* BIOS */
1942 uint8_t *bios;
1943 bool is_atom_bios;
1944 uint16_t bios_header_start;
1945 struct amdgpu_bo *stollen_vga_memory;
1946 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1947
1948 /* Register/doorbell mmio */
1949 resource_size_t rmmio_base;
1950 resource_size_t rmmio_size;
1951 void __iomem *rmmio;
1952 /* protects concurrent MM_INDEX/DATA based register access */
1953 spinlock_t mmio_idx_lock;
1954 /* protects concurrent SMC based register access */
1955 spinlock_t smc_idx_lock;
1956 amdgpu_rreg_t smc_rreg;
1957 amdgpu_wreg_t smc_wreg;
1958 /* protects concurrent PCIE register access */
1959 spinlock_t pcie_idx_lock;
1960 amdgpu_rreg_t pcie_rreg;
1961 amdgpu_wreg_t pcie_wreg;
1962 /* protects concurrent UVD register access */
1963 spinlock_t uvd_ctx_idx_lock;
1964 amdgpu_rreg_t uvd_ctx_rreg;
1965 amdgpu_wreg_t uvd_ctx_wreg;
1966 /* protects concurrent DIDT register access */
1967 spinlock_t didt_idx_lock;
1968 amdgpu_rreg_t didt_rreg;
1969 amdgpu_wreg_t didt_wreg;
1970 /* protects concurrent ENDPOINT (audio) register access */
1971 spinlock_t audio_endpt_idx_lock;
1972 amdgpu_block_rreg_t audio_endpt_rreg;
1973 amdgpu_block_wreg_t audio_endpt_wreg;
1974 void __iomem *rio_mem;
1975 resource_size_t rio_mem_size;
1976 struct amdgpu_doorbell doorbell;
1977
1978 /* clock/pll info */
1979 struct amdgpu_clock clock;
1980
1981 /* MC */
1982 struct amdgpu_mc mc;
1983 struct amdgpu_gart gart;
1984 struct amdgpu_dummy_page dummy_page;
1985 struct amdgpu_vm_manager vm_manager;
1986
1987 /* memory management */
1988 struct amdgpu_mman mman;
1989 struct amdgpu_gem gem;
1990 struct amdgpu_vram_scratch vram_scratch;
1991 struct amdgpu_wb wb;
1992 atomic64_t vram_usage;
1993 atomic64_t vram_vis_usage;
1994 atomic64_t gtt_usage;
1995 atomic64_t num_bytes_moved;
1996 atomic_t gpu_reset_counter;
1997
1998 /* display */
1999 struct amdgpu_mode_info mode_info;
2000 struct work_struct hotplug_work;
2001 struct amdgpu_irq_src crtc_irq;
2002 struct amdgpu_irq_src pageflip_irq;
2003 struct amdgpu_irq_src hpd_irq;
2004
2005 /* rings */
2006 unsigned fence_context;
2007 struct mutex ring_lock;
2008 unsigned num_rings;
2009 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2010 bool ib_pool_ready;
2011 struct amdgpu_sa_manager ring_tmp_bo;
2012
2013 /* interrupts */
2014 struct amdgpu_irq irq;
2015
2016 /* dpm */
2017 struct amdgpu_pm pm;
2018 u32 cg_flags;
2019 u32 pg_flags;
2020
2021 /* amdgpu smumgr */
2022 struct amdgpu_smumgr smu;
2023
2024 /* gfx */
2025 struct amdgpu_gfx gfx;
2026
2027 /* sdma */
2028 struct amdgpu_sdma sdma;
2029
2030 /* uvd */
2031 bool has_uvd;
2032 struct amdgpu_uvd uvd;
2033
2034 /* vce */
2035 struct amdgpu_vce vce;
2036
2037 /* firmwares */
2038 struct amdgpu_firmware firmware;
2039
2040 /* GDS */
2041 struct amdgpu_gds gds;
2042
2043 const struct amdgpu_ip_block_version *ip_blocks;
2044 int num_ip_blocks;
2045 struct amdgpu_ip_block_status *ip_block_status;
2046 struct mutex mn_lock;
2047 DECLARE_HASHTABLE(mn_hash, 7);
2048
2049 /* tracking pinned memory */
2050 u64 vram_pin_size;
2051 u64 gart_pin_size;
2052
2053 /* amdkfd interface */
2054 struct kfd_dev *kfd;
2055
2056 /* kernel conext for IB submission */
2057 struct amdgpu_ctx kernel_ctx;
2058 };
2059
2060 bool amdgpu_device_is_px(struct drm_device *dev);
2061 int amdgpu_device_init(struct amdgpu_device *adev,
2062 struct drm_device *ddev,
2063 struct pci_dev *pdev,
2064 uint32_t flags);
2065 void amdgpu_device_fini(struct amdgpu_device *adev);
2066 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2067
2068 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2069 bool always_indirect);
2070 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2071 bool always_indirect);
2072 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2073 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2074
2075 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2076 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2077
2078 /*
2079 * Cast helper
2080 */
2081 extern const struct fence_ops amdgpu_fence_ops;
2082 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2083 {
2084 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2085
2086 if (__f->base.ops == &amdgpu_fence_ops)
2087 return __f;
2088
2089 return NULL;
2090 }
2091
2092 /*
2093 * Registers read & write functions.
2094 */
2095 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2096 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2097 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2098 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2099 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2100 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2101 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2102 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2103 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2104 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2105 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2106 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2107 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2108 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2109 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2110 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2111 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2112 #define WREG32_P(reg, val, mask) \
2113 do { \
2114 uint32_t tmp_ = RREG32(reg); \
2115 tmp_ &= (mask); \
2116 tmp_ |= ((val) & ~(mask)); \
2117 WREG32(reg, tmp_); \
2118 } while (0)
2119 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2120 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2121 #define WREG32_PLL_P(reg, val, mask) \
2122 do { \
2123 uint32_t tmp_ = RREG32_PLL(reg); \
2124 tmp_ &= (mask); \
2125 tmp_ |= ((val) & ~(mask)); \
2126 WREG32_PLL(reg, tmp_); \
2127 } while (0)
2128 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2129 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2130 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2131
2132 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2133 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2134
2135 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2136 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2137
2138 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2139 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2140 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2141
2142 #define REG_GET_FIELD(value, reg, field) \
2143 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2144
2145 /*
2146 * BIOS helpers.
2147 */
2148 #define RBIOS8(i) (adev->bios[i])
2149 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2150 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2151
2152 /*
2153 * RING helpers.
2154 */
2155 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2156 {
2157 if (ring->count_dw <= 0)
2158 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2159 ring->ring[ring->wptr++] = v;
2160 ring->wptr &= ring->ptr_mask;
2161 ring->count_dw--;
2162 ring->ring_free_dw--;
2163 }
2164
2165 static inline struct amdgpu_sdma_instance *
2166 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2167 {
2168 struct amdgpu_device *adev = ring->adev;
2169 int i;
2170
2171 for (i = 0; i < adev->sdma.num_instances; i++)
2172 if (&adev->sdma.instance[i].ring == ring)
2173 break;
2174
2175 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2176 return &adev->sdma.instance[i];
2177 else
2178 return NULL;
2179 }
2180
2181 /*
2182 * ASICs macro.
2183 */
2184 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2185 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2186 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2187 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2188 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2189 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2190 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2191 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2192 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2193 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2194 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2195 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2196 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2197 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2198 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2199 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2200 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2201 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2202 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2203 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2204 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2205 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2206 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2207 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2208 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2209 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2210 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2211 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2212 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2213 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2214 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2215 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2216 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2217 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2218 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2219 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2220 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2221 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2222 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2223 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2224 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2225 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2226 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2227 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2228 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2229 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2230 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2231 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2232 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2233 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2234 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2235 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2236 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2237 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2238 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2239 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2240 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2241 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2242 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2243 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2244 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2245 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2246 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2247 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2248 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2249 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2250 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2251
2252 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2253
2254 /* Common functions */
2255 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2256 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2257 bool amdgpu_card_posted(struct amdgpu_device *adev);
2258 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2259 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2260 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2261 struct drm_file *filp,
2262 struct amdgpu_ctx *ctx,
2263 struct amdgpu_ib *ibs,
2264 uint32_t num_ibs);
2265
2266 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2267 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2268 u32 ip_instance, u32 ring,
2269 struct amdgpu_ring **out_ring);
2270 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2271 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2272 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2273 uint32_t flags);
2274 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2275 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2276 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2277 struct ttm_mem_reg *mem);
2278 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2279 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2280 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2281 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2282 const u32 *registers,
2283 const u32 array_size);
2284
2285 bool amdgpu_device_is_px(struct drm_device *dev);
2286 /* atpx handler */
2287 #if defined(CONFIG_VGA_SWITCHEROO)
2288 void amdgpu_register_atpx_handler(void);
2289 void amdgpu_unregister_atpx_handler(void);
2290 #else
2291 static inline void amdgpu_register_atpx_handler(void) {}
2292 static inline void amdgpu_unregister_atpx_handler(void) {}
2293 #endif
2294
2295 /*
2296 * KMS
2297 */
2298 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2299 extern int amdgpu_max_kms_ioctl;
2300
2301 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2302 int amdgpu_driver_unload_kms(struct drm_device *dev);
2303 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2304 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2305 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2306 struct drm_file *file_priv);
2307 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2308 struct drm_file *file_priv);
2309 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2310 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2311 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2312 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2313 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2314 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2315 int *max_error,
2316 struct timeval *vblank_time,
2317 unsigned flags);
2318 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2319 unsigned long arg);
2320
2321 /*
2322 * vm
2323 */
2324 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2325 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2326 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2327 struct amdgpu_vm *vm,
2328 struct list_head *head);
2329 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2330 struct amdgpu_sync *sync);
2331 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2332 struct amdgpu_vm *vm,
2333 struct fence *updates);
2334 void amdgpu_vm_fence(struct amdgpu_device *adev,
2335 struct amdgpu_vm *vm,
2336 struct amdgpu_fence *fence);
2337 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2338 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2339 struct amdgpu_vm *vm);
2340 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2341 struct amdgpu_vm *vm);
2342 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2343 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2344 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2345 struct amdgpu_bo_va *bo_va,
2346 struct ttm_mem_reg *mem);
2347 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2348 struct amdgpu_bo *bo);
2349 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2350 struct amdgpu_bo *bo);
2351 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2352 struct amdgpu_vm *vm,
2353 struct amdgpu_bo *bo);
2354 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2355 struct amdgpu_bo_va *bo_va,
2356 uint64_t addr, uint64_t offset,
2357 uint64_t size, uint32_t flags);
2358 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2359 struct amdgpu_bo_va *bo_va,
2360 uint64_t addr);
2361 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2362 struct amdgpu_bo_va *bo_va);
2363 int amdgpu_vm_free_job(struct amdgpu_job *job);
2364 /*
2365 * functions used by amdgpu_encoder.c
2366 */
2367 struct amdgpu_afmt_acr {
2368 u32 clock;
2369
2370 int n_32khz;
2371 int cts_32khz;
2372
2373 int n_44_1khz;
2374 int cts_44_1khz;
2375
2376 int n_48khz;
2377 int cts_48khz;
2378
2379 };
2380
2381 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2382
2383 /* amdgpu_acpi.c */
2384 #if defined(CONFIG_ACPI)
2385 int amdgpu_acpi_init(struct amdgpu_device *adev);
2386 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2387 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2388 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2389 u8 perf_req, bool advertise);
2390 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2391 #else
2392 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2393 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2394 #endif
2395
2396 struct amdgpu_bo_va_mapping *
2397 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2398 uint64_t addr, struct amdgpu_bo **bo);
2399
2400 #include "amdgpu_object.h"
2401
2402 #endif