2 * Driver for NEC VR4100 series General-purpose I/O Unit.
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/errno.h>
24 #include <linux/gpio.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/smp_lock.h>
33 #include <linux/spinlock.h>
34 #include <linux/types.h>
36 #include <asm/vr41xx/giu.h>
37 #include <asm/vr41xx/irq.h>
38 #include <asm/vr41xx/vr41xx.h>
40 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
41 MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
42 MODULE_LICENSE("GPL");
44 #define GIUIOSELL 0x00
45 #define GIUIOSELH 0x02
48 #define GIUINTSTATL 0x08
49 #define GIUINTSTATH 0x0a
50 #define GIUINTENL 0x0c
51 #define GIUINTENH 0x0e
52 #define GIUINTTYPL 0x10
53 #define GIUINTTYPH 0x12
54 #define GIUINTALSELL 0x14
55 #define GIUINTALSELH 0x16
56 #define GIUINTHTSELL 0x18
57 #define GIUINTHTSELH 0x1a
58 #define GIUPODATL 0x1c
59 #define GIUPODATEN 0x1c
60 #define GIUPODATH 0x1e
64 #define GIUFEDGEINHL 0x20
65 #define GIUFEDGEINHH 0x22
66 #define GIUREDGEINHL 0x24
67 #define GIUREDGEINHH 0x26
69 #define GIUUSEUPDN 0x1e0
70 #define GIUTERMUPDN 0x1e2
72 #define GPIO_HAS_PULLUPDOWN_IO 0x0001
73 #define GPIO_HAS_OUTPUT_ENABLE 0x0002
74 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
81 static DEFINE_SPINLOCK(giu_lock
);
82 static unsigned long giu_flags
;
84 static void __iomem
*giu_base
;
86 #define giu_read(offset) readw(giu_base + (offset))
87 #define giu_write(offset, value) writew((value), giu_base + (offset))
89 #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
90 #define GIUINT_HIGH_OFFSET 16
91 #define GIUINT_HIGH_MAX 32
93 static inline u16
giu_set(u16 offset
, u16 set
)
97 data
= giu_read(offset
);
99 giu_write(offset
, data
);
104 static inline u16
giu_clear(u16 offset
, u16 clear
)
108 data
= giu_read(offset
);
110 giu_write(offset
, data
);
115 static void ack_giuint_low(unsigned int irq
)
117 giu_write(GIUINTSTATL
, 1 << GPIO_PIN_OF_IRQ(irq
));
120 static void mask_giuint_low(unsigned int irq
)
122 giu_clear(GIUINTENL
, 1 << GPIO_PIN_OF_IRQ(irq
));
125 static void mask_ack_giuint_low(unsigned int irq
)
129 pin
= GPIO_PIN_OF_IRQ(irq
);
130 giu_clear(GIUINTENL
, 1 << pin
);
131 giu_write(GIUINTSTATL
, 1 << pin
);
134 static void unmask_giuint_low(unsigned int irq
)
136 giu_set(GIUINTENL
, 1 << GPIO_PIN_OF_IRQ(irq
));
139 static struct irq_chip giuint_low_irq_chip
= {
141 .ack
= ack_giuint_low
,
142 .mask
= mask_giuint_low
,
143 .mask_ack
= mask_ack_giuint_low
,
144 .unmask
= unmask_giuint_low
,
147 static void ack_giuint_high(unsigned int irq
)
149 giu_write(GIUINTSTATH
,
150 1 << (GPIO_PIN_OF_IRQ(irq
) - GIUINT_HIGH_OFFSET
));
153 static void mask_giuint_high(unsigned int irq
)
155 giu_clear(GIUINTENH
, 1 << (GPIO_PIN_OF_IRQ(irq
) - GIUINT_HIGH_OFFSET
));
158 static void mask_ack_giuint_high(unsigned int irq
)
162 pin
= GPIO_PIN_OF_IRQ(irq
) - GIUINT_HIGH_OFFSET
;
163 giu_clear(GIUINTENH
, 1 << pin
);
164 giu_write(GIUINTSTATH
, 1 << pin
);
167 static void unmask_giuint_high(unsigned int irq
)
169 giu_set(GIUINTENH
, 1 << (GPIO_PIN_OF_IRQ(irq
) - GIUINT_HIGH_OFFSET
));
172 static struct irq_chip giuint_high_irq_chip
= {
174 .ack
= ack_giuint_high
,
175 .mask
= mask_giuint_high
,
176 .mask_ack
= mask_ack_giuint_high
,
177 .unmask
= unmask_giuint_high
,
180 static int giu_get_irq(unsigned int irq
)
182 u16 pendl
, pendh
, maskl
, maskh
;
185 pendl
= giu_read(GIUINTSTATL
);
186 pendh
= giu_read(GIUINTSTATH
);
187 maskl
= giu_read(GIUINTENL
);
188 maskh
= giu_read(GIUINTENH
);
194 for (i
= 0; i
< 16; i
++) {
195 if (maskl
& (1 << i
))
199 for (i
= 0; i
< 16; i
++) {
200 if (maskh
& (1 << i
))
201 return GIU_IRQ(i
+ GIUINT_HIGH_OFFSET
);
205 printk(KERN_ERR
"spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
206 maskl
, pendl
, maskh
, pendh
);
208 atomic_inc(&irq_err_count
);
213 void vr41xx_set_irq_trigger(unsigned int pin
, irq_trigger_t trigger
,
218 if (pin
< GIUINT_HIGH_OFFSET
) {
220 if (trigger
!= IRQ_TRIGGER_LEVEL
) {
221 giu_set(GIUINTTYPL
, mask
);
222 if (signal
== IRQ_SIGNAL_HOLD
)
223 giu_set(GIUINTHTSELL
, mask
);
225 giu_clear(GIUINTHTSELL
, mask
);
226 if (giu_flags
& GPIO_HAS_INTERRUPT_EDGE_SELECT
) {
228 case IRQ_TRIGGER_EDGE_FALLING
:
229 giu_set(GIUFEDGEINHL
, mask
);
230 giu_clear(GIUREDGEINHL
, mask
);
232 case IRQ_TRIGGER_EDGE_RISING
:
233 giu_clear(GIUFEDGEINHL
, mask
);
234 giu_set(GIUREDGEINHL
, mask
);
237 giu_set(GIUFEDGEINHL
, mask
);
238 giu_set(GIUREDGEINHL
, mask
);
242 set_irq_chip_and_handler(GIU_IRQ(pin
),
243 &giuint_low_irq_chip
,
246 giu_clear(GIUINTTYPL
, mask
);
247 giu_clear(GIUINTHTSELL
, mask
);
248 set_irq_chip_and_handler(GIU_IRQ(pin
),
249 &giuint_low_irq_chip
,
252 giu_write(GIUINTSTATL
, mask
);
253 } else if (pin
< GIUINT_HIGH_MAX
) {
254 mask
= 1 << (pin
- GIUINT_HIGH_OFFSET
);
255 if (trigger
!= IRQ_TRIGGER_LEVEL
) {
256 giu_set(GIUINTTYPH
, mask
);
257 if (signal
== IRQ_SIGNAL_HOLD
)
258 giu_set(GIUINTHTSELH
, mask
);
260 giu_clear(GIUINTHTSELH
, mask
);
261 if (giu_flags
& GPIO_HAS_INTERRUPT_EDGE_SELECT
) {
263 case IRQ_TRIGGER_EDGE_FALLING
:
264 giu_set(GIUFEDGEINHH
, mask
);
265 giu_clear(GIUREDGEINHH
, mask
);
267 case IRQ_TRIGGER_EDGE_RISING
:
268 giu_clear(GIUFEDGEINHH
, mask
);
269 giu_set(GIUREDGEINHH
, mask
);
272 giu_set(GIUFEDGEINHH
, mask
);
273 giu_set(GIUREDGEINHH
, mask
);
277 set_irq_chip_and_handler(GIU_IRQ(pin
),
278 &giuint_high_irq_chip
,
281 giu_clear(GIUINTTYPH
, mask
);
282 giu_clear(GIUINTHTSELH
, mask
);
283 set_irq_chip_and_handler(GIU_IRQ(pin
),
284 &giuint_high_irq_chip
,
287 giu_write(GIUINTSTATH
, mask
);
290 EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger
);
292 void vr41xx_set_irq_level(unsigned int pin
, irq_level_t level
)
296 if (pin
< GIUINT_HIGH_OFFSET
) {
298 if (level
== IRQ_LEVEL_HIGH
)
299 giu_set(GIUINTALSELL
, mask
);
301 giu_clear(GIUINTALSELL
, mask
);
302 giu_write(GIUINTSTATL
, mask
);
303 } else if (pin
< GIUINT_HIGH_MAX
) {
304 mask
= 1 << (pin
- GIUINT_HIGH_OFFSET
);
305 if (level
== IRQ_LEVEL_HIGH
)
306 giu_set(GIUINTALSELH
, mask
);
308 giu_clear(GIUINTALSELH
, mask
);
309 giu_write(GIUINTSTATH
, mask
);
312 EXPORT_SYMBOL_GPL(vr41xx_set_irq_level
);
314 static int giu_set_direction(struct gpio_chip
*chip
, unsigned pin
, int dir
)
316 u16 offset
, mask
, reg
;
319 if (pin
>= chip
->ngpio
)
325 } else if (pin
< 32) {
327 mask
= 1 << (pin
- 16);
329 if (giu_flags
& GPIO_HAS_OUTPUT_ENABLE
) {
331 mask
= 1 << (pin
- 32);
348 spin_lock_irqsave(&giu_lock
, flags
);
350 reg
= giu_read(offset
);
351 if (dir
== GPIO_OUTPUT
)
355 giu_write(offset
, reg
);
357 spin_unlock_irqrestore(&giu_lock
, flags
);
362 int vr41xx_gpio_pullupdown(unsigned int pin
, gpio_pull_t pull
)
367 if ((giu_flags
& GPIO_HAS_PULLUPDOWN_IO
) != GPIO_HAS_PULLUPDOWN_IO
)
375 spin_lock_irqsave(&giu_lock
, flags
);
377 if (pull
== GPIO_PULL_UP
|| pull
== GPIO_PULL_DOWN
) {
378 reg
= giu_read(GIUTERMUPDN
);
379 if (pull
== GPIO_PULL_UP
)
383 giu_write(GIUTERMUPDN
, reg
);
385 reg
= giu_read(GIUUSEUPDN
);
387 giu_write(GIUUSEUPDN
, reg
);
389 reg
= giu_read(GIUUSEUPDN
);
391 giu_write(GIUUSEUPDN
, reg
);
394 spin_unlock_irqrestore(&giu_lock
, flags
);
398 EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown
);
400 static int vr41xx_gpio_get(struct gpio_chip
*chip
, unsigned pin
)
404 if (pin
>= chip
->ngpio
)
408 reg
= giu_read(GIUPIODL
);
410 } else if (pin
< 32) {
411 reg
= giu_read(GIUPIODH
);
412 mask
= 1 << (pin
- 16);
413 } else if (pin
< 48) {
414 reg
= giu_read(GIUPODATL
);
415 mask
= 1 << (pin
- 32);
417 reg
= giu_read(GIUPODATH
);
418 mask
= 1 << (pin
- 48);
427 static void vr41xx_gpio_set(struct gpio_chip
*chip
, unsigned pin
,
430 u16 offset
, mask
, reg
;
433 if (pin
>= chip
->ngpio
)
439 } else if (pin
< 32) {
441 mask
= 1 << (pin
- 16);
442 } else if (pin
< 48) {
444 mask
= 1 << (pin
- 32);
447 mask
= 1 << (pin
- 48);
450 spin_lock_irqsave(&giu_lock
, flags
);
452 reg
= giu_read(offset
);
457 giu_write(offset
, reg
);
459 spin_unlock_irqrestore(&giu_lock
, flags
);
463 static int vr41xx_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
465 return giu_set_direction(chip
, offset
, GPIO_INPUT
);
468 static int vr41xx_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
471 vr41xx_gpio_set(chip
, offset
, value
);
473 return giu_set_direction(chip
, offset
, GPIO_OUTPUT
);
476 static int vr41xx_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
478 if (offset
>= chip
->ngpio
)
481 return GIU_IRQ_BASE
+ offset
;
484 static struct gpio_chip vr41xx_gpio_chip
= {
486 .owner
= THIS_MODULE
,
487 .direction_input
= vr41xx_gpio_direction_input
,
488 .get
= vr41xx_gpio_get
,
489 .direction_output
= vr41xx_gpio_direction_output
,
490 .set
= vr41xx_gpio_set
,
491 .to_irq
= vr41xx_gpio_to_irq
,
494 static int __devinit
giu_probe(struct platform_device
*pdev
)
496 struct resource
*res
;
497 unsigned int trigger
, i
, pin
;
498 struct irq_chip
*chip
;
502 case GPIO_50PINS_PULLUPDOWN
:
503 giu_flags
= GPIO_HAS_PULLUPDOWN_IO
;
504 vr41xx_gpio_chip
.ngpio
= 50;
507 vr41xx_gpio_chip
.ngpio
= 36;
509 case GPIO_48PINS_EDGE_SELECT
:
510 giu_flags
= GPIO_HAS_INTERRUPT_EDGE_SELECT
;
511 vr41xx_gpio_chip
.ngpio
= 48;
514 dev_err(&pdev
->dev
, "GIU: unknown ID %d\n", pdev
->id
);
518 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
522 giu_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
526 vr41xx_gpio_chip
.dev
= &pdev
->dev
;
528 retval
= gpiochip_add(&vr41xx_gpio_chip
);
530 giu_write(GIUINTENL
, 0);
531 giu_write(GIUINTENH
, 0);
533 trigger
= giu_read(GIUINTTYPH
) << 16;
534 trigger
|= giu_read(GIUINTTYPL
);
535 for (i
= GIU_IRQ_BASE
; i
<= GIU_IRQ_LAST
; i
++) {
536 pin
= GPIO_PIN_OF_IRQ(i
);
537 if (pin
< GIUINT_HIGH_OFFSET
)
538 chip
= &giuint_low_irq_chip
;
540 chip
= &giuint_high_irq_chip
;
542 if (trigger
& (1 << pin
))
543 set_irq_chip_and_handler(i
, chip
, handle_edge_irq
);
545 set_irq_chip_and_handler(i
, chip
, handle_level_irq
);
549 irq
= platform_get_irq(pdev
, 0);
550 if (irq
< 0 || irq
>= nr_irqs
)
553 return cascade_irq(irq
, giu_get_irq
);
556 static int __devexit
giu_remove(struct platform_device
*pdev
)
566 static struct platform_driver giu_device_driver
= {
568 .remove
= __devexit_p(giu_remove
),
571 .owner
= THIS_MODULE
,
575 static int __init
vr41xx_giu_init(void)
577 return platform_driver_register(&giu_device_driver
);
580 static void __exit
vr41xx_giu_exit(void)
582 platform_driver_unregister(&giu_device_driver
);
585 module_init(vr41xx_giu_init
);
586 module_exit(vr41xx_giu_exit
);