drivers/gpio/langwell_gpio.c

   1 /* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
   2  * Copyright (c) 2008 - 2009,  Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16  */
  17
  18 /* Supports:
  19  * Moorestown platform Langwell chip.
  20  * Medfield platform Penwell chip.
  21  * Whitney point.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/stddef.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/init.h>
  32 #include <linux/irq.h>
  33 #include <linux/io.h>
  34 #include <linux/gpio.h>
  35 #include <linux/slab.h>
  36
  37 /*
  38  * Langwell chip has 64 pins and thus there are 2 32bit registers to control
  39  * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
  40  * registers to control them, so we only define the order here instead of a
  41  * structure, to get a bit offset for a pin (use GPDR as an example):
  42  *
  43  * nreg = ngpio / 32;
  44  * reg = offset / 32;
  45  * bit = offset % 32;
  46  * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
  47  *
  48  * so the bit of reg_addr is to control pin offset's GPDR feature
  49 */
  50
  51 enum GPIO_REG {
  52         GPLR = 0,       /* pin level read-only */
  53         GPDR,           /* pin direction */
  54         GPSR,           /* pin set */
  55         GPCR,           /* pin clear */
  56         GRER,           /* rising edge detect */
  57         GFER,           /* falling edge detect */
  58         GEDR,           /* edge detect result */
  59 };
  60
  61 struct lnw_gpio {
  62         struct gpio_chip                chip;
  63         void                            *reg_base;
  64         spinlock_t                      lock;
  65         unsigned                        irq_base;
  66 };
  67
  68 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
  69                         enum GPIO_REG reg_type)
  70 {
  71         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
  72         unsigned nreg = chip->ngpio / 32;
  73         u8 reg = offset / 32;
  74         void __iomem *ptr;
  75
  76         ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
  77         return ptr;
  78 }
  79
  80 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
  81 {
  82         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  83
  84         return readl(gplr) & BIT(offset % 32);
  85 }
  86
  87 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  88 {
  89         void __iomem *gpsr, *gpcr;
  90
  91         if (value) {
  92                 gpsr = gpio_reg(chip, offset, GPSR);
  93                 writel(BIT(offset % 32), gpsr);
  94         } else {
  95                 gpcr = gpio_reg(chip, offset, GPCR);
  96                 writel(BIT(offset % 32), gpcr);
  97         }
  98 }
  99
 100 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 101 {
 102         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
 103         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 104         u32 value;
 105         unsigned long flags;
 106
 107         spin_lock_irqsave(&lnw->lock, flags);
 108         value = readl(gpdr);
 109         value &= ~BIT(offset % 32);
 110         writel(value, gpdr);
 111         spin_unlock_irqrestore(&lnw->lock, flags);
 112         return 0;
 113 }
 114
 115 static int lnw_gpio_direction_output(struct gpio_chip *chip,
 116                         unsigned offset, int value)
 117 {
 118         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
 119         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 120         unsigned long flags;
 121
 122         lnw_gpio_set(chip, offset, value);
 123         spin_lock_irqsave(&lnw->lock, flags);
 124         value = readl(gpdr);
 125         value |= BIT(offset % 32);
 126         writel(value, gpdr);
 127         spin_unlock_irqrestore(&lnw->lock, flags);
 128         return 0;
 129 }
 130
 131 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 132 {
 133         struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
 134         return lnw->irq_base + offset;
 135 }
 136
 137 static int lnw_irq_type(struct irq_data *d, unsigned type)
 138 {
 139         struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
 140         u32 gpio = d->irq - lnw->irq_base;
 141         unsigned long flags;
 142         u32 value;
 143         void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
 144         void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
 145
 146         if (gpio >= lnw->chip.ngpio)
 147                 return -EINVAL;
 148         spin_lock_irqsave(&lnw->lock, flags);
 149         if (type & IRQ_TYPE_EDGE_RISING)
 150                 value = readl(grer) | BIT(gpio % 32);
 151         else
 152                 value = readl(grer) & (~BIT(gpio % 32));
 153         writel(value, grer);
 154
 155         if (type & IRQ_TYPE_EDGE_FALLING)
 156                 value = readl(gfer) | BIT(gpio % 32);
 157         else
 158                 value = readl(gfer) & (~BIT(gpio % 32));
 159         writel(value, gfer);
 160         spin_unlock_irqrestore(&lnw->lock, flags);
 161
 162         return 0;
 163 }
 164
 165 static void lnw_irq_unmask(struct irq_data *d)
 166 {
 167 }
 168
 169 static void lnw_irq_mask(struct irq_data *d)
 170 {
 171 }
 172
 173 static struct irq_chip lnw_irqchip = {
 174         .name           = "LNW-GPIO",
 175         .irq_mask       = lnw_irq_mask,
 176         .irq_unmask     = lnw_irq_unmask,
 177         .irq_set_type   = lnw_irq_type,
 178 };
 179
 180 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {   /* pin number */
 181         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
 182         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
 183         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
 184         { 0, }
 185 };
 186 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
 187
 188 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
 189 {
 190         struct irq_data *data = irq_desc_get_irq_data(desc);
 191         struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
 192         struct irq_chip *chip = irq_data_get_irq_chip(data);
 193         u32 base, gpio, mask;
 194         unsigned long pending;
 195         void __iomem *gedr;
 196
 197         /* check GPIO controller to check which pin triggered the interrupt */
 198         for (base = 0; base < lnw->chip.ngpio; base += 32) {
 199                 gedr = gpio_reg(&lnw->chip, base, GEDR);
 200                 pending = readl(gedr);
 201                 while (pending) {
 202                         gpio = __ffs(pending) - 1;
 203                         mask = BIT(gpio);
 204                         pending &= ~mask;
 205                         /* Clear before handling so we can't lose an edge */
 206                         writel(mask, gedr);
 207                         generic_handle_irq(lnw->irq_base + base + gpio);
 208                 }
 209         }
 210
 211         chip->irq_eoi(data);
 212 }
 213
 214 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
 215                         const struct pci_device_id *id)
 216 {
 217         void *base;
 218         int i;
 219         resource_size_t start, len;
 220         struct lnw_gpio *lnw;
 221         u32 irq_base;
 222         u32 gpio_base;
 223         int retval = 0;
 224
 225         retval = pci_enable_device(pdev);
 226         if (retval)
 227                 goto done;
 228
 229         retval = pci_request_regions(pdev, "langwell_gpio");
 230         if (retval) {
 231                 dev_err(&pdev->dev, "error requesting resources\n");
 232                 goto err2;
 233         }
 234         /* get the irq_base from bar1 */
 235         start = pci_resource_start(pdev, 1);
 236         len = pci_resource_len(pdev, 1);
 237         base = ioremap_nocache(start, len);
 238         if (!base) {
 239                 dev_err(&pdev->dev, "error mapping bar1\n");
 240                 goto err3;
 241         }
 242         irq_base = *(u32 *)base;
 243         gpio_base = *((u32 *)base + 1);
 244         /* release the IO mapping, since we already get the info from bar1 */
 245         iounmap(base);
 246         /* get the register base from bar0 */
 247         start = pci_resource_start(pdev, 0);
 248         len = pci_resource_len(pdev, 0);
 249         base = ioremap_nocache(start, len);
 250         if (!base) {
 251                 dev_err(&pdev->dev, "error mapping bar0\n");
 252                 retval = -EFAULT;
 253                 goto err3;
 254         }
 255
 256         lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
 257         if (!lnw) {
 258                 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
 259                 retval = -ENOMEM;
 260                 goto err4;
 261         }
 262         lnw->reg_base = base;
 263         lnw->irq_base = irq_base;
 264         lnw->chip.label = dev_name(&pdev->dev);
 265         lnw->chip.direction_input = lnw_gpio_direction_input;
 266         lnw->chip.direction_output = lnw_gpio_direction_output;
 267         lnw->chip.get = lnw_gpio_get;
 268         lnw->chip.set = lnw_gpio_set;
 269         lnw->chip.to_irq = lnw_gpio_to_irq;
 270         lnw->chip.base = gpio_base;
 271         lnw->chip.ngpio = id->driver_data;
 272         lnw->chip.can_sleep = 0;
 273         pci_set_drvdata(pdev, lnw);
 274         retval = gpiochip_add(&lnw->chip);
 275         if (retval) {
 276                 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
 277                 goto err5;
 278         }
 279         irq_set_handler_data(pdev->irq, lnw);
 280         irq_set_chained_handler(pdev->irq, lnw_irq_handler);
 281         for (i = 0; i < lnw->chip.ngpio; i++) {
 282                 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
 283                                               handle_simple_irq, "demux");
 284                 irq_set_chip_data(i + lnw->irq_base, lnw);
 285         }
 286
 287         spin_lock_init(&lnw->lock);
 288         goto done;
 289 err5:
 290         kfree(lnw);
 291 err4:
 292         iounmap(base);
 293 err3:
 294         pci_release_regions(pdev);
 295 err2:
 296         pci_disable_device(pdev);
 297 done:
 298         return retval;
 299 }
 300
 301 static struct pci_driver lnw_gpio_driver = {
 302         .name           = "langwell_gpio",
 303         .id_table       = lnw_gpio_ids,
 304         .probe          = lnw_gpio_probe,
 305 };
 306
 307
 308 static int __devinit wp_gpio_probe(struct platform_device *pdev)
 309 {
 310         struct lnw_gpio *lnw;
 311         struct gpio_chip *gc;
 312         struct resource *rc;
 313         int retval = 0;
 314
 315         rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 316         if (!rc)
 317                 return -EINVAL;
 318
 319         lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
 320         if (!lnw) {
 321                 dev_err(&pdev->dev,
 322                         "can't allocate whitneypoint_gpio chip data\n");
 323                 return -ENOMEM;
 324         }
 325         lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
 326         if (lnw->reg_base == NULL) {
 327                 retval = -EINVAL;
 328                 goto err_kmalloc;
 329         }
 330         spin_lock_init(&lnw->lock);
 331         gc = &lnw->chip;
 332         gc->label = dev_name(&pdev->dev);
 333         gc->owner = THIS_MODULE;
 334         gc->direction_input = lnw_gpio_direction_input;
 335         gc->direction_output = lnw_gpio_direction_output;
 336         gc->get = lnw_gpio_get;
 337         gc->set = lnw_gpio_set;
 338         gc->to_irq = NULL;
 339         gc->base = 0;
 340         gc->ngpio = 64;
 341         gc->can_sleep = 0;
 342         retval = gpiochip_add(gc);
 343         if (retval) {
 344                 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
 345                                                                 retval);
 346                 goto err_ioremap;
 347         }
 348         platform_set_drvdata(pdev, lnw);
 349         return 0;
 350 err_ioremap:
 351         iounmap(lnw->reg_base);
 352 err_kmalloc:
 353         kfree(lnw);
 354         return retval;
 355 }
 356
 357 static int __devexit wp_gpio_remove(struct platform_device *pdev)
 358 {
 359         struct lnw_gpio *lnw = platform_get_drvdata(pdev);
 360         int err;
 361         err = gpiochip_remove(&lnw->chip);
 362         if (err)
 363                 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
 364         iounmap(lnw->reg_base);
 365         kfree(lnw);
 366         platform_set_drvdata(pdev, NULL);
 367         return 0;
 368 }
 369
 370 static struct platform_driver wp_gpio_driver = {
 371         .probe          = wp_gpio_probe,
 372         .remove         = __devexit_p(wp_gpio_remove),
 373         .driver         = {
 374                 .name   = "wp_gpio",
 375                 .owner  = THIS_MODULE,
 376         },
 377 };
 378
 379 static int __init lnw_gpio_init(void)
 380 {
 381         int ret;
 382         ret =  pci_register_driver(&lnw_gpio_driver);
 383         if (ret < 0)
 384                 return ret;
 385         ret = platform_driver_register(&wp_gpio_driver);
 386         if (ret < 0)
 387                 pci_unregister_driver(&lnw_gpio_driver);
 388         return ret;
 389 }
 390
 391 device_initcall(lnw_gpio_init);