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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-pxa.c
1 /*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio-pxa.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/slab.h>
29
30 #include <mach/irqs.h>
31
32 /*
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
35 *
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 *
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
44 *
45 * NOTE:
46 * BANK 3 is only available on PXA27x and later processors.
47 * BANK 4 and 5 are only available on PXA935
48 */
49
50 #define GPLR_OFFSET 0x00
51 #define GPDR_OFFSET 0x0C
52 #define GPSR_OFFSET 0x18
53 #define GPCR_OFFSET 0x24
54 #define GRER_OFFSET 0x30
55 #define GFER_OFFSET 0x3C
56 #define GEDR_OFFSET 0x48
57 #define GAFR_OFFSET 0x54
58 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59
60 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
61
62 int pxa_last_gpio;
63 static int irq_base;
64
65 #ifdef CONFIG_OF
66 static struct irq_domain *domain;
67 static struct device_node *pxa_gpio_of_node;
68 #endif
69
70 struct pxa_gpio_chip {
71 struct gpio_chip chip;
72 void __iomem *regbase;
73 char label[10];
74
75 unsigned long irq_mask;
76 unsigned long irq_edge_rise;
77 unsigned long irq_edge_fall;
78 int (*set_wake)(unsigned int gpio, unsigned int on);
79
80 #ifdef CONFIG_PM
81 unsigned long saved_gplr;
82 unsigned long saved_gpdr;
83 unsigned long saved_grer;
84 unsigned long saved_gfer;
85 #endif
86 };
87
88 enum {
89 PXA25X_GPIO = 0,
90 PXA26X_GPIO,
91 PXA27X_GPIO,
92 PXA3XX_GPIO,
93 PXA93X_GPIO,
94 MMP_GPIO = 0x10,
95 };
96
97 static DEFINE_SPINLOCK(gpio_lock);
98 static struct pxa_gpio_chip *pxa_gpio_chips;
99 static int gpio_type;
100 static void __iomem *gpio_reg_base;
101
102 #define for_each_gpio_chip(i, c) \
103 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
104
105 static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
106 {
107 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
108 }
109
110 static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
111 {
112 return &pxa_gpio_chips[gpio_to_bank(gpio)];
113 }
114
115 static inline int gpio_is_pxa_type(int type)
116 {
117 return (type & MMP_GPIO) == 0;
118 }
119
120 static inline int gpio_is_mmp_type(int type)
121 {
122 return (type & MMP_GPIO) != 0;
123 }
124
125 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
126 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
127 */
128 static inline int __gpio_is_inverted(int gpio)
129 {
130 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
131 return 1;
132 return 0;
133 }
134
135 /*
136 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
137 * function of a GPIO, and GPDRx cannot be altered once configured. It
138 * is attributed as "occupied" here (I know this terminology isn't
139 * accurate, you are welcome to propose a better one :-)
140 */
141 static inline int __gpio_is_occupied(unsigned gpio)
142 {
143 struct pxa_gpio_chip *pxachip;
144 void __iomem *base;
145 unsigned long gafr = 0, gpdr = 0;
146 int ret, af = 0, dir = 0;
147
148 pxachip = gpio_to_pxachip(gpio);
149 base = gpio_chip_base(&pxachip->chip);
150 gpdr = readl_relaxed(base + GPDR_OFFSET);
151
152 switch (gpio_type) {
153 case PXA25X_GPIO:
154 case PXA26X_GPIO:
155 case PXA27X_GPIO:
156 gafr = readl_relaxed(base + GAFR_OFFSET);
157 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
158 dir = gpdr & GPIO_bit(gpio);
159
160 if (__gpio_is_inverted(gpio))
161 ret = (af != 1) || (dir == 0);
162 else
163 ret = (af != 0) || (dir != 0);
164 break;
165 default:
166 ret = gpdr & GPIO_bit(gpio);
167 break;
168 }
169 return ret;
170 }
171
172 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
173 {
174 return chip->base + offset + irq_base;
175 }
176
177 int pxa_irq_to_gpio(int irq)
178 {
179 return irq - irq_base;
180 }
181
182 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
183 {
184 void __iomem *base = gpio_chip_base(chip);
185 uint32_t value, mask = 1 << offset;
186 unsigned long flags;
187
188 spin_lock_irqsave(&gpio_lock, flags);
189
190 value = readl_relaxed(base + GPDR_OFFSET);
191 if (__gpio_is_inverted(chip->base + offset))
192 value |= mask;
193 else
194 value &= ~mask;
195 writel_relaxed(value, base + GPDR_OFFSET);
196
197 spin_unlock_irqrestore(&gpio_lock, flags);
198 return 0;
199 }
200
201 static int pxa_gpio_direction_output(struct gpio_chip *chip,
202 unsigned offset, int value)
203 {
204 void __iomem *base = gpio_chip_base(chip);
205 uint32_t tmp, mask = 1 << offset;
206 unsigned long flags;
207
208 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
209
210 spin_lock_irqsave(&gpio_lock, flags);
211
212 tmp = readl_relaxed(base + GPDR_OFFSET);
213 if (__gpio_is_inverted(chip->base + offset))
214 tmp &= ~mask;
215 else
216 tmp |= mask;
217 writel_relaxed(tmp, base + GPDR_OFFSET);
218
219 spin_unlock_irqrestore(&gpio_lock, flags);
220 return 0;
221 }
222
223 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
224 {
225 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
226 }
227
228 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
229 {
230 writel_relaxed(1 << offset, gpio_chip_base(chip) +
231 (value ? GPSR_OFFSET : GPCR_OFFSET));
232 }
233
234 #ifdef CONFIG_OF_GPIO
235 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
236 const struct of_phandle_args *gpiospec,
237 u32 *flags)
238 {
239 if (gpiospec->args[0] > pxa_last_gpio)
240 return -EINVAL;
241
242 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
243 return -EINVAL;
244
245 if (flags)
246 *flags = gpiospec->args[1];
247
248 return gpiospec->args[0] % 32;
249 }
250 #endif
251
252 static int pxa_init_gpio_chip(int gpio_end,
253 int (*set_wake)(unsigned int, unsigned int))
254 {
255 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
256 struct pxa_gpio_chip *chips;
257
258 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
259 if (chips == NULL) {
260 pr_err("%s: failed to allocate GPIO chips\n", __func__);
261 return -ENOMEM;
262 }
263
264 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
265 struct gpio_chip *c = &chips[i].chip;
266
267 sprintf(chips[i].label, "gpio-%d", i);
268 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
269 chips[i].set_wake = set_wake;
270
271 c->base = gpio;
272 c->label = chips[i].label;
273
274 c->direction_input = pxa_gpio_direction_input;
275 c->direction_output = pxa_gpio_direction_output;
276 c->get = pxa_gpio_get;
277 c->set = pxa_gpio_set;
278 c->to_irq = pxa_gpio_to_irq;
279 #ifdef CONFIG_OF_GPIO
280 c->of_node = pxa_gpio_of_node;
281 c->of_xlate = pxa_gpio_of_xlate;
282 c->of_gpio_n_cells = 2;
283 #endif
284
285 /* number of GPIOs on last bank may be less than 32 */
286 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
287 gpiochip_add(c);
288 }
289 pxa_gpio_chips = chips;
290 return 0;
291 }
292
293 /* Update only those GRERx and GFERx edge detection register bits if those
294 * bits are set in c->irq_mask
295 */
296 static inline void update_edge_detect(struct pxa_gpio_chip *c)
297 {
298 uint32_t grer, gfer;
299
300 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
301 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
302 grer |= c->irq_edge_rise & c->irq_mask;
303 gfer |= c->irq_edge_fall & c->irq_mask;
304 writel_relaxed(grer, c->regbase + GRER_OFFSET);
305 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
306 }
307
308 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
309 {
310 struct pxa_gpio_chip *c;
311 int gpio = pxa_irq_to_gpio(d->irq);
312 unsigned long gpdr, mask = GPIO_bit(gpio);
313
314 c = gpio_to_pxachip(gpio);
315
316 if (type == IRQ_TYPE_PROBE) {
317 /* Don't mess with enabled GPIOs using preconfigured edges or
318 * GPIOs set to alternate function or to output during probe
319 */
320 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
321 return 0;
322
323 if (__gpio_is_occupied(gpio))
324 return 0;
325
326 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
327 }
328
329 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
330
331 if (__gpio_is_inverted(gpio))
332 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
333 else
334 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
335
336 if (type & IRQ_TYPE_EDGE_RISING)
337 c->irq_edge_rise |= mask;
338 else
339 c->irq_edge_rise &= ~mask;
340
341 if (type & IRQ_TYPE_EDGE_FALLING)
342 c->irq_edge_fall |= mask;
343 else
344 c->irq_edge_fall &= ~mask;
345
346 update_edge_detect(c);
347
348 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
349 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
350 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
351 return 0;
352 }
353
354 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
355 {
356 struct pxa_gpio_chip *c;
357 int loop, gpio, gpio_base, n;
358 unsigned long gedr;
359 struct irq_chip *chip = irq_desc_get_chip(desc);
360
361 chained_irq_enter(chip, desc);
362
363 do {
364 loop = 0;
365 for_each_gpio_chip(gpio, c) {
366 gpio_base = c->chip.base;
367
368 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
369 gedr = gedr & c->irq_mask;
370 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
371
372 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
373 loop = 1;
374
375 generic_handle_irq(gpio_to_irq(gpio_base + n));
376 }
377 }
378 } while (loop);
379
380 chained_irq_exit(chip, desc);
381 }
382
383 static void pxa_ack_muxed_gpio(struct irq_data *d)
384 {
385 int gpio = pxa_irq_to_gpio(d->irq);
386 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
387
388 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
389 }
390
391 static void pxa_mask_muxed_gpio(struct irq_data *d)
392 {
393 int gpio = pxa_irq_to_gpio(d->irq);
394 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
395 uint32_t grer, gfer;
396
397 c->irq_mask &= ~GPIO_bit(gpio);
398
399 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
400 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
401 writel_relaxed(grer, c->regbase + GRER_OFFSET);
402 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
403 }
404
405 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
406 {
407 int gpio = pxa_irq_to_gpio(d->irq);
408 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
409
410 if (c->set_wake)
411 return c->set_wake(gpio, on);
412 else
413 return 0;
414 }
415
416 static void pxa_unmask_muxed_gpio(struct irq_data *d)
417 {
418 int gpio = pxa_irq_to_gpio(d->irq);
419 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
420
421 c->irq_mask |= GPIO_bit(gpio);
422 update_edge_detect(c);
423 }
424
425 static struct irq_chip pxa_muxed_gpio_chip = {
426 .name = "GPIO",
427 .irq_ack = pxa_ack_muxed_gpio,
428 .irq_mask = pxa_mask_muxed_gpio,
429 .irq_unmask = pxa_unmask_muxed_gpio,
430 .irq_set_type = pxa_gpio_irq_type,
431 .irq_set_wake = pxa_gpio_set_wake,
432 };
433
434 static int pxa_gpio_nums(void)
435 {
436 int count = 0;
437
438 #ifdef CONFIG_ARCH_PXA
439 if (cpu_is_pxa25x()) {
440 #ifdef CONFIG_CPU_PXA26x
441 count = 89;
442 gpio_type = PXA26X_GPIO;
443 #elif defined(CONFIG_PXA25x)
444 count = 84;
445 gpio_type = PXA26X_GPIO;
446 #endif /* CONFIG_CPU_PXA26x */
447 } else if (cpu_is_pxa27x()) {
448 count = 120;
449 gpio_type = PXA27X_GPIO;
450 } else if (cpu_is_pxa93x()) {
451 count = 191;
452 gpio_type = PXA93X_GPIO;
453 } else if (cpu_is_pxa3xx()) {
454 count = 127;
455 gpio_type = PXA3XX_GPIO;
456 }
457 #endif /* CONFIG_ARCH_PXA */
458
459 #ifdef CONFIG_ARCH_MMP
460 if (cpu_is_pxa168() || cpu_is_pxa910()) {
461 count = 127;
462 gpio_type = MMP_GPIO;
463 } else if (cpu_is_mmp2()) {
464 count = 191;
465 gpio_type = MMP_GPIO;
466 }
467 #endif /* CONFIG_ARCH_MMP */
468 return count;
469 }
470
471 #ifdef CONFIG_OF
472 static struct of_device_id pxa_gpio_dt_ids[] = {
473 { .compatible = "mrvl,pxa-gpio" },
474 { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
475 {}
476 };
477
478 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
479 irq_hw_number_t hw)
480 {
481 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
482 handle_edge_irq);
483 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
484 return 0;
485 }
486
487 const struct irq_domain_ops pxa_irq_domain_ops = {
488 .map = pxa_irq_domain_map,
489 .xlate = irq_domain_xlate_twocell,
490 };
491
492 static int pxa_gpio_probe_dt(struct platform_device *pdev)
493 {
494 int ret, nr_banks, nr_gpios;
495 struct device_node *prev, *next, *np = pdev->dev.of_node;
496 const struct of_device_id *of_id =
497 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
498
499 if (!of_id) {
500 dev_err(&pdev->dev, "Failed to find gpio controller\n");
501 return -EFAULT;
502 }
503 gpio_type = (int)of_id->data;
504
505 next = of_get_next_child(np, NULL);
506 prev = next;
507 if (!next) {
508 dev_err(&pdev->dev, "Failed to find child gpio node\n");
509 ret = -EINVAL;
510 goto err;
511 }
512 for (nr_banks = 1; ; nr_banks++) {
513 next = of_get_next_child(np, prev);
514 if (!next)
515 break;
516 prev = next;
517 }
518 of_node_put(prev);
519 nr_gpios = nr_banks << 5;
520 pxa_last_gpio = nr_gpios - 1;
521
522 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
523 if (irq_base < 0) {
524 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
525 goto err;
526 }
527 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
528 &pxa_irq_domain_ops, NULL);
529 pxa_gpio_of_node = np;
530 return 0;
531 err:
532 iounmap(gpio_reg_base);
533 return ret;
534 }
535 #else
536 #define pxa_gpio_probe_dt(pdev) (-1)
537 #endif
538
539 static int pxa_gpio_probe(struct platform_device *pdev)
540 {
541 struct pxa_gpio_chip *c;
542 struct resource *res;
543 struct clk *clk;
544 struct pxa_gpio_platform_data *info;
545 int gpio, irq, ret, use_of = 0;
546 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
547
548 ret = pxa_gpio_probe_dt(pdev);
549 if (ret < 0) {
550 pxa_last_gpio = pxa_gpio_nums();
551 #ifdef CONFIG_ARCH_PXA
552 if (gpio_is_pxa_type(gpio_type))
553 irq_base = PXA_GPIO_TO_IRQ(0);
554 #endif
555 #ifdef CONFIG_ARCH_MMP
556 if (gpio_is_mmp_type(gpio_type))
557 irq_base = MMP_GPIO_TO_IRQ(0);
558 #endif
559 } else {
560 use_of = 1;
561 }
562
563 if (!pxa_last_gpio)
564 return -EINVAL;
565
566 irq0 = platform_get_irq_byname(pdev, "gpio0");
567 irq1 = platform_get_irq_byname(pdev, "gpio1");
568 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
569 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
570 || (irq_mux <= 0))
571 return -EINVAL;
572 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
573 if (!res)
574 return -EINVAL;
575 gpio_reg_base = ioremap(res->start, resource_size(res));
576 if (!gpio_reg_base)
577 return -EINVAL;
578
579 if (irq0 > 0)
580 gpio_offset = 2;
581
582 clk = clk_get(&pdev->dev, NULL);
583 if (IS_ERR(clk)) {
584 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
585 PTR_ERR(clk));
586 iounmap(gpio_reg_base);
587 return PTR_ERR(clk);
588 }
589 ret = clk_prepare_enable(clk);
590 if (ret) {
591 clk_put(clk);
592 iounmap(gpio_reg_base);
593 return ret;
594 }
595
596 /* Initialize GPIO chips */
597 info = dev_get_platdata(&pdev->dev);
598 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
599
600 /* clear all GPIO edge detects */
601 for_each_gpio_chip(gpio, c) {
602 writel_relaxed(0, c->regbase + GFER_OFFSET);
603 writel_relaxed(0, c->regbase + GRER_OFFSET);
604 writel_relaxed(~0,c->regbase + GEDR_OFFSET);
605 /* unmask GPIO edge detect for AP side */
606 if (gpio_is_mmp_type(gpio_type))
607 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
608 }
609
610 if (!use_of) {
611 #ifdef CONFIG_ARCH_PXA
612 irq = gpio_to_irq(0);
613 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
614 handle_edge_irq);
615 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
616 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
617
618 irq = gpio_to_irq(1);
619 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
620 handle_edge_irq);
621 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
622 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
623 #endif
624
625 for (irq = gpio_to_irq(gpio_offset);
626 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
627 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
628 handle_edge_irq);
629 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
630 }
631 }
632
633 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
634 return 0;
635 }
636
637 static struct platform_driver pxa_gpio_driver = {
638 .probe = pxa_gpio_probe,
639 .driver = {
640 .name = "pxa-gpio",
641 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
642 },
643 };
644
645 static int __init pxa_gpio_init(void)
646 {
647 return platform_driver_register(&pxa_gpio_driver);
648 }
649 postcore_initcall(pxa_gpio_init);
650
651 #ifdef CONFIG_PM
652 static int pxa_gpio_suspend(void)
653 {
654 struct pxa_gpio_chip *c;
655 int gpio;
656
657 for_each_gpio_chip(gpio, c) {
658 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
659 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
660 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
661 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
662
663 /* Clear GPIO transition detect bits */
664 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
665 }
666 return 0;
667 }
668
669 static void pxa_gpio_resume(void)
670 {
671 struct pxa_gpio_chip *c;
672 int gpio;
673
674 for_each_gpio_chip(gpio, c) {
675 /* restore level with set/clear */
676 writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
677 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
678
679 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
680 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
681 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
682 }
683 }
684 #else
685 #define pxa_gpio_suspend NULL
686 #define pxa_gpio_resume NULL
687 #endif
688
689 struct syscore_ops pxa_gpio_syscore_ops = {
690 .suspend = pxa_gpio_suspend,
691 .resume = pxa_gpio_resume,
692 };
693
694 static int __init pxa_gpio_sysinit(void)
695 {
696 register_syscore_ops(&pxa_gpio_syscore_ops);
697 return 0;
698 }
699 postcore_initcall(pxa_gpio_sysinit);
kernel source for telekom puls (alcatel/mediatek)