drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/basic_mmio_gpio.h>
  31 #include <linux/module.h>
  32 #include <mach/mxs.h>
  33
  34 #define MXS_SET         0x4
  35 #define MXS_CLR         0x8
  36
  37 #define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
  38 #define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
  39 #define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
  40 #define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
  41 #define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
  42 #define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
  43 #define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
  44 #define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
  45
  46 #define GPIO_INT_FALL_EDGE      0x0
  47 #define GPIO_INT_LOW_LEV        0x1
  48 #define GPIO_INT_RISE_EDGE      0x2
  49 #define GPIO_INT_HIGH_LEV       0x3
  50 #define GPIO_INT_LEV_MASK       (1 << 0)
  51 #define GPIO_INT_POL_MASK       (1 << 1)
  52
  53 #define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
  54
  55 struct mxs_gpio_port {
  56         void __iomem *base;
  57         int id;
  58         int irq;
  59         int virtual_irq_start;
  60         struct bgpio_chip bgc;
  61 };
  62
  63 /* Note: This driver assumes 32 GPIOs are handled in one register */
  64
  65 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  66 {
  67         u32 gpio = irq_to_gpio(d->irq);
  68         u32 pin_mask = 1 << (gpio & 31);
  69         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  70         struct mxs_gpio_port *port = gc->private;
  71         void __iomem *pin_addr;
  72         int edge;
  73
  74         switch (type) {
  75         case IRQ_TYPE_EDGE_RISING:
  76                 edge = GPIO_INT_RISE_EDGE;
  77                 break;
  78         case IRQ_TYPE_EDGE_FALLING:
  79                 edge = GPIO_INT_FALL_EDGE;
  80                 break;
  81         case IRQ_TYPE_LEVEL_LOW:
  82                 edge = GPIO_INT_LOW_LEV;
  83                 break;
  84         case IRQ_TYPE_LEVEL_HIGH:
  85                 edge = GPIO_INT_HIGH_LEV;
  86                 break;
  87         default:
  88                 return -EINVAL;
  89         }
  90
  91         /* set level or edge */
  92         pin_addr = port->base + PINCTRL_IRQLEV(port->id);
  93         if (edge & GPIO_INT_LEV_MASK)
  94                 writel(pin_mask, pin_addr + MXS_SET);
  95         else
  96                 writel(pin_mask, pin_addr + MXS_CLR);
  97
  98         /* set polarity */
  99         pin_addr = port->base + PINCTRL_IRQPOL(port->id);
 100         if (edge & GPIO_INT_POL_MASK)
 101                 writel(pin_mask, pin_addr + MXS_SET);
 102         else
 103                 writel(pin_mask, pin_addr + MXS_CLR);
 104
 105         writel(1 << (gpio & 0x1f),
 106                port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 107
 108         return 0;
 109 }
 110
 111 /* MXS has one interrupt *per* gpio port */
 112 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 113 {
 114         u32 irq_stat;
 115         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 116         u32 gpio_irq_no_base = port->virtual_irq_start;
 117
 118         desc->irq_data.chip->irq_ack(&desc->irq_data);
 119
 120         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
 121                         readl(port->base + PINCTRL_IRQEN(port->id));
 122
 123         while (irq_stat != 0) {
 124                 int irqoffset = fls(irq_stat) - 1;
 125                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 126                 irq_stat &= ~(1 << irqoffset);
 127         }
 128 }
 129
 130 /*
 131  * Set interrupt number "irq" in the GPIO as a wake-up source.
 132  * While system is running, all registered GPIO interrupts need to have
 133  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 134  * need to have wake-up enabled.
 135  * @param  irq          interrupt source number
 136  * @param  enable       enable as wake-up if equal to non-zero
 137  * @return       This function returns 0 on success.
 138  */
 139 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 140 {
 141         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 142         struct mxs_gpio_port *port = gc->private;
 143
 144         if (enable)
 145                 enable_irq_wake(port->irq);
 146         else
 147                 disable_irq_wake(port->irq);
 148
 149         return 0;
 150 }
 151
 152 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 153 {
 154         struct irq_chip_generic *gc;
 155         struct irq_chip_type *ct;
 156
 157         gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
 158                                     port->base, handle_level_irq);
 159         gc->private = port;
 160
 161         ct = gc->chip_types;
 162         ct->chip.irq_ack = irq_gc_ack_set_bit;
 163         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 164         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 165         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 166         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 167         ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
 168         ct->regs.mask = PINCTRL_IRQEN(port->id);
 169
 170         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 171 }
 172
 173 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 174 {
 175         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 176         struct mxs_gpio_port *port =
 177                 container_of(bgc, struct mxs_gpio_port, bgc);
 178
 179         return port->virtual_irq_start + offset;
 180 }
 181
 182 static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 183 {
 184         static void __iomem *base;
 185         struct mxs_gpio_port *port;
 186         struct resource *iores = NULL;
 187         int err;
 188
 189         port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
 190         if (!port)
 191                 return -ENOMEM;
 192
 193         port->id = pdev->id;
 194         port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 195
 196         /*
 197          * map memory region only once, as all the gpio ports
 198          * share the same one
 199          */
 200         if (!base) {
 201                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 202                 if (!iores) {
 203                         err = -ENODEV;
 204                         goto out_kfree;
 205                 }
 206
 207                 if (!request_mem_region(iores->start, resource_size(iores),
 208                                         pdev->name)) {
 209                         err = -EBUSY;
 210                         goto out_kfree;
 211                 }
 212
 213                 base = ioremap(iores->start, resource_size(iores));
 214                 if (!base) {
 215                         err = -ENOMEM;
 216                         goto out_release_mem;
 217                 }
 218         }
 219         port->base = base;
 220
 221         port->irq = platform_get_irq(pdev, 0);
 222         if (port->irq < 0) {
 223                 err = -EINVAL;
 224                 goto out_iounmap;
 225         }
 226
 227         /*
 228          * select the pin interrupt functionality but initially
 229          * disable the interrupts
 230          */
 231         writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
 232         writel(0, port->base + PINCTRL_IRQEN(port->id));
 233
 234         /* clear address has to be used to clear IRQSTAT bits */
 235         writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 236
 237         /* gpio-mxs can be a generic irq chip */
 238         mxs_gpio_init_gc(port);
 239
 240         /* setup one handler for each entry */
 241         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 242         irq_set_handler_data(port->irq, port);
 243
 244         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 245                          port->base + PINCTRL_DIN(port->id),
 246                          port->base + PINCTRL_DOUT(port->id), NULL,
 247                          port->base + PINCTRL_DOE(port->id), NULL, 0);
 248         if (err)
 249                 goto out_iounmap;
 250
 251         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 252         port->bgc.gc.base = port->id * 32;
 253
 254         err = gpiochip_add(&port->bgc.gc);
 255         if (err)
 256                 goto out_bgpio_remove;
 257
 258         return 0;
 259
 260 out_bgpio_remove:
 261         bgpio_remove(&port->bgc);
 262 out_iounmap:
 263         if (iores)
 264                 iounmap(port->base);
 265 out_release_mem:
 266         if (iores)
 267                 release_mem_region(iores->start, resource_size(iores));
 268 out_kfree:
 269         kfree(port);
 270         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 271         return err;
 272 }
 273
 274 static struct platform_driver mxs_gpio_driver = {
 275         .driver         = {
 276                 .name   = "gpio-mxs",
 277                 .owner  = THIS_MODULE,
 278         },
 279         .probe          = mxs_gpio_probe,
 280 };
 281
 282 static int __init mxs_gpio_init(void)
 283 {
 284         return platform_driver_register(&mxs_gpio_driver);
 285 }
 286 postcore_initcall(mxs_gpio_init);
 287
 288 MODULE_AUTHOR("Freescale Semiconductor, "
 289               "Daniel Mack <danielncaiaq.de>, "
 290               "Juergen Beisert <kernel@pengutronix.de>");
 291 MODULE_DESCRIPTION("Freescale MXS GPIO");
 292 MODULE_LICENSE("GPL");