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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-msm-v1.c
1 /*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/gpio.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/platform_device.h>
24
25 #include <mach/msm_gpiomux.h>
26
27 /* see 80-VA736-2 Rev C pp 695-751
28 **
29 ** These are actually the *shadow* gpio registers, since the
30 ** real ones (which allow full access) are only available to the
31 ** ARM9 side of the world.
32 **
33 ** Since the _BASE need to be page-aligned when we're mapping them
34 ** to virtual addresses, adjust for the additional offset in these
35 ** macros.
36 */
37
38 #define MSM_GPIO1_REG(off) (off)
39 #define MSM_GPIO2_REG(off) (off)
40 #define MSM_GPIO1_SHADOW_REG(off) (off)
41 #define MSM_GPIO2_SHADOW_REG(off) (off)
42
43 /*
44 * MSM7X00 registers
45 */
46 /* output value */
47 #define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
48 #define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
49 #define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
50 #define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
51 #define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
52 #define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
53
54 /* same pin map as above, output enable */
55 #define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
56 #define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
57 #define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
58 #define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
59 #define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
60 #define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
61
62 /* same pin map as above, input read */
63 #define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
64 #define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
65 #define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
66 #define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
67 #define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
68 #define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
69
70 /* same pin map as above, 1=edge 0=level interrup */
71 #define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
72 #define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
73 #define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
74 #define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
75 #define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
76 #define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
77
78 /* same pin map as above, 1=positive 0=negative */
79 #define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
80 #define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
81 #define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
82 #define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
83 #define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
84 #define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
85
86 /* same pin map as above, interrupt enable */
87 #define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
88 #define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
89 #define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
90 #define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)
91 #define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C)
92 #define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8)
93
94 /* same pin map as above, write 1 to clear interrupt */
95 #define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90)
96 #define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
97 #define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94)
98 #define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98)
99 #define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C)
100 #define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4)
101
102 /* same pin map as above, 1=interrupt pending */
103 #define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0)
104 #define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
105 #define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4)
106 #define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8)
107 #define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC)
108 #define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0)
109
110 /*
111 * QSD8X50 registers
112 */
113 /* output value */
114 #define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
115 #define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
116 #define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
117 #define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
118 #define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
119 #define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
120 #define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
121 #define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
122
123 /* same pin map as above, output enable */
124 #define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20)
125 #define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
126 #define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24)
127 #define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28)
128 #define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C)
129 #define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30)
130 #define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34)
131 #define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38)
132
133 /* same pin map as above, input read */
134 #define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50)
135 #define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
136 #define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54)
137 #define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58)
138 #define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C)
139 #define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60)
140 #define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64)
141 #define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68)
142
143 /* same pin map as above, 1=edge 0=level interrup */
144 #define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
145 #define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
146 #define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
147 #define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
148 #define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
149 #define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
150 #define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
151 #define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
152
153 /* same pin map as above, 1=positive 0=negative */
154 #define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90)
155 #define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
156 #define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94)
157 #define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98)
158 #define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C)
159 #define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0)
160 #define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4)
161 #define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8)
162
163 /* same pin map as above, interrupt enable */
164 #define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0)
165 #define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
166 #define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4)
167 #define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8)
168 #define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC)
169 #define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0)
170 #define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4)
171 #define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8)
172
173 /* same pin map as above, write 1 to clear interrupt */
174 #define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0)
175 #define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
176 #define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4)
177 #define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8)
178 #define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC)
179 #define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0)
180 #define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4)
181 #define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8)
182
183 /* same pin map as above, 1=interrupt pending */
184 #define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0)
185 #define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
186 #define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4)
187 #define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8)
188 #define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC)
189 #define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100)
190 #define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104)
191 #define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108)
192
193 /*
194 * MSM7X30 registers
195 */
196 /* output value */
197 #define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
198 #define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
199 #define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
200 #define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
201 #define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
202 #define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
203 #define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
204 #define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205
206 /* same pin map as above, output enable */
207 #define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10)
208 #define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08)
209 #define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14)
210 #define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18)
211 #define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
212 #define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54)
213 #define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
214 #define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218)
215
216 /* same pin map as above, input read */
217 #define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34)
218 #define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20)
219 #define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38)
220 #define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
221 #define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40)
222 #define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44)
223 #define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
224 #define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
225
226 /* same pin map as above, 1=edge 0=level interrup */
227 #define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
228 #define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
229 #define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
230 #define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
231 #define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
232 #define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
233 #define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
234 #define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
235
236 /* same pin map as above, 1=positive 0=negative */
237 #define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
238 #define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
239 #define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
240 #define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
241 #define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
242 #define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
243 #define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
244 #define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
245
246 /* same pin map as above, interrupt enable */
247 #define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
248 #define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
249 #define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
250 #define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
251 #define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
252 #define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
253 #define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
254 #define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
255
256 /* same pin map as above, write 1 to clear interrupt */
257 #define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
258 #define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
259 #define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
260 #define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
261 #define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
262 #define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
263 #define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
264 #define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
265
266 /* same pin map as above, 1=interrupt pending */
267 #define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
268 #define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
269 #define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
270 #define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
271 #define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
272 #define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
273 #define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
274 #define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
275
276 #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
277
278 #define MSM_GPIO_BANK(soc, bank, first, last) \
279 { \
280 .regs[MSM_GPIO_OUT] = soc##_GPIO_OUT_##bank, \
281 .regs[MSM_GPIO_IN] = soc##_GPIO_IN_##bank, \
282 .regs[MSM_GPIO_INT_STATUS] = soc##_GPIO_INT_STATUS_##bank, \
283 .regs[MSM_GPIO_INT_CLEAR] = soc##_GPIO_INT_CLEAR_##bank, \
284 .regs[MSM_GPIO_INT_EN] = soc##_GPIO_INT_EN_##bank, \
285 .regs[MSM_GPIO_INT_EDGE] = soc##_GPIO_INT_EDGE_##bank, \
286 .regs[MSM_GPIO_INT_POS] = soc##_GPIO_INT_POS_##bank, \
287 .regs[MSM_GPIO_OE] = soc##_GPIO_OE_##bank, \
288 .chip = { \
289 .base = (first), \
290 .ngpio = (last) - (first) + 1, \
291 .get = msm_gpio_get, \
292 .set = msm_gpio_set, \
293 .direction_input = msm_gpio_direction_input, \
294 .direction_output = msm_gpio_direction_output, \
295 .to_irq = msm_gpio_to_irq, \
296 .request = msm_gpio_request, \
297 .free = msm_gpio_free, \
298 } \
299 }
300
301 #define MSM_GPIO_BROKEN_INT_CLEAR 1
302
303 enum msm_gpio_reg {
304 MSM_GPIO_IN,
305 MSM_GPIO_OUT,
306 MSM_GPIO_INT_STATUS,
307 MSM_GPIO_INT_CLEAR,
308 MSM_GPIO_INT_EN,
309 MSM_GPIO_INT_EDGE,
310 MSM_GPIO_INT_POS,
311 MSM_GPIO_OE,
312 MSM_GPIO_REG_NR
313 };
314
315 struct msm_gpio_chip {
316 spinlock_t lock;
317 struct gpio_chip chip;
318 unsigned long regs[MSM_GPIO_REG_NR];
319 #if MSM_GPIO_BROKEN_INT_CLEAR
320 unsigned int_status_copy;
321 #endif
322 unsigned int both_edge_detect;
323 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
324 void __iomem *base;
325 };
326
327 struct msm_gpio_initdata {
328 struct msm_gpio_chip *chips;
329 int count;
330 };
331
332 static void msm_gpio_writel(struct msm_gpio_chip *chip, u32 val,
333 enum msm_gpio_reg reg)
334 {
335 writel(val, chip->base + chip->regs[reg]);
336 }
337
338 static u32 msm_gpio_readl(struct msm_gpio_chip *chip, enum msm_gpio_reg reg)
339 {
340 return readl(chip->base + chip->regs[reg]);
341 }
342
343 static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
344 unsigned offset, unsigned on)
345 {
346 unsigned mask = BIT(offset);
347 unsigned val;
348
349 val = msm_gpio_readl(msm_chip, MSM_GPIO_OUT);
350 if (on)
351 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_OUT);
352 else
353 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_OUT);
354 return 0;
355 }
356
357 static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
358 {
359 int loop_limit = 100;
360 unsigned pol, val, val2, intstat;
361 do {
362 val = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
363 pol = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
364 pol = (pol & ~msm_chip->both_edge_detect) |
365 (~val & msm_chip->both_edge_detect);
366 msm_gpio_writel(msm_chip, pol, MSM_GPIO_INT_POS);
367 intstat = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
368 val2 = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
369 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
370 return;
371 } while (loop_limit-- > 0);
372 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
373 "failed to reach stable state %x != %x\n", val, val2);
374 }
375
376 static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
377 unsigned offset)
378 {
379 unsigned bit = BIT(offset);
380
381 #if MSM_GPIO_BROKEN_INT_CLEAR
382 /* Save interrupts that already triggered before we loose them. */
383 /* Any interrupt that triggers between the read of int_status */
384 /* and the write to int_clear will still be lost though. */
385 msm_chip->int_status_copy |=
386 msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
387 msm_chip->int_status_copy &= ~bit;
388 #endif
389 msm_gpio_writel(msm_chip, bit, MSM_GPIO_INT_CLEAR);
390 msm_gpio_update_both_edge_detect(msm_chip);
391 return 0;
392 }
393
394 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
395 {
396 struct msm_gpio_chip *msm_chip;
397 unsigned long irq_flags;
398 u32 val;
399
400 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
401 spin_lock_irqsave(&msm_chip->lock, irq_flags);
402 val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) & ~BIT(offset);
403 msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
404 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
405 return 0;
406 }
407
408 static int
409 msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
410 {
411 struct msm_gpio_chip *msm_chip;
412 unsigned long irq_flags;
413 u32 val;
414
415 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
416 spin_lock_irqsave(&msm_chip->lock, irq_flags);
417 msm_gpio_write(msm_chip, offset, value);
418 val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) | BIT(offset);
419 msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
420 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
421 return 0;
422 }
423
424 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
425 {
426 struct msm_gpio_chip *msm_chip;
427
428 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
429 return (msm_gpio_readl(msm_chip, MSM_GPIO_IN) & (1U << offset)) ? 1 : 0;
430 }
431
432 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
433 {
434 struct msm_gpio_chip *msm_chip;
435 unsigned long irq_flags;
436
437 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
438 spin_lock_irqsave(&msm_chip->lock, irq_flags);
439 msm_gpio_write(msm_chip, offset, value);
440 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
441 }
442
443 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
444 {
445 return MSM_GPIO_TO_INT(chip->base + offset);
446 }
447
448 #ifdef CONFIG_MSM_GPIOMUX
449 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
450 {
451 return msm_gpiomux_get(chip->base + offset);
452 }
453
454 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
455 {
456 msm_gpiomux_put(chip->base + offset);
457 }
458 #else
459 #define msm_gpio_request NULL
460 #define msm_gpio_free NULL
461 #endif
462
463 static struct msm_gpio_chip *msm_gpio_chips;
464 static int msm_gpio_count;
465
466 static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
467 MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
468 MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
469 MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
470 MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
471 MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
472 MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
473 };
474
475 static struct msm_gpio_initdata msm_gpio_7x01_init = {
476 .chips = msm_gpio_chips_msm7x01,
477 .count = ARRAY_SIZE(msm_gpio_chips_msm7x01),
478 };
479
480 static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
481 MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
482 MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
483 MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
484 MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
485 MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
486 MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
487 MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
488 MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
489 };
490
491 static struct msm_gpio_initdata msm_gpio_7x30_init = {
492 .chips = msm_gpio_chips_msm7x30,
493 .count = ARRAY_SIZE(msm_gpio_chips_msm7x30),
494 };
495
496 static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
497 MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
498 MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
499 MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
500 MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
501 MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
502 MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
503 MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
504 MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
505 };
506
507 static struct msm_gpio_initdata msm_gpio_8x50_init = {
508 .chips = msm_gpio_chips_qsd8x50,
509 .count = ARRAY_SIZE(msm_gpio_chips_qsd8x50),
510 };
511
512 static void msm_gpio_irq_ack(struct irq_data *d)
513 {
514 unsigned long irq_flags;
515 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
516 spin_lock_irqsave(&msm_chip->lock, irq_flags);
517 msm_gpio_clear_detect_status(msm_chip,
518 d->irq - gpio_to_irq(msm_chip->chip.base));
519 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
520 }
521
522 static void msm_gpio_irq_mask(struct irq_data *d)
523 {
524 unsigned long irq_flags;
525 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
526 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
527
528 spin_lock_irqsave(&msm_chip->lock, irq_flags);
529 /* level triggered interrupts are also latched */
530 if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
531 msm_gpio_clear_detect_status(msm_chip, offset);
532 msm_chip->int_enable[0] &= ~BIT(offset);
533 msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
534 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
535 }
536
537 static void msm_gpio_irq_unmask(struct irq_data *d)
538 {
539 unsigned long irq_flags;
540 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
541 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
542
543 spin_lock_irqsave(&msm_chip->lock, irq_flags);
544 /* level triggered interrupts are also latched */
545 if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
546 msm_gpio_clear_detect_status(msm_chip, offset);
547 msm_chip->int_enable[0] |= BIT(offset);
548 msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
549 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
550 }
551
552 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
553 {
554 unsigned long irq_flags;
555 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
556 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
557
558 spin_lock_irqsave(&msm_chip->lock, irq_flags);
559
560 if (on)
561 msm_chip->int_enable[1] |= BIT(offset);
562 else
563 msm_chip->int_enable[1] &= ~BIT(offset);
564
565 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
566 return 0;
567 }
568
569 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
570 {
571 unsigned long irq_flags;
572 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
573 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
574 unsigned val, mask = BIT(offset);
575
576 spin_lock_irqsave(&msm_chip->lock, irq_flags);
577 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE);
578 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
579 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_INT_EDGE);
580 __irq_set_handler_locked(d->irq, handle_edge_irq);
581 } else {
582 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_INT_EDGE);
583 __irq_set_handler_locked(d->irq, handle_level_irq);
584 }
585 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
586 msm_chip->both_edge_detect |= mask;
587 msm_gpio_update_both_edge_detect(msm_chip);
588 } else {
589 msm_chip->both_edge_detect &= ~mask;
590 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
591 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
592 val |= mask;
593 else
594 val &= ~mask;
595 msm_gpio_writel(msm_chip, val, MSM_GPIO_INT_POS);
596 }
597 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
598 return 0;
599 }
600
601 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
602 {
603 int i, j, mask;
604 unsigned val;
605
606 for (i = 0; i < msm_gpio_count; i++) {
607 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
608 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
609 val &= msm_chip->int_enable[0];
610 while (val) {
611 mask = val & -val;
612 j = fls(mask) - 1;
613 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
614 __func__, v, m, j, msm_chip->chip.start + j,
615 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
616 val &= ~mask;
617 generic_handle_irq(FIRST_GPIO_IRQ +
618 msm_chip->chip.base + j);
619 }
620 }
621 desc->irq_data.chip->irq_ack(&desc->irq_data);
622 }
623
624 static struct irq_chip msm_gpio_irq_chip = {
625 .name = "msmgpio",
626 .irq_ack = msm_gpio_irq_ack,
627 .irq_mask = msm_gpio_irq_mask,
628 .irq_unmask = msm_gpio_irq_unmask,
629 .irq_set_wake = msm_gpio_irq_set_wake,
630 .irq_set_type = msm_gpio_irq_set_type,
631 };
632
633 static int __devinit gpio_msm_v1_probe(struct platform_device *pdev)
634 {
635 int i, j = 0;
636 const struct platform_device_id *dev_id = platform_get_device_id(pdev);
637 struct msm_gpio_initdata *data;
638 int irq1, irq2;
639 struct resource *res;
640 void __iomem *base1, __iomem *base2;
641
642 data = (struct msm_gpio_initdata *)dev_id->driver_data;
643 msm_gpio_chips = data->chips;
644 msm_gpio_count = data->count;
645
646 irq1 = platform_get_irq(pdev, 0);
647 if (irq1 < 0)
648 return irq1;
649
650 irq2 = platform_get_irq(pdev, 1);
651 if (irq2 < 0)
652 return irq2;
653
654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 base1 = devm_request_and_ioremap(&pdev->dev, res);
656 if (!base1)
657 return -EADDRNOTAVAIL;
658
659 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
660 base2 = devm_request_and_ioremap(&pdev->dev, res);
661 if (!base2)
662 return -EADDRNOTAVAIL;
663
664 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
665 if (i - FIRST_GPIO_IRQ >=
666 msm_gpio_chips[j].chip.base +
667 msm_gpio_chips[j].chip.ngpio)
668 j++;
669 irq_set_chip_data(i, &msm_gpio_chips[j]);
670 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
671 handle_edge_irq);
672 set_irq_flags(i, IRQF_VALID);
673 }
674
675 for (i = 0; i < msm_gpio_count; i++) {
676 if (i == 1)
677 msm_gpio_chips[i].base = base2;
678 else
679 msm_gpio_chips[i].base = base1;
680 spin_lock_init(&msm_gpio_chips[i].lock);
681 msm_gpio_writel(&msm_gpio_chips[i], 0, MSM_GPIO_INT_EN);
682 gpiochip_add(&msm_gpio_chips[i].chip);
683 }
684
685 irq_set_chained_handler(irq1, msm_gpio_irq_handler);
686 irq_set_chained_handler(irq2, msm_gpio_irq_handler);
687 irq_set_irq_wake(irq1, 1);
688 irq_set_irq_wake(irq2, 2);
689 return 0;
690 }
691
692 static struct platform_device_id gpio_msm_v1_device_ids[] = {
693 { "gpio-msm-7201", (unsigned long)&msm_gpio_7x01_init },
694 { "gpio-msm-7x30", (unsigned long)&msm_gpio_7x30_init },
695 { "gpio-msm-8x50", (unsigned long)&msm_gpio_8x50_init },
696 { }
697 };
698 MODULE_DEVICE_TABLE(platform, gpio_msm_v1_device_ids);
699
700 static struct platform_driver gpio_msm_v1_driver = {
701 .driver = {
702 .name = "gpio-msm-v1",
703 .owner = THIS_MODULE,
704 },
705 .probe = gpio_msm_v1_probe,
706 .id_table = gpio_msm_v1_device_ids,
707 };
708
709 static int __init gpio_msm_v1_init(void)
710 {
711 return platform_driver_register(&gpio_msm_v1_driver);
712 }
713 postcore_initcall(gpio_msm_v1_init);
714 MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)