drivers/gpio/gpio-ep93xx.c

   1 /*
   2  * Generic EP93xx GPIO handling
   3  *
   4  * Copyright (c) 2008 Ryan Mallon
   5  * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
   6  *
   7  * Based on code originally from:
   8  *  linux/arch/arm/mach-ep93xx/core.c
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/gpio.h>
  22 #include <linux/irq.h>
  23 #include <linux/slab.h>
  24 #include <linux/basic_mmio_gpio.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/gpio-ep93xx.h>
  28
  29 #define irq_to_gpio(irq)        ((irq) - gpio_to_irq(0))
  30
  31 struct ep93xx_gpio {
  32         void __iomem            *mmio_base;
  33         struct bgpio_chip       bgc[8];
  34 };
  35
  36 /*************************************************************************
  37  * Interrupt handling for EP93xx on-chip GPIOs
  38  *************************************************************************/
  39 static unsigned char gpio_int_unmasked[3];
  40 static unsigned char gpio_int_enabled[3];
  41 static unsigned char gpio_int_type1[3];
  42 static unsigned char gpio_int_type2[3];
  43 static unsigned char gpio_int_debounce[3];
  44
  45 /* Port ordering is: A B F */
  46 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
  47 static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
  48 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
  49 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
  50 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
  51
  52 static void ep93xx_gpio_update_int_params(unsigned port)
  53 {
  54         BUG_ON(port > 2);
  55
  56         __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
  57
  58         __raw_writeb(gpio_int_type2[port],
  59                 EP93XX_GPIO_REG(int_type2_register_offset[port]));
  60
  61         __raw_writeb(gpio_int_type1[port],
  62                 EP93XX_GPIO_REG(int_type1_register_offset[port]));
  63
  64         __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
  65                 EP93XX_GPIO_REG(int_en_register_offset[port]));
  66 }
  67
  68 static inline void ep93xx_gpio_int_mask(unsigned line)
  69 {
  70         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
  71 }
  72
  73 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
  74 {
  75         int line = irq_to_gpio(irq);
  76         int port = line >> 3;
  77         int port_mask = 1 << (line & 7);
  78
  79         if (enable)
  80                 gpio_int_debounce[port] |= port_mask;
  81         else
  82                 gpio_int_debounce[port] &= ~port_mask;
  83
  84         __raw_writeb(gpio_int_debounce[port],
  85                 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
  86 }
  87
  88 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
  89 {
  90         unsigned char status;
  91         int i;
  92
  93         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
  94         for (i = 0; i < 8; i++) {
  95                 if (status & (1 << i)) {
  96                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
  97                         generic_handle_irq(gpio_irq);
  98                 }
  99         }
 100
 101         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
 102         for (i = 0; i < 8; i++) {
 103                 if (status & (1 << i)) {
 104                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
 105                         generic_handle_irq(gpio_irq);
 106                 }
 107         }
 108 }
 109
 110 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
 111 {
 112         /*
 113          * map discontiguous hw irq range to continuous sw irq range:
 114          *
 115          *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
 116          */
 117         int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
 118         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
 119
 120         generic_handle_irq(gpio_irq);
 121 }
 122
 123 static void ep93xx_gpio_irq_ack(struct irq_data *d)
 124 {
 125         int line = irq_to_gpio(d->irq);
 126         int port = line >> 3;
 127         int port_mask = 1 << (line & 7);
 128
 129         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 130                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 131                 ep93xx_gpio_update_int_params(port);
 132         }
 133
 134         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 135 }
 136
 137 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
 138 {
 139         int line = irq_to_gpio(d->irq);
 140         int port = line >> 3;
 141         int port_mask = 1 << (line & 7);
 142
 143         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
 144                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 145
 146         gpio_int_unmasked[port] &= ~port_mask;
 147         ep93xx_gpio_update_int_params(port);
 148
 149         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 150 }
 151
 152 static void ep93xx_gpio_irq_mask(struct irq_data *d)
 153 {
 154         int line = irq_to_gpio(d->irq);
 155         int port = line >> 3;
 156
 157         gpio_int_unmasked[port] &= ~(1 << (line & 7));
 158         ep93xx_gpio_update_int_params(port);
 159 }
 160
 161 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
 162 {
 163         int line = irq_to_gpio(d->irq);
 164         int port = line >> 3;
 165
 166         gpio_int_unmasked[port] |= 1 << (line & 7);
 167         ep93xx_gpio_update_int_params(port);
 168 }
 169
 170 /*
 171  * gpio_int_type1 controls whether the interrupt is level (0) or
 172  * edge (1) triggered, while gpio_int_type2 controls whether it
 173  * triggers on low/falling (0) or high/rising (1).
 174  */
 175 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
 176 {
 177         const int gpio = irq_to_gpio(d->irq);
 178         const int port = gpio >> 3;
 179         const int port_mask = 1 << (gpio & 7);
 180         irq_flow_handler_t handler;
 181
 182         gpio_direction_input(gpio);
 183
 184         switch (type) {
 185         case IRQ_TYPE_EDGE_RISING:
 186                 gpio_int_type1[port] |= port_mask;
 187                 gpio_int_type2[port] |= port_mask;
 188                 handler = handle_edge_irq;
 189                 break;
 190         case IRQ_TYPE_EDGE_FALLING:
 191                 gpio_int_type1[port] |= port_mask;
 192                 gpio_int_type2[port] &= ~port_mask;
 193                 handler = handle_edge_irq;
 194                 break;
 195         case IRQ_TYPE_LEVEL_HIGH:
 196                 gpio_int_type1[port] &= ~port_mask;
 197                 gpio_int_type2[port] |= port_mask;
 198                 handler = handle_level_irq;
 199                 break;
 200         case IRQ_TYPE_LEVEL_LOW:
 201                 gpio_int_type1[port] &= ~port_mask;
 202                 gpio_int_type2[port] &= ~port_mask;
 203                 handler = handle_level_irq;
 204                 break;
 205         case IRQ_TYPE_EDGE_BOTH:
 206                 gpio_int_type1[port] |= port_mask;
 207                 /* set initial polarity based on current input level */
 208                 if (gpio_get_value(gpio))
 209                         gpio_int_type2[port] &= ~port_mask; /* falling */
 210                 else
 211                         gpio_int_type2[port] |= port_mask; /* rising */
 212                 handler = handle_edge_irq;
 213                 break;
 214         default:
 215                 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
 216                 return -EINVAL;
 217         }
 218
 219         __irq_set_handler_locked(d->irq, handler);
 220
 221         gpio_int_enabled[port] |= port_mask;
 222
 223         ep93xx_gpio_update_int_params(port);
 224
 225         return 0;
 226 }
 227
 228 static struct irq_chip ep93xx_gpio_irq_chip = {
 229         .name           = "GPIO",
 230         .irq_ack        = ep93xx_gpio_irq_ack,
 231         .irq_mask_ack   = ep93xx_gpio_irq_mask_ack,
 232         .irq_mask       = ep93xx_gpio_irq_mask,
 233         .irq_unmask     = ep93xx_gpio_irq_unmask,
 234         .irq_set_type   = ep93xx_gpio_irq_type,
 235 };
 236
 237 static void ep93xx_gpio_init_irq(void)
 238 {
 239         int gpio_irq;
 240
 241         for (gpio_irq = gpio_to_irq(0);
 242              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
 243                 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
 244                                          handle_level_irq);
 245                 set_irq_flags(gpio_irq, IRQF_VALID);
 246         }
 247
 248         irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
 249                                 ep93xx_gpio_ab_irq_handler);
 250         irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
 251                                 ep93xx_gpio_f_irq_handler);
 252         irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
 253                                 ep93xx_gpio_f_irq_handler);
 254         irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
 255                                 ep93xx_gpio_f_irq_handler);
 256         irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
 257                                 ep93xx_gpio_f_irq_handler);
 258         irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
 259                                 ep93xx_gpio_f_irq_handler);
 260         irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
 261                                 ep93xx_gpio_f_irq_handler);
 262         irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
 263                                 ep93xx_gpio_f_irq_handler);
 264         irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
 265                                 ep93xx_gpio_f_irq_handler);
 266 }
 267
 268
 269 /*************************************************************************
 270  * gpiolib interface for EP93xx on-chip GPIOs
 271  *************************************************************************/
 272 struct ep93xx_gpio_bank {
 273         const char      *label;
 274         int             data;
 275         int             dir;
 276         int             base;
 277         bool            has_debounce;
 278 };
 279
 280 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
 281         {                                                       \
 282                 .label          = _label,                       \
 283                 .data           = _data,                        \
 284                 .dir            = _dir,                         \
 285                 .base           = _base,                        \
 286                 .has_debounce   = _debounce,                    \
 287         }
 288
 289 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
 290         EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
 291         EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
 292         EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
 293         EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
 294         EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
 295         EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
 296         EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
 297         EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
 298 };
 299
 300 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
 301                                     unsigned offset, unsigned debounce)
 302 {
 303         int gpio = chip->base + offset;
 304         int irq = gpio_to_irq(gpio);
 305
 306         if (irq < 0)
 307                 return -EINVAL;
 308
 309         ep93xx_gpio_int_debounce(irq, debounce ? true : false);
 310
 311         return 0;
 312 }
 313
 314 /*
 315  * Map GPIO A0..A7  (0..7)  to irq 64..71,
 316  *          B0..B7  (7..15) to irq 72..79, and
 317  *          F0..F7 (16..24) to irq 80..87.
 318  */
 319 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 320 {
 321         int gpio = chip->base + offset;
 322
 323         if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
 324                 return -EINVAL;
 325
 326         return 64 + gpio;
 327 }
 328
 329 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
 330         void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
 331 {
 332         void __iomem *data = mmio_base + bank->data;
 333         void __iomem *dir =  mmio_base + bank->dir;
 334         int err;
 335
 336         err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
 337         if (err)
 338                 return err;
 339
 340         bgc->gc.label = bank->label;
 341         bgc->gc.base = bank->base;
 342
 343         if (bank->has_debounce) {
 344                 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
 345                 bgc->gc.to_irq = ep93xx_gpio_to_irq;
 346         }
 347
 348         return gpiochip_add(&bgc->gc);
 349 }
 350
 351 static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
 352 {
 353         struct ep93xx_gpio *ep93xx_gpio;
 354         struct resource *res;
 355         void __iomem *mmio;
 356         int i;
 357         int ret;
 358
 359         ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
 360         if (!ep93xx_gpio)
 361                 return -ENOMEM;
 362
 363         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 364         if (!res) {
 365                 ret = -ENXIO;
 366                 goto exit_free;
 367         }
 368
 369         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 370                 ret = -EBUSY;
 371                 goto exit_free;
 372         }
 373
 374         mmio = ioremap(res->start, resource_size(res));
 375         if (!mmio) {
 376                 ret = -ENXIO;
 377                 goto exit_release;
 378         }
 379         ep93xx_gpio->mmio_base = mmio;
 380
 381         /* Default all ports to GPIO */
 382         ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
 383                                EP93XX_SYSCON_DEVCFG_GONK |
 384                                EP93XX_SYSCON_DEVCFG_EONIDE |
 385                                EP93XX_SYSCON_DEVCFG_GONIDE |
 386                                EP93XX_SYSCON_DEVCFG_HONIDE);
 387
 388         for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
 389                 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
 390                 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
 391
 392                 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
 393                         dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
 394                                 bank->label);
 395         }
 396
 397         ep93xx_gpio_init_irq();
 398
 399         return 0;
 400
 401 exit_release:
 402         release_mem_region(res->start, resource_size(res));
 403 exit_free:
 404         kfree(ep93xx_gpio);
 405         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
 406         return ret;
 407 }
 408
 409 static struct platform_driver ep93xx_gpio_driver = {
 410         .driver         = {
 411                 .name   = "gpio-ep93xx",
 412                 .owner  = THIS_MODULE,
 413         },
 414         .probe          = ep93xx_gpio_probe,
 415 };
 416
 417 static int __init ep93xx_gpio_init(void)
 418 {
 419         return platform_driver_register(&ep93xx_gpio_driver);
 420 }
 421 postcore_initcall(ep93xx_gpio_init);
 422
 423 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
 424                 "H Hartley Sweeten <hsweeten@visionengravers.com>");
 425 MODULE_DESCRIPTION("EP93XX GPIO driver");
 426 MODULE_LICENSE("GPL");