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vdec: add work to substitude directly calling vp9_recycle_mmu_buf [1/1]
[GitHub/LineageOS/G12/android_hardware_amlogic_kernel-modules_media.git] / drivers / frame_provider / decoder / vp9 / vvp9.c
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17 #define DEBUG
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/interrupt.h>
23 #include <linux/semaphore.h>
24 #include <linux/delay.h>
25 #include <linux/timer.h>
26 #include <linux/kfifo.h>
27 #include <linux/kthread.h>
28 #include <linux/spinlock.h>
29 #include <linux/platform_device.h>
30 #include <linux/amlogic/media/vfm/vframe.h>
31 #include <linux/amlogic/media/utils/amstream.h>
32 #include <linux/amlogic/media/utils/vformat.h>
33 #include <linux/amlogic/media/frame_sync/ptsserv.h>
34 #include <linux/amlogic/media/canvas/canvas.h>
35 #include <linux/amlogic/media/vfm/vframe_provider.h>
36 #include <linux/amlogic/media/vfm/vframe_receiver.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/dma-contiguous.h>
39 #include <linux/slab.h>
40 #include <linux/amlogic/tee.h>
41 #include "../../../stream_input/amports/amports_priv.h"
42 #include <linux/amlogic/media/codec_mm/codec_mm.h>
43 #include "../utils/decoder_mmu_box.h"
44 #include "../utils/decoder_bmmu_box.h"
45
46 #define MEM_NAME "codec_vp9"
47 /* #include <mach/am_regs.h> */
48 #include <linux/amlogic/media/utils/vdec_reg.h>
49 #include "../utils/vdec.h"
50 #include "../utils/amvdec.h"
51 #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52 #include "../utils/vdec_profile.h"
53 #endif
54
55 #include <linux/amlogic/media/video_sink/video.h>
56 #include <linux/amlogic/media/codec_mm/configs.h>
57 #include "../utils/config_parser.h"
58 #include "../utils/firmware.h"
59 #include "../../../common/chips/decoder_cpu_ver_info.h"
60 #include "../utils/vdec_v4l2_buffer_ops.h"
61 #include <media/v4l2-mem2mem.h>
62
63 #define MIX_STREAM_SUPPORT
64
65 #include "vvp9.h"
66
67
68 /*#define SUPPORT_FB_DECODING*/
69 /*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72 #define HW_MASK_FRONT 0x1
73 #define HW_MASK_BACK 0x2
74
75 #define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76 #define VP9D_MPP_REFINFO_DATA 0x3443
77 #define VP9D_MPP_REF_SCALE_ENBL 0x3441
78 #define HEVC_MPRED_CTRL4 0x324c
79 #define HEVC_CM_HEADER_START_ADDR 0x3628
80 #define HEVC_DBLK_CFGB 0x350b
81 #define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82 #define HEVC_SAO_MMU_VH1_ADDR 0x363b
83 #define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85 #define HEVC_MV_INFO 0x310d
86 #define HEVC_QP_INFO 0x3137
87 #define HEVC_SKIP_INFO 0x3136
88
89 #define VP9_10B_DEC_IDLE 0
90 #define VP9_10B_DEC_FRAME_HEADER 1
91 #define VP9_10B_DEC_SLICE_SEGMENT 2
92 #define VP9_10B_DECODE_SLICE 5
93 #define VP9_10B_DISCARD_NAL 6
94 #define VP9_DUMP_LMEM 7
95 #define HEVC_DECPIC_DATA_DONE 0xa
96 #define HEVC_DECPIC_DATA_ERROR 0xb
97 #define HEVC_NAL_DECODE_DONE 0xe
98 #define HEVC_DECODE_BUFEMPTY 0x20
99 #define HEVC_DECODE_TIMEOUT 0x21
100 #define HEVC_SEARCH_BUFEMPTY 0x22
101 #define HEVC_DECODE_OVER_SIZE 0x23
102 #define HEVC_S2_DECODING_DONE 0x50
103 #define VP9_HEAD_PARSER_DONE 0xf0
104 #define VP9_HEAD_SEARCH_DONE 0xf1
105 #define VP9_EOS 0xf2
106 #define HEVC_ACTION_DONE 0xff
107
108 #define VF_POOL_SIZE 32
109
110 #undef pr_info
111 #define pr_info printk
112
113 #define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114 #define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115 #define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116 #define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117 #define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119 #define VP9_TRIGGER_FRAME_DONE 0x100
120 #define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122 #define MV_MEM_UNIT 0x240
123 /*---------------------------------------------------
124 * Include "parser_cmd.h"
125 *---------------------------------------------------
126 */
127 #define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129 #define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131 #define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133 #define PARSER_CMD_NUMBER 37
134
135 /*#define HEVC_PIC_STRUCT_SUPPORT*/
136 /* to remove, fix build error */
137
138 /*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140 #define MULTI_INSTANCE_SUPPORT
141 #define SUPPORT_10BIT
142 /* #define ERROR_HANDLE_DEBUG */
143
144 #ifndef STAT_KTHREAD
145 #define STAT_KTHREAD 0x40
146 #endif
147
148 #ifdef MULTI_INSTANCE_SUPPORT
149 #define MAX_DECODE_INSTANCE_NUM 9
150 #define MULTI_DRIVER_NAME "ammvdec_vp9"
151 static unsigned int max_decode_instance_num
152 = MAX_DECODE_INSTANCE_NUM;
153 static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154 static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155 static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156 static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157 static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158 static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160 static u32 decode_timeout_val = 200;
161 static int start_decode_buf_level = 0x8000;
162 static u32 work_buf_size;
163
164 static u32 mv_buf_margin;
165
166 /* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
167 /* double_write_mode:
168 * 0, no double write;
169 * 1, 1:1 ratio;
170 * 2, (1/4):(1/4) ratio;
171 * 3, (1/4):(1/4) ratio, with both compressed frame included
172 * 4, (1/2):(1/2) ratio;
173 * 0x10, double write only
174 * 0x100, if > 1080p,use mode 4,else use mode 1;
175 * 0x200, if > 1080p,use mode 2,else use mode 1;
176 * 0x300, if > 720p, use mode 4, else use mode 1;
177 */
178 static u32 double_write_mode;
179
180 #define DRIVER_NAME "amvdec_vp9"
181 #define MODULE_NAME "amvdec_vp9"
182 #define DRIVER_HEADER_NAME "amvdec_vp9_header"
183
184
185 #define PUT_INTERVAL (HZ/100)
186 #define ERROR_SYSTEM_RESET_COUNT 200
187
188 #define PTS_NORMAL 0
189 #define PTS_NONE_REF_USE_DURATION 1
190
191 #define PTS_MODE_SWITCHING_THRESHOLD 3
192 #define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
193
194 #define DUR2PTS(x) ((x)*90/96)
195
196 struct VP9Decoder_s;
197 static int vvp9_vf_states(struct vframe_states *states, void *);
198 static struct vframe_s *vvp9_vf_peek(void *);
199 static struct vframe_s *vvp9_vf_get(void *);
200 static void vvp9_vf_put(struct vframe_s *, void *);
201 static int vvp9_event_cb(int type, void *data, void *private_data);
202
203 static int vvp9_stop(struct VP9Decoder_s *pbi);
204 #ifdef MULTI_INSTANCE_SUPPORT
205 static s32 vvp9_init(struct vdec_s *vdec);
206 #else
207 static s32 vvp9_init(struct VP9Decoder_s *pbi);
208 #endif
209 static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
210 static int vvp9_local_init(struct VP9Decoder_s *pbi);
211 static void vvp9_put_timer_func(unsigned long arg);
212 static void dump_data(struct VP9Decoder_s *pbi, int size);
213 static unsigned char get_data_check_sum
214 (struct VP9Decoder_s *pbi, int size);
215 static void dump_pic_list(struct VP9Decoder_s *pbi);
216 static int vp9_alloc_mmu(
217 struct VP9Decoder_s *pbi,
218 int cur_buf_idx,
219 int pic_width,
220 int pic_height,
221 unsigned short bit_depth,
222 unsigned int *mmu_index_adr);
223
224
225 static const char vvp9_dec_id[] = "vvp9-dev";
226
227 #define PROVIDER_NAME "decoder.vp9"
228 #define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
229
230 static const struct vframe_operations_s vvp9_vf_provider = {
231 .peek = vvp9_vf_peek,
232 .get = vvp9_vf_get,
233 .put = vvp9_vf_put,
234 .event_cb = vvp9_event_cb,
235 .vf_states = vvp9_vf_states,
236 };
237
238 static struct vframe_provider_s vvp9_vf_prov;
239
240 static u32 bit_depth_luma;
241 static u32 bit_depth_chroma;
242 static u32 frame_width;
243 static u32 frame_height;
244 static u32 video_signal_type;
245
246 static u32 on_no_keyframe_skiped;
247
248 #define PROB_SIZE (496 * 2 * 4)
249 #define PROB_BUF_SIZE (0x5000)
250 #define COUNT_BUF_SIZE (0x300 * 4 * 4)
251 /*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
252 #define MAX_FRAME_4K_NUM 0x1200
253 #define MAX_FRAME_8K_NUM 0x4800
254
255 #define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
256
257 #ifdef SUPPORT_FB_DECODING
258 /* register define */
259 #define HEVC_ASSIST_HED_FB_W_CTL 0x3006
260 #define HEVC_ASSIST_HED_FB_R_CTL 0x3007
261 #define HEVC_ASSIST_HED_FB_ADDR 0x3008
262 #define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
263 #define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
264
265
266 #define MAX_STAGE_PAGE_NUM 0x1200
267 #define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
268 #endif
269 static inline int div_r32(int64_t m, int n)
270 {
271 /*
272 *return (int)(m/n)
273 */
274 #ifndef CONFIG_ARM64
275 int64_t qu = 0;
276 qu = div_s64(m, n);
277 return (int)qu;
278 #else
279 return (int)(m/n);
280 #endif
281 }
282
283 /*USE_BUF_BLOCK*/
284 struct BUF_s {
285 int index;
286 unsigned int alloc_flag;
287 /*buffer */
288 unsigned int cma_page_count;
289 unsigned long alloc_addr;
290 unsigned long start_adr;
291 unsigned int size;
292
293 unsigned int free_start_adr;
294 ulong v4l_ref_buf_addr;
295 ulong header_addr;
296 u32 header_size;
297 u32 luma_size;
298 } /*BUF_t */;
299
300 struct MVBUF_s {
301 unsigned long start_adr;
302 unsigned int size;
303 int used_flag;
304 } /*MVBUF_t */;
305
306 /* #undef BUFMGR_ONLY to enable hardware configuration */
307
308 /*#define TEST_WR_PTR_INC*/
309 /*#define WR_PTR_INC_NUM 128*/
310 #define WR_PTR_INC_NUM 1
311
312 #define SIMULATION
313 #define DOS_PROJECT
314 #undef MEMORY_MAP_IN_REAL_CHIP
315
316 /*#undef DOS_PROJECT*/
317 /*#define MEMORY_MAP_IN_REAL_CHIP*/
318
319 /*#define BUFFER_MGR_ONLY*/
320 /*#define CONFIG_HEVC_CLK_FORCED_ON*/
321 /*#define ENABLE_SWAP_TEST*/
322 #define MCRCC_ENABLE
323
324 #define VP9_LPF_LVL_UPDATE
325 /*#define DBG_LF_PRINT*/
326
327 #ifdef VP9_10B_NV21
328 #else
329 #define LOSLESS_COMPRESS_MODE
330 #endif
331
332 #define DOUBLE_WRITE_YSTART_TEMP 0x02000000
333 #define DOUBLE_WRITE_CSTART_TEMP 0x02900000
334
335
336
337 typedef unsigned int u32;
338 typedef unsigned short u16;
339
340 #define VP9_DEBUG_BUFMGR 0x01
341 #define VP9_DEBUG_BUFMGR_MORE 0x02
342 #define VP9_DEBUG_BUFMGR_DETAIL 0x04
343 #define VP9_DEBUG_OUT_PTS 0x10
344 #define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
345 #define VP9_DEBUG_MERGE 0x200
346 #define VP9_DEBUG_DBG_LF_PRINT 0x400
347 #define VP9_DEBUG_REG 0x800
348 #define VP9_DEBUG_2_STAGE 0x1000
349 #define VP9_DEBUG_2_STAGE_MORE 0x2000
350 #define VP9_DEBUG_QOS_INFO 0x4000
351 #define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
352 #define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
353 #define VP9_DEBUG_DUMP_PIC_LIST 0x40000
354 #define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
355 #define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
356 #define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
357 #define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
358 #define VP9_DEBUG_DUMP_DATA 0x800000
359 #define VP9_DEBUG_CACHE 0x1000000
360 #define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
361 #define IGNORE_PARAM_FROM_CONFIG 0x8000000
362 #ifdef MULTI_INSTANCE_SUPPORT
363 #define PRINT_FLAG_ERROR 0x0
364 #define PRINT_FLAG_V4L_DETAIL 0x10000000
365 #define PRINT_FLAG_VDEC_STATUS 0x20000000
366 #define PRINT_FLAG_VDEC_DETAIL 0x40000000
367 #define PRINT_FLAG_VDEC_DATA 0x80000000
368 #endif
369
370 static u32 debug;
371 static bool is_reset;
372 /*for debug*/
373 /*
374 udebug_flag:
375 bit 0, enable ucode print
376 bit 1, enable ucode detail print
377 bit [31:16] not 0, pos to dump lmem
378 bit 2, pop bits to lmem
379 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
380 */
381 static u32 udebug_flag;
382 /*
383 when udebug_flag[1:0] is not 0
384 udebug_pause_pos not 0,
385 pause position
386 */
387 static u32 udebug_pause_pos;
388 /*
389 when udebug_flag[1:0] is not 0
390 and udebug_pause_pos is not 0,
391 pause only when DEBUG_REG2 is equal to this val
392 */
393 static u32 udebug_pause_val;
394
395 static u32 udebug_pause_decode_idx;
396
397 static u32 without_display_mode;
398
399 #define DEBUG_REG
400 #ifdef DEBUG_REG
401 void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
402 {
403 if (debug & VP9_DEBUG_REG)
404 pr_info("%s(%x, %x)\n", __func__, adr, val);
405 if (adr != 0)
406 WRITE_VREG(adr, val);
407 }
408
409 #undef WRITE_VREG
410 #define WRITE_VREG WRITE_VREG_DBG2
411 #endif
412
413 #define FRAME_CNT_WINDOW_SIZE 59
414 #define RATE_CORRECTION_THRESHOLD 5
415 /**************************************************
416
417 VP9 buffer management start
418
419 ***************************************************/
420
421 #define MMU_COMPRESS_HEADER_SIZE 0x48000
422 #define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
423 #define MAX_SIZE_8K (8192 * 4608)
424 #define MAX_SIZE_4K (4096 * 2304)
425 #define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
426
427 #define INVALID_IDX -1 /* Invalid buffer index.*/
428
429 #define RPM_BEGIN 0x200
430 #define RPM_END 0x280
431
432 union param_u {
433 struct {
434 unsigned short data[RPM_END - RPM_BEGIN];
435 } l;
436 struct {
437 /* from ucode lmem, do not change this struct */
438 unsigned short profile;
439 unsigned short show_existing_frame;
440 unsigned short frame_to_show_idx;
441 unsigned short frame_type; /*1 bit*/
442 unsigned short show_frame; /*1 bit*/
443 unsigned short error_resilient_mode; /*1 bit*/
444 unsigned short intra_only; /*1 bit*/
445 unsigned short display_size_present; /*1 bit*/
446 unsigned short reset_frame_context;
447 unsigned short refresh_frame_flags;
448 unsigned short width;
449 unsigned short height;
450 unsigned short display_width;
451 unsigned short display_height;
452 /*
453 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
456 */
457 unsigned short ref_info;
458 /*
459 *bit[2]: same_frame_size0
460 *bit[1]: same_frame_size1
461 *bit[0]: same_frame_size2
462 */
463 unsigned short same_frame_size;
464
465 unsigned short mode_ref_delta_enabled;
466 unsigned short ref_deltas[4];
467 unsigned short mode_deltas[2];
468 unsigned short filter_level;
469 unsigned short sharpness_level;
470 unsigned short bit_depth;
471 unsigned short seg_quant_info[8];
472 unsigned short seg_enabled;
473 unsigned short seg_abs_delta;
474 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
475 unsigned short seg_lf_info[8];
476 } p;
477 };
478
479
480 struct vpx_codec_frame_buffer_s {
481 uint8_t *data; /**< Pointer to the data buffer */
482 size_t size; /**< Size of data in bytes */
483 void *priv; /**< Frame's private data */
484 };
485
486 enum vpx_color_space_t {
487 VPX_CS_UNKNOWN = 0, /**< Unknown */
488 VPX_CS_BT_601 = 1, /**< BT.601 */
489 VPX_CS_BT_709 = 2, /**< BT.709 */
490 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
491 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
492 VPX_CS_BT_2020 = 5, /**< BT.2020 */
493 VPX_CS_RESERVED = 6, /**< Reserved */
494 VPX_CS_SRGB = 7 /**< sRGB */
495 }; /**< alias for enum vpx_color_space */
496
497 enum vpx_bit_depth_t {
498 VPX_BITS_8 = 8, /**< 8 bits */
499 VPX_BITS_10 = 10, /**< 10 bits */
500 VPX_BITS_12 = 12, /**< 12 bits */
501 };
502
503 #define MAX_SLICE_NUM 1024
504 struct PIC_BUFFER_CONFIG_s {
505 int index;
506 int BUF_index;
507 int mv_buf_index;
508 int comp_body_size;
509 int buf_size;
510 int vf_ref;
511 int y_canvas_index;
512 int uv_canvas_index;
513 #ifdef MULTI_INSTANCE_SUPPORT
514 struct canvas_config_s canvas_config[2];
515 #endif
516 int decode_idx;
517 int slice_type;
518 int stream_offset;
519 u32 pts;
520 u64 pts64;
521 u64 timestamp;
522 uint8_t error_mark;
523 /**/
524 int slice_idx;
525 /*buffer*/
526 unsigned long header_adr;
527 unsigned long mpred_mv_wr_start_addr;
528 /*unsigned long mc_y_adr;
529 *unsigned long mc_u_v_adr;
530 */
531 unsigned int dw_y_adr;
532 unsigned int dw_u_v_adr;
533 int mc_canvas_y;
534 int mc_canvas_u_v;
535
536 int lcu_total;
537 /**/
538 int y_width;
539 int y_height;
540 int y_crop_width;
541 int y_crop_height;
542 int y_stride;
543
544 int uv_width;
545 int uv_height;
546 int uv_crop_width;
547 int uv_crop_height;
548 int uv_stride;
549
550 int alpha_width;
551 int alpha_height;
552 int alpha_stride;
553
554 uint8_t *y_buffer;
555 uint8_t *u_buffer;
556 uint8_t *v_buffer;
557 uint8_t *alpha_buffer;
558
559 uint8_t *buffer_alloc;
560 int buffer_alloc_sz;
561 int border;
562 int frame_size;
563 int subsampling_x;
564 int subsampling_y;
565 unsigned int bit_depth;
566 enum vpx_color_space_t color_space;
567
568 int corrupted;
569 int flags;
570 unsigned long cma_alloc_addr;
571
572 int double_write_mode;
573
574 /* picture qos infomation*/
575 int max_qp;
576 int avg_qp;
577 int min_qp;
578 int max_skip;
579 int avg_skip;
580 int min_skip;
581 int max_mv;
582 int min_mv;
583 int avg_mv;
584
585 bool vframe_bound;
586 } PIC_BUFFER_CONFIG;
587
588 enum BITSTREAM_PROFILE {
589 PROFILE_0,
590 PROFILE_1,
591 PROFILE_2,
592 PROFILE_3,
593 MAX_PROFILES
594 };
595
596 enum FRAME_TYPE {
597 KEY_FRAME = 0,
598 INTER_FRAME = 1,
599 FRAME_TYPES,
600 };
601
602 enum REFERENCE_MODE {
603 SINGLE_REFERENCE = 0,
604 COMPOUND_REFERENCE = 1,
605 REFERENCE_MODE_SELECT = 2,
606 REFERENCE_MODES = 3,
607 };
608
609 #define NONE -1
610 #define INTRA_FRAME 0
611 #define LAST_FRAME 1
612 #define GOLDEN_FRAME 2
613 #define ALTREF_FRAME 3
614 #define MAX_REF_FRAMES 4
615
616 #define REFS_PER_FRAME 3
617
618 #define REF_FRAMES_LOG2 3
619 #define REF_FRAMES (1 << REF_FRAMES_LOG2)
620 #define REF_FRAMES_4K (6)
621
622 /*4 scratch frames for the new frames to support a maximum of 4 cores decoding
623 *in parallel, 3 for scaled references on the encoder.
624 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
625 * // of framebuffers.
626 *TODO(jkoleszar): These 3 extra references could probably come from the
627 *normal reference pool.
628 */
629 #define FRAME_BUFFERS (REF_FRAMES + 16)
630 #define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
631 #define MAX_BUF_NUM (FRAME_BUFFERS)
632 #define MV_BUFFER_NUM FRAME_BUFFERS
633 #ifdef SUPPORT_FB_DECODING
634 #define STAGE_MAX_BUFFERS 16
635 #else
636 #define STAGE_MAX_BUFFERS 0
637 #endif
638
639 #define FRAME_CONTEXTS_LOG2 2
640 #define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
641 /*buffer + header buffer + workspace*/
642 #ifdef MV_USE_FIXED_BUF
643 #define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
644 #define VF_BUFFER_IDX(n) (n)
645 #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
646 #define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
647 #else
648 #define MAX_BMMU_BUFFER_NUM \
649 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
650 #define VF_BUFFER_IDX(n) (n)
651 #define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
652 #define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
653 #define WORK_SPACE_BUF_ID \
654 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
655 #endif
656
657 struct RefCntBuffer_s {
658 int ref_count;
659 /*MV_REF *mvs;*/
660 int mi_rows;
661 int mi_cols;
662 struct vpx_codec_frame_buffer_s raw_frame_buffer;
663 struct PIC_BUFFER_CONFIG_s buf;
664
665 /*The Following variables will only be used in frame parallel decode.
666 *
667 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
668 *that no FrameWorker owns, or is decoding, this buffer.
669 *VP9Worker *frame_worker_owner;
670 *
671 *row and col indicate which position frame has been decoded to in real
672 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
673 *when the frame is fully decoded.
674 */
675 int row;
676 int col;
677 } RefCntBuffer;
678
679 struct RefBuffer_s {
680 /*TODO(dkovalev): idx is not really required and should be removed, now it
681 *is used in vp9_onyxd_if.c
682 */
683 int idx;
684 struct PIC_BUFFER_CONFIG_s *buf;
685 /*struct scale_factors sf;*/
686 } RefBuffer;
687
688 struct InternalFrameBuffer_s {
689 uint8_t *data;
690 size_t size;
691 int in_use;
692 } InternalFrameBuffer;
693
694 struct InternalFrameBufferList_s {
695 int num_internal_frame_buffers;
696 struct InternalFrameBuffer_s *int_fb;
697 } InternalFrameBufferList;
698
699 struct BufferPool_s {
700 /*Protect BufferPool from being accessed by several FrameWorkers at
701 *the same time during frame parallel decode.
702 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
703 *
704 *Private data associated with the frame buffer callbacks.
705 *void *cb_priv;
706 *
707 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
708 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
709 */
710
711 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
712
713 /*Frame buffers allocated internally by the codec.*/
714 struct InternalFrameBufferList_s int_frame_buffers;
715 unsigned long flags;
716 spinlock_t lock;
717
718 } BufferPool;
719
720 #define lock_buffer_pool(pool, flags) \
721 spin_lock_irqsave(&pool->lock, flags)
722
723 #define unlock_buffer_pool(pool, flags) \
724 spin_unlock_irqrestore(&pool->lock, flags)
725
726 struct VP9_Common_s {
727 enum vpx_color_space_t color_space;
728 int width;
729 int height;
730 int display_width;
731 int display_height;
732 int last_width;
733 int last_height;
734
735 int subsampling_x;
736 int subsampling_y;
737
738 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
739
740 struct PIC_BUFFER_CONFIG_s *frame_to_show;
741 struct RefCntBuffer_s *prev_frame;
742
743 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
744 struct RefCntBuffer_s *cur_frame;
745
746 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
747
748 /*Prepare ref_frame_map for the next frame.
749 *Only used in frame parallel decode.
750 */
751 int next_ref_frame_map[REF_FRAMES];
752
753 /* TODO(jkoleszar): could expand active_ref_idx to 4,
754 *with 0 as intra, and roll new_fb_idx into it.
755 */
756
757 /*Each frame can reference REFS_PER_FRAME buffers*/
758 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
759
760 int prev_fb_idx;
761 int new_fb_idx;
762 int cur_fb_idx_mmu;
763 /*last frame's frame type for motion search*/
764 enum FRAME_TYPE last_frame_type;
765 enum FRAME_TYPE frame_type;
766
767 int show_frame;
768 int last_show_frame;
769 int show_existing_frame;
770
771 /*Flag signaling that the frame is encoded using only INTRA modes.*/
772 uint8_t intra_only;
773 uint8_t last_intra_only;
774
775 int allow_high_precision_mv;
776
777 /*Flag signaling that the frame context should be reset to default
778 *values. 0 or 1 implies don't reset, 2 reset just the context
779 *specified in the frame header, 3 reset all contexts.
780 */
781 int reset_frame_context;
782
783 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
784 * MODE_INFO (8-pixel) units.
785 */
786 int MBs;
787 int mb_rows, mi_rows;
788 int mb_cols, mi_cols;
789 int mi_stride;
790
791 /*Whether to use previous frame's motion vectors for prediction.*/
792 int use_prev_frame_mvs;
793
794 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
795
796 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
797
798 /*struct loopfilter lf;*/
799 /*struct segmentation seg;*/
800
801 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
802 /* in pbi.*/
803 int frame_parallel_decode; /* frame-based threading.*/
804
805 /*Context probabilities for reference frame prediction*/
806 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
807 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
808 enum REFERENCE_MODE reference_mode;
809
810 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
811 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
812 /*unsigned int frame_context_idx; *//* Context to use/update */
813 /*FRAME_COUNTS counts;*/
814
815 unsigned int current_video_frame;
816 enum BITSTREAM_PROFILE profile;
817
818 enum vpx_bit_depth_t bit_depth;
819
820 int error_resilient_mode;
821 int frame_parallel_decoding_mode;
822
823 int byte_alignment;
824 int skip_loop_filter;
825
826 /*External BufferPool passed from outside.*/
827 struct BufferPool_s *buffer_pool;
828
829 int above_context_alloc_cols;
830
831 };
832
833 static void set_canvas(struct VP9Decoder_s *pbi,
834 struct PIC_BUFFER_CONFIG_s *pic_config);
835 static int prepare_display_buf(struct VP9Decoder_s *pbi,
836 struct PIC_BUFFER_CONFIG_s *pic_config);
837
838 static void fill_frame_info(struct VP9Decoder_s *pbi,
839 struct PIC_BUFFER_CONFIG_s *frame,
840 unsigned int framesize,
841 unsigned int pts);
842
843 static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
844 {
845 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
846 }
847
848 static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
849 {
850 const int ref_index = *idx;
851
852 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
853 bufs[ref_index].ref_count--;
854 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
855 * ref_index, bufs[ref_index].ref_count);
856 */
857 }
858
859 *idx = new_idx;
860
861 bufs[new_idx].ref_count++;
862 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
863 * new_idx, bufs[new_idx].ref_count);
864 */
865 }
866
867 int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
868 {
869 struct InternalFrameBuffer_s *const int_fb =
870 (struct InternalFrameBuffer_s *)fb->priv;
871 if (int_fb)
872 int_fb->in_use = 0;
873 return 0;
874 }
875
876 static int compute_losless_comp_body_size(int width, int height,
877 uint8_t is_bit_depth_10);
878
879 static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
880 int print_header_info)
881 {
882 cm->display_width = cm->width;
883 cm->display_height = cm->height;
884 if (params->p.display_size_present) {
885 if (print_header_info)
886 pr_info(" * 1-bit display_size_present read : 1\n");
887 cm->display_width = params->p.display_width;
888 cm->display_height = params->p.display_height;
889 /*vp9_read_frame_size(rb, &cm->display_width,
890 * &cm->display_height);
891 */
892 } else {
893 if (print_header_info)
894 pr_info(" * 1-bit display_size_present read : 0\n");
895 }
896 }
897
898
899 uint8_t print_header_info = 0;
900
901 struct buff_s {
902 u32 buf_start;
903 u32 buf_size;
904 u32 buf_end;
905 } buff_t;
906
907 struct BuffInfo_s {
908 u32 max_width;
909 u32 max_height;
910 u32 start_adr;
911 u32 end_adr;
912 struct buff_s ipp;
913 struct buff_s sao_abv;
914 struct buff_s sao_vb;
915 struct buff_s short_term_rps;
916 struct buff_s vps;
917 struct buff_s sps;
918 struct buff_s pps;
919 struct buff_s sao_up;
920 struct buff_s swap_buf;
921 struct buff_s swap_buf2;
922 struct buff_s scalelut;
923 struct buff_s dblk_para;
924 struct buff_s dblk_data;
925 struct buff_s seg_map;
926 struct buff_s mmu_vbh;
927 struct buff_s cm_header;
928 struct buff_s mpred_above;
929 #ifdef MV_USE_FIXED_BUF
930 struct buff_s mpred_mv;
931 #endif
932 struct buff_s rpm;
933 struct buff_s lmem;
934 } BuffInfo_t;
935 #ifdef MULTI_INSTANCE_SUPPORT
936 #define DEC_RESULT_NONE 0
937 #define DEC_RESULT_DONE 1
938 #define DEC_RESULT_AGAIN 2
939 #define DEC_RESULT_CONFIG_PARAM 3
940 #define DEC_RESULT_ERROR 4
941 #define DEC_INIT_PICLIST 5
942 #define DEC_UNINIT_PICLIST 6
943 #define DEC_RESULT_GET_DATA 7
944 #define DEC_RESULT_GET_DATA_RETRY 8
945 #define DEC_RESULT_EOS 9
946 #define DEC_RESULT_FORCE_EXIT 10
947 #define DEC_V4L2_CONTINUE_DECODING 18
948
949 #define DEC_S1_RESULT_NONE 0
950 #define DEC_S1_RESULT_DONE 1
951 #define DEC_S1_RESULT_FORCE_EXIT 2
952 #define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
953
954 #ifdef FB_DECODING_TEST_SCHEDULE
955 #define TEST_SET_NONE 0
956 #define TEST_SET_PIC_DONE 1
957 #define TEST_SET_S2_DONE 2
958 #endif
959
960 static void vp9_work(struct work_struct *work);
961 #endif
962 struct loop_filter_info_n;
963 struct loopfilter;
964 struct segmentation;
965
966 #ifdef SUPPORT_FB_DECODING
967 static void mpred_process(struct VP9Decoder_s *pbi);
968 static void vp9_s1_work(struct work_struct *work);
969
970 struct stage_buf_s {
971 int index;
972 unsigned short rpm[RPM_END - RPM_BEGIN];
973 };
974
975 static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
976
977 static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
978
979 #ifdef FB_DECODING_TEST_SCHEDULE
980 u32 stage_buf_num; /* = 16;*/
981 #else
982 u32 stage_buf_num;
983 #endif
984 #endif
985
986 struct VP9Decoder_s {
987 #ifdef MULTI_INSTANCE_SUPPORT
988 unsigned char index;
989
990 struct device *cma_dev;
991 struct platform_device *platform_dev;
992 void (*vdec_cb)(struct vdec_s *, void *);
993 void *vdec_cb_arg;
994 struct vframe_chunk_s *chunk;
995 int dec_result;
996 struct work_struct work;
997 struct work_struct recycle_mmu_work;
998 struct work_struct set_clk_work;
999 u32 start_shift_bytes;
1000
1001 struct BuffInfo_s work_space_buf_store;
1002 unsigned long buf_start;
1003 u32 buf_size;
1004 u32 cma_alloc_count;
1005 unsigned long cma_alloc_addr;
1006 uint8_t eos;
1007 unsigned long int start_process_time;
1008 unsigned last_lcu_idx;
1009 int decode_timeout_count;
1010 unsigned timeout_num;
1011 int save_buffer_mode;
1012
1013 int double_write_mode;
1014 #endif
1015 long used_4k_num;
1016
1017 unsigned char m_ins_flag;
1018 char *provider_name;
1019 union param_u param;
1020 int frame_count;
1021 int pic_count;
1022 u32 stat;
1023 struct timer_list timer;
1024 u32 frame_dur;
1025 u32 frame_ar;
1026 int fatal_error;
1027 uint8_t init_flag;
1028 uint8_t first_sc_checked;
1029 uint8_t process_busy;
1030 #define PROC_STATE_INIT 0
1031 #define PROC_STATE_DECODESLICE 1
1032 #define PROC_STATE_SENDAGAIN 2
1033 uint8_t process_state;
1034 u32 ucode_pause_pos;
1035
1036 int show_frame_num;
1037 struct buff_s mc_buf_spec;
1038 struct dec_sysinfo vvp9_amstream_dec_info;
1039 void *rpm_addr;
1040 void *lmem_addr;
1041 dma_addr_t rpm_phy_addr;
1042 dma_addr_t lmem_phy_addr;
1043 unsigned short *lmem_ptr;
1044 unsigned short *debug_ptr;
1045
1046 void *prob_buffer_addr;
1047 void *count_buffer_addr;
1048 dma_addr_t prob_buffer_phy_addr;
1049 dma_addr_t count_buffer_phy_addr;
1050
1051 void *frame_mmu_map_addr;
1052 dma_addr_t frame_mmu_map_phy_addr;
1053
1054 unsigned int use_cma_flag;
1055
1056 struct BUF_s m_BUF[MAX_BUF_NUM];
1057 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1058 u32 used_buf_num;
1059 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1060 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1061 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1062 struct vframe_s vfpool[VF_POOL_SIZE];
1063 u32 vf_pre_count;
1064 u32 vf_get_count;
1065 u32 vf_put_count;
1066 int buf_num;
1067 int pic_num;
1068 int lcu_size_log2;
1069 unsigned int losless_comp_body_size;
1070
1071 u32 video_signal_type;
1072
1073 int pts_mode;
1074 int last_lookup_pts;
1075 int last_pts;
1076 u64 last_lookup_pts_us64;
1077 u64 last_pts_us64;
1078 u64 shift_byte_count;
1079
1080 u32 pts_unstable;
1081 u32 frame_cnt_window;
1082 u32 pts1, pts2;
1083 u32 last_duration;
1084 u32 duration_from_pts_done;
1085 bool vp9_first_pts_ready;
1086
1087 u32 shift_byte_count_lo;
1088 u32 shift_byte_count_hi;
1089 int pts_mode_switching_count;
1090 int pts_mode_recovery_count;
1091
1092 bool get_frame_dur;
1093 u32 saved_resolution;
1094
1095 /**/
1096 struct VP9_Common_s common;
1097 struct RefCntBuffer_s *cur_buf;
1098 int refresh_frame_flags;
1099 uint8_t need_resync;
1100 uint8_t hold_ref_buf;
1101 uint8_t ready_for_new_data;
1102 struct BufferPool_s vp9_buffer_pool;
1103
1104 struct BuffInfo_s *work_space_buf;
1105
1106 struct buff_s *mc_buf;
1107
1108 unsigned int frame_width;
1109 unsigned int frame_height;
1110
1111 unsigned short *rpm_ptr;
1112 int init_pic_w;
1113 int init_pic_h;
1114 int lcu_total;
1115 int lcu_size;
1116
1117 int slice_type;
1118
1119 int skip_flag;
1120 int decode_idx;
1121 int slice_idx;
1122 uint8_t has_keyframe;
1123 uint8_t wait_buf;
1124 uint8_t error_flag;
1125
1126 /* bit 0, for decoding; bit 1, for displaying */
1127 uint8_t ignore_bufmgr_error;
1128 int PB_skip_mode;
1129 int PB_skip_count_after_decoding;
1130 /*hw*/
1131
1132 /*lf*/
1133 int default_filt_lvl;
1134 struct loop_filter_info_n *lfi;
1135 struct loopfilter *lf;
1136 struct segmentation *seg_4lf;
1137 /**/
1138 struct vdec_info *gvs;
1139
1140 u32 pre_stream_offset;
1141
1142 unsigned int dec_status;
1143 u32 last_put_idx;
1144 int new_frame_displayed;
1145 void *mmu_box;
1146 void *bmmu_box;
1147 int mmu_enable;
1148 struct vframe_master_display_colour_s vf_dp;
1149 struct firmware_s *fw;
1150 int max_pic_w;
1151 int max_pic_h;
1152 #ifdef SUPPORT_FB_DECODING
1153 int dec_s1_result;
1154 int s1_test_cmd;
1155 struct work_struct s1_work;
1156 int used_stage_buf_num;
1157 int s1_pos;
1158 int s2_pos;
1159 void *stage_mmu_map_addr;
1160 dma_addr_t stage_mmu_map_phy_addr;
1161 struct stage_buf_s *s1_buf;
1162 struct stage_buf_s *s2_buf;
1163 struct stage_buf_s *stage_bufs
1164 [STAGE_MAX_BUFFERS];
1165 unsigned char run2_busy;
1166
1167 int s1_mv_buf_index;
1168 int s1_mv_buf_index_pre;
1169 int s1_mv_buf_index_pre_pre;
1170 unsigned long s1_mpred_mv_wr_start_addr;
1171 unsigned long s1_mpred_mv_wr_start_addr_pre;
1172 unsigned short s1_intra_only;
1173 unsigned short s1_frame_type;
1174 unsigned short s1_width;
1175 unsigned short s1_height;
1176 unsigned short s1_last_show_frame;
1177 union param_u s1_param;
1178 u8 back_not_run_ready;
1179 #endif
1180 int need_cache_size;
1181 u64 sc_start_time;
1182 bool postproc_done;
1183 int low_latency_flag;
1184 bool no_head;
1185 bool pic_list_init_done;
1186 bool pic_list_init_done2;
1187 bool is_used_v4l;
1188 void *v4l2_ctx;
1189 bool v4l_params_parsed;
1190 int frameinfo_enable;
1191 struct vframe_qos_s vframe_qos;
1192 u32 mem_map_mode;
1193 u32 dynamic_buf_num_margin;
1194 struct vframe_s vframe_dummy;
1195 };
1196
1197 static int vp9_print(struct VP9Decoder_s *pbi,
1198 int flag, const char *fmt, ...)
1199 {
1200 #define HEVC_PRINT_BUF 256
1201 unsigned char buf[HEVC_PRINT_BUF];
1202 int len = 0;
1203
1204 if (pbi == NULL ||
1205 (flag == 0) ||
1206 (debug & flag)) {
1207 va_list args;
1208
1209 va_start(args, fmt);
1210 if (pbi)
1211 len = sprintf(buf, "[%d]", pbi->index);
1212 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1213 pr_debug("%s", buf);
1214 va_end(args);
1215 }
1216 return 0;
1217 }
1218
1219 static int is_oversize(int w, int h)
1220 {
1221 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1222 MAX_SIZE_8K : MAX_SIZE_4K;
1223
1224 if (w <= 0 || h <= 0)
1225 return true;
1226
1227 if (h != 0 && (w > max / h))
1228 return true;
1229
1230 return false;
1231 }
1232
1233 static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1234 struct PIC_BUFFER_CONFIG_s *pic);
1235
1236 static void resize_context_buffers(struct VP9Decoder_s *pbi,
1237 struct VP9_Common_s *cm, int width, int height)
1238 {
1239 if (cm->width != width || cm->height != height) {
1240 /* to do ..*/
1241 if (pbi != NULL) {
1242 pbi->vp9_first_pts_ready = 0;
1243 pbi->duration_from_pts_done = 0;
1244 }
1245 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1246 cm->height, width, height);
1247 cm->width = width;
1248 cm->height = height;
1249 }
1250 /*
1251 *if (cm->cur_frame->mvs == NULL ||
1252 * cm->mi_rows > cm->cur_frame->mi_rows ||
1253 * cm->mi_cols > cm->cur_frame->mi_cols) {
1254 * resize_mv_buffer(cm);
1255 *}
1256 */
1257 }
1258
1259 static int valid_ref_frame_size(int ref_width, int ref_height,
1260 int this_width, int this_height) {
1261 return 2 * this_width >= ref_width &&
1262 2 * this_height >= ref_height &&
1263 this_width <= 16 * ref_width &&
1264 this_height <= 16 * ref_height;
1265 }
1266
1267 /*
1268 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1269 * int ref_xss, int ref_yss,
1270 * enum vpx_bit_depth_t this_bit_depth,
1271 * int this_xss, int this_yss) {
1272 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1273 * ref_yss == this_yss;
1274 *}
1275 */
1276
1277
1278 static int setup_frame_size(
1279 struct VP9Decoder_s *pbi,
1280 struct VP9_Common_s *cm, union param_u *params,
1281 unsigned int *mmu_index_adr,
1282 int print_header_info) {
1283 int width, height;
1284 struct BufferPool_s * const pool = cm->buffer_pool;
1285 struct PIC_BUFFER_CONFIG_s *ybf;
1286 int ret = 0;
1287
1288 width = params->p.width;
1289 height = params->p.height;
1290 if (is_oversize(width, height)) {
1291 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1292 return -1;
1293 }
1294
1295 /*vp9_read_frame_size(rb, &width, &height);*/
1296 if (print_header_info)
1297 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1298 if (print_header_info)
1299 pr_info
1300 (" * 16-bits h read : %d (height : %d)\n", width, height);
1301
1302 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1303 #ifdef VP9_10B_HED_FB
1304 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1305 #endif
1306 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1307 ret = vp9_alloc_mmu(pbi,
1308 cm->new_fb_idx,
1309 params->p.width,
1310 params->p.height,
1311 params->p.bit_depth,
1312 mmu_index_adr);
1313 if (ret != 0) {
1314 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1315 cm->new_fb_idx,
1316 ret);
1317 return ret;
1318 }
1319 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1320 }
1321
1322 resize_context_buffers(pbi, cm, width, height);
1323 setup_display_size(cm, params, print_header_info);
1324 #if 0
1325 lock_buffer_pool(pool);
1326 if (vp9_realloc_frame_buffer(
1327 get_frame_new_buffer(cm), cm->width, cm->height,
1328 cm->subsampling_x, cm->subsampling_y,
1329 #if CONFIG_VP9_HIGHBITDEPTH
1330 cm->use_highbitdepth,
1331 #endif
1332 VP9_DEC_BORDER_IN_PIXELS,
1333 cm->byte_alignment,
1334 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1335 pool->get_fb_cb, pool->cb_priv)) {
1336 unlock_buffer_pool(pool);
1337 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1338 "Failed to allocate frame buffer");
1339 }
1340 unlock_buffer_pool(pool);
1341 #else
1342 /* porting */
1343 ybf = get_frame_new_buffer(cm);
1344 if (!ybf)
1345 return -1;
1346
1347 ybf->y_crop_width = width;
1348 ybf->y_crop_height = height;
1349 ybf->bit_depth = params->p.bit_depth;
1350 #endif
1351 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1352 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1353 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1354 (unsigned int)cm->bit_depth;
1355 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1356 return ret;
1357 }
1358
1359 static int setup_frame_size_with_refs(
1360 struct VP9Decoder_s *pbi,
1361 struct VP9_Common_s *cm,
1362 union param_u *params,
1363 unsigned int *mmu_index_adr,
1364 int print_header_info) {
1365
1366 int width, height;
1367 int found = 0, i;
1368 int has_valid_ref_frame = 0;
1369 struct PIC_BUFFER_CONFIG_s *ybf;
1370 struct BufferPool_s * const pool = cm->buffer_pool;
1371 int ret = 0;
1372
1373 for (i = 0; i < REFS_PER_FRAME; ++i) {
1374 if ((params->p.same_frame_size >>
1375 (REFS_PER_FRAME - i - 1)) & 0x1) {
1376 struct PIC_BUFFER_CONFIG_s *const buf =
1377 cm->frame_refs[i].buf;
1378 /*if (print_header_info)
1379 * pr_info
1380 * ("1-bit same_frame_size[%d] read : 1\n", i);
1381 */
1382 width = buf->y_crop_width;
1383 height = buf->y_crop_height;
1384 /*if (print_header_info)
1385 * pr_info
1386 * (" - same_frame_size width : %d\n", width);
1387 */
1388 /*if (print_header_info)
1389 * pr_info
1390 * (" - same_frame_size height : %d\n", height);
1391 */
1392 found = 1;
1393 break;
1394 } else {
1395 /*if (print_header_info)
1396 * pr_info
1397 * ("1-bit same_frame_size[%d] read : 0\n", i);
1398 */
1399 }
1400 }
1401
1402 if (!found) {
1403 /*vp9_read_frame_size(rb, &width, &height);*/
1404 width = params->p.width;
1405 height = params->p.height;
1406 /*if (print_header_info)
1407 * pr_info
1408 * (" * 16-bits w read : %d (width : %d)\n",
1409 * width, height);
1410 *if (print_header_info)
1411 * pr_info
1412 * (" * 16-bits h read : %d (height : %d)\n",
1413 * width, height);
1414 */
1415 }
1416
1417 if (is_oversize(width, height)) {
1418 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1419 return -1;
1420 }
1421
1422 params->p.width = width;
1423 params->p.height = height;
1424
1425 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1426 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1427 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1428 *cm->prev_fb_idx = cm->new_fb_idx;
1429 */
1430 /* pr_info
1431 * ("[DEBUG DEBUG]Before alloc_mmu,
1432 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1433 * cm->prev_fb_idx, cm->new_fb_idx);
1434 */
1435 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1436 params->p.width, params->p.height,
1437 params->p.bit_depth, mmu_index_adr);
1438 if (ret != 0) {
1439 pr_err("can't alloc need mmu,idx %d\r\n",
1440 cm->new_fb_idx);
1441 return ret;
1442 }
1443 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1444 }
1445
1446 /*Check to make sure at least one of frames that this frame references
1447 *has valid dimensions.
1448 */
1449 for (i = 0; i < REFS_PER_FRAME; ++i) {
1450 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1451
1452 has_valid_ref_frame |=
1453 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1454 ref_frame->buf->y_crop_height,
1455 width, height);
1456 }
1457 if (!has_valid_ref_frame) {
1458 pr_err("Error: Referenced frame has invalid size\r\n");
1459 return -1;
1460 }
1461 #if 0
1462 for (i = 0; i < REFS_PER_FRAME; ++i) {
1463 struct RefBuffer_s * const ref_frame =
1464 &cm->frame_refs[i];
1465 if (!valid_ref_frame_img_fmt(
1466 ref_frame->buf->bit_depth,
1467 ref_frame->buf->subsampling_x,
1468 ref_frame->buf->subsampling_y,
1469 cm->bit_depth,
1470 cm->subsampling_x,
1471 cm->subsampling_y))
1472 pr_err
1473 ("Referenced frame incompatible color fmt\r\n");
1474 return -1;
1475 }
1476 #endif
1477 resize_context_buffers(pbi, cm, width, height);
1478 setup_display_size(cm, params, print_header_info);
1479
1480 #if 0
1481 lock_buffer_pool(pool);
1482 if (vp9_realloc_frame_buffer(
1483 get_frame_new_buffer(cm), cm->width, cm->height,
1484 cm->subsampling_x, cm->subsampling_y,
1485 #if CONFIG_VP9_HIGHBITDEPTH
1486 cm->use_highbitdepth,
1487 #endif
1488 VP9_DEC_BORDER_IN_PIXELS,
1489 cm->byte_alignment,
1490 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1491 pool->get_fb_cb,
1492 pool->cb_priv)) {
1493 unlock_buffer_pool(pool);
1494 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1495 "Failed to allocate frame buffer");
1496 }
1497 unlock_buffer_pool(pool);
1498 #else
1499 /* porting */
1500 ybf = get_frame_new_buffer(cm);
1501 if (!ybf)
1502 return -1;
1503
1504 ybf->y_crop_width = width;
1505 ybf->y_crop_height = height;
1506 ybf->bit_depth = params->p.bit_depth;
1507 #endif
1508 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1509 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1510 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1511 (unsigned int)cm->bit_depth;
1512 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1513 return ret;
1514 }
1515
1516 static inline bool close_to(int a, int b, int m)
1517 {
1518 return (abs(a - b) < m) ? true : false;
1519 }
1520
1521 #ifdef MULTI_INSTANCE_SUPPORT
1522 static int vp9_print_cont(struct VP9Decoder_s *pbi,
1523 int flag, const char *fmt, ...)
1524 {
1525 unsigned char buf[HEVC_PRINT_BUF];
1526 int len = 0;
1527
1528 if (pbi == NULL ||
1529 (flag == 0) ||
1530 (debug & flag)) {
1531 va_list args;
1532
1533 va_start(args, fmt);
1534 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1535 pr_debug("%s", buf);
1536 va_end(args);
1537 }
1538 return 0;
1539 }
1540
1541 static void trigger_schedule(struct VP9Decoder_s *pbi)
1542 {
1543 if (pbi->is_used_v4l) {
1544 struct aml_vcodec_ctx *ctx =
1545 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1546
1547 if (ctx->param_sets_from_ucode &&
1548 !pbi->v4l_params_parsed)
1549 vdec_v4l_write_frame_sync(ctx);
1550 }
1551
1552 if (pbi->vdec_cb)
1553 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1554 }
1555
1556 static void reset_process_time(struct VP9Decoder_s *pbi)
1557 {
1558 if (pbi->start_process_time) {
1559 unsigned process_time =
1560 1000 * (jiffies - pbi->start_process_time) / HZ;
1561 pbi->start_process_time = 0;
1562 if (process_time > max_process_time[pbi->index])
1563 max_process_time[pbi->index] = process_time;
1564 }
1565 }
1566
1567 static void start_process_time(struct VP9Decoder_s *pbi)
1568 {
1569 pbi->start_process_time = jiffies;
1570 pbi->decode_timeout_count = 0;
1571 pbi->last_lcu_idx = 0;
1572 }
1573
1574 static void timeout_process(struct VP9Decoder_s *pbi)
1575 {
1576 pbi->timeout_num++;
1577 amhevc_stop();
1578 vp9_print(pbi,
1579 0, "%s decoder timeout\n", __func__);
1580
1581 pbi->dec_result = DEC_RESULT_DONE;
1582 reset_process_time(pbi);
1583 vdec_schedule_work(&pbi->work);
1584 }
1585
1586 static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1587 {
1588 return ((double_write_mode & 0x80000000) == 0) ?
1589 pbi->double_write_mode :
1590 (double_write_mode & 0x7fffffff);
1591 }
1592
1593 static int get_double_write_mode(struct VP9Decoder_s *pbi)
1594 {
1595 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1596 u32 dw;
1597 int w, h;
1598 struct VP9_Common_s *cm = &pbi->common;
1599 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1600
1601 /* mask for supporting double write value bigger than 0x100 */
1602 if (valid_dw_mode & 0xffffff00) {
1603 if (!cm->cur_frame)
1604 return 1;/*no valid frame,*/
1605 cur_pic_config = &cm->cur_frame->buf;
1606 w = cur_pic_config->y_crop_width;
1607 h = cur_pic_config->y_crop_height;
1608
1609 dw = 0x1; /*1:1*/
1610 switch (valid_dw_mode) {
1611 case 0x100:
1612 if (w > 1920 && h > 1088)
1613 dw = 0x4; /*1:2*/
1614 break;
1615 case 0x200:
1616 if (w > 1920 && h > 1088)
1617 dw = 0x2; /*1:4*/
1618 break;
1619 case 0x300:
1620 if (w > 1280 && h > 720)
1621 dw = 0x4; /*1:2*/
1622 break;
1623 default:
1624 break;
1625 }
1626 return dw;
1627 }
1628
1629 return valid_dw_mode;
1630 }
1631
1632 /* for double write buf alloc */
1633 static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1634 {
1635 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1636 u32 dw;
1637 int w = pbi->init_pic_w;
1638 int h = pbi->init_pic_h;
1639
1640 dw = 0x1; /*1:1*/
1641 switch (valid_dw_mode) {
1642 case 0x100:
1643 if (w > 1920 && h > 1088)
1644 dw = 0x4; /*1:2*/
1645 break;
1646 case 0x200:
1647 if (w > 1920 && h > 1088)
1648 dw = 0x2; /*1:4*/
1649 break;
1650 case 0x300:
1651 if (w > 1280 && h > 720)
1652 dw = 0x4; /*1:2*/
1653 break;
1654 default:
1655 dw = valid_dw_mode;
1656 break;
1657 }
1658 return dw;
1659 }
1660 #endif
1661
1662 static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1663 int dw_mode)
1664 {
1665 int ratio = 1;
1666 if ((dw_mode == 2) ||
1667 (dw_mode == 3))
1668 ratio = 4;
1669 else if (dw_mode == 4)
1670 ratio = 2;
1671 return ratio;
1672 }
1673
1674 //#define MAX_4K_NUM 0x1200
1675
1676 int vp9_alloc_mmu(
1677 struct VP9Decoder_s *pbi,
1678 int cur_buf_idx,
1679 int pic_width,
1680 int pic_height,
1681 unsigned short bit_depth,
1682 unsigned int *mmu_index_adr)
1683 {
1684 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1685 int picture_size;
1686 int cur_mmu_4k_number, max_frame_num;
1687 if (!pbi->mmu_box) {
1688 pr_err("error no mmu box!\n");
1689 return -1;
1690 }
1691 if (pbi->double_write_mode & 0x10)
1692 return 0;
1693 if (bit_depth >= VPX_BITS_12) {
1694 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1695 pr_err("fatal_error, un support bit depth 12!\n\n");
1696 return -1;
1697 }
1698 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1699 bit_depth_10);
1700 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1701
1702 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1703 max_frame_num = MAX_FRAME_8K_NUM;
1704 else
1705 max_frame_num = MAX_FRAME_4K_NUM;
1706
1707 if (cur_mmu_4k_number > max_frame_num) {
1708 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1709 cur_mmu_4k_number, pic_width, pic_height);
1710 return -1;
1711 }
1712 return decoder_mmu_box_alloc_idx(
1713 pbi->mmu_box,
1714 cur_buf_idx,
1715 cur_mmu_4k_number,
1716 mmu_index_adr);
1717 }
1718
1719
1720 #ifndef MV_USE_FIXED_BUF
1721 static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1722 {
1723 int i;
1724 for (i = 0; i < MV_BUFFER_NUM; i++) {
1725 if (pbi->m_mv_BUF[i].start_adr) {
1726 if (debug)
1727 pr_info(
1728 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1729 i, pbi->m_mv_BUF[i].start_adr,
1730 pbi->m_mv_BUF[i].size,
1731 pbi->m_mv_BUF[i].used_flag);
1732 decoder_bmmu_box_free_idx(
1733 pbi->bmmu_box,
1734 MV_BUFFER_IDX(i));
1735 pbi->m_mv_BUF[i].start_adr = 0;
1736 pbi->m_mv_BUF[i].size = 0;
1737 pbi->m_mv_BUF[i].used_flag = 0;
1738 }
1739 }
1740 }
1741
1742 static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1743 int i, int size)
1744 {
1745 int ret = 0;
1746
1747 if (pbi->m_mv_BUF[i].start_adr &&
1748 size > pbi->m_mv_BUF[i].size) {
1749 dealloc_mv_bufs(pbi);
1750 } else if (pbi->m_mv_BUF[i].start_adr)
1751 return 0;
1752
1753 if (decoder_bmmu_box_alloc_buf_phy
1754 (pbi->bmmu_box,
1755 MV_BUFFER_IDX(i), size,
1756 DRIVER_NAME,
1757 &pbi->m_mv_BUF[i].start_adr) < 0) {
1758 pbi->m_mv_BUF[i].start_adr = 0;
1759 ret = -1;
1760 } else {
1761 pbi->m_mv_BUF[i].size = size;
1762 pbi->m_mv_BUF[i].used_flag = 0;
1763 ret = 0;
1764 if (debug) {
1765 pr_info(
1766 "MV Buffer %d: start_adr %p size %x\n",
1767 i,
1768 (void *)pbi->m_mv_BUF[i].start_adr,
1769 pbi->m_mv_BUF[i].size);
1770 }
1771 }
1772 return ret;
1773 }
1774
1775 static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1776 {
1777 int i;
1778 int ret = 0;
1779 int count = MV_BUFFER_NUM;
1780 int pic_width = pbi->init_pic_w;
1781 int pic_height = pbi->init_pic_h;
1782 int lcu_size = 64; /*fixed 64*/
1783 int pic_width_64 = (pic_width + 63) & (~0x3f);
1784 int pic_height_32 = (pic_height + 31) & (~0x1f);
1785 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1786 pic_width_64 / lcu_size + 1
1787 : pic_width_64 / lcu_size;
1788 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1789 pic_height_32 / lcu_size + 1
1790 : pic_height_32 / lcu_size;
1791 int lcu_total = pic_width_lcu * pic_height_lcu;
1792 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1793 (~0xffff);
1794 if (mv_buf_margin > 0)
1795 count = REF_FRAMES + mv_buf_margin;
1796
1797 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1798 count = REF_FRAMES_4K + mv_buf_margin;
1799
1800 if (debug) {
1801 pr_info("%s w:%d, h:%d, count: %d\n",
1802 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1803 }
1804
1805 for (i = 0;
1806 i < count && i < MV_BUFFER_NUM; i++) {
1807 if (alloc_mv_buf(pbi, i, size) < 0) {
1808 ret = -1;
1809 break;
1810 }
1811 }
1812 return ret;
1813 }
1814
1815 static int get_mv_buf(struct VP9Decoder_s *pbi,
1816 int *mv_buf_index,
1817 unsigned long *mpred_mv_wr_start_addr)
1818 {
1819 int i;
1820 int ret = -1;
1821 for (i = 0; i < MV_BUFFER_NUM; i++) {
1822 if (pbi->m_mv_BUF[i].start_adr &&
1823 pbi->m_mv_BUF[i].used_flag == 0) {
1824 pbi->m_mv_BUF[i].used_flag = 1;
1825 ret = i;
1826 break;
1827 }
1828 }
1829
1830 if (ret >= 0) {
1831 *mv_buf_index = ret;
1832 *mpred_mv_wr_start_addr =
1833 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1834 (~0xffff);
1835 if (debug & VP9_DEBUG_BUFMGR_MORE)
1836 pr_info(
1837 "%s => %d (%ld) size 0x%x\n",
1838 __func__, ret,
1839 *mpred_mv_wr_start_addr,
1840 pbi->m_mv_BUF[ret].size);
1841 } else {
1842 pr_info(
1843 "%s: Error, mv buf is not enough\n",
1844 __func__);
1845 }
1846 return ret;
1847 }
1848
1849 static void put_mv_buf(struct VP9Decoder_s *pbi,
1850 int *mv_buf_index)
1851 {
1852 int i = *mv_buf_index;
1853 if (i >= MV_BUFFER_NUM) {
1854 if (debug & VP9_DEBUG_BUFMGR_MORE)
1855 pr_info(
1856 "%s: index %d beyond range\n",
1857 __func__, i);
1858 return;
1859 }
1860 if (debug & VP9_DEBUG_BUFMGR_MORE)
1861 pr_info(
1862 "%s(%d): used_flag(%d)\n",
1863 __func__, i,
1864 pbi->m_mv_BUF[i].used_flag);
1865
1866 *mv_buf_index = -1;
1867 if (pbi->m_mv_BUF[i].start_adr &&
1868 pbi->m_mv_BUF[i].used_flag)
1869 pbi->m_mv_BUF[i].used_flag = 0;
1870 }
1871
1872 static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1873 {
1874 struct VP9_Common_s *const cm = &pbi->common;
1875 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1876 int i;
1877 for (i = 0; i < pbi->used_buf_num; ++i) {
1878 if ((frame_bufs[i].ref_count == 0) &&
1879 (frame_bufs[i].buf.index != -1) &&
1880 (frame_bufs[i].buf.mv_buf_index >= 0)
1881 )
1882 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1883 }
1884 }
1885
1886 #ifdef SUPPORT_FB_DECODING
1887 static bool mv_buf_available(struct VP9Decoder_s *pbi)
1888 {
1889 int i;
1890 bool ret = 0;
1891 for (i = 0; i < MV_BUFFER_NUM; i++) {
1892 if (pbi->m_mv_BUF[i].start_adr &&
1893 pbi->m_mv_BUF[i].used_flag == 0) {
1894 ret = 1;
1895 break;
1896 }
1897 }
1898 return ret;
1899 }
1900 #endif
1901 #endif
1902
1903 #ifdef SUPPORT_FB_DECODING
1904 static void init_stage_buf(struct VP9Decoder_s *pbi)
1905 {
1906 uint i;
1907 for (i = 0; i < STAGE_MAX_BUFFERS
1908 && i < stage_buf_num; i++) {
1909 pbi->stage_bufs[i] =
1910 vmalloc(sizeof(struct stage_buf_s));
1911 if (pbi->stage_bufs[i] == NULL) {
1912 vp9_print(pbi,
1913 0, "%s vmalloc fail\n", __func__);
1914 break;
1915 }
1916 pbi->stage_bufs[i]->index = i;
1917 }
1918 pbi->used_stage_buf_num = i;
1919 pbi->s1_pos = 0;
1920 pbi->s2_pos = 0;
1921 pbi->s1_buf = NULL;
1922 pbi->s2_buf = NULL;
1923 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1924 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1925 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1926
1927 if (pbi->used_stage_buf_num > 0)
1928 vp9_print(pbi,
1929 0, "%s 2 stage decoding buf %d\n",
1930 __func__,
1931 pbi->used_stage_buf_num);
1932 }
1933
1934 static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1935 {
1936 int i;
1937 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1938 if (pbi->stage_bufs[i])
1939 vfree(pbi->stage_bufs[i]);
1940 pbi->stage_bufs[i] = NULL;
1941 }
1942 pbi->used_stage_buf_num = 0;
1943 pbi->s1_pos = 0;
1944 pbi->s2_pos = 0;
1945 pbi->s1_buf = NULL;
1946 pbi->s2_buf = NULL;
1947 }
1948
1949 static int get_s1_buf(
1950 struct VP9Decoder_s *pbi)
1951 {
1952 struct stage_buf_s *buf = NULL;
1953 int ret = -1;
1954 int buf_page_num = MAX_STAGE_PAGE_NUM;
1955 int next_s1_pos = pbi->s1_pos + 1;
1956
1957 if (next_s1_pos >= pbi->used_stage_buf_num)
1958 next_s1_pos = 0;
1959 if (next_s1_pos == pbi->s2_pos) {
1960 pbi->s1_buf = NULL;
1961 return ret;
1962 }
1963
1964 buf = pbi->stage_bufs[pbi->s1_pos];
1965 ret = decoder_mmu_box_alloc_idx(
1966 pbi->mmu_box,
1967 buf->index,
1968 buf_page_num,
1969 pbi->stage_mmu_map_addr);
1970 if (ret < 0) {
1971 vp9_print(pbi, 0,
1972 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1973 __func__, buf->index,
1974 pbi->s1_pos, pbi->s2_pos);
1975 buf = NULL;
1976 } else {
1977 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1978 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1979 __func__, buf_page_num, buf->index,
1980 pbi->s1_pos, pbi->s2_pos);
1981 }
1982 pbi->s1_buf = buf;
1983 return ret;
1984 }
1985
1986 static void inc_s1_pos(struct VP9Decoder_s *pbi)
1987 {
1988 struct stage_buf_s *buf =
1989 pbi->stage_bufs[pbi->s1_pos];
1990
1991 int used_page_num =
1992 #ifdef FB_DECODING_TEST_SCHEDULE
1993 MAX_STAGE_PAGE_NUM/2;
1994 #else
1995 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
1996 #endif
1997 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
1998 FRAME_BUFFERS + buf->index, used_page_num);
1999
2000 pbi->s1_pos++;
2001 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2002 pbi->s1_pos = 0;
2003
2004 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2005 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2006 __func__, used_page_num, buf->index,
2007 pbi->s1_pos, pbi->s2_pos);
2008 }
2009
2010 #define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2011
2012 static int get_s2_buf(
2013 struct VP9Decoder_s *pbi)
2014 {
2015 int ret = -1;
2016 struct stage_buf_s *buf = NULL;
2017 if (s2_buf_available(pbi)) {
2018 buf = pbi->stage_bufs[pbi->s2_pos];
2019 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2020 "%s for index %d (s1_pos %d s2_pos %d)\n",
2021 __func__, buf->index,
2022 pbi->s1_pos, pbi->s2_pos);
2023 pbi->s2_buf = buf;
2024 ret = 0;
2025 }
2026 return ret;
2027 }
2028
2029 static void inc_s2_pos(struct VP9Decoder_s *pbi)
2030 {
2031 struct stage_buf_s *buf =
2032 pbi->stage_bufs[pbi->s2_pos];
2033 decoder_mmu_box_free_idx(pbi->mmu_box,
2034 FRAME_BUFFERS + buf->index);
2035 pbi->s2_pos++;
2036 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2037 pbi->s2_pos = 0;
2038 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2039 "%s for index %d (s1_pos %d s2_pos %d)\n",
2040 __func__, buf->index,
2041 pbi->s1_pos, pbi->s2_pos);
2042 }
2043
2044 static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2045 {
2046 int num;
2047 if (pbi->s1_pos >= pbi->s2_pos)
2048 num = pbi->used_stage_buf_num -
2049 (pbi->s1_pos - pbi->s2_pos) - 1;
2050 else
2051 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2052 return num;
2053 }
2054
2055 #ifndef FB_DECODING_TEST_SCHEDULE
2056 static DEFINE_SPINLOCK(fb_core_spin_lock);
2057
2058 static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2059 {
2060 /* to do: VLSI review
2061 completion of last LCU decoding in BACK
2062 */
2063 return 1;
2064 }
2065
2066 static void start_s1_decoding(struct VP9Decoder_s *pbi)
2067 {
2068 /* to do: VLSI review
2069 after parser, how to start LCU decoding in BACK
2070 */
2071 }
2072
2073 static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2074 {
2075 /* to do: VLSI review
2076 1. how to disconnect DMC for FRONT and BACK
2077 2. reset bit 13, 24, FRONT or BACK ??
2078 */
2079
2080 unsigned long flags;
2081 u32 reset_bits = 0;
2082 if (mask & HW_MASK_FRONT)
2083 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2084 spin_lock_irqsave(&fb_core_spin_lock, flags);
2085 codec_dmcbus_write(DMC_REQ_CTRL,
2086 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2087 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2088
2089 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2090 & (1 << 4)))
2091 ;
2092
2093 if ((mask & HW_MASK_FRONT) &&
2094 input_frame_based(vdec))
2095 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2096
2097 /*
2098 * 2: assist
2099 * 3: parser
2100 * 4: parser_state
2101 * 8: dblk
2102 * 11:mcpu
2103 * 12:ccpu
2104 * 13:ddr
2105 * 14:iqit
2106 * 15:ipp
2107 * 17:qdct
2108 * 18:mpred
2109 * 19:sao
2110 * 24:hevc_afifo
2111 */
2112 if (mask & HW_MASK_FRONT) {
2113 reset_bits =
2114 (1<<3)|(1<<4)|(1<<11)|
2115 (1<<12)|(1<<18);
2116 }
2117 if (mask & HW_MASK_BACK) {
2118 reset_bits =
2119 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2120 (1<<17)|(1<<19)|(1<<24);
2121 }
2122 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2123 #if 0
2124 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2125 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2126 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2127 #endif
2128 WRITE_VREG(DOS_SW_RESET3, 0);
2129
2130
2131 spin_lock_irqsave(&fb_core_spin_lock, flags);
2132 codec_dmcbus_write(DMC_REQ_CTRL,
2133 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2134 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2135
2136 }
2137 #endif
2138
2139 #endif
2140
2141 static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2142
2143 static int get_free_fb(struct VP9Decoder_s *pbi)
2144 {
2145 struct VP9_Common_s *const cm = &pbi->common;
2146 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2147 int i;
2148 unsigned long flags;
2149
2150 lock_buffer_pool(cm->buffer_pool, flags);
2151 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2152 for (i = 0; i < pbi->used_buf_num; ++i) {
2153 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2154 __func__, i, frame_bufs[i].ref_count,
2155 frame_bufs[i].buf.vf_ref,
2156 frame_bufs[i].buf.index);
2157 }
2158 }
2159 for (i = 0; i < pbi->used_buf_num; ++i) {
2160 if ((frame_bufs[i].ref_count == 0) &&
2161 (frame_bufs[i].buf.vf_ref == 0) &&
2162 (frame_bufs[i].buf.index != -1)
2163 )
2164 break;
2165 }
2166 if (i != pbi->used_buf_num) {
2167 frame_bufs[i].ref_count = 1;
2168 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2169 i, frame_bufs[i].ref_count);*/
2170 } else {
2171 /* Reset i to be INVALID_IDX to indicate
2172 no free buffer found*/
2173 i = INVALID_IDX;
2174 }
2175
2176 unlock_buffer_pool(cm->buffer_pool, flags);
2177 return i;
2178 }
2179
2180 static int v4l_get_free_fb(struct VP9Decoder_s *pbi)
2181 {
2182 struct VP9_Common_s *const cm = &pbi->common;
2183 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2184 struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx;
2185 struct v4l_buff_pool *pool = &v4l->cap_pool;
2186 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2187 int i, idx = INVALID_IDX;
2188 ulong flags;
2189
2190 lock_buffer_pool(cm->buffer_pool, flags);
2191
2192 for (i = 0; i < pool->in; ++i) {
2193 u32 state = (pool->seq[i] >> 16);
2194 u32 index = (pool->seq[i] & 0xffff);
2195
2196 switch (state) {
2197 case V4L_CAP_BUFF_IN_DEC:
2198 pic = &frame_bufs[i].buf;
2199 if ((frame_bufs[i].ref_count == 0) &&
2200 (pic->vf_ref == 0) &&
2201 (pic->index != -1) &&
2202 pic->cma_alloc_addr) {
2203 idx = i;
2204 }
2205 break;
2206 case V4L_CAP_BUFF_IN_M2M:
2207 pic = &frame_bufs[index].buf;
2208 pic->y_crop_width = pbi->frame_width;
2209 pic->y_crop_height = pbi->frame_height;
2210 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2211 set_canvas(pbi, pic);
2212 init_pic_list_hw(pbi);
2213 idx = index;
2214 }
2215 break;
2216 default:
2217 pr_err("v4l buffer state err %d.\n", state);
2218 break;
2219 }
2220
2221 if (idx != INVALID_IDX) {
2222 frame_bufs[idx].ref_count = 1;
2223 break;
2224 }
2225 }
2226
2227 unlock_buffer_pool(cm->buffer_pool, flags);
2228
2229 return idx;
2230 }
2231
2232 static int get_free_buf_count(struct VP9Decoder_s *pbi)
2233 {
2234 struct VP9_Common_s *const cm = &pbi->common;
2235 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2236 int i;
2237 int free_buf_count = 0;
2238 for (i = 0; i < pbi->used_buf_num; ++i)
2239 if ((frame_bufs[i].ref_count == 0) &&
2240 (frame_bufs[i].buf.vf_ref == 0) &&
2241 (frame_bufs[i].buf.index != -1)
2242 )
2243 free_buf_count++;
2244 return free_buf_count;
2245 }
2246
2247 static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2248 struct BufferPool_s *const pool)
2249 {
2250 if (idx >= 0) {
2251 --frame_bufs[idx].ref_count;
2252 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2253 * frame_bufs[idx].ref_count);
2254 */
2255 /*A worker may only get a free framebuffer index when
2256 *calling get_free_fb. But the private buffer is not set up
2257 *until finish decoding header. So any error happens during
2258 *decoding header, the frame_bufs will not have valid priv
2259 *buffer.
2260 */
2261
2262 if (frame_bufs[idx].ref_count == 0 &&
2263 frame_bufs[idx].raw_frame_buffer.priv)
2264 vp9_release_frame_buffer
2265 (&frame_bufs[idx].raw_frame_buffer);
2266 }
2267 }
2268
2269 static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2270 {
2271 struct VP9_Common_s *const cm = &pbi->common;
2272 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2273 struct BufferPool_s *const pool = cm->buffer_pool;
2274 int mask, ref_index = 0;
2275 unsigned long flags;
2276
2277 /* Generate next_ref_frame_map.*/
2278 lock_buffer_pool(pool, flags);
2279 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2280 if (mask & 1) {
2281 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2282 ++frame_bufs[cm->new_fb_idx].ref_count;
2283 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2284 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2285 */
2286 } else
2287 cm->next_ref_frame_map[ref_index] =
2288 cm->ref_frame_map[ref_index];
2289 /* Current thread holds the reference frame.*/
2290 if (cm->ref_frame_map[ref_index] >= 0) {
2291 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2292 /*pr_info
2293 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2294 *cm->ref_frame_map[ref_index],
2295 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2296 */
2297 }
2298 ++ref_index;
2299 }
2300
2301 for (; ref_index < REF_FRAMES; ++ref_index) {
2302 cm->next_ref_frame_map[ref_index] =
2303 cm->ref_frame_map[ref_index];
2304 /* Current thread holds the reference frame.*/
2305 if (cm->ref_frame_map[ref_index] >= 0) {
2306 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2307 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2308 *cm->ref_frame_map[ref_index],
2309 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2310 */
2311 }
2312 }
2313 unlock_buffer_pool(pool, flags);
2314 return;
2315 }
2316
2317 static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2318
2319 {
2320 struct VP9_Common_s *const cm = &pbi->common;
2321 struct BufferPool_s *pool = cm->buffer_pool;
2322 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2323 int mask, ref_index = 0;
2324 unsigned long flags;
2325
2326 lock_buffer_pool(pool, flags);
2327 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2328 const int old_idx = cm->ref_frame_map[ref_index];
2329 /*Current thread releases the holding of reference frame.*/
2330 decrease_ref_count(old_idx, frame_bufs, pool);
2331
2332 /*Release the reference frame in reference map.*/
2333 if ((mask & 1) && old_idx >= 0)
2334 decrease_ref_count(old_idx, frame_bufs, pool);
2335 cm->ref_frame_map[ref_index] =
2336 cm->next_ref_frame_map[ref_index];
2337 ++ref_index;
2338 }
2339
2340 /*Current thread releases the holding of reference frame.*/
2341 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2342 ++ref_index) {
2343 const int old_idx = cm->ref_frame_map[ref_index];
2344
2345 decrease_ref_count(old_idx, frame_bufs, pool);
2346 cm->ref_frame_map[ref_index] =
2347 cm->next_ref_frame_map[ref_index];
2348 }
2349 unlock_buffer_pool(pool, flags);
2350 return;
2351 }
2352
2353 int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2354 {
2355 struct VP9_Common_s *const cm = &pbi->common;
2356 struct BufferPool_s *pool = cm->buffer_pool;
2357 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2358 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2359 int i;
2360 int ret;
2361
2362 pbi->ready_for_new_data = 0;
2363
2364 if (pbi->has_keyframe == 0 &&
2365 params->p.frame_type != KEY_FRAME){
2366 on_no_keyframe_skiped++;
2367 return -2;
2368 }
2369 pbi->has_keyframe = 1;
2370 on_no_keyframe_skiped = 0;
2371 #if 0
2372 if (pbi->mmu_enable) {
2373 if (!pbi->m_ins_flag)
2374 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2375 if (cm->prev_fb_idx >= 0) {
2376 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2377 cm->prev_fb_idx, pbi->used_4k_num);
2378 }
2379 }
2380 #endif
2381 if (cm->new_fb_idx >= 0
2382 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2383 vp9_release_frame_buffer
2384 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2385 }
2386 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2387 cm->prev_fb_idx, cm->new_fb_idx);*/
2388 #ifndef MV_USE_FIXED_BUF
2389 put_un_used_mv_bufs(pbi);
2390 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2391 dump_pic_list(pbi);
2392 #endif
2393 cm->new_fb_idx = pbi->is_used_v4l ?
2394 v4l_get_free_fb(pbi) :
2395 get_free_fb(pbi);
2396 if (cm->new_fb_idx == INVALID_IDX) {
2397 pr_info("get_free_fb error\r\n");
2398 return -1;
2399 }
2400 #ifndef MV_USE_FIXED_BUF
2401 #ifdef SUPPORT_FB_DECODING
2402 if (pbi->used_stage_buf_num == 0) {
2403 #endif
2404 if (get_mv_buf(pbi,
2405 &pool->frame_bufs[cm->new_fb_idx].
2406 buf.mv_buf_index,
2407 &pool->frame_bufs[cm->new_fb_idx].
2408 buf.mpred_mv_wr_start_addr
2409 ) < 0) {
2410 pr_info("get_mv_buf fail\r\n");
2411 return -1;
2412 }
2413 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2414 dump_pic_list(pbi);
2415 #ifdef SUPPORT_FB_DECODING
2416 }
2417 #endif
2418 #endif
2419 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2420 /*if (debug & VP9_DEBUG_BUFMGR)
2421 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2422 cm->new_fb_idx);*/
2423
2424 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2425 if (pbi->mmu_enable) {
2426 /* moved to after picture size ready
2427 *alloc_mmu(cm, params->p.width, params->p.height,
2428 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2429 */
2430 cm->prev_fb_idx = cm->new_fb_idx;
2431 }
2432 /*read_uncompressed_header()*/
2433 cm->last_frame_type = cm->frame_type;
2434 cm->last_intra_only = cm->intra_only;
2435 cm->profile = params->p.profile;
2436 if (cm->profile >= MAX_PROFILES) {
2437 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2438 return -1;
2439 }
2440 cm->show_existing_frame = params->p.show_existing_frame;
2441 if (cm->show_existing_frame) {
2442 /* Show an existing frame directly.*/
2443 int frame_to_show_idx = params->p.frame_to_show_idx;
2444 int frame_to_show;
2445 unsigned long flags;
2446 if (frame_to_show_idx >= REF_FRAMES) {
2447 pr_info("frame_to_show_idx %d exceed max index\r\n",
2448 frame_to_show_idx);
2449 return -1;
2450 }
2451
2452 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2453 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2454 lock_buffer_pool(pool, flags);
2455 if (frame_to_show < 0 ||
2456 frame_bufs[frame_to_show].ref_count < 1) {
2457 unlock_buffer_pool(pool, flags);
2458 pr_err
2459 ("Error:Buffer %d does not contain a decoded frame",
2460 frame_to_show);
2461 return -1;
2462 }
2463
2464 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2465 unlock_buffer_pool(pool, flags);
2466 pbi->refresh_frame_flags = 0;
2467 /*cm->lf.filter_level = 0;*/
2468 cm->show_frame = 1;
2469
2470 /*
2471 *if (pbi->frame_parallel_decode) {
2472 * for (i = 0; i < REF_FRAMES; ++i)
2473 * cm->next_ref_frame_map[i] =
2474 * cm->ref_frame_map[i];
2475 *}
2476 */
2477 /* do not decode, search next start code */
2478 return 1;
2479 }
2480 cm->frame_type = params->p.frame_type;
2481 cm->show_frame = params->p.show_frame;
2482 cm->error_resilient_mode = params->p.error_resilient_mode;
2483
2484
2485 if (cm->frame_type == KEY_FRAME) {
2486 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2487
2488 for (i = 0; i < REFS_PER_FRAME; ++i) {
2489 cm->frame_refs[i].idx = INVALID_IDX;
2490 cm->frame_refs[i].buf = NULL;
2491 }
2492
2493 ret = setup_frame_size(pbi,
2494 cm, params, pbi->frame_mmu_map_addr,
2495 print_header_info);
2496 if (ret)
2497 return -1;
2498 if (pbi->need_resync) {
2499 memset(&cm->ref_frame_map, -1,
2500 sizeof(cm->ref_frame_map));
2501 pbi->need_resync = 0;
2502 }
2503 } else {
2504 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2505 /*if (print_header_info) {
2506 * if (cm->show_frame)
2507 * pr_info
2508 * ("intra_only set to 0 because of show_frame\n");
2509 * else
2510 * pr_info
2511 * ("1-bit intra_only read: %d\n", cm->intra_only);
2512 *}
2513 */
2514
2515
2516 cm->reset_frame_context = cm->error_resilient_mode ?
2517 0 : params->p.reset_frame_context;
2518 if (print_header_info) {
2519 if (cm->error_resilient_mode)
2520 pr_info
2521 ("reset to 0 error_resilient_mode\n");
2522 else
2523 pr_info
2524 (" * 2-bits reset_frame_context read : %d\n",
2525 cm->reset_frame_context);
2526 }
2527
2528 if (cm->intra_only) {
2529 if (cm->profile > PROFILE_0) {
2530 /*read_bitdepth_colorspace_sampling(cm,
2531 * rb, print_header_info);
2532 */
2533 } else {
2534 /*NOTE: The intra-only frame header
2535 *does not include the specification
2536 *of either the color format or
2537 *color sub-sampling
2538 *in profile 0. VP9 specifies that the default
2539 *color format should be YUV 4:2:0 in this
2540 *case (normative).
2541 */
2542 cm->color_space = VPX_CS_BT_601;
2543 cm->subsampling_y = cm->subsampling_x = 1;
2544 cm->bit_depth = VPX_BITS_8;
2545 cm->use_highbitdepth = 0;
2546 }
2547
2548 pbi->refresh_frame_flags =
2549 params->p.refresh_frame_flags;
2550 /*if (print_header_info)
2551 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2552 * REF_FRAMES, pbi->refresh_frame_flags);
2553 */
2554 ret = setup_frame_size(pbi,
2555 cm,
2556 params,
2557 pbi->frame_mmu_map_addr,
2558 print_header_info);
2559 if (ret)
2560 return -1;
2561 if (pbi->need_resync) {
2562 memset(&cm->ref_frame_map, -1,
2563 sizeof(cm->ref_frame_map));
2564 pbi->need_resync = 0;
2565 }
2566 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2567 pbi->refresh_frame_flags =
2568 params->p.refresh_frame_flags;
2569 if (print_header_info)
2570 pr_info
2571 ("*%d-bits refresh_frame read:0x%x\n",
2572 REF_FRAMES, pbi->refresh_frame_flags);
2573 for (i = 0; i < REFS_PER_FRAME; ++i) {
2574 const int ref =
2575 (params->p.ref_info >>
2576 (((REFS_PER_FRAME-i-1)*4)+1))
2577 & 0x7;
2578 const int idx =
2579 cm->ref_frame_map[ref];
2580 struct RefBuffer_s * const ref_frame =
2581 &cm->frame_refs[i];
2582 if (print_header_info)
2583 pr_info("*%d-bits ref[%d]read:%d\n",
2584 REF_FRAMES_LOG2, i, ref);
2585 ref_frame->idx = idx;
2586 ref_frame->buf = &frame_bufs[idx].buf;
2587 cm->ref_frame_sign_bias[LAST_FRAME + i]
2588 = (params->p.ref_info >>
2589 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2590 if (print_header_info)
2591 pr_info("1bit ref_frame_sign_bias");
2592 /*pr_info
2593 *("%dread: %d\n",
2594 *LAST_FRAME+i,
2595 *cm->ref_frame_sign_bias
2596 *[LAST_FRAME + i]);
2597 */
2598 /*pr_info
2599 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2600 *__func__, ref_frame->idx);
2601 */
2602
2603 }
2604
2605 ret = setup_frame_size_with_refs(
2606 pbi,
2607 cm,
2608 params,
2609 pbi->frame_mmu_map_addr,
2610 print_header_info);
2611 if (ret)
2612 return -1;
2613 for (i = 0; i < REFS_PER_FRAME; ++i) {
2614 /*struct RefBuffer_s *const ref_buf =
2615 *&cm->frame_refs[i];
2616 */
2617 /* to do:
2618 *vp9_setup_scale_factors_for_frame
2619 */
2620 }
2621 }
2622 }
2623
2624 pic = get_frame_new_buffer(cm);
2625 if (!pic)
2626 return -1;
2627
2628 pic->bit_depth = cm->bit_depth;
2629 pic->color_space = cm->color_space;
2630 pic->slice_type = cm->frame_type;
2631
2632 if (pbi->need_resync) {
2633 pr_err
2634 ("Error: Keyframe/intra-only frame required to reset\r\n");
2635 return -1;
2636 }
2637 generate_next_ref_frames(pbi);
2638 pbi->hold_ref_buf = 1;
2639
2640 #if 0
2641 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2642 vp9_setup_past_independence(cm);
2643 setup_loopfilter(&cm->lf, rb, print_header_info);
2644 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2645 setup_segmentation(&cm->seg, rb, print_header_info);
2646 setup_segmentation_dequant(cm, print_header_info);
2647
2648 setup_tile_info(cm, rb, print_header_info);
2649 sz = vp9_rb_read_literal(rb, 16);
2650 if (print_header_info)
2651 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2652
2653 if (sz == 0)
2654 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2655 "Invalid header size");
2656 #endif
2657 /*end read_uncompressed_header()*/
2658 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2659 cm->width == cm->last_width &&
2660 cm->height == cm->last_height &&
2661 !cm->last_intra_only &&
2662 cm->last_show_frame &&
2663 (cm->last_frame_type != KEY_FRAME);
2664
2665 /*pr_info
2666 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2667 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2668 *pr_info
2669 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2670 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2671 */
2672 return 0;
2673 }
2674
2675
2676 void swap_frame_buffers(struct VP9Decoder_s *pbi)
2677 {
2678 int ref_index = 0;
2679 struct VP9_Common_s *const cm = &pbi->common;
2680 struct BufferPool_s *const pool = cm->buffer_pool;
2681 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2682 unsigned long flags;
2683 refresh_ref_frames(pbi);
2684 pbi->hold_ref_buf = 0;
2685 cm->frame_to_show = get_frame_new_buffer(cm);
2686
2687 if (cm->frame_to_show) {
2688 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2689 lock_buffer_pool(pool, flags);
2690 --frame_bufs[cm->new_fb_idx].ref_count;
2691 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2692 * frame_bufs[cm->new_fb_idx].ref_count);
2693 */
2694 unlock_buffer_pool(pool, flags);
2695 /*}*/
2696 }
2697
2698 /*Invalidate these references until the next frame starts.*/
2699 for (ref_index = 0; ref_index < 3; ref_index++)
2700 cm->frame_refs[ref_index].idx = -1;
2701 }
2702
2703 #if 0
2704 static void check_resync(vpx_codec_alg_priv_t *const ctx,
2705 const struct VP9Decoder_s *const pbi)
2706 {
2707 /* Clear resync flag if worker got a key frame or intra only frame.*/
2708 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2709 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2710 ctx->need_resync = 0;
2711 }
2712 #endif
2713
2714 int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2715 {
2716 struct VP9_Common_s *const cm = &pbi->common;
2717 int ret = -1;
2718
2719 if (pbi->ready_for_new_data == 1)
2720 return ret;
2721
2722 pbi->ready_for_new_data = 1;
2723
2724 /* no raw frame to show!!! */
2725 if (!cm->show_frame)
2726 return ret;
2727
2728 /* may not be get buff in v4l2 */
2729 if (!cm->frame_to_show)
2730 return ret;
2731
2732 pbi->ready_for_new_data = 1;
2733
2734 *sd = *cm->frame_to_show;
2735 ret = 0;
2736
2737 return ret;
2738 }
2739
2740 int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2741 struct buff_s *mc_buf_i) {
2742 struct VP9_Common_s *cm = &pbi->common;
2743
2744 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2745 pbi->frame_count = 0;
2746 pbi->pic_count = 0;
2747 pbi->pre_stream_offset = 0;
2748 cm->buffer_pool = &pbi->vp9_buffer_pool;
2749 spin_lock_init(&cm->buffer_pool->lock);
2750 cm->prev_fb_idx = INVALID_IDX;
2751 cm->new_fb_idx = INVALID_IDX;
2752 pbi->used_4k_num = -1;
2753 cm->cur_fb_idx_mmu = INVALID_IDX;
2754 pr_debug
2755 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2756 cm->prev_fb_idx, cm->new_fb_idx);
2757 pbi->need_resync = 1;
2758 /* Initialize the references to not point to any frame buffers.*/
2759 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2760 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2761 cm->current_video_frame = 0;
2762 pbi->ready_for_new_data = 1;
2763
2764 /* private init */
2765 pbi->work_space_buf = buf_spec_i;
2766 if (!pbi->mmu_enable)
2767 pbi->mc_buf = mc_buf_i;
2768
2769 pbi->rpm_addr = NULL;
2770 pbi->lmem_addr = NULL;
2771
2772 pbi->use_cma_flag = 0;
2773 pbi->decode_idx = 0;
2774 pbi->slice_idx = 0;
2775 /*int m_uiMaxCUWidth = 1<<7;*/
2776 /*int m_uiMaxCUHeight = 1<<7;*/
2777 pbi->has_keyframe = 0;
2778 pbi->skip_flag = 0;
2779 pbi->wait_buf = 0;
2780 pbi->error_flag = 0;
2781
2782 pbi->pts_mode = PTS_NORMAL;
2783 pbi->last_pts = 0;
2784 pbi->last_lookup_pts = 0;
2785 pbi->last_pts_us64 = 0;
2786 pbi->last_lookup_pts_us64 = 0;
2787 pbi->shift_byte_count = 0;
2788 pbi->shift_byte_count_lo = 0;
2789 pbi->shift_byte_count_hi = 0;
2790 pbi->pts_mode_switching_count = 0;
2791 pbi->pts_mode_recovery_count = 0;
2792
2793 pbi->buf_num = 0;
2794 pbi->pic_num = 0;
2795
2796 return 0;
2797 }
2798
2799 int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2800 {
2801 struct VP9_Common_s *cm = &pbi->common;
2802 struct PIC_BUFFER_CONFIG_s sd;
2803
2804 if (pbi->postproc_done)
2805 return 0;
2806 pbi->postproc_done = 1;
2807 swap_frame_buffers(pbi);
2808 if (!cm->show_existing_frame) {
2809 cm->last_show_frame = cm->show_frame;
2810 cm->prev_frame = cm->cur_frame;
2811 #if 0
2812 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2813 vp9_swap_current_and_last_seg_map(cm);
2814 #endif
2815 }
2816 cm->last_width = cm->width;
2817 cm->last_height = cm->height;
2818 if (cm->show_frame)
2819 cm->current_video_frame++;
2820
2821 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2822 /*pr_info("Display frame index %d\r\n", sd.index);*/
2823 sd.stream_offset = pbi->pre_stream_offset;
2824 prepare_display_buf(pbi, &sd);
2825 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2826 }
2827
2828 /* else
2829 * pr_info
2830 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2831 * pbi->ready_for_new_data, cm->show_frame);
2832 */
2833 return 0;
2834 }
2835
2836 /*struct VP9Decoder_s vp9_decoder;*/
2837 union param_u vp9_param;
2838
2839 /**************************************************
2840 *
2841 *VP9 buffer management end
2842 *
2843 ***************************************************
2844 */
2845
2846
2847 #define HEVC_CM_BODY_START_ADDR 0x3626
2848 #define HEVC_CM_BODY_LENGTH 0x3627
2849 #define HEVC_CM_HEADER_LENGTH 0x3629
2850 #define HEVC_CM_HEADER_OFFSET 0x362b
2851
2852 #define LOSLESS_COMPRESS_MODE
2853
2854 /*#define DECOMP_HEADR_SURGENT*/
2855 #ifdef VP9_10B_NV21
2856 static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2857 #else
2858 static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2859 #endif
2860 static u32 enable_mem_saving = 1;
2861 static u32 force_w_h;
2862
2863 static u32 force_fps;
2864
2865
2866 const u32 vp9_version = 201602101;
2867 static u32 debug;
2868 static u32 radr;
2869 static u32 rval;
2870 static u32 pop_shorts;
2871 static u32 dbg_cmd;
2872 static u32 dbg_skip_decode_index;
2873 static u32 endian = 0xff0;
2874 #ifdef ERROR_HANDLE_DEBUG
2875 static u32 dbg_nal_skip_flag;
2876 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2877 static u32 dbg_nal_skip_count;
2878 #endif
2879 /*for debug*/
2880 static u32 decode_pic_begin;
2881 static uint slice_parse_begin;
2882 static u32 step;
2883 #ifdef MIX_STREAM_SUPPORT
2884 static u32 buf_alloc_width = 4096;
2885 static u32 buf_alloc_height = 2304;
2886 static u32 vp9_max_pic_w = 4096;
2887 static u32 vp9_max_pic_h = 2304;
2888
2889 static u32 dynamic_buf_num_margin;
2890 #else
2891 static u32 buf_alloc_width;
2892 static u32 buf_alloc_height;
2893 static u32 dynamic_buf_num_margin = 7;
2894 #endif
2895 static u32 buf_alloc_depth = 10;
2896 static u32 buf_alloc_size;
2897 /*
2898 *bit[0]: 0,
2899 * bit[1]: 0, always release cma buffer when stop
2900 * bit[1]: 1, never release cma buffer when stop
2901 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2902 *do not release cma buffer is blackout is not 1
2903 *
2904 *bit[2]: 0, when start decoding, check current displayed buffer
2905 * (only for buffer decoded by vp9) if blackout is 0
2906 * 1, do not check current displayed buffer
2907 *
2908 *bit[3]: 1, if blackout is not 1, do not release current
2909 * displayed cma buffer always.
2910 */
2911 /* set to 1 for fast play;
2912 * set to 8 for other case of "keep last frame"
2913 */
2914 static u32 buffer_mode = 1;
2915 /* buffer_mode_dbg: debug only*/
2916 static u32 buffer_mode_dbg = 0xffff0000;
2917 /**/
2918
2919 /*
2920 *bit 0, 1: only display I picture;
2921 *bit 1, 1: only decode I picture;
2922 */
2923 static u32 i_only_flag;
2924
2925 static u32 low_latency_flag;
2926
2927 static u32 no_head;
2928
2929 static u32 max_decoding_time;
2930 /*
2931 *error handling
2932 */
2933 /*error_handle_policy:
2934 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2935 *1, skip error_skip_nal_count nals before error recovery;
2936 *bit 1 (valid only when bit0 == 1):
2937 *1, wait vps/sps/pps after error recovery;
2938 *bit 2 (valid only when bit0 == 0):
2939 *0, auto search after error recovery (vp9_recover() called);
2940 *1, manual search after error recovery
2941 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2942 *
2943 *bit 4: 0, set error_mark after reset/recover
2944 * 1, do not set error_mark after reset/recover
2945 *bit 5: 0, check total lcu for every picture
2946 * 1, do not check total lcu
2947 *
2948 */
2949
2950 static u32 error_handle_policy;
2951 /*static u32 parser_sei_enable = 1;*/
2952 #define MAX_BUF_NUM_NORMAL 12
2953 #define MAX_BUF_NUM_LESS 10
2954 static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2955 #define MAX_BUF_NUM_SAVE_BUF 8
2956
2957 static u32 run_ready_min_buf_num = 2;
2958
2959
2960 static DEFINE_MUTEX(vvp9_mutex);
2961 #ifndef MULTI_INSTANCE_SUPPORT
2962 static struct device *cma_dev;
2963 #endif
2964
2965 #define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2966 #define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2967 #define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2968 #define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2969 #define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2970 #define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2971 #define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2972 #define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2973 #define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2974 #define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2975 #define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2976 #define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2977 #define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2978 #define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2979 #define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2980 #define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2981 #define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2982 #ifdef MULTI_INSTANCE_SUPPORT
2983 #define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2984 #define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2985 #else
2986 #define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2987 #define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2988 #endif
2989 #define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2990 #define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2991
2992
2993 /*
2994 *ucode parser/search control
2995 *bit 0: 0, header auto parse; 1, header manual parse
2996 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2997 *bit [3:2]: valid when bit1==0;
2998 *0, auto skip nal before first vps/sps/pps/idr;
2999 *1, auto skip nal before first vps/sps/pps
3000 *2, auto skip nal before first vps/sps/pps,
3001 * and not decode until the first I slice (with slice address of 0)
3002 *
3003 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
3004 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
3005 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
3006 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
3007 *bit [17]: for NAL_SEI when bit0 is 0:
3008 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
3009 *bit [31:20]: used by ucode for debug purpose
3010 */
3011 #define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
3012 /*[31:24] chip feature
3013 31: 0, use MBOX1; 1, use MBOX0
3014 */
3015 #define DECODE_MODE HEVC_ASSIST_SCRATCH_J
3016 #define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
3017
3018 #ifdef MULTI_INSTANCE_SUPPORT
3019 #define RPM_BUF_SIZE (0x400 * 2)
3020 #else
3021 #define RPM_BUF_SIZE (0x80*2)
3022 #endif
3023 #define LMEM_BUF_SIZE (0x400 * 2)
3024
3025 #define WORK_BUF_SPEC_NUM 3
3026 static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
3027 {
3028 /* 8M bytes */
3029 .max_width = 1920,
3030 .max_height = 1088,
3031 .ipp = {
3032 /* IPP work space calculation :
3033 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3034 */
3035 .buf_size = 0x4000,
3036 },
3037 .sao_abv = {
3038 .buf_size = 0x30000,
3039 },
3040 .sao_vb = {
3041 .buf_size = 0x30000,
3042 },
3043 .short_term_rps = {
3044 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3045 * total 64x16x2 = 2048 bytes (0x800)
3046 */
3047 .buf_size = 0x800,
3048 },
3049 .vps = {
3050 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3051 * total 0x0800 bytes
3052 */
3053 .buf_size = 0x800,
3054 },
3055 .sps = {
3056 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3057 * total 0x0800 bytes
3058 */
3059 .buf_size = 0x800,
3060 },
3061 .pps = {
3062 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3063 * total 0x2000 bytes
3064 */
3065 .buf_size = 0x2000,
3066 },
3067 .sao_up = {
3068 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3069 * each has 16 bytes total 0x2800 bytes
3070 */
3071 .buf_size = 0x2800,
3072 },
3073 .swap_buf = {
3074 /* 256cyclex64bit = 2K bytes 0x800
3075 * (only 144 cycles valid)
3076 */
3077 .buf_size = 0x800,
3078 },
3079 .swap_buf2 = {
3080 .buf_size = 0x800,
3081 },
3082 .scalelut = {
3083 /* support up to 32 SCALELUT 1024x32 =
3084 * 32Kbytes (0x8000)
3085 */
3086 .buf_size = 0x8000,
3087 },
3088 .dblk_para = {
3089 /* DBLK -> Max 256(4096/16) LCU,
3090 *each para 1024bytes(total:0x40000),
3091 *data 1024bytes(total:0x40000)
3092 */
3093 .buf_size = 0x80000,
3094 },
3095 .dblk_data = {
3096 .buf_size = 0x80000,
3097 },
3098 .seg_map = {
3099 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3100 .buf_size = 0xd800,
3101 },
3102 .mmu_vbh = {
3103 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3104 },
3105 #if 0
3106 .cm_header = {
3107 /*add one for keeper.*/
3108 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3109 (FRAME_BUFFERS + 1),
3110 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3111 },
3112 #endif
3113 .mpred_above = {
3114 .buf_size = 0x10000, /* 2 * size of hevc*/
3115 },
3116 #ifdef MV_USE_FIXED_BUF
3117 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3118 .buf_size = 0x40000 * FRAME_BUFFERS,
3119 },
3120 #endif
3121 .rpm = {
3122 .buf_size = RPM_BUF_SIZE,
3123 },
3124 .lmem = {
3125 .buf_size = 0x400 * 2,
3126 }
3127 },
3128 {
3129 .max_width = 4096,
3130 .max_height = 2304,
3131 .ipp = {
3132 /* IPP work space calculation :
3133 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3134 */
3135 .buf_size = 0x4000,
3136 },
3137 .sao_abv = {
3138 .buf_size = 0x30000,
3139 },
3140 .sao_vb = {
3141 .buf_size = 0x30000,
3142 },
3143 .short_term_rps = {
3144 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3145 * total 64x16x2 = 2048 bytes (0x800)
3146 */
3147 .buf_size = 0x800,
3148 },
3149 .vps = {
3150 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3151 * total 0x0800 bytes
3152 */
3153 .buf_size = 0x800,
3154 },
3155 .sps = {
3156 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3157 * total 0x0800 bytes
3158 */
3159 .buf_size = 0x800,
3160 },
3161 .pps = {
3162 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3163 * total 0x2000 bytes
3164 */
3165 .buf_size = 0x2000,
3166 },
3167 .sao_up = {
3168 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3169 * each has 16 bytes total 0x2800 bytes
3170 */
3171 .buf_size = 0x2800,
3172 },
3173 .swap_buf = {
3174 /* 256cyclex64bit = 2K bytes 0x800
3175 * (only 144 cycles valid)
3176 */
3177 .buf_size = 0x800,
3178 },
3179 .swap_buf2 = {
3180 .buf_size = 0x800,
3181 },
3182 .scalelut = {
3183 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3184 * (0x8000)
3185 */
3186 .buf_size = 0x8000,
3187 },
3188 .dblk_para = {
3189 /* DBLK -> Max 256(4096/16) LCU,
3190 *each para 1024bytes(total:0x40000),
3191 *data 1024bytes(total:0x40000)
3192 */
3193 .buf_size = 0x80000,
3194 },
3195 .dblk_data = {
3196 .buf_size = 0x80000,
3197 },
3198 .seg_map = {
3199 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3200 .buf_size = 0xd800,
3201 },
3202 .mmu_vbh = {
3203 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3204 },
3205 #if 0
3206 .cm_header = {
3207 /*add one for keeper.*/
3208 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3209 (FRAME_BUFFERS + 1),
3210 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3211 },
3212 #endif
3213 .mpred_above = {
3214 .buf_size = 0x10000, /* 2 * size of hevc*/
3215 },
3216 #ifdef MV_USE_FIXED_BUF
3217 .mpred_mv = {
3218 /* .buf_size = 0x100000*16,
3219 * //4k2k , 0x100000 per buffer
3220 */
3221 /* 4096x2304 , 0x120000 per buffer */
3222 .buf_size = 0x120000 * FRAME_BUFFERS,
3223 },
3224 #endif
3225 .rpm = {
3226 .buf_size = RPM_BUF_SIZE,
3227 },
3228 .lmem = {
3229 .buf_size = 0x400 * 2,
3230 }
3231 },
3232 {
3233 .max_width = 4096*2,
3234 .max_height = 2304*2,
3235 .ipp = {
3236 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3237 .buf_size = 0x4000*2,
3238 },
3239 .sao_abv = {
3240 .buf_size = 0x30000*2,
3241 },
3242 .sao_vb = {
3243 .buf_size = 0x30000*2,
3244 },
3245 .short_term_rps = {
3246 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3247 .buf_size = 0x800,
3248 },
3249 .vps = {
3250 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3251 .buf_size = 0x800,
3252 },
3253 .sps = {
3254 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3255 .buf_size = 0x800,
3256 },
3257 .pps = {
3258 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3259 .buf_size = 0x2000,
3260 },
3261 .sao_up = {
3262 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3263 .buf_size = 0x2800*2,
3264 },
3265 .swap_buf = {
3266 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3267 .buf_size = 0x800,
3268 },
3269 .swap_buf2 = {
3270 .buf_size = 0x800,
3271 },
3272 .scalelut = {
3273 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3274 .buf_size = 0x8000*2,
3275 },
3276 .dblk_para = {
3277 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3278 .buf_size = 0x80000*2,
3279 },
3280 .dblk_data = {
3281 .buf_size = 0x80000*2,
3282 },
3283 .seg_map = {
3284 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3285 .buf_size = 0xd800*4,
3286 },
3287 .mmu_vbh = {
3288 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3289 },
3290 #if 0
3291 .cm_header = {
3292 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3293 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3294 },
3295 #endif
3296 .mpred_above = {
3297 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3298 },
3299 #ifdef MV_USE_FIXED_BUF
3300 .mpred_mv = {
3301 //4k2k , 0x100000 per buffer */
3302 /* 4096x2304 , 0x120000 per buffer */
3303 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3304 },
3305 #endif
3306 .rpm = {
3307 .buf_size = RPM_BUF_SIZE,
3308 },
3309 .lmem = {
3310 .buf_size = 0x400 * 2,
3311 }
3312 }
3313 };
3314
3315
3316 /*Losless compression body buffer size 4K per 64x32 (jt)*/
3317 int compute_losless_comp_body_size(int width, int height,
3318 uint8_t is_bit_depth_10)
3319 {
3320 int width_x64;
3321 int height_x32;
3322 int bsize;
3323
3324 width_x64 = width + 63;
3325 width_x64 >>= 6;
3326 height_x32 = height + 31;
3327 height_x32 >>= 5;
3328 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3329 if (debug & VP9_DEBUG_BUFMGR_MORE)
3330 pr_info("%s(%d,%d,%d)=>%d\n",
3331 __func__, width, height,
3332 is_bit_depth_10, bsize);
3333
3334 return bsize;
3335 }
3336
3337 /* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3338 static int compute_losless_comp_header_size(int width, int height)
3339 {
3340 int width_x128;
3341 int height_x64;
3342 int hsize;
3343
3344 width_x128 = width + 127;
3345 width_x128 >>= 7;
3346 height_x64 = height + 63;
3347 height_x64 >>= 6;
3348
3349 hsize = 32 * width_x128 * height_x64;
3350 if (debug & VP9_DEBUG_BUFMGR_MORE)
3351 pr_info("%s(%d,%d)=>%d\n",
3352 __func__, width, height,
3353 hsize);
3354
3355 return hsize;
3356 }
3357
3358 static void init_buff_spec(struct VP9Decoder_s *pbi,
3359 struct BuffInfo_s *buf_spec)
3360 {
3361 void *mem_start_virt;
3362
3363 buf_spec->ipp.buf_start = buf_spec->start_adr;
3364 buf_spec->sao_abv.buf_start =
3365 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3366
3367 buf_spec->sao_vb.buf_start =
3368 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3369 buf_spec->short_term_rps.buf_start =
3370 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3371 buf_spec->vps.buf_start =
3372 buf_spec->short_term_rps.buf_start +
3373 buf_spec->short_term_rps.buf_size;
3374 buf_spec->sps.buf_start =
3375 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3376 buf_spec->pps.buf_start =
3377 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3378 buf_spec->sao_up.buf_start =
3379 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3380 buf_spec->swap_buf.buf_start =
3381 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3382 buf_spec->swap_buf2.buf_start =
3383 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3384 buf_spec->scalelut.buf_start =
3385 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3386 buf_spec->dblk_para.buf_start =
3387 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3388 buf_spec->dblk_data.buf_start =
3389 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3390 buf_spec->seg_map.buf_start =
3391 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3392 if (pbi == NULL || pbi->mmu_enable) {
3393 buf_spec->mmu_vbh.buf_start =
3394 buf_spec->seg_map.buf_start +
3395 buf_spec->seg_map.buf_size;
3396 buf_spec->mpred_above.buf_start =
3397 buf_spec->mmu_vbh.buf_start +
3398 buf_spec->mmu_vbh.buf_size;
3399 } else {
3400 buf_spec->mpred_above.buf_start =
3401 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3402 }
3403 #ifdef MV_USE_FIXED_BUF
3404 buf_spec->mpred_mv.buf_start =
3405 buf_spec->mpred_above.buf_start +
3406 buf_spec->mpred_above.buf_size;
3407
3408 buf_spec->rpm.buf_start =
3409 buf_spec->mpred_mv.buf_start +
3410 buf_spec->mpred_mv.buf_size;
3411 #else
3412 buf_spec->rpm.buf_start =
3413 buf_spec->mpred_above.buf_start +
3414 buf_spec->mpred_above.buf_size;
3415
3416 #endif
3417 buf_spec->lmem.buf_start =
3418 buf_spec->rpm.buf_start +
3419 buf_spec->rpm.buf_size;
3420 buf_spec->end_adr =
3421 buf_spec->lmem.buf_start +
3422 buf_spec->lmem.buf_size;
3423
3424 if (!pbi)
3425 return;
3426
3427 if (!vdec_secure(hw_to_vdec(pbi))) {
3428 mem_start_virt =
3429 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3430 if (mem_start_virt) {
3431 memset(mem_start_virt, 0,
3432 buf_spec->dblk_para.buf_size);
3433 codec_mm_dma_flush(mem_start_virt,
3434 buf_spec->dblk_para.buf_size,
3435 DMA_TO_DEVICE);
3436 } else {
3437 mem_start_virt = codec_mm_vmap(
3438 buf_spec->dblk_para.buf_start,
3439 buf_spec->dblk_para.buf_size);
3440 if (mem_start_virt) {
3441 memset(mem_start_virt, 0,
3442 buf_spec->dblk_para.buf_size);
3443 codec_mm_dma_flush(mem_start_virt,
3444 buf_spec->dblk_para.buf_size,
3445 DMA_TO_DEVICE);
3446 codec_mm_unmap_phyaddr(mem_start_virt);
3447 } else {
3448 /*not virt for tvp playing,
3449 may need clear on ucode.*/
3450 pr_err("mem_start_virt failed\n");
3451 }
3452 }
3453 }
3454
3455 if (debug) {
3456 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3457 buf_spec->start_adr, buf_spec->end_adr,
3458 buf_spec->end_adr - buf_spec->start_adr);
3459 }
3460
3461 if (debug) {
3462 pr_info("ipp.buf_start :%x\n",
3463 buf_spec->ipp.buf_start);
3464 pr_info("sao_abv.buf_start :%x\n",
3465 buf_spec->sao_abv.buf_start);
3466 pr_info("sao_vb.buf_start :%x\n",
3467 buf_spec->sao_vb.buf_start);
3468 pr_info("short_term_rps.buf_start :%x\n",
3469 buf_spec->short_term_rps.buf_start);
3470 pr_info("vps.buf_start :%x\n",
3471 buf_spec->vps.buf_start);
3472 pr_info("sps.buf_start :%x\n",
3473 buf_spec->sps.buf_start);
3474 pr_info("pps.buf_start :%x\n",
3475 buf_spec->pps.buf_start);
3476 pr_info("sao_up.buf_start :%x\n",
3477 buf_spec->sao_up.buf_start);
3478 pr_info("swap_buf.buf_start :%x\n",
3479 buf_spec->swap_buf.buf_start);
3480 pr_info("swap_buf2.buf_start :%x\n",
3481 buf_spec->swap_buf2.buf_start);
3482 pr_info("scalelut.buf_start :%x\n",
3483 buf_spec->scalelut.buf_start);
3484 pr_info("dblk_para.buf_start :%x\n",
3485 buf_spec->dblk_para.buf_start);
3486 pr_info("dblk_data.buf_start :%x\n",
3487 buf_spec->dblk_data.buf_start);
3488 pr_info("seg_map.buf_start :%x\n",
3489 buf_spec->seg_map.buf_start);
3490 if (pbi->mmu_enable) {
3491 pr_info("mmu_vbh.buf_start :%x\n",
3492 buf_spec->mmu_vbh.buf_start);
3493 }
3494 pr_info("mpred_above.buf_start :%x\n",
3495 buf_spec->mpred_above.buf_start);
3496 #ifdef MV_USE_FIXED_BUF
3497 pr_info("mpred_mv.buf_start :%x\n",
3498 buf_spec->mpred_mv.buf_start);
3499 #endif
3500 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3501 pr_info("rpm.buf_start :%x\n",
3502 buf_spec->rpm.buf_start);
3503 }
3504 }
3505 }
3506
3507 /* cache_util.c */
3508 #define THODIYIL_MCRCC_CANVAS_ALGX 4
3509
3510 static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3511
3512 static void mcrcc_perfcount_reset(void)
3513 {
3514 if (debug & VP9_DEBUG_CACHE)
3515 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3516 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3517 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3518 return;
3519 }
3520
3521 static unsigned raw_mcr_cnt_total_prev;
3522 static unsigned hit_mcr_0_cnt_total_prev;
3523 static unsigned hit_mcr_1_cnt_total_prev;
3524 static unsigned byp_mcr_cnt_nchcanv_total_prev;
3525 static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3526
3527 static void mcrcc_get_hitrate(unsigned reset_pre)
3528 {
3529 unsigned delta_hit_mcr_0_cnt;
3530 unsigned delta_hit_mcr_1_cnt;
3531 unsigned delta_raw_mcr_cnt;
3532 unsigned delta_mcr_cnt_nchcanv;
3533 unsigned delta_mcr_cnt_nchoutwin;
3534
3535 unsigned tmp;
3536 unsigned raw_mcr_cnt;
3537 unsigned hit_mcr_cnt;
3538 unsigned byp_mcr_cnt_nchoutwin;
3539 unsigned byp_mcr_cnt_nchcanv;
3540 int hitrate;
3541 if (reset_pre) {
3542 raw_mcr_cnt_total_prev = 0;
3543 hit_mcr_0_cnt_total_prev = 0;
3544 hit_mcr_1_cnt_total_prev = 0;
3545 byp_mcr_cnt_nchcanv_total_prev = 0;
3546 byp_mcr_cnt_nchoutwin_total_prev = 0;
3547 }
3548 if (debug & VP9_DEBUG_CACHE)
3549 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3550 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3551 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3552 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3553 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3554 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3555 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3556 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3557 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3558
3559 if (debug & VP9_DEBUG_CACHE)
3560 pr_info("raw_mcr_cnt_total: %d\n",
3561 raw_mcr_cnt);
3562 if (debug & VP9_DEBUG_CACHE)
3563 pr_info("hit_mcr_cnt_total: %d\n",
3564 hit_mcr_cnt);
3565 if (debug & VP9_DEBUG_CACHE)
3566 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3567 byp_mcr_cnt_nchoutwin);
3568 if (debug & VP9_DEBUG_CACHE)
3569 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3570 byp_mcr_cnt_nchcanv);
3571
3572 delta_raw_mcr_cnt = raw_mcr_cnt -
3573 raw_mcr_cnt_total_prev;
3574 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3575 byp_mcr_cnt_nchcanv_total_prev;
3576 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3577 byp_mcr_cnt_nchoutwin_total_prev;
3578 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3579 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3580 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3581
3582 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3583 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3584 if (debug & VP9_DEBUG_CACHE)
3585 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3586 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3587 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3588 if (debug & VP9_DEBUG_CACHE)
3589 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3590 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3591 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3592 if (debug & VP9_DEBUG_CACHE)
3593 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3594 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3595 hit_mcr_0_cnt_total_prev = tmp;
3596 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3597 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3598 if (debug & VP9_DEBUG_CACHE)
3599 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3600 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3601 hit_mcr_1_cnt_total_prev = tmp;
3602
3603 if (delta_raw_mcr_cnt != 0) {
3604 hitrate = 100 * delta_hit_mcr_0_cnt
3605 / delta_raw_mcr_cnt;
3606 if (debug & VP9_DEBUG_CACHE)
3607 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3608 hitrate = 100 * delta_hit_mcr_1_cnt
3609 / delta_raw_mcr_cnt;
3610 if (debug & VP9_DEBUG_CACHE)
3611 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3612 hitrate = 100 * delta_mcr_cnt_nchcanv
3613 / delta_raw_mcr_cnt;
3614 if (debug & VP9_DEBUG_CACHE)
3615 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3616 hitrate = 100 * delta_mcr_cnt_nchoutwin
3617 / delta_raw_mcr_cnt;
3618 if (debug & VP9_DEBUG_CACHE)
3619 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3620 }
3621
3622
3623 if (raw_mcr_cnt != 0) {
3624 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3625 if (debug & VP9_DEBUG_CACHE)
3626 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3627 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3628 / raw_mcr_cnt;
3629 if (debug & VP9_DEBUG_CACHE)
3630 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3631 } else {
3632 if (debug & VP9_DEBUG_CACHE)
3633 pr_info("MCRCC_HIT_RATE : na\n");
3634 if (debug & VP9_DEBUG_CACHE)
3635 pr_info("MCRCC_BYP_RATE : na\n");
3636 }
3637 return;
3638 }
3639
3640
3641 static void decomp_perfcount_reset(void)
3642 {
3643 if (debug & VP9_DEBUG_CACHE)
3644 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3645 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3646 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3647 return;
3648 }
3649
3650 static void decomp_get_hitrate(void)
3651 {
3652 unsigned raw_mcr_cnt;
3653 unsigned hit_mcr_cnt;
3654 int hitrate;
3655 if (debug & VP9_DEBUG_CACHE)
3656 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3657 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3658 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3659 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3660 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3661
3662 if (debug & VP9_DEBUG_CACHE)
3663 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3664 if (debug & VP9_DEBUG_CACHE)
3665 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3666
3667 if (raw_mcr_cnt != 0) {
3668 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3669 if (debug & VP9_DEBUG_CACHE)
3670 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3671 } else {
3672 if (debug & VP9_DEBUG_CACHE)
3673 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3674 }
3675 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3676 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3677 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3678 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3679
3680 if (debug & VP9_DEBUG_CACHE)
3681 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3682 if (debug & VP9_DEBUG_CACHE)
3683 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3684
3685 if (raw_mcr_cnt != 0) {
3686 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3687 if (debug & VP9_DEBUG_CACHE)
3688 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3689 } else {
3690 if (debug & VP9_DEBUG_CACHE)
3691 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3692 }
3693 return;
3694 }
3695
3696 static void decomp_get_comprate(void)
3697 {
3698 unsigned raw_ucomp_cnt;
3699 unsigned fast_comp_cnt;
3700 unsigned slow_comp_cnt;
3701 int comprate;
3702
3703 if (debug & VP9_DEBUG_CACHE)
3704 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3705 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3706 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3707 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3708 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3709 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3710 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3711
3712 if (debug & VP9_DEBUG_CACHE)
3713 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3714 if (debug & VP9_DEBUG_CACHE)
3715 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3716 if (debug & VP9_DEBUG_CACHE)
3717 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3718
3719 if (raw_ucomp_cnt != 0) {
3720 comprate = (fast_comp_cnt + slow_comp_cnt)
3721 * 100 / raw_ucomp_cnt;
3722 if (debug & VP9_DEBUG_CACHE)
3723 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3724 } else {
3725 if (debug & VP9_DEBUG_CACHE)
3726 pr_info("DECOMP_COMP_RATIO : na\n");
3727 }
3728 return;
3729 }
3730 /* cache_util.c end */
3731
3732 /*====================================================
3733 *========================================================================
3734 *vp9_prob define
3735 *========================================================================
3736 */
3737 #define VP9_PARTITION_START 0
3738 #define VP9_PARTITION_SIZE_STEP (3 * 4)
3739 #define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3740 #define VP9_PARTITION_KEY_START 0
3741 #define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3742 #define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3743 #define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3744 #define VP9_SKIP_SIZE 4 /* only use 3*/
3745 #define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3746 #define VP9_TX_MODE_8_0_OFFSET 0
3747 #define VP9_TX_MODE_8_1_OFFSET 1
3748 #define VP9_TX_MODE_16_0_OFFSET 2
3749 #define VP9_TX_MODE_16_1_OFFSET 4
3750 #define VP9_TX_MODE_32_0_OFFSET 6
3751 #define VP9_TX_MODE_32_1_OFFSET 9
3752 #define VP9_TX_MODE_SIZE 12
3753 #define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3754 #define VP9_COEF_BAND_0_OFFSET 0
3755 #define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3756 #define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3757 #define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3758 #define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3759 #define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3760 #define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3761 #define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3762 #define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3763 #define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3764 #define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3765 #define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3766 #define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3767 #define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3768 #define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3769 #define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3770 #define VP9_INTERP_SIZE 8
3771 #define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3772 #define VP9_INTRA_INTER_SIZE 4
3773 #define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3774 #define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3775 #define VP9_COMP_INTER_START \
3776 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3777 #define VP9_COMP_INTER_SIZE 5
3778 #define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3779 #define VP9_COMP_REF_SIZE 5
3780 #define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3781 #define VP9_SINGLE_REF_SIZE 10
3782 #define VP9_REF_MODE_START VP9_COMP_INTER_START
3783 #define VP9_REF_MODE_SIZE \
3784 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3785 #define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3786 #define VP9_IF_Y_MODE_SIZE 36
3787 #define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3788 #define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3789 #define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3790 #define VP9_MV_JOINTS_SIZE 3
3791 #define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3792 #define VP9_MV_SIGN_0_SIZE 1
3793 #define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3794 #define VP9_MV_CLASSES_0_SIZE 10
3795 #define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3796 #define VP9_MV_CLASS0_0_SIZE 1
3797 #define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3798 #define VP9_MV_BITS_0_SIZE 10
3799 #define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3800 #define VP9_MV_SIGN_1_SIZE 1
3801 #define VP9_MV_CLASSES_1_START \
3802 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3803 #define VP9_MV_CLASSES_1_SIZE 10
3804 #define VP9_MV_CLASS0_1_START \
3805 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3806 #define VP9_MV_CLASS0_1_SIZE 1
3807 #define VP9_MV_BITS_1_START \
3808 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3809 #define VP9_MV_BITS_1_SIZE 10
3810 #define VP9_MV_CLASS0_FP_0_START \
3811 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3812 #define VP9_MV_CLASS0_FP_0_SIZE 9
3813 #define VP9_MV_CLASS0_FP_1_START \
3814 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3815 #define VP9_MV_CLASS0_FP_1_SIZE 9
3816 #define VP9_MV_CLASS0_HP_0_START \
3817 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3818 #define VP9_MV_CLASS0_HP_0_SIZE 2
3819 #define VP9_MV_CLASS0_HP_1_START \
3820 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3821 #define VP9_MV_CLASS0_HP_1_SIZE 2
3822 #define VP9_MV_START VP9_MV_JOINTS_START
3823 #define VP9_MV_SIZE 72 /*only use 69*/
3824
3825 #define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3826
3827
3828 /*========================================================================
3829 * vp9_count_mem define
3830 *========================================================================
3831 */
3832 #define VP9_COEF_COUNT_START 0
3833 #define VP9_COEF_COUNT_BAND_0_OFFSET 0
3834 #define VP9_COEF_COUNT_BAND_1_OFFSET \
3835 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3836 #define VP9_COEF_COUNT_BAND_2_OFFSET \
3837 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3838 #define VP9_COEF_COUNT_BAND_3_OFFSET \
3839 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3840 #define VP9_COEF_COUNT_BAND_4_OFFSET \
3841 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3842 #define VP9_COEF_COUNT_BAND_5_OFFSET \
3843 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3844 #define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3845 #define VP9_COEF_COUNT_4X4_START \
3846 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3847 #define VP9_COEF_COUNT_8X8_START \
3848 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3849 #define VP9_COEF_COUNT_16X16_START \
3850 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3851 #define VP9_COEF_COUNT_32X32_START \
3852 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3853 #define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3854 #define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3855
3856 #define VP9_INTRA_INTER_COUNT_START \
3857 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3858 #define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3859 #define VP9_COMP_INTER_COUNT_START \
3860 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3861 #define VP9_COMP_INTER_COUNT_SIZE (5*2)
3862 #define VP9_COMP_REF_COUNT_START \
3863 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3864 #define VP9_COMP_REF_COUNT_SIZE (5*2)
3865 #define VP9_SINGLE_REF_COUNT_START \
3866 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3867 #define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3868 #define VP9_TX_MODE_COUNT_START \
3869 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3870 #define VP9_TX_MODE_COUNT_SIZE (12*2)
3871 #define VP9_SKIP_COUNT_START \
3872 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3873 #define VP9_SKIP_COUNT_SIZE (3*2)
3874 #define VP9_MV_SIGN_0_COUNT_START \
3875 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3876 #define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3877 #define VP9_MV_SIGN_1_COUNT_START \
3878 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3879 #define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3880 #define VP9_MV_BITS_0_COUNT_START \
3881 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3882 #define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3883 #define VP9_MV_BITS_1_COUNT_START \
3884 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3885 #define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3886 #define VP9_MV_CLASS0_HP_0_COUNT_START \
3887 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3888 #define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3889 #define VP9_MV_CLASS0_HP_1_COUNT_START \
3890 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3891 #define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3892 /* Start merge_tree*/
3893 #define VP9_INTER_MODE_COUNT_START \
3894 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3895 #define VP9_INTER_MODE_COUNT_SIZE (7*4)
3896 #define VP9_IF_Y_MODE_COUNT_START \
3897 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3898 #define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3899 #define VP9_IF_UV_MODE_COUNT_START \
3900 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3901 #define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3902 #define VP9_PARTITION_P_COUNT_START \
3903 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3904 #define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3905 #define VP9_INTERP_COUNT_START \
3906 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3907 #define VP9_INTERP_COUNT_SIZE (4*3)
3908 #define VP9_MV_JOINTS_COUNT_START \
3909 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3910 #define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3911 #define VP9_MV_CLASSES_0_COUNT_START \
3912 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3913 #define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3914 #define VP9_MV_CLASS0_0_COUNT_START \
3915 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3916 #define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3917 #define VP9_MV_CLASSES_1_COUNT_START \
3918 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3919 #define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3920 #define VP9_MV_CLASS0_1_COUNT_START \
3921 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3922 #define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3923 #define VP9_MV_CLASS0_FP_0_COUNT_START \
3924 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3925 #define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3926 #define VP9_MV_CLASS0_FP_1_COUNT_START \
3927 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3928 #define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3929
3930
3931 #define DC_PRED 0 /* Average of above and left pixels*/
3932 #define V_PRED 1 /* Vertical*/
3933 #define H_PRED 2 /* Horizontal*/
3934 #define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3935 #define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3936 #define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3937 #define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3938 #define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3939 #define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3940 #define TM_PRED 9 /*True-motion*/
3941
3942 int clip_prob(int p)
3943 {
3944 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3945 }
3946
3947 #define ROUND_POWER_OF_TWO(value, n) \
3948 (((value) + (1 << ((n) - 1))) >> (n))
3949
3950 #define MODE_MV_COUNT_SAT 20
3951 static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3952 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3953 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3954 };
3955
3956 void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3957 int coef_node_start, int tree_left, int tree_right, int tree_i,
3958 int node) {
3959
3960 int prob_32, prob_res, prob_shift;
3961 int pre_prob, new_prob;
3962 int den, m_count, get_prob, factor;
3963
3964 prob_32 = prev_prob[coef_node_start / 4 * 2];
3965 prob_res = coef_node_start & 3;
3966 prob_shift = prob_res * 8;
3967 pre_prob = (prob_32 >> prob_shift) & 0xff;
3968
3969 den = tree_left + tree_right;
3970
3971 if (den == 0)
3972 new_prob = pre_prob;
3973 else {
3974 m_count = (den < MODE_MV_COUNT_SAT) ?
3975 den : MODE_MV_COUNT_SAT;
3976 get_prob = clip_prob(
3977 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3978 den));
3979 /*weighted_prob*/
3980 factor = count_to_update_factor[m_count];
3981 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3982 + get_prob * factor, 8);
3983 }
3984 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3985 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3986
3987 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3988 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3989 *cur_prob[coef_node_start/4*2]);
3990 */
3991 }
3992
3993
3994 /*void adapt_coef_probs(void)*/
3995 void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3996 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3997 {
3998 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3999 *unsigned int prev_prob[496*2];
4000 *unsigned int cur_prob[496*2];
4001 *0x300 * 128bits = 0x3000 (32K Bytes)
4002 *unsigned int count[0x300*4];
4003 */
4004
4005 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
4006 int plane, coef_plane_start, coef_count_plane_start;
4007 int type, coef_type_start, coef_count_type_start;
4008 int band, coef_band_start, coef_count_band_start;
4009 int cxt_num;
4010 int cxt, coef_cxt_start, coef_count_cxt_start;
4011 int node, coef_node_start, coef_count_node_start;
4012
4013 int tree_i, tree_left, tree_right;
4014 int mvd_i;
4015
4016 int count_sat = 24;
4017 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
4018 *use 128
4019 */
4020 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
4021 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
4022 int update_factor = cur_kf ? 112 :
4023 prev_kf ? 128 : 112;
4024
4025 int prob_32;
4026 int prob_res;
4027 int prob_shift;
4028 int pre_prob;
4029
4030 int num, den;
4031 int get_prob;
4032 int m_count;
4033 int factor;
4034
4035 int new_prob;
4036
4037 if (debug & VP9_DEBUG_MERGE)
4038 pr_info
4039 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4040 pre_fc, prev_kf, cur_kf);
4041
4042 /*adapt_coef_probs*/
4043 for (tx_size = 0; tx_size < 4; tx_size++) {
4044 coef_tx_size_start = VP9_COEF_START
4045 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4046 coef_count_tx_size_start = VP9_COEF_COUNT_START
4047 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4048 coef_plane_start = coef_tx_size_start;
4049 coef_count_plane_start = coef_count_tx_size_start;
4050 for (plane = 0; plane < 2; plane++) {
4051 coef_type_start = coef_plane_start;
4052 coef_count_type_start = coef_count_plane_start;
4053 for (type = 0; type < 2; type++) {
4054 coef_band_start = coef_type_start;
4055 coef_count_band_start = coef_count_type_start;
4056 for (band = 0; band < 6; band++) {
4057 if (band == 0)
4058 cxt_num = 3;
4059 else
4060 cxt_num = 6;
4061 coef_cxt_start = coef_band_start;
4062 coef_count_cxt_start =
4063 coef_count_band_start;
4064 for (cxt = 0; cxt < cxt_num; cxt++) {
4065 const int n0 =
4066 count[coef_count_cxt_start];
4067 const int n1 =
4068 count[coef_count_cxt_start + 1];
4069 const int n2 =
4070 count[coef_count_cxt_start + 2];
4071 const int neob =
4072 count[coef_count_cxt_start + 3];
4073 const int nneob =
4074 count[coef_count_cxt_start + 4];
4075 const unsigned int
4076 branch_ct[3][2] = {
4077 { neob, nneob },
4078 { n0, n1 + n2 },
4079 { n1, n2 }
4080 };
4081 coef_node_start =
4082 coef_cxt_start;
4083 for
4084 (node = 0; node < 3; node++) {
4085 prob_32 =
4086 prev_prob[
4087 coef_node_start
4088 / 4 * 2];
4089 prob_res =
4090 coef_node_start & 3;
4091 prob_shift =
4092 prob_res * 8;
4093 pre_prob =
4094 (prob_32 >> prob_shift)
4095 & 0xff;
4096
4097 /*get_binary_prob*/
4098 num =
4099 branch_ct[node][0];
4100 den =
4101 branch_ct[node][0] +
4102 branch_ct[node][1];
4103 m_count = (den <
4104 count_sat)
4105 ? den : count_sat;
4106
4107 get_prob =
4108 (den == 0) ? 128u :
4109 clip_prob(
4110 div_r32(((int64_t)
4111 num * 256
4112 + (den >> 1)),
4113 den));
4114
4115 factor =
4116 update_factor * m_count
4117 / count_sat;
4118 new_prob =
4119 ROUND_POWER_OF_TWO
4120 (pre_prob *
4121 (256 - factor) +
4122 get_prob * factor, 8);
4123
4124 cur_prob[coef_node_start
4125 / 4 * 2] =
4126 (cur_prob
4127 [coef_node_start
4128 / 4 * 2] & (~(0xff <<
4129 prob_shift))) |
4130 (new_prob <<
4131 prob_shift);
4132
4133 coef_node_start += 1;
4134 }
4135
4136 coef_cxt_start =
4137 coef_cxt_start + 3;
4138 coef_count_cxt_start =
4139 coef_count_cxt_start
4140 + 5;
4141 }
4142 if (band == 0) {
4143 coef_band_start += 10;
4144 coef_count_band_start += 15;
4145 } else {
4146 coef_band_start += 18;
4147 coef_count_band_start += 30;
4148 }
4149 }
4150 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4151 coef_count_type_start +=
4152 VP9_COEF_COUNT_SIZE_ONE_SET;
4153 }
4154 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4155 coef_count_plane_start +=
4156 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4157 }
4158 }
4159
4160 if (cur_kf == 0) {
4161 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4162 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4163 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4164 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4165
4166 if (coef_count_node_start ==
4167 VP9_INTRA_INTER_COUNT_START) {
4168 if (debug & VP9_DEBUG_MERGE)
4169 pr_info(" # merge_intra_inter_prob\n");
4170 coef_node_start = VP9_INTRA_INTER_START;
4171 } else if (coef_count_node_start ==
4172 VP9_COMP_INTER_COUNT_START) {
4173 if (debug & VP9_DEBUG_MERGE)
4174 pr_info(" # merge_comp_inter_prob\n");
4175 coef_node_start = VP9_COMP_INTER_START;
4176 }
4177 /*
4178 *else if (coef_count_node_start ==
4179 * VP9_COMP_REF_COUNT_START) {
4180 * pr_info(" # merge_comp_inter_prob\n");
4181 * coef_node_start = VP9_COMP_REF_START;
4182 *}
4183 *else if (coef_count_node_start ==
4184 * VP9_SINGLE_REF_COUNT_START) {
4185 * pr_info(" # merge_comp_inter_prob\n");
4186 * coef_node_start = VP9_SINGLE_REF_START;
4187 *}
4188 */
4189 else if (coef_count_node_start ==
4190 VP9_TX_MODE_COUNT_START) {
4191 if (debug & VP9_DEBUG_MERGE)
4192 pr_info(" # merge_tx_mode_probs\n");
4193 coef_node_start = VP9_TX_MODE_START;
4194 } else if (coef_count_node_start ==
4195 VP9_SKIP_COUNT_START) {
4196 if (debug & VP9_DEBUG_MERGE)
4197 pr_info(" # merge_skip_probs\n");
4198 coef_node_start = VP9_SKIP_START;
4199 } else if (coef_count_node_start ==
4200 VP9_MV_SIGN_0_COUNT_START) {
4201 if (debug & VP9_DEBUG_MERGE)
4202 pr_info(" # merge_sign_0\n");
4203 coef_node_start = VP9_MV_SIGN_0_START;
4204 } else if (coef_count_node_start ==
4205 VP9_MV_SIGN_1_COUNT_START) {
4206 if (debug & VP9_DEBUG_MERGE)
4207 pr_info(" # merge_sign_1\n");
4208 coef_node_start = VP9_MV_SIGN_1_START;
4209 } else if (coef_count_node_start ==
4210 VP9_MV_BITS_0_COUNT_START) {
4211 if (debug & VP9_DEBUG_MERGE)
4212 pr_info(" # merge_bits_0\n");
4213 coef_node_start = VP9_MV_BITS_0_START;
4214 } else if (coef_count_node_start ==
4215 VP9_MV_BITS_1_COUNT_START) {
4216 if (debug & VP9_DEBUG_MERGE)
4217 pr_info(" # merge_bits_1\n");
4218 coef_node_start = VP9_MV_BITS_1_START;
4219 } else if (coef_count_node_start ==
4220 VP9_MV_CLASS0_HP_0_COUNT_START) {
4221 if (debug & VP9_DEBUG_MERGE)
4222 pr_info(" # merge_class0_hp\n");
4223 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4224 }
4225
4226
4227 den = count[coef_count_node_start] +
4228 count[coef_count_node_start + 1];
4229
4230 prob_32 = prev_prob[coef_node_start / 4 * 2];
4231 prob_res = coef_node_start & 3;
4232 prob_shift = prob_res * 8;
4233 pre_prob = (prob_32 >> prob_shift) & 0xff;
4234
4235 if (den == 0)
4236 new_prob = pre_prob;
4237 else {
4238 m_count = (den < MODE_MV_COUNT_SAT) ?
4239 den : MODE_MV_COUNT_SAT;
4240 get_prob =
4241 clip_prob(
4242 div_r32(((int64_t)count[coef_count_node_start]
4243 * 256 + (den >> 1)),
4244 den));
4245 /*weighted_prob*/
4246 factor = count_to_update_factor[m_count];
4247 new_prob =
4248 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4249 + get_prob * factor, 8);
4250 }
4251 cur_prob[coef_node_start / 4 * 2] =
4252 (cur_prob[coef_node_start / 4 * 2] &
4253 (~(0xff << prob_shift)))
4254 | (new_prob << prob_shift);
4255
4256 coef_node_start = coef_node_start + 1;
4257 }
4258 if (debug & VP9_DEBUG_MERGE)
4259 pr_info(" # merge_vp9_inter_mode_tree\n");
4260 coef_node_start = VP9_INTER_MODE_START;
4261 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4262 for (tree_i = 0; tree_i < 7; tree_i++) {
4263 for (node = 0; node < 3; node++) {
4264 switch (node) {
4265 case 2:
4266 tree_left =
4267 count[coef_count_node_start + 1];
4268 tree_right =
4269 count[coef_count_node_start + 3];
4270 break;
4271 case 1:
4272 tree_left =
4273 count[coef_count_node_start + 0];
4274 tree_right =
4275 count[coef_count_node_start + 1]
4276 + count[coef_count_node_start + 3];
4277 break;
4278 default:
4279 tree_left =
4280 count[coef_count_node_start + 2];
4281 tree_right =
4282 count[coef_count_node_start + 0]
4283 + count[coef_count_node_start + 1]
4284 + count[coef_count_node_start + 3];
4285 break;
4286
4287 }
4288
4289 vp9_tree_merge_probs(prev_prob, cur_prob,
4290 coef_node_start, tree_left, tree_right,
4291 tree_i, node);
4292
4293 coef_node_start = coef_node_start + 1;
4294 }
4295 coef_count_node_start = coef_count_node_start + 4;
4296 }
4297 if (debug & VP9_DEBUG_MERGE)
4298 pr_info(" # merge_vp9_intra_mode_tree\n");
4299 coef_node_start = VP9_IF_Y_MODE_START;
4300 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4301 for (tree_i = 0; tree_i < 14; tree_i++) {
4302 for (node = 0; node < 9; node++) {
4303 switch (node) {
4304 case 8:
4305 tree_left =
4306 count[coef_count_node_start+D153_PRED];
4307 tree_right =
4308 count[coef_count_node_start+D207_PRED];
4309 break;
4310 case 7:
4311 tree_left =
4312 count[coef_count_node_start+D63_PRED];
4313 tree_right =
4314 count[coef_count_node_start+D207_PRED] +
4315 count[coef_count_node_start+D153_PRED];
4316 break;
4317 case 6:
4318 tree_left =
4319 count[coef_count_node_start + D45_PRED];
4320 tree_right =
4321 count[coef_count_node_start+D207_PRED] +
4322 count[coef_count_node_start+D153_PRED] +
4323 count[coef_count_node_start+D63_PRED];
4324 break;
4325 case 5:
4326 tree_left =
4327 count[coef_count_node_start+D135_PRED];
4328 tree_right =
4329 count[coef_count_node_start+D117_PRED];
4330 break;
4331 case 4:
4332 tree_left =
4333 count[coef_count_node_start+H_PRED];
4334 tree_right =
4335 count[coef_count_node_start+D117_PRED] +
4336 count[coef_count_node_start+D135_PRED];
4337 break;
4338 case 3:
4339 tree_left =
4340 count[coef_count_node_start+H_PRED] +
4341 count[coef_count_node_start+D117_PRED] +
4342 count[coef_count_node_start+D135_PRED];
4343 tree_right =
4344 count[coef_count_node_start+D45_PRED] +
4345 count[coef_count_node_start+D207_PRED] +
4346 count[coef_count_node_start+D153_PRED] +
4347 count[coef_count_node_start+D63_PRED];
4348 break;
4349 case 2:
4350 tree_left =
4351 count[coef_count_node_start+V_PRED];
4352 tree_right =
4353 count[coef_count_node_start+H_PRED] +
4354 count[coef_count_node_start+D117_PRED] +
4355 count[coef_count_node_start+D135_PRED] +
4356 count[coef_count_node_start+D45_PRED] +
4357 count[coef_count_node_start+D207_PRED] +
4358 count[coef_count_node_start+D153_PRED] +
4359 count[coef_count_node_start+D63_PRED];
4360 break;
4361 case 1:
4362 tree_left =
4363 count[coef_count_node_start+TM_PRED];
4364 tree_right =
4365 count[coef_count_node_start+V_PRED] +
4366 count[coef_count_node_start+H_PRED] +
4367 count[coef_count_node_start+D117_PRED] +
4368 count[coef_count_node_start+D135_PRED] +
4369 count[coef_count_node_start+D45_PRED] +
4370 count[coef_count_node_start+D207_PRED] +
4371 count[coef_count_node_start+D153_PRED] +
4372 count[coef_count_node_start+D63_PRED];
4373 break;
4374 default:
4375 tree_left =
4376 count[coef_count_node_start+DC_PRED];
4377 tree_right =
4378 count[coef_count_node_start+TM_PRED] +
4379 count[coef_count_node_start+V_PRED] +
4380 count[coef_count_node_start+H_PRED] +
4381 count[coef_count_node_start+D117_PRED] +
4382 count[coef_count_node_start+D135_PRED] +
4383 count[coef_count_node_start+D45_PRED] +
4384 count[coef_count_node_start+D207_PRED] +
4385 count[coef_count_node_start+D153_PRED] +
4386 count[coef_count_node_start+D63_PRED];
4387 break;
4388
4389 }
4390
4391 vp9_tree_merge_probs(prev_prob, cur_prob,
4392 coef_node_start, tree_left, tree_right,
4393 tree_i, node);
4394
4395 coef_node_start = coef_node_start + 1;
4396 }
4397 coef_count_node_start = coef_count_node_start + 10;
4398 }
4399
4400 if (debug & VP9_DEBUG_MERGE)
4401 pr_info(" # merge_vp9_partition_tree\n");
4402 coef_node_start = VP9_PARTITION_P_START;
4403 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4404 for (tree_i = 0; tree_i < 16; tree_i++) {
4405 for (node = 0; node < 3; node++) {
4406 switch (node) {
4407 case 2:
4408 tree_left =
4409 count[coef_count_node_start + 2];
4410 tree_right =
4411 count[coef_count_node_start + 3];
4412 break;
4413 case 1:
4414 tree_left =
4415 count[coef_count_node_start + 1];
4416 tree_right =
4417 count[coef_count_node_start + 2] +
4418 count[coef_count_node_start + 3];
4419 break;
4420 default:
4421 tree_left =
4422 count[coef_count_node_start + 0];
4423 tree_right =
4424 count[coef_count_node_start + 1] +
4425 count[coef_count_node_start + 2] +
4426 count[coef_count_node_start + 3];
4427 break;
4428
4429 }
4430
4431 vp9_tree_merge_probs(prev_prob, cur_prob,
4432 coef_node_start,
4433 tree_left, tree_right, tree_i, node);
4434
4435 coef_node_start = coef_node_start + 1;
4436 }
4437 coef_count_node_start = coef_count_node_start + 4;
4438 }
4439
4440 if (debug & VP9_DEBUG_MERGE)
4441 pr_info(" # merge_vp9_switchable_interp_tree\n");
4442 coef_node_start = VP9_INTERP_START;
4443 coef_count_node_start = VP9_INTERP_COUNT_START;
4444 for (tree_i = 0; tree_i < 4; tree_i++) {
4445 for (node = 0; node < 2; node++) {
4446 switch (node) {
4447 case 1:
4448 tree_left =
4449 count[coef_count_node_start + 1];
4450 tree_right =
4451 count[coef_count_node_start + 2];
4452 break;
4453 default:
4454 tree_left =
4455 count[coef_count_node_start + 0];
4456 tree_right =
4457 count[coef_count_node_start + 1] +
4458 count[coef_count_node_start + 2];
4459 break;
4460
4461 }
4462
4463 vp9_tree_merge_probs(prev_prob, cur_prob,
4464 coef_node_start,
4465 tree_left, tree_right, tree_i, node);
4466
4467 coef_node_start = coef_node_start + 1;
4468 }
4469 coef_count_node_start = coef_count_node_start + 3;
4470 }
4471
4472 if (debug & VP9_DEBUG_MERGE)
4473 pr_info("# merge_vp9_mv_joint_tree\n");
4474 coef_node_start = VP9_MV_JOINTS_START;
4475 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4476 for (tree_i = 0; tree_i < 1; tree_i++) {
4477 for (node = 0; node < 3; node++) {
4478 switch (node) {
4479 case 2:
4480 tree_left =
4481 count[coef_count_node_start + 2];
4482 tree_right =
4483 count[coef_count_node_start + 3];
4484 break;
4485 case 1:
4486 tree_left =
4487 count[coef_count_node_start + 1];
4488 tree_right =
4489 count[coef_count_node_start + 2] +
4490 count[coef_count_node_start + 3];
4491 break;
4492 default:
4493 tree_left =
4494 count[coef_count_node_start + 0];
4495 tree_right =
4496 count[coef_count_node_start + 1] +
4497 count[coef_count_node_start + 2] +
4498 count[coef_count_node_start + 3];
4499 break;
4500 }
4501
4502 vp9_tree_merge_probs(prev_prob, cur_prob,
4503 coef_node_start,
4504 tree_left, tree_right, tree_i, node);
4505
4506 coef_node_start = coef_node_start + 1;
4507 }
4508 coef_count_node_start = coef_count_node_start + 4;
4509 }
4510
4511 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4512 if (debug & VP9_DEBUG_MERGE)
4513 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4514 coef_node_start =
4515 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4516 coef_count_node_start =
4517 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4518 : VP9_MV_CLASSES_0_COUNT_START;
4519 tree_i = 0;
4520 for (node = 0; node < 10; node++) {
4521 switch (node) {
4522 case 9:
4523 tree_left =
4524 count[coef_count_node_start + 9];
4525 tree_right =
4526 count[coef_count_node_start + 10];
4527 break;
4528 case 8:
4529 tree_left =
4530 count[coef_count_node_start + 7];
4531 tree_right =
4532 count[coef_count_node_start + 8];
4533 break;
4534 case 7:
4535 tree_left =
4536 count[coef_count_node_start + 7] +
4537 count[coef_count_node_start + 8];
4538 tree_right =
4539 count[coef_count_node_start + 9] +
4540 count[coef_count_node_start + 10];
4541 break;
4542 case 6:
4543 tree_left =
4544 count[coef_count_node_start + 6];
4545 tree_right =
4546 count[coef_count_node_start + 7] +
4547 count[coef_count_node_start + 8] +
4548 count[coef_count_node_start + 9] +
4549 count[coef_count_node_start + 10];
4550 break;
4551 case 5:
4552 tree_left =
4553 count[coef_count_node_start + 4];
4554 tree_right =
4555 count[coef_count_node_start + 5];
4556 break;
4557 case 4:
4558 tree_left =
4559 count[coef_count_node_start + 4] +
4560 count[coef_count_node_start + 5];
4561 tree_right =
4562 count[coef_count_node_start + 6] +
4563 count[coef_count_node_start + 7] +
4564 count[coef_count_node_start + 8] +
4565 count[coef_count_node_start + 9] +
4566 count[coef_count_node_start + 10];
4567 break;
4568 case 3:
4569 tree_left =
4570 count[coef_count_node_start + 2];
4571 tree_right =
4572 count[coef_count_node_start + 3];
4573 break;
4574 case 2:
4575 tree_left =
4576 count[coef_count_node_start + 2] +
4577 count[coef_count_node_start + 3];
4578 tree_right =
4579 count[coef_count_node_start + 4] +
4580 count[coef_count_node_start + 5] +
4581 count[coef_count_node_start + 6] +
4582 count[coef_count_node_start + 7] +
4583 count[coef_count_node_start + 8] +
4584 count[coef_count_node_start + 9] +
4585 count[coef_count_node_start + 10];
4586 break;
4587 case 1:
4588 tree_left =
4589 count[coef_count_node_start + 1];
4590 tree_right =
4591 count[coef_count_node_start + 2] +
4592 count[coef_count_node_start + 3] +
4593 count[coef_count_node_start + 4] +
4594 count[coef_count_node_start + 5] +
4595 count[coef_count_node_start + 6] +
4596 count[coef_count_node_start + 7] +
4597 count[coef_count_node_start + 8] +
4598 count[coef_count_node_start + 9] +
4599 count[coef_count_node_start + 10];
4600 break;
4601 default:
4602 tree_left =
4603 count[coef_count_node_start + 0];
4604 tree_right =
4605 count[coef_count_node_start + 1] +
4606 count[coef_count_node_start + 2] +
4607 count[coef_count_node_start + 3] +
4608 count[coef_count_node_start + 4] +
4609 count[coef_count_node_start + 5] +
4610 count[coef_count_node_start + 6] +
4611 count[coef_count_node_start + 7] +
4612 count[coef_count_node_start + 8] +
4613 count[coef_count_node_start + 9] +
4614 count[coef_count_node_start + 10];
4615 break;
4616
4617 }
4618
4619 vp9_tree_merge_probs(prev_prob, cur_prob,
4620 coef_node_start, tree_left, tree_right,
4621 tree_i, node);
4622
4623 coef_node_start = coef_node_start + 1;
4624 }
4625
4626 if (debug & VP9_DEBUG_MERGE)
4627 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4628 coef_node_start =
4629 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4630 coef_count_node_start =
4631 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4632 VP9_MV_CLASS0_0_COUNT_START;
4633 tree_i = 0;
4634 node = 0;
4635 tree_left = count[coef_count_node_start + 0];
4636 tree_right = count[coef_count_node_start + 1];
4637
4638 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4639 tree_left, tree_right, tree_i, node);
4640 if (debug & VP9_DEBUG_MERGE)
4641 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4642 mvd_i);
4643 coef_node_start =
4644 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4645 VP9_MV_CLASS0_FP_0_START;
4646 coef_count_node_start =
4647 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4648 VP9_MV_CLASS0_FP_0_COUNT_START;
4649 for (tree_i = 0; tree_i < 3; tree_i++) {
4650 for (node = 0; node < 3; node++) {
4651 switch (node) {
4652 case 2:
4653 tree_left =
4654 count[coef_count_node_start + 2];
4655 tree_right =
4656 count[coef_count_node_start + 3];
4657 break;
4658 case 1:
4659 tree_left =
4660 count[coef_count_node_start + 1];
4661 tree_right =
4662 count[coef_count_node_start + 2]
4663 + count[coef_count_node_start + 3];
4664 break;
4665 default:
4666 tree_left =
4667 count[coef_count_node_start + 0];
4668 tree_right =
4669 count[coef_count_node_start + 1]
4670 + count[coef_count_node_start + 2]
4671 + count[coef_count_node_start + 3];
4672 break;
4673
4674 }
4675
4676 vp9_tree_merge_probs(prev_prob, cur_prob,
4677 coef_node_start, tree_left, tree_right,
4678 tree_i, node);
4679
4680 coef_node_start = coef_node_start + 1;
4681 }
4682 coef_count_node_start = coef_count_node_start + 4;
4683 }
4684
4685 } /* for mvd_i (mvd_y or mvd_x)*/
4686 }
4687
4688 }
4689
4690 static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4691 {
4692 int i;
4693 struct VP9_Common_s *const cm = &pbi->common;
4694 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4695
4696 for (i = 0; i < pbi->used_buf_num; ++i) {
4697 if (frame_bufs[i].buf.vframe_bound)
4698 return true;
4699 }
4700
4701 return false;
4702 }
4703
4704 static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4705 {
4706 struct VP9_Common_s *const cm = &pbi->common;
4707 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4708 int i;
4709
4710 /* release workspace */
4711 if (pbi->bmmu_box)
4712 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4713 WORK_SPACE_BUF_ID);
4714 /*
4715 * it's only when vframe get back to driver, right now we can be sure
4716 * that vframe and fd are related. if the playback exits, the capture
4717 * requires the upper app to release when the fd is closed, and others
4718 * buffers drivers are released by driver.
4719 */
4720 for (i = 0; i < pbi->used_buf_num; ++i) {
4721 if (!frame_bufs[i].buf.vframe_bound) {
4722 if (pbi->bmmu_box)
4723 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4724 HEADER_BUFFER_IDX(i));
4725 if (pbi->mmu_box)
4726 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4727
4728 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4729 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4730 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4731 }
4732 }
4733 }
4734
4735 static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4736 {
4737 #ifndef MV_USE_FIXED_BUF
4738 dealloc_mv_bufs(pbi);
4739 #endif
4740 if (pbi->is_used_v4l &&
4741 v4l_is_there_vframe_bound(pbi)) {
4742 if (get_double_write_mode(pbi) != 0x10) {
4743 v4l_mmu_buffer_release(pbi);
4744 return;
4745 }
4746 }
4747
4748 if (pbi->mmu_box)
4749 decoder_mmu_box_free(pbi->mmu_box);
4750 pbi->mmu_box = NULL;
4751
4752 if (pbi->bmmu_box)
4753 decoder_bmmu_box_free(pbi->bmmu_box);
4754 pbi->bmmu_box = NULL;
4755 }
4756
4757 static int calc_luc_quantity(u32 w, u32 h)
4758 {
4759 int lcu_size = 64; /*fixed 64*/
4760 int pic_width_64 = (w + 63) & (~0x3f);
4761 int pic_height_32 = (h + 31) & (~0x1f);
4762 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4763 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4764 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4765 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4766
4767 return pic_width_lcu * pic_height_lcu;
4768 }
4769
4770 static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4771 struct PIC_BUFFER_CONFIG_s *pic)
4772 {
4773 int ret = -1;
4774 int i = pic->index;
4775 int dw_mode = get_double_write_mode_init(pbi);
4776 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4777 #ifdef MV_USE_FIXED_BUF
4778 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4779 pbi->work_space_buf->mpred_mv.buf_size;
4780 #endif
4781 struct vdec_v4l2_buffer *fb = NULL;
4782
4783 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4784 if (ret < 0) {
4785 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4786 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4787 return ret;
4788 }
4789
4790 if (pbi->mmu_enable) {
4791 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4792 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4793 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4794 pr_info("MMU header_adr %d: %ld\n",
4795 i, pbi->m_BUF[i].header_addr);
4796 }
4797 }
4798
4799 #ifdef MV_USE_FIXED_BUF
4800 if ((pbi->work_space_buf->mpred_mv.buf_start +
4801 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4802 <= mpred_mv_end) {
4803 #endif
4804 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4805 pic->cma_alloc_addr = fb->m.mem[0].addr;
4806 if (fb->num_planes == 1) {
4807 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4808 pbi->m_BUF[i].size = fb->m.mem[0].size;
4809 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4810 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4811 } else if (fb->num_planes == 2) {
4812 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4813 pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4814 pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4815 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4816 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4817 }
4818
4819 /* config frame buffer */
4820 if (pbi->mmu_enable)
4821 pic->header_adr = pbi->m_BUF[i].header_addr;
4822
4823 pic->BUF_index = i;
4824 pic->lcu_total = lcu_total;
4825 pic->mc_canvas_y = pic->index;
4826 pic->mc_canvas_u_v = pic->index;
4827
4828 if (dw_mode & 0x10) {
4829 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4830 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4831 pic->mc_canvas_y = (pic->index << 1);
4832 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4833 } else if (dw_mode) {
4834 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4835 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4836 }
4837
4838 #ifdef MV_USE_FIXED_BUF
4839 pic->mpred_mv_wr_start_addr =
4840 pbi->work_space_buf->mpred_mv.buf_start +
4841 ((pic->index * lcu_total) * MV_MEM_UNIT);
4842 #endif
4843 if (debug) {
4844 pr_info("%s index %d BUF_index %d ",
4845 __func__, pic->index,
4846 pic->BUF_index);
4847 pr_info("comp_body_size %x comp_buf_size %x ",
4848 pic->comp_body_size,
4849 pic->buf_size);
4850 pr_info("mpred_mv_wr_start_adr %ld\n",
4851 pic->mpred_mv_wr_start_addr);
4852 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4853 pic->dw_y_adr,
4854 pic->dw_u_v_adr);
4855 }
4856 #ifdef MV_USE_FIXED_BUF
4857 }
4858 #endif
4859 return ret;
4860 }
4861
4862 static int config_pic(struct VP9Decoder_s *pbi,
4863 struct PIC_BUFFER_CONFIG_s *pic_config)
4864 {
4865 int ret = -1;
4866 int i;
4867 int pic_width = pbi->init_pic_w;
4868 int pic_height = pbi->init_pic_h;
4869 int lcu_size = 64; /*fixed 64*/
4870 int pic_width_64 = (pic_width + 63) & (~0x3f);
4871 int pic_height_32 = (pic_height + 31) & (~0x1f);
4872 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4873 pic_width_64 / lcu_size + 1
4874 : pic_width_64 / lcu_size;
4875 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4876 pic_height_32 / lcu_size + 1
4877 : pic_height_32 / lcu_size;
4878 int lcu_total = pic_width_lcu * pic_height_lcu;
4879 #ifdef MV_USE_FIXED_BUF
4880 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4881 pbi->work_space_buf->mpred_mv.buf_size;
4882 #endif
4883 u32 y_adr = 0;
4884 int buf_size = 0;
4885
4886 int losless_comp_header_size =
4887 compute_losless_comp_header_size(pic_width,
4888 pic_height);
4889 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4890 pic_height, buf_alloc_depth == 10);
4891 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4892 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4893 int mc_buffer_size_u_v = 0;
4894 int mc_buffer_size_u_v_h = 0;
4895 int dw_mode = get_double_write_mode_init(pbi);
4896
4897 pbi->lcu_total = lcu_total;
4898
4899 if (dw_mode) {
4900 int pic_width_dw = pic_width /
4901 get_double_write_ratio(pbi, dw_mode);
4902 int pic_height_dw = pic_height /
4903 get_double_write_ratio(pbi, dw_mode);
4904
4905 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4906 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4907 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4908 pic_width_64_dw / lcu_size + 1
4909 : pic_width_64_dw / lcu_size;
4910 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4911 pic_height_32_dw / lcu_size + 1
4912 : pic_height_32_dw / lcu_size;
4913 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4914 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4915 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4916 /*64k alignment*/
4917 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4918 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4919 }
4920
4921 if (mc_buffer_size & 0xffff) /*64k alignment*/
4922 mc_buffer_size_h += 1;
4923 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4924 buf_size += (mc_buffer_size_h << 16);
4925
4926 if (pbi->mmu_enable) {
4927 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4928 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4929
4930 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4931 pr_info("MMU header_adr %d: %ld\n",
4932 pic_config->index, pic_config->header_adr);
4933 }
4934 }
4935
4936 i = pic_config->index;
4937 #ifdef MV_USE_FIXED_BUF
4938 if ((pbi->work_space_buf->mpred_mv.buf_start +
4939 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4940 <= mpred_mv_end
4941 ) {
4942 #endif
4943 if (buf_size > 0) {
4944 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4945 VF_BUFFER_IDX(i),
4946 buf_size, DRIVER_NAME,
4947 &pic_config->cma_alloc_addr);
4948 if (ret < 0) {
4949 pr_info(
4950 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4951 VF_BUFFER_IDX(i),
4952 buf_size
4953 );
4954 return ret;
4955 }
4956
4957 if (pic_config->cma_alloc_addr)
4958 y_adr = pic_config->cma_alloc_addr;
4959 else {
4960 pr_info(
4961 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4962 VF_BUFFER_IDX(i),
4963 buf_size
4964 );
4965 return -1;
4966 }
4967 }
4968 {
4969 /*ensure get_pic_by_POC()
4970 not get the buffer not decoded*/
4971 pic_config->BUF_index = i;
4972 pic_config->lcu_total = lcu_total;
4973
4974 pic_config->comp_body_size = losless_comp_body_size;
4975 pic_config->buf_size = buf_size;
4976
4977 pic_config->mc_canvas_y = pic_config->index;
4978 pic_config->mc_canvas_u_v = pic_config->index;
4979 if (dw_mode & 0x10) {
4980 pic_config->dw_y_adr = y_adr;
4981 pic_config->dw_u_v_adr = y_adr +
4982 ((mc_buffer_size_u_v_h << 16) << 1);
4983
4984 pic_config->mc_canvas_y =
4985 (pic_config->index << 1);
4986 pic_config->mc_canvas_u_v =
4987 (pic_config->index << 1) + 1;
4988 } else if (dw_mode) {
4989 pic_config->dw_y_adr = y_adr;
4990 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4991 ((mc_buffer_size_u_v_h << 16) << 1);
4992 }
4993 #ifdef MV_USE_FIXED_BUF
4994 pic_config->mpred_mv_wr_start_addr =
4995 pbi->work_space_buf->mpred_mv.buf_start +
4996 ((pic_config->index * lcu_total)
4997 * MV_MEM_UNIT);
4998 #endif
4999 if (debug) {
5000 pr_info
5001 ("%s index %d BUF_index %d ",
5002 __func__, pic_config->index,
5003 pic_config->BUF_index);
5004 pr_info
5005 ("comp_body_size %x comp_buf_size %x ",
5006 pic_config->comp_body_size,
5007 pic_config->buf_size);
5008 pr_info
5009 ("mpred_mv_wr_start_adr %ld\n",
5010 pic_config->mpred_mv_wr_start_addr);
5011 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
5012 pic_config->dw_y_adr,
5013 pic_config->dw_u_v_adr);
5014 }
5015 ret = 0;
5016 }
5017 #ifdef MV_USE_FIXED_BUF
5018 }
5019 #endif
5020 return ret;
5021 }
5022
5023 static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
5024 {
5025 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5026 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5027 return (MMU_COMPRESS_8K_HEADER_SIZE);
5028
5029 return (MMU_COMPRESS_HEADER_SIZE);
5030 }
5031
5032 /*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5033 static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5034 {
5035 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5036 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5037 return (MAX_FRAME_8K_NUM * 4);
5038
5039 return (MAX_FRAME_4K_NUM * 4);
5040 }
5041
5042 static void init_pic_list(struct VP9Decoder_s *pbi)
5043 {
5044 int i;
5045 struct VP9_Common_s *cm = &pbi->common;
5046 struct PIC_BUFFER_CONFIG_s *pic_config;
5047 u32 header_size;
5048 struct vdec_s *vdec = hw_to_vdec(pbi);
5049
5050 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5051 header_size = vvp9_mmu_compress_header_size(pbi);
5052 /*alloc VP9 compress header first*/
5053 for (i = 0; i < pbi->used_buf_num; i++) {
5054 unsigned long buf_addr;
5055 if (decoder_bmmu_box_alloc_buf_phy
5056 (pbi->bmmu_box,
5057 HEADER_BUFFER_IDX(i), header_size,
5058 DRIVER_HEADER_NAME,
5059 &buf_addr) < 0) {
5060 pr_info("%s malloc compress header failed %d\n",
5061 DRIVER_HEADER_NAME, i);
5062 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5063 return;
5064 }
5065 }
5066 }
5067 for (i = 0; i < pbi->used_buf_num; i++) {
5068 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5069 pic_config->index = i;
5070 pic_config->BUF_index = -1;
5071 pic_config->mv_buf_index = -1;
5072 if (vdec->parallel_dec == 1) {
5073 pic_config->y_canvas_index = -1;
5074 pic_config->uv_canvas_index = -1;
5075 }
5076 pic_config->y_crop_width = pbi->init_pic_w;
5077 pic_config->y_crop_height = pbi->init_pic_h;
5078 pic_config->double_write_mode = get_double_write_mode(pbi);
5079
5080 if (!pbi->is_used_v4l) {
5081 if (config_pic(pbi, pic_config) < 0) {
5082 if (debug)
5083 pr_info("Config_pic %d fail\n",
5084 pic_config->index);
5085 pic_config->index = -1;
5086 break;
5087 }
5088
5089 if (pic_config->double_write_mode) {
5090 set_canvas(pbi, pic_config);
5091 }
5092 }
5093 }
5094 for (; i < pbi->used_buf_num; i++) {
5095 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5096 pic_config->index = -1;
5097 pic_config->BUF_index = -1;
5098 pic_config->mv_buf_index = -1;
5099 if (vdec->parallel_dec == 1) {
5100 pic_config->y_canvas_index = -1;
5101 pic_config->uv_canvas_index = -1;
5102 }
5103 }
5104 pr_info("%s ok, used_buf_num = %d\n",
5105 __func__, pbi->used_buf_num);
5106 }
5107
5108 static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5109 {
5110 int i;
5111 struct VP9_Common_s *cm = &pbi->common;
5112 struct PIC_BUFFER_CONFIG_s *pic_config;
5113 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5114 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5115 (0x1 << 1) | (0x1 << 2));
5116
5117
5118 for (i = 0; i < pbi->used_buf_num; i++) {
5119 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5120 if (pic_config->index < 0)
5121 break;
5122
5123 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5124
5125 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5126 pic_config->header_adr >> 5);
5127 } else {
5128 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5129 * pic_config->mc_y_adr
5130 * | (pic_config->mc_canvas_y << 8) | 0x1);
5131 */
5132 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5133 pic_config->dw_y_adr >> 5);
5134 }
5135 #ifndef LOSLESS_COMPRESS_MODE
5136 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5137 * pic_config->mc_u_v_adr
5138 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5139 */
5140 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5141 pic_config->header_adr >> 5);
5142 #else
5143 if (pic_config->double_write_mode & 0x10) {
5144 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5145 pic_config->dw_u_v_adr >> 5);
5146 }
5147 #endif
5148 }
5149 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5150
5151 /*Zero out canvas registers in IPP -- avoid simulation X*/
5152 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5153 (0 << 8) | (0 << 1) | 1);
5154 for (i = 0; i < 32; i++)
5155 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5156 }
5157
5158
5159 static void dump_pic_list(struct VP9Decoder_s *pbi)
5160 {
5161 struct VP9_Common_s *const cm = &pbi->common;
5162 struct PIC_BUFFER_CONFIG_s *pic_config;
5163 int i;
5164 for (i = 0; i < FRAME_BUFFERS; i++) {
5165 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5166 vp9_print(pbi, 0,
5167 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5168 i,
5169 pic_config->index,
5170 #ifndef MV_USE_FIXED_BUF
5171 pic_config->mv_buf_index,
5172 #else
5173 -1,
5174 #endif
5175 cm->buffer_pool->
5176 frame_bufs[i].ref_count,
5177 pic_config->vf_ref,
5178 pic_config->decode_idx,
5179 pic_config->slice_type,
5180 pic_config->y_crop_width,
5181 pic_config->y_crop_height,
5182 pic_config->cma_alloc_addr
5183 );
5184 }
5185 return;
5186 }
5187
5188 static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5189 {
5190 #ifdef LOSLESS_COMPRESS_MODE
5191 unsigned int data32;
5192 #endif
5193 int losless_comp_header_size, losless_comp_body_size;
5194 struct VP9_Common_s *cm = &pbi->common;
5195 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5196
5197 frame_width = cur_pic_config->y_crop_width;
5198 frame_height = cur_pic_config->y_crop_height;
5199 cur_pic_config->bit_depth = bit_depth;
5200 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5201 losless_comp_header_size =
5202 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5203 cur_pic_config->y_crop_height);
5204 losless_comp_body_size =
5205 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5206 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5207 cur_pic_config->comp_body_size = losless_comp_body_size;
5208 #ifdef LOSLESS_COMPRESS_MODE
5209 data32 = READ_VREG(HEVC_SAO_CTRL5);
5210 if (bit_depth == VPX_BITS_10)
5211 data32 &= ~(1 << 9);
5212 else
5213 data32 |= (1 << 9);
5214
5215 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5216
5217 if (pbi->mmu_enable) {
5218 /*bit[4] : paged_mem_mode*/
5219 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5220 } else {
5221 /*bit[3] smem mdoe*/
5222 if (bit_depth == VPX_BITS_10)
5223 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5224 else
5225 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5226 }
5227 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5228 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5229 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5230 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5231 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5232 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5233 if (get_double_write_mode(pbi) & 0x10)
5234 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5235 #else
5236 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5237 #endif
5238 return 0;
5239 }
5240
5241 static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5242 {
5243 int i;
5244 struct VP9_Common_s *cm = &pbi->common;
5245 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5246 uint8_t scale_enable = 0;
5247
5248 if (debug&VP9_DEBUG_BUFMGR_MORE)
5249 pr_info("config_mc_buffer entered .....\n");
5250
5251 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5252 (0 << 8) | (0 << 1) | 1);
5253 for (i = 0; i < REFS_PER_FRAME; ++i) {
5254 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5255 if (!pic_config)
5256 continue;
5257 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5258 (pic_config->mc_canvas_u_v << 16)
5259 | (pic_config->mc_canvas_u_v << 8)
5260 | pic_config->mc_canvas_y);
5261 if (debug & VP9_DEBUG_BUFMGR_MORE)
5262 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5263 i, pic_config->mc_canvas_u_v,
5264 pic_config->mc_canvas_y);
5265 }
5266 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5267 (16 << 8) | (0 << 1) | 1);
5268 for (i = 0; i < REFS_PER_FRAME; ++i) {
5269 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5270 if (!pic_config)
5271 continue;
5272 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5273 (pic_config->mc_canvas_u_v << 16)
5274 | (pic_config->mc_canvas_u_v << 8)
5275 | pic_config->mc_canvas_y);
5276 }
5277
5278 /*auto_inc start index:0 field:0*/
5279 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5280 /*index 0:last 1:golden 2:altref*/
5281 for (i = 0; i < REFS_PER_FRAME; i++) {
5282 int ref_pic_body_size;
5283 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5284 if (!pic_config)
5285 continue;
5286 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5287 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5288
5289 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5290 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5291 scale_enable |= (1 << i);
5292 }
5293 ref_pic_body_size =
5294 compute_losless_comp_body_size(pic_config->y_crop_width,
5295 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5296 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5297 (pic_config->y_crop_width << 14)
5298 / cur_pic_config->y_crop_width);
5299 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5300 (pic_config->y_crop_height << 14)
5301 / cur_pic_config->y_crop_height);
5302 if (pbi->mmu_enable)
5303 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5304 else
5305 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5306 }
5307 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5308 return 0;
5309 }
5310
5311 static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5312 {
5313 unsigned int data32;
5314
5315 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5316 data32 &= (~(1 << 6));
5317 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5318 }
5319
5320 static void config_mpred_hw(struct VP9Decoder_s *pbi)
5321 {
5322 struct VP9_Common_s *cm = &pbi->common;
5323 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5324 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5325 &cm->prev_frame->buf;
5326
5327 unsigned int data32;
5328 int mpred_curr_lcu_x;
5329 int mpred_curr_lcu_y;
5330 int mpred_mv_rd_end_addr;
5331
5332
5333 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5334 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5335
5336 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5337 mpred_curr_lcu_x = data32 & 0xffff;
5338 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5339
5340 if (debug & VP9_DEBUG_BUFMGR)
5341 pr_info("cur pic_config index %d col pic_config index %d\n",
5342 cur_pic_config->index, last_frame_pic_config->index);
5343 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5344 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5345 pbi->work_space_buf->mpred_above.buf_start);
5346
5347 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5348
5349 data32 &= (~(1 << 6));
5350 data32 |= (cm->use_prev_frame_mvs << 6);
5351 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5352
5353 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5354 cur_pic_config->mpred_mv_wr_start_addr);
5355 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5356
5357 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5358 last_frame_pic_config->mpred_mv_wr_start_addr);
5359 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5360 last_frame_pic_config->mpred_mv_wr_start_addr);
5361 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5362 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5363 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5364 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5365
5366 }
5367
5368 static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5369 {
5370 struct VP9_Common_s *cm = &pbi->common;
5371 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5372
5373 unsigned int data32;
5374 int lcu_size = 64;
5375 int mc_buffer_size_u_v =
5376 pic_config->lcu_total * lcu_size*lcu_size/2;
5377 int mc_buffer_size_u_v_h =
5378 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5379 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5380
5381 if (get_double_write_mode(pbi)) {
5382 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5383 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5384 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5385 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5386 } else {
5387 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5388 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5389 }
5390 if (pbi->mmu_enable)
5391 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5392
5393 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5394 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5395 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5396 */
5397 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5398
5399 data32 = (mc_buffer_size_u_v_h << 16);
5400 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5401
5402 #ifdef VP9_10B_NV21
5403 #ifdef DOS_PROJECT
5404 data32 = READ_VREG(HEVC_SAO_CTRL1);
5405 data32 &= (~0x3000);
5406 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5407 data32 |= (pbi->mem_map_mode << 12);
5408 data32 &= (~0x3);
5409 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5410 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5411 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5412 * [17:16] dw_h0_ctrl
5413 */
5414 data32 = READ_VREG(HEVC_SAO_CTRL5);
5415 /*set them all 0 for H265_NV21 (no down-scale)*/
5416 data32 &= ~(0xff << 16);
5417 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5418 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5419 data32 &= (~0x30);
5420 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5421 data32 |= (pbi->mem_map_mode << 4);
5422 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5423 #else
5424 /*m8baby test1902*/
5425 data32 = READ_VREG(HEVC_SAO_CTRL1);
5426 data32 &= (~0x3000);
5427 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5428 data32 |= (pbi->mem_map_mode << 12);
5429 data32 &= (~0xff0);
5430 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5431 data32 |= 0x880; /*.Big-Endian per 64-bit */
5432 data32 &= (~0x3);
5433 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5434 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5435 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5436 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5437 */
5438 data32 = READ_VREG(HEVC_SAO_CTRL5);
5439 /* set them all 0 for H265_NV21 (no down-scale)*/
5440 data32 &= ~(0xff << 16);
5441 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5442
5443 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5444 data32 &= (~0x30);
5445 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5446 data32 |= (pbi->mem_map_mode << 4);
5447 data32 &= (~0xF);
5448 data32 |= 0x8; /*Big-Endian per 64-bit*/
5449 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5450 #endif
5451 #else
5452 data32 = READ_VREG(HEVC_SAO_CTRL1);
5453 data32 &= (~0x3000);
5454 data32 |= (pbi->mem_map_mode <<
5455 12);
5456
5457 /* [13:12] axi_aformat, 0-Linear,
5458 * 1-32x32, 2-64x32
5459 */
5460 data32 &= (~0xff0);
5461 /* data32 |= 0x670; // Big-Endian per 64-bit */
5462 data32 |= endian; /* Big-Endian per 64-bit */
5463 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5464 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5465 if (get_double_write_mode(pbi) == 0)
5466 data32 |= 0x2; /*disable double write*/
5467 else if (get_double_write_mode(pbi) & 0x10)
5468 data32 |= 0x1; /*disable cm*/
5469 } else { /* >= G12A dw write control */
5470 unsigned int data;
5471 data = READ_VREG(HEVC_DBLK_CFGB);
5472 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5473 if (get_double_write_mode(pbi) == 0)
5474 data |= (0x1 << 8); /*enable first write*/
5475 else if (get_double_write_mode(pbi) & 0x10)
5476 data |= (0x1 << 9); /*double write only*/
5477 else
5478 data |= ((0x1 << 8) |(0x1 << 9));
5479 WRITE_VREG(HEVC_DBLK_CFGB, data);
5480 }
5481
5482 /* swap uv */
5483 if (pbi->is_used_v4l) {
5484 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5485 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5486 data32 &= ~(1 << 8); /* NV21 */
5487 else
5488 data32 |= (1 << 8); /* NV12 */
5489 }
5490
5491 /*
5492 * [31:24] ar_fifo1_axi_thred
5493 * [23:16] ar_fifo0_axi_thred
5494 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5495 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5496 * [11:08] axi_lendian_C
5497 * [07:04] axi_lendian_Y
5498 * [3] reserved
5499 * [2] clk_forceon
5500 * [1] dw_disable:disable double write output
5501 * [0] cm_disable:disable compress output
5502 */
5503 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5504
5505 if (get_double_write_mode(pbi) & 0x10) {
5506 /* [23:22] dw_v1_ctrl
5507 *[21:20] dw_v0_ctrl
5508 *[19:18] dw_h1_ctrl
5509 *[17:16] dw_h0_ctrl
5510 */
5511 data32 = READ_VREG(HEVC_SAO_CTRL5);
5512 /*set them all 0 for H265_NV21 (no down-scale)*/
5513 data32 &= ~(0xff << 16);
5514 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5515 } else {
5516 data32 = READ_VREG(HEVC_SAO_CTRL5);
5517 data32 &= (~(0xff << 16));
5518 if (get_double_write_mode(pbi) == 2 ||
5519 get_double_write_mode(pbi) == 3)
5520 data32 |= (0xff<<16);
5521 else if (get_double_write_mode(pbi) == 4)
5522 data32 |= (0x33<<16);
5523 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5524 }
5525
5526 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5527 data32 &= (~0x30);
5528 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5529 data32 |= (pbi->mem_map_mode <<
5530 4);
5531 data32 &= (~0xF);
5532 data32 |= 0xf; /* valid only when double write only */
5533 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5534
5535 /* swap uv */
5536 if (pbi->is_used_v4l) {
5537 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5538 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5539 data32 |= (1 << 12); /* NV21 */
5540 else
5541 data32 &= ~(1 << 12); /* NV12 */
5542 }
5543
5544 /*
5545 * [3:0] little_endian
5546 * [5:4] address_format 00:linear 01:32x32 10:64x32
5547 * [7:6] reserved
5548 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5549 * [11:10] reserved
5550 * [12] CbCr_byte_swap
5551 * [31:13] reserved
5552 */
5553 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5554 #endif
5555 }
5556
5557 static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5558 {
5559 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5560 unsigned int data32;
5561
5562 if (debug && pbi->init_flag == 0)
5563 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5564 __func__,
5565 buf_spec->ipp.buf_start,
5566 buf_spec->start_adr,
5567 buf_spec->short_term_rps.buf_start,
5568 buf_spec->vps.buf_start,
5569 buf_spec->sps.buf_start,
5570 buf_spec->pps.buf_start,
5571 buf_spec->sao_up.buf_start,
5572 buf_spec->swap_buf.buf_start,
5573 buf_spec->swap_buf2.buf_start,
5574 buf_spec->scalelut.buf_start,
5575 buf_spec->dblk_para.buf_start,
5576 buf_spec->dblk_data.buf_start);
5577
5578 if (mask & HW_MASK_FRONT) {
5579 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5580 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5581
5582 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5583 buf_spec->short_term_rps.buf_start);
5584 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5585 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5586 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5587 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5588 buf_spec->swap_buf.buf_start);
5589 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5590 buf_spec->swap_buf2.buf_start);
5591 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5592
5593 }
5594
5595 if (mask & HW_MASK_BACK) {
5596 #ifdef LOSLESS_COMPRESS_MODE
5597 int losless_comp_header_size =
5598 compute_losless_comp_header_size(pbi->init_pic_w,
5599 pbi->init_pic_h);
5600 int losless_comp_body_size =
5601 compute_losless_comp_body_size(pbi->init_pic_w,
5602 pbi->init_pic_h, buf_alloc_depth == 10);
5603 #endif
5604 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5605 buf_spec->ipp.buf_start);
5606 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5607 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5608 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5609 /* cfg_addr_adp*/
5610 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5611 if (debug & VP9_DEBUG_BUFMGR_MORE)
5612 pr_info("Write HEVC_DBLK_CFGE\n");
5613 }
5614 /* cfg_p_addr */
5615 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5616 /* cfg_d_addr */
5617 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5618
5619 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5620 /*
5621 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5622 * data32 = data32 * 2;
5623 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5624 * data32 = data32 * 2;
5625 */
5626 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5627 }
5628 #ifdef LOSLESS_COMPRESS_MODE
5629 if (pbi->mmu_enable) {
5630 /*bit[4] : paged_mem_mode*/
5631 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5632 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5633 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5634 } else {
5635 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5636 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5637 */
5638 /*bit[3] smem mdoe*/
5639 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5640 /*bit[3] smem mdoe*/
5641 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5642 (losless_comp_body_size >> 5));
5643 }
5644 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5645 (losless_comp_body_size >> 5));*/
5646 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5647 (0xff<<20) | (0xff<<10) | 0xff);*/
5648 /*8-bit mode */
5649 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5650 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5651 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5652 if (get_double_write_mode(pbi) & 0x10)
5653 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5654 #else
5655 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5656 #endif
5657
5658 if (pbi->mmu_enable) {
5659 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5660 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5661 + buf_spec->mmu_vbh.buf_size/2);
5662 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5663 /*data32 |= 0x1;*/
5664 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5665
5666 /* use HEVC_CM_HEADER_START_ADDR */
5667 data32 = READ_VREG(HEVC_SAO_CTRL5);
5668 data32 |= (1<<10);
5669 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5670 }
5671
5672 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5673
5674 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5675 /**/
5676 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5677 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5678 if (pbi->mmu_enable) {
5679 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5680 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5681 else
5682 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5683 }
5684 }
5685 }
5686
5687
5688 #ifdef VP9_LPF_LVL_UPDATE
5689 /*
5690 * Defines, declarations, sub-functions for vp9 de-block loop
5691 filter Thr/Lvl table update
5692 * - struct segmentation is for loop filter only (removed something)
5693 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5694 be instantiated in C_Entry
5695 * - vp9_loop_filter_init run once before decoding start
5696 * - vp9_loop_filter_frame_init run before every frame decoding start
5697 * - set video format to VP9 is in vp9_loop_filter_init
5698 */
5699 #define MAX_LOOP_FILTER 63
5700 #define MAX_REF_LF_DELTAS 4
5701 #define MAX_MODE_LF_DELTAS 2
5702 /*#define INTRA_FRAME 0*/
5703 /*#define LAST_FRAME 1*/
5704 /*#define MAX_REF_FRAMES 4*/
5705 #define SEGMENT_DELTADATA 0
5706 #define SEGMENT_ABSDATA 1
5707 #define MAX_SEGMENTS 8
5708 /*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5709 /*no use for loop filter, if this struct for common use, pls add it back*/
5710 /*#define PREDICTION_PROBS 3*/
5711 /* no use for loop filter, if this struct for common use, pls add it back*/
5712
5713 enum SEG_LVL_FEATURES {
5714 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5715 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5716 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5717 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5718 SEG_LVL_MAX = 4 /*Number of features supported*/
5719 };
5720
5721 struct segmentation {
5722 uint8_t enabled;
5723 uint8_t update_map;
5724 uint8_t update_data;
5725 uint8_t abs_delta;
5726 uint8_t temporal_update;
5727
5728 /*no use for loop filter, if this struct
5729 *for common use, pls add it back
5730 */
5731 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5732 /* no use for loop filter, if this struct
5733 * for common use, pls add it back
5734 */
5735 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5736
5737 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5738 unsigned int feature_mask[MAX_SEGMENTS];
5739 };
5740
5741 struct loop_filter_thresh {
5742 uint8_t mblim;
5743 uint8_t lim;
5744 uint8_t hev_thr;
5745 };
5746
5747 struct loop_filter_info_n {
5748 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5749 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5750 };
5751
5752 struct loopfilter {
5753 int filter_level;
5754
5755 int sharpness_level;
5756 int last_sharpness_level;
5757
5758 uint8_t mode_ref_delta_enabled;
5759 uint8_t mode_ref_delta_update;
5760
5761 /*0 = Intra, Last, GF, ARF*/
5762 signed char ref_deltas[MAX_REF_LF_DELTAS];
5763 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5764
5765 /*0 = ZERO_MV, MV*/
5766 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5767 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5768 };
5769
5770 static int vp9_clamp(int value, int low, int high)
5771 {
5772 return value < low ? low : (value > high ? high : value);
5773 }
5774
5775 int segfeature_active(struct segmentation *seg,
5776 int segment_id,
5777 enum SEG_LVL_FEATURES feature_id) {
5778 return seg->enabled &&
5779 (seg->feature_mask[segment_id] & (1 << feature_id));
5780 }
5781
5782 int get_segdata(struct segmentation *seg, int segment_id,
5783 enum SEG_LVL_FEATURES feature_id) {
5784 return seg->feature_data[segment_id][feature_id];
5785 }
5786
5787 static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5788 int sharpness_lvl)
5789 {
5790 int lvl;
5791 /*For each possible value for the loop filter fill out limits*/
5792 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5793 /*Set loop filter parameters that control sharpness.*/
5794 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5795 (sharpness_lvl > 4));
5796
5797 if (sharpness_lvl > 0) {
5798 if (block_inside_limit > (9 - sharpness_lvl))
5799 block_inside_limit = (9 - sharpness_lvl);
5800 }
5801
5802 if (block_inside_limit < 1)
5803 block_inside_limit = 1;
5804
5805 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5806 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5807 block_inside_limit);
5808 }
5809 }
5810
5811 /*instantiate this function once when decode is started*/
5812 void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5813 {
5814 struct loop_filter_info_n *lfi = pbi->lfi;
5815 struct loopfilter *lf = pbi->lf;
5816 struct segmentation *seg_4lf = pbi->seg_4lf;
5817 int i;
5818 unsigned int data32;
5819
5820 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5821 memset(lf, 0, sizeof(struct loopfilter));
5822 memset(seg_4lf, 0, sizeof(struct segmentation));
5823 lf->sharpness_level = 0; /*init to 0 */
5824 /*init limits for given sharpness*/
5825 vp9_update_sharpness(lfi, lf->sharpness_level);
5826 lf->last_sharpness_level = lf->sharpness_level;
5827 /*init hev threshold const vectors (actually no use)
5828 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5829 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5830 */
5831
5832 /*Write to register*/
5833 for (i = 0; i < 32; i++) {
5834 unsigned int thr;
5835
5836 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5837 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5838 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5839 (lfi->lfthr[i * 2].mblim & 0xff);
5840 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5841 }
5842
5843 /*video format is VP9*/
5844 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5845 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5846 (0x3 << 12) | // (dw fifo thres r or b)
5847 (0x3 << 10) | // (dw fifo thres not r/b)
5848 (0x3 << 8) | // 1st/2nd write both enable
5849 (0x1 << 0); // vp9 video format
5850 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5851 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5852 (0x1 << 0); /*vp9 video format*/
5853 } else
5854 data32 = 0x40400001;
5855
5856 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5857 if (debug & VP9_DEBUG_BUFMGR_MORE)
5858 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5859 }
5860 /* perform this function per frame*/
5861 void vp9_loop_filter_frame_init(struct segmentation *seg,
5862 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5863 int default_filt_lvl) {
5864 int i;
5865 int seg_id;
5866 /*n_shift is the multiplier for lf_deltas
5867 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5868 *2 when filter_lvl is between 32 and 63
5869 */
5870 const int scale = 1 << (default_filt_lvl >> 5);
5871
5872 /*update limits if sharpness has changed*/
5873 if (lf->last_sharpness_level != lf->sharpness_level) {
5874 vp9_update_sharpness(lfi, lf->sharpness_level);
5875 lf->last_sharpness_level = lf->sharpness_level;
5876
5877 /*Write to register*/
5878 for (i = 0; i < 32; i++) {
5879 unsigned int thr;
5880
5881 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5882 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5883 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5884 | (lfi->lfthr[i * 2].mblim & 0xff);
5885 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5886 }
5887 }
5888
5889 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5890 int lvl_seg = default_filt_lvl;
5891
5892 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5893 const int data = get_segdata(seg, seg_id,
5894 SEG_LVL_ALT_LF);
5895 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5896 data : default_filt_lvl + data,
5897 0, MAX_LOOP_FILTER);
5898 #ifdef DBG_LF_PRINT
5899 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5900 #endif
5901 }
5902
5903 if (!lf->mode_ref_delta_enabled) {
5904 /*we could get rid of this if we assume that deltas are set to
5905 *zero when not in use; encoder always uses deltas
5906 */
5907 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5908 } else {
5909 int ref, mode;
5910 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5911 * scale;
5912 #ifdef DBG_LF_PRINT
5913 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5914 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5915 #endif
5916 lfi->lvl[seg_id][INTRA_FRAME][0] =
5917 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5918
5919 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5920 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5921 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5922 /*MAX_MODE_LF_DELTAS = 2*/
5923 const int inter_lvl =
5924 lvl_seg + lf->ref_deltas[ref] * scale
5925 + lf->mode_deltas[mode] * scale;
5926 #ifdef DBG_LF_PRINT
5927 #endif
5928 lfi->lvl[seg_id][ref][mode] =
5929 vp9_clamp(inter_lvl, 0,
5930 MAX_LOOP_FILTER);
5931 }
5932 }
5933 }
5934 }
5935
5936 #ifdef DBG_LF_PRINT
5937 /*print out thr/lvl table per frame*/
5938 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5939 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5940 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5941 lfi->lfthr[i].lim);
5942 }
5943 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5944 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5945 seg_id, lfi->lvl[seg_id][0][0],
5946 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5947 lfi->lvl[seg_id][3][0]);
5948 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5949 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5950 lfi->lvl[seg_id][3][1]);
5951 }
5952 #endif
5953
5954 /*Write to register */
5955 for (i = 0; i < 16; i++) {
5956 unsigned int level;
5957
5958 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5959 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5960 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5961 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5962 if (!default_filt_lvl)
5963 level = 0;
5964 WRITE_VREG(HEVC_DBLK_CFGA, level);
5965 }
5966 }
5967 /* VP9_LPF_LVL_UPDATE */
5968 #endif
5969
5970 static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5971 {
5972 unsigned int data32;
5973 int i;
5974 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5975 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5976 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5977 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5978 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5979 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5980 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5981 0x7C00
5982 };
5983 #if 0
5984 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5985 /* Set MCR fetch priorities*/
5986 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5987 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5988 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5989 }
5990 #endif
5991 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5992 pr_info("%s\n", __func__);*/
5993 if (mask & HW_MASK_FRONT) {
5994 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5995 #if 1
5996 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5997 data32 &= ~(7 << 29);
5998 data32 |= (3 << 29);
5999 #endif
6000 data32 = data32 |
6001 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
6002 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
6003 (1 << 7) |/*dec_done_int_cpu_enable*/
6004 (1 << 4) |/*startcode_found_int_cpu_enable*/
6005 (0 << 3) |/*startcode_found_int_amrisc_enable*/
6006 (1 << 0) /*parser_int_enable*/
6007 ;
6008 #ifdef SUPPORT_FB_DECODING
6009 #ifndef FB_DECODING_TEST_SCHEDULE
6010 /*fed_fb_slice_done_int_cpu_enable*/
6011 if (pbi->used_stage_buf_num > 0)
6012 data32 |= (1 << 10);
6013 #endif
6014 #endif
6015 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
6016
6017 data32 = READ_VREG(HEVC_SHIFT_STATUS);
6018 data32 = data32 |
6019 (0 << 1) |/*emulation_check_off VP9
6020 do not have emulation*/
6021 (1 << 0)/*startcode_check_on*/
6022 ;
6023 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
6024 WRITE_VREG(HEVC_SHIFT_CONTROL,
6025 (0 << 14) | /*disable_start_code_protect*/
6026 (1 << 10) | /*length_zero_startcode_en for VP9*/
6027 (1 << 9) | /*length_valid_startcode_en for VP9*/
6028 (3 << 6) | /*sft_valid_wr_position*/
6029 (2 << 4) | /*emulate_code_length_sub_1*/
6030 (3 << 1) | /*start_code_length_sub_1
6031 VP9 use 0x00000001 as startcode (4 Bytes)*/
6032 (1 << 0) /*stream_shift_enable*/
6033 );
6034
6035 WRITE_VREG(HEVC_CABAC_CONTROL,
6036 (1 << 0)/*cabac_enable*/
6037 );
6038
6039 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6040 (1 << 0)/* hevc_parser_core_clk_en*/
6041 );
6042
6043
6044 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6045
6046 }
6047
6048 if (mask & HW_MASK_BACK) {
6049 /*Initial IQIT_SCALELUT memory
6050 -- just to avoid X in simulation*/
6051
6052 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6053 for (i = 0; i < 1024; i++)
6054 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6055 }
6056
6057 if (mask & HW_MASK_FRONT) {
6058 u32 decode_mode;
6059 #ifdef ENABLE_SWAP_TEST
6060 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6061 #else
6062 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6063 #endif
6064 #ifdef MULTI_INSTANCE_SUPPORT
6065 if (!pbi->m_ins_flag) {
6066 if (pbi->low_latency_flag)
6067 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6068 else
6069 decode_mode = DECODE_MODE_SINGLE;
6070 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6071 decode_mode = pbi->no_head ?
6072 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6073 DECODE_MODE_MULTI_FRAMEBASE;
6074 else
6075 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6076 #ifdef SUPPORT_FB_DECODING
6077 #ifndef FB_DECODING_TEST_SCHEDULE
6078 if (pbi->used_stage_buf_num > 0)
6079 decode_mode |= (0x01 << 24);
6080 #endif
6081 #endif
6082 WRITE_VREG(DECODE_MODE, decode_mode);
6083 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6084 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6085 #else
6086 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6087 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6088 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6089 #endif
6090 /*Send parser_cmd*/
6091 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6092 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6093 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6094 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6095 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6096 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6097
6098
6099 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6100 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6101 (1 << 5) | /*parser_sao_if_en*/
6102 (1 << 2) | /*parser_mpred_if_en*/
6103 (1 << 0) /*parser_scaler_if_en*/
6104 );
6105 }
6106
6107 if (mask & HW_MASK_BACK) {
6108 /*Changed to Start MPRED in microcode*/
6109 /*
6110 pr_info("[test.c] Start MPRED\n");
6111 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6112 (1<<31)
6113 );
6114 */
6115 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6116 (0 << 1) | /*enable ipp*/
6117 (1 << 0) /*software reset ipp and mpp*/
6118 );
6119 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6120 (1 << 1) | /*enable ipp*/
6121 (0 << 0) /*software reset ipp and mpp*/
6122 );
6123 if (get_double_write_mode(pbi) & 0x10) {
6124 /*Enable NV21 reference read mode for MC*/
6125 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6126 }
6127
6128 /*Initialize mcrcc and decomp perf counters*/
6129 if (mcrcc_cache_alg_flag &&
6130 pbi->init_flag == 0) {
6131 mcrcc_perfcount_reset();
6132 decomp_perfcount_reset();
6133 }
6134 }
6135 return;
6136 }
6137
6138
6139 #ifdef CONFIG_HEVC_CLK_FORCED_ON
6140 static void config_vp9_clk_forced_on(void)
6141 {
6142 unsigned int rdata32;
6143 /*IQIT*/
6144 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6145 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6146
6147 /* DBLK*/
6148 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6149 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6150
6151 /* SAO*/
6152 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6153 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6154
6155 /*MPRED*/
6156 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6157 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6158
6159 /* PARSER*/
6160 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6161 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6162 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6163 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6164 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6165 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6166 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6167 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6168 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6169 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6170 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6171 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6172 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6173
6174 /*IPP*/
6175 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6176 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6177
6178 /* MCRCC*/
6179 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6180 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6181 }
6182 #endif
6183
6184
6185 #ifdef MCRCC_ENABLE
6186 static void dump_hit_rate(struct VP9Decoder_s *pbi)
6187 {
6188 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6189 mcrcc_get_hitrate(pbi->m_ins_flag);
6190 decomp_get_hitrate();
6191 decomp_get_comprate();
6192 }
6193 }
6194
6195 static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6196 {
6197 unsigned int rdata32;
6198 unsigned short is_inter;
6199 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6200 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6201 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6202 (!pbi->common.intra_only)) ? 1 : 0;
6203 if (!is_inter) { /* I-PIC*/
6204 /*remove reset -- disables clock*/
6205 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6206 return;
6207 }
6208
6209 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6210 mcrcc_get_hitrate(pbi->m_ins_flag);
6211 decomp_get_hitrate();
6212 decomp_get_comprate();
6213 }
6214
6215 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6216 (0 << 8) | (1 << 1) | 0);
6217 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6218 rdata32 = rdata32 & 0xffff;
6219 rdata32 = rdata32 | (rdata32 << 16);
6220 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6221 /*Programme canvas1 */
6222 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6223 rdata32 = rdata32 & 0xffff;
6224 rdata32 = rdata32 | (rdata32 << 16);
6225 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6226 /*enable mcrcc progressive-mode*/
6227 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6228 }
6229
6230 static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6231 {
6232 u32 curr_picnum = -1;
6233 u32 lastref_picnum = -1;
6234 u32 goldenref_picnum = -1;
6235 u32 altref_picnum = -1;
6236
6237 u32 lastref_delta_picnum;
6238 u32 goldenref_delta_picnum;
6239 u32 altref_delta_picnum;
6240
6241 u32 rdata32;
6242
6243 u32 lastcanvas;
6244 u32 goldencanvas;
6245 u32 altrefcanvas;
6246
6247 u16 is_inter;
6248 u16 lastref_inref;
6249 u16 goldenref_inref;
6250 u16 altref_inref;
6251
6252 u32 refcanvas_array[3], utmp;
6253 int deltapicnum_array[3], tmp;
6254
6255 struct VP9_Common_s *cm = &pbi->common;
6256 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6257 = &cm->cur_frame->buf;
6258 curr_picnum = cur_pic_config->decode_idx;
6259 if (cm->frame_refs[0].buf)
6260 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6261 if (cm->frame_refs[1].buf)
6262 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6263 if (cm->frame_refs[2].buf)
6264 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6265
6266 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6267 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6268 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6269 (goldenref_picnum - curr_picnum) :
6270 (curr_picnum - goldenref_picnum);
6271 altref_delta_picnum =
6272 (altref_picnum >= curr_picnum) ?
6273 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6274
6275 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6276 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6277 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6278
6279 if (debug & VP9_DEBUG_CACHE)
6280 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6281 __func__, lastref_inref, goldenref_inref, altref_inref);
6282
6283 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6284
6285 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6286 && (!pbi->common.intra_only)) ? 1 : 0;
6287
6288 if (!is_inter) { /* I-PIC */
6289 /* remove reset -- disables clock */
6290 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6291 return;
6292 }
6293
6294 if (!pbi->m_ins_flag)
6295 dump_hit_rate(pbi);
6296
6297 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6298 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6299 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6300 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6301
6302 if (debug & VP9_DEBUG_CACHE)
6303 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6304 lastcanvas, goldencanvas, altrefcanvas);
6305
6306 altref_inref = ((altref_inref == 1) &&
6307 (altrefcanvas != (goldenref_inref
6308 ? goldencanvas : 0xffffffff)) &&
6309 (altrefcanvas != (lastref_inref ?
6310 lastcanvas : 0xffffffff))) ? 1 : 0;
6311 goldenref_inref = ((goldenref_inref == 1) &&
6312 (goldencanvas != (lastref_inref ?
6313 lastcanvas : 0xffffffff))) ? 1 : 0;
6314 if (debug & VP9_DEBUG_CACHE)
6315 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6316 lastref_inref, goldenref_inref, altref_inref);
6317
6318 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6319 goldenref_delta_picnum = goldenref_inref ?
6320 goldenref_delta_picnum : 0x7fffffff;
6321 lastref_delta_picnum = lastref_inref ?
6322 lastref_delta_picnum : 0x7fffffff;
6323 if (debug & VP9_DEBUG_CACHE)
6324 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6325 lastref_delta_picnum, goldenref_delta_picnum,
6326 altref_delta_picnum);
6327 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6328
6329 refcanvas_array[0] = lastcanvas;
6330 refcanvas_array[1] = goldencanvas;
6331 refcanvas_array[2] = altrefcanvas;
6332
6333 deltapicnum_array[0] = lastref_delta_picnum;
6334 deltapicnum_array[1] = goldenref_delta_picnum;
6335 deltapicnum_array[2] = altref_delta_picnum;
6336
6337 /* sort0 : 2-to-1 */
6338 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6339 utmp = refcanvas_array[2];
6340 refcanvas_array[2] = refcanvas_array[1];
6341 refcanvas_array[1] = utmp;
6342 tmp = deltapicnum_array[2];
6343 deltapicnum_array[2] = deltapicnum_array[1];
6344 deltapicnum_array[1] = tmp;
6345 }
6346 /* sort1 : 1-to-0 */
6347 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6348 utmp = refcanvas_array[1];
6349 refcanvas_array[1] = refcanvas_array[0];
6350 refcanvas_array[0] = utmp;
6351 tmp = deltapicnum_array[1];
6352 deltapicnum_array[1] = deltapicnum_array[0];
6353 deltapicnum_array[0] = tmp;
6354 }
6355 /* sort2 : 2-to-1 */
6356 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6357 utmp = refcanvas_array[2]; refcanvas_array[2] =
6358 refcanvas_array[1]; refcanvas_array[1] = utmp;
6359 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6360 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6361 }
6362 if (mcrcc_cache_alg_flag ==
6363 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6364 /* lowest delta_picnum */
6365 rdata32 = refcanvas_array[0];
6366 rdata32 = rdata32 & 0xffff;
6367 rdata32 = rdata32 | (rdata32 << 16);
6368 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6369
6370 /* 2nd-lowest delta_picnum */
6371 rdata32 = refcanvas_array[1];
6372 rdata32 = rdata32 & 0xffff;
6373 rdata32 = rdata32 | (rdata32 << 16);
6374 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6375 } else {
6376 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6377 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6378 (0 << 8) | (1<<1) | 0);
6379 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6380 rdata32 = rdata32 & 0xffff;
6381 rdata32 = rdata32 | (rdata32 << 16);
6382 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6383
6384 /* Programme canvas1 */
6385 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6386 rdata32 = rdata32 & 0xffff;
6387 rdata32 = rdata32 | (rdata32 << 16);
6388 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6389 }
6390
6391 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6392 return;
6393 }
6394
6395 #endif
6396
6397
6398 static void free_lf_buf(struct VP9Decoder_s *pbi)
6399 {
6400 if (pbi->lfi)
6401 vfree(pbi->lfi);
6402 if (pbi->lf)
6403 vfree(pbi->lf);
6404 if (pbi->seg_4lf)
6405 vfree(pbi->seg_4lf);
6406 pbi->lfi = NULL;
6407 pbi->lf = NULL;
6408 pbi->seg_4lf = NULL;
6409 }
6410
6411 static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6412 {
6413 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6414 pbi->lf = vmalloc(sizeof(struct loopfilter));
6415 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6416 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6417 free_lf_buf(pbi);
6418 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6419 return -1;
6420 }
6421 return 0;
6422 }
6423
6424 static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6425 {
6426 pbi->rpm_ptr = NULL;
6427 pbi->lmem_ptr = NULL;
6428 if (pbi->rpm_addr) {
6429 dma_free_coherent(amports_get_dma_device(),
6430 RPM_BUF_SIZE,
6431 pbi->rpm_addr,
6432 pbi->rpm_phy_addr);
6433 pbi->rpm_addr = NULL;
6434 }
6435 if (pbi->lmem_addr) {
6436 if (pbi->lmem_phy_addr)
6437 dma_free_coherent(amports_get_dma_device(),
6438 LMEM_BUF_SIZE, pbi->lmem_addr,
6439 pbi->lmem_phy_addr);
6440 pbi->lmem_addr = NULL;
6441 }
6442 if (pbi->prob_buffer_addr) {
6443 if (pbi->prob_buffer_phy_addr)
6444 dma_free_coherent(amports_get_dma_device(),
6445 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6446 pbi->prob_buffer_phy_addr);
6447
6448 pbi->prob_buffer_addr = NULL;
6449 }
6450 if (pbi->count_buffer_addr) {
6451 if (pbi->count_buffer_phy_addr)
6452 dma_free_coherent(amports_get_dma_device(),
6453 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6454 pbi->count_buffer_phy_addr);
6455
6456 pbi->count_buffer_addr = NULL;
6457 }
6458 if (pbi->mmu_enable) {
6459 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6460 if (pbi->frame_mmu_map_addr) {
6461 if (pbi->frame_mmu_map_phy_addr)
6462 dma_free_coherent(amports_get_dma_device(),
6463 mmu_map_size,
6464 pbi->frame_mmu_map_addr,
6465 pbi->frame_mmu_map_phy_addr);
6466 pbi->frame_mmu_map_addr = NULL;
6467 }
6468 }
6469 #ifdef SUPPORT_FB_DECODING
6470 if (pbi->stage_mmu_map_addr) {
6471 if (pbi->stage_mmu_map_phy_addr)
6472 dma_free_coherent(amports_get_dma_device(),
6473 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6474 pbi->stage_mmu_map_addr,
6475 pbi->stage_mmu_map_phy_addr);
6476 pbi->stage_mmu_map_addr = NULL;
6477 }
6478
6479 uninit_stage_buf(pbi);
6480 #endif
6481
6482 #ifdef VP9_LPF_LVL_UPDATE
6483 free_lf_buf(pbi);
6484 #endif
6485 if (pbi->gvs)
6486 vfree(pbi->gvs);
6487 pbi->gvs = NULL;
6488 }
6489
6490 static int vp9_local_init(struct VP9Decoder_s *pbi)
6491 {
6492 int ret = -1;
6493 /*int losless_comp_header_size, losless_comp_body_size;*/
6494
6495 struct BuffInfo_s *cur_buf_info = NULL;
6496
6497 memset(&pbi->param, 0, sizeof(union param_u));
6498 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6499 #ifdef MULTI_INSTANCE_SUPPORT
6500 cur_buf_info = &pbi->work_space_buf_store;
6501
6502 if (vdec_is_support_4k()) {
6503 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6504 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6505 sizeof(struct BuffInfo_s));
6506 } else
6507 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6508 sizeof(struct BuffInfo_s));
6509 } else
6510 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6511 sizeof(struct BuffInfo_s));
6512
6513 cur_buf_info->start_adr = pbi->buf_start;
6514 if (!pbi->mmu_enable)
6515 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6516
6517 #else
6518 /*! MULTI_INSTANCE_SUPPORT*/
6519 if (vdec_is_support_4k()) {
6520 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6521 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6522 else
6523 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6524 } else
6525 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6526
6527 #endif
6528
6529 init_buff_spec(pbi, cur_buf_info);
6530 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6531
6532 if (!vdec_is_support_4k()
6533 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6534 buf_alloc_width = 1920;
6535 buf_alloc_height = 1088;
6536 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6537 pbi->max_pic_w = 1920;
6538 pbi->max_pic_h = 1088;
6539 }
6540 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6541 buf_alloc_width = 8192;
6542 buf_alloc_height = 4608;
6543 }
6544 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6545 (buf_alloc_width ? buf_alloc_width :
6546 (pbi->vvp9_amstream_dec_info.width ?
6547 pbi->vvp9_amstream_dec_info.width :
6548 pbi->work_space_buf->max_width));
6549 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6550 (buf_alloc_height ? buf_alloc_height :
6551 (pbi->vvp9_amstream_dec_info.height ?
6552 pbi->vvp9_amstream_dec_info.height :
6553 pbi->work_space_buf->max_height));
6554
6555 /* video is not support unaligned with 64 in tl1
6556 ** vdec canvas mode will be linear when dump yuv is set
6557 */
6558 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6559 (pbi->double_write_mode != 0) &&
6560 (((pbi->max_pic_w % 64) != 0) ||
6561 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6562 if (hw_to_vdec(pbi)->canvas_mode !=
6563 CANVAS_BLKMODE_LINEAR)
6564 pbi->mem_map_mode = 2;
6565 else {
6566 pbi->mem_map_mode = 0;
6567 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6568 }
6569 }
6570
6571 #ifndef MV_USE_FIXED_BUF
6572 if (init_mv_buf_list(pbi) < 0) {
6573 pr_err("%s: init_mv_buf_list fail\n", __func__);
6574 return -1;
6575 }
6576 #endif
6577 if (pbi->save_buffer_mode)
6578 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6579 else {
6580 if (pbi->is_used_v4l)
6581 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6582 else
6583 pbi->used_buf_num = max_buf_num;
6584 }
6585
6586 if (pbi->used_buf_num > MAX_BUF_NUM)
6587 pbi->used_buf_num = MAX_BUF_NUM;
6588 if (pbi->used_buf_num > FRAME_BUFFERS)
6589 pbi->used_buf_num = FRAME_BUFFERS;
6590
6591 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6592 & 0x40) >> 6;
6593
6594 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6595 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6596 RPM_BUF_SIZE,
6597 &pbi->rpm_phy_addr, GFP_KERNEL);
6598 if (pbi->rpm_addr == NULL) {
6599 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6600 return -1;
6601 }
6602
6603 pbi->rpm_ptr = pbi->rpm_addr;
6604 }
6605
6606 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6607 LMEM_BUF_SIZE,
6608 &pbi->lmem_phy_addr, GFP_KERNEL);
6609 if (pbi->lmem_addr == NULL) {
6610 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6611 return -1;
6612 }
6613 pbi->lmem_ptr = pbi->lmem_addr;
6614
6615 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6616 PROB_BUF_SIZE,
6617 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6618 if (pbi->prob_buffer_addr == NULL) {
6619 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6620 return -1;
6621 }
6622 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6623 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6624 COUNT_BUF_SIZE,
6625 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6626 if (pbi->count_buffer_addr == NULL) {
6627 pr_err("%s: failed to alloc count_buffer\n", __func__);
6628 return -1;
6629 }
6630 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6631
6632 if (pbi->mmu_enable) {
6633 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6634 pbi->frame_mmu_map_addr =
6635 dma_alloc_coherent(amports_get_dma_device(),
6636 mmu_map_size,
6637 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6638 if (pbi->frame_mmu_map_addr == NULL) {
6639 pr_err("%s: failed to alloc count_buffer\n", __func__);
6640 return -1;
6641 }
6642 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6643 }
6644 #ifdef SUPPORT_FB_DECODING
6645 if (pbi->m_ins_flag && stage_buf_num > 0) {
6646 pbi->stage_mmu_map_addr =
6647 dma_alloc_coherent(amports_get_dma_device(),
6648 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6649 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6650 if (pbi->stage_mmu_map_addr == NULL) {
6651 pr_err("%s: failed to alloc count_buffer\n", __func__);
6652 return -1;
6653 }
6654 memset(pbi->stage_mmu_map_addr,
6655 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6656
6657 init_stage_buf(pbi);
6658 }
6659 #endif
6660
6661 ret = 0;
6662 return ret;
6663 }
6664
6665 /********************************************
6666 * Mailbox command
6667 ********************************************/
6668 #define CMD_FINISHED 0
6669 #define CMD_ALLOC_VIEW 1
6670 #define CMD_FRAME_DISPLAY 3
6671 #define CMD_DEBUG 10
6672
6673
6674 #define DECODE_BUFFER_NUM_MAX 32
6675 #define DISPLAY_BUFFER_NUM 6
6676
6677 #define video_domain_addr(adr) (adr&0x7fffffff)
6678 #define DECODER_WORK_SPACE_SIZE 0x800000
6679
6680 #define spec2canvas(x) \
6681 (((x)->uv_canvas_index << 16) | \
6682 ((x)->uv_canvas_index << 8) | \
6683 ((x)->y_canvas_index << 0))
6684
6685
6686 static void set_canvas(struct VP9Decoder_s *pbi,
6687 struct PIC_BUFFER_CONFIG_s *pic_config)
6688 {
6689 struct vdec_s *vdec = hw_to_vdec(pbi);
6690 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6691 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6692 int blkmode = pbi->mem_map_mode;
6693 /*CANVAS_BLKMODE_64X32*/
6694 if (pic_config->double_write_mode) {
6695 canvas_w = pic_config->y_crop_width /
6696 get_double_write_ratio(pbi,
6697 pic_config->double_write_mode);
6698 canvas_h = pic_config->y_crop_height /
6699 get_double_write_ratio(pbi,
6700 pic_config->double_write_mode);
6701
6702 if (pbi->mem_map_mode == 0)
6703 canvas_w = ALIGN(canvas_w, 32);
6704 else
6705 canvas_w = ALIGN(canvas_w, 64);
6706 canvas_h = ALIGN(canvas_h, 32);
6707
6708 if (vdec->parallel_dec == 1) {
6709 if (pic_config->y_canvas_index == -1)
6710 pic_config->y_canvas_index =
6711 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6712 if (pic_config->uv_canvas_index == -1)
6713 pic_config->uv_canvas_index =
6714 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6715 } else {
6716 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6717 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6718 }
6719
6720 canvas_config_ex(pic_config->y_canvas_index,
6721 pic_config->dw_y_adr, canvas_w, canvas_h,
6722 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6723 canvas_config_ex(pic_config->uv_canvas_index,
6724 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6725 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6726
6727 #ifdef MULTI_INSTANCE_SUPPORT
6728 pic_config->canvas_config[0].phy_addr =
6729 pic_config->dw_y_adr;
6730 pic_config->canvas_config[0].width =
6731 canvas_w;
6732 pic_config->canvas_config[0].height =
6733 canvas_h;
6734 pic_config->canvas_config[0].block_mode =
6735 blkmode;
6736 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6737
6738 pic_config->canvas_config[1].phy_addr =
6739 pic_config->dw_u_v_adr;
6740 pic_config->canvas_config[1].width =
6741 canvas_w;
6742 pic_config->canvas_config[1].height =
6743 canvas_h;
6744 pic_config->canvas_config[1].block_mode =
6745 blkmode;
6746 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6747 #endif
6748 }
6749 }
6750
6751
6752 static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6753 {
6754 unsigned int ar;
6755 vf->duration = pbi->frame_dur;
6756 vf->duration_pulldown = 0;
6757 vf->flag = 0;
6758 vf->prop.master_display_colour = pbi->vf_dp;
6759 vf->signal_type = pbi->video_signal_type;
6760 if (vf->compWidth && vf->compHeight)
6761 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6762 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6763 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6764
6765 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6766 struct aml_vdec_hdr_infos hdr;
6767 struct aml_vcodec_ctx *ctx =
6768 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6769
6770 memset(&hdr, 0, sizeof(hdr));
6771 hdr.signal_type = vf->signal_type;
6772 hdr.color_parms = pbi->vf_dp;
6773 vdec_v4l_set_hdr_infos(ctx, &hdr);
6774 }
6775 }
6776
6777 static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6778 {
6779 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6780
6781 states->vf_pool_size = VF_POOL_SIZE;
6782 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6783 states->buf_avail_num = kfifo_len(&pbi->display_q);
6784
6785 if (step == 2)
6786 states->buf_avail_num = 0;
6787 return 0;
6788 }
6789
6790 static struct vframe_s *vvp9_vf_peek(void *op_arg)
6791 {
6792 struct vframe_s *vf[2] = {0, 0};
6793 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6794
6795 if (step == 2)
6796 return NULL;
6797
6798 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6799 if (vf[1]) {
6800 vf[0]->next_vf_pts_valid = true;
6801 vf[0]->next_vf_pts = vf[1]->pts;
6802 } else
6803 vf[0]->next_vf_pts_valid = false;
6804 return vf[0];
6805 }
6806
6807 return NULL;
6808 }
6809
6810 static struct vframe_s *vvp9_vf_get(void *op_arg)
6811 {
6812 struct vframe_s *vf;
6813 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6814
6815 if (step == 2)
6816 return NULL;
6817 else if (step == 1)
6818 step = 2;
6819
6820 if (kfifo_get(&pbi->display_q, &vf)) {
6821 struct vframe_s *next_vf;
6822 uint8_t index = vf->index & 0xff;
6823 if (index < pbi->used_buf_num ||
6824 (vf->type & VIDTYPE_V4L_EOS)) {
6825 vf->index_disp = pbi->vf_get_count;
6826 pbi->vf_get_count++;
6827 if (debug & VP9_DEBUG_BUFMGR)
6828 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6829 __func__, vf->type,
6830 vf->width, vf->height,
6831 vf->pts,
6832 vf->pts_us64);
6833
6834 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6835 vf->next_vf_pts_valid = true;
6836 vf->next_vf_pts = next_vf->pts;
6837 } else
6838 vf->next_vf_pts_valid = false;
6839
6840 return vf;
6841 }
6842 }
6843 return NULL;
6844 }
6845
6846 static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6847 {
6848 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6849 uint8_t index = vf->index & 0xff;
6850
6851 if (vf == (&pbi->vframe_dummy))
6852 return;
6853
6854 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6855 pbi->vf_put_count++;
6856 if (index < pbi->used_buf_num) {
6857 struct VP9_Common_s *cm = &pbi->common;
6858 struct BufferPool_s *pool = cm->buffer_pool;
6859 unsigned long flags;
6860
6861 lock_buffer_pool(pool, flags);
6862 if (pool->frame_bufs[index].buf.vf_ref > 0)
6863 pool->frame_bufs[index].buf.vf_ref--;
6864
6865 if (pbi->is_used_v4l)
6866 pool->frame_bufs[index].buf.vframe_bound = true;
6867
6868 if (pbi->wait_buf)
6869 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6870 0x1);
6871 pbi->last_put_idx = index;
6872 pbi->new_frame_displayed++;
6873 unlock_buffer_pool(pool, flags);
6874 #ifdef SUPPORT_FB_DECODING
6875 if (pbi->used_stage_buf_num > 0 &&
6876 pbi->back_not_run_ready)
6877 trigger_schedule(pbi);
6878 #endif
6879 }
6880
6881 }
6882
6883 static int vvp9_event_cb(int type, void *data, void *private_data)
6884 {
6885 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6886 #if 0
6887 unsigned long flags;
6888
6889 amhevc_stop();
6890 #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6891 vf_light_unreg_provider(&vvp9_vf_prov);
6892 #endif
6893 spin_lock_irqsave(&pbi->lock, flags);
6894 vvp9_local_init();
6895 vvp9_prot_init();
6896 spin_unlock_irqrestore(&pbi->lock, flags);
6897 #ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6898 vf_reg_provider(&vvp9_vf_prov);
6899 #endif
6900 amhevc_start();
6901 #endif
6902 }
6903
6904 return 0;
6905 }
6906
6907 void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6908 {
6909 struct VP9_Common_s *cm = &pbi->common;
6910
6911 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6912
6913 if (debug & VP9_DEBUG_BUFMGR_MORE)
6914 pr_info("%s index = %d new vf_ref = %d\r\n",
6915 __func__, index,
6916 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6917 }
6918
6919 static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6920 {
6921 u32 old_duration, pts_duration = 0;
6922 u32 pts = vf->pts;
6923
6924 if (pbi->get_frame_dur == true)
6925 return true;
6926
6927 pbi->frame_cnt_window++;
6928 if (!(pbi->vp9_first_pts_ready == 1)) {
6929 if (valid) {
6930 pbi->pts1 = pts;
6931 pbi->frame_cnt_window = 0;
6932 pbi->duration_from_pts_done = 0;
6933 pbi->vp9_first_pts_ready = 1;
6934 } else {
6935 return false;
6936 }
6937 } else {
6938 if (pts < pbi->pts1) {
6939 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6940 pbi->pts1 = pts;
6941 pbi->frame_cnt_window = 0;
6942 }
6943 }
6944
6945 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6946 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6947 old_duration = pbi->frame_dur;
6948 pbi->pts2 = pts;
6949 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6950 (pbi->frame_cnt_window * 15));
6951
6952 if (close_to(pts_duration, old_duration, 2000)) {
6953 pbi->frame_dur = pts_duration;
6954 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6955 pr_info("use calc duration %d\n", pts_duration);
6956 }
6957
6958 if (pbi->duration_from_pts_done == 0) {
6959 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6960 pbi->duration_from_pts_done = 1;
6961 } else {
6962 if (!close_to(pts_duration,
6963 old_duration, 1000) &&
6964 !close_to(pts_duration,
6965 pbi->frame_dur, 1000) &&
6966 close_to(pts_duration,
6967 pbi->last_duration, 200)) {
6968 /* frame_dur must
6969 * wrong,recover it.
6970 */
6971 pbi->frame_dur = pts_duration;
6972 }
6973 pbi->pts1 = pbi->pts2;
6974 pbi->frame_cnt_window = 0;
6975 pbi->duration_from_pts_done = 0;
6976 }
6977 }
6978 pbi->last_duration = pts_duration;
6979 }
6980 }
6981 return true;
6982 }
6983
6984 static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6985 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6986 {
6987 if (pic->index < 0) {
6988 vf->mem_handle = NULL;
6989 vf->mem_head_handle = NULL;
6990 } else if (vf->type & VIDTYPE_SCATTER) {
6991 vf->mem_handle =
6992 decoder_mmu_box_get_mem_handle(
6993 pbi->mmu_box, pic->index);
6994 vf->mem_head_handle =
6995 decoder_bmmu_box_get_mem_handle(
6996 pbi->bmmu_box,
6997 HEADER_BUFFER_IDX(pic->BUF_index));
6998 } else {
6999 vf->mem_handle =
7000 decoder_bmmu_box_get_mem_handle(
7001 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
7002 vf->mem_head_handle = NULL;
7003 /*vf->mem_head_handle =
7004 *decoder_bmmu_box_get_mem_handle(
7005 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
7006 */
7007 }
7008 }
7009
7010 static int prepare_display_buf(struct VP9Decoder_s *pbi,
7011 struct PIC_BUFFER_CONFIG_s *pic_config)
7012 {
7013 struct vframe_s *vf = NULL;
7014 int stream_offset = pic_config->stream_offset;
7015 unsigned short slice_type = pic_config->slice_type;
7016 u32 pts_valid = 0, pts_us64_valid = 0;
7017 u32 pts_save;
7018 u64 pts_us64_save;
7019 u32 frame_size;
7020
7021 if (debug & VP9_DEBUG_BUFMGR)
7022 pr_info("%s index = %d\r\n", __func__, pic_config->index);
7023 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
7024 pr_info("fatal error, no available buffer slot.");
7025 return -1;
7026 }
7027
7028 if (pic_config->double_write_mode)
7029 set_canvas(pbi, pic_config);
7030
7031 display_frame_count[pbi->index]++;
7032 if (vf) {
7033 if (pbi->is_used_v4l) {
7034 vf->v4l_mem_handle
7035 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7036 if (pbi->mmu_enable) {
7037 vf->mm_box.bmmu_box = pbi->bmmu_box;
7038 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7039 vf->mm_box.mmu_box = pbi->mmu_box;
7040 vf->mm_box.mmu_idx = pic_config->index;
7041 }
7042 }
7043
7044 #ifdef MULTI_INSTANCE_SUPPORT
7045 if (vdec_frame_based(hw_to_vdec(pbi))) {
7046 vf->pts = pic_config->pts;
7047 vf->pts_us64 = pic_config->pts64;
7048 vf->timestamp = pic_config->timestamp;
7049 if (vf->pts != 0 || vf->pts_us64 != 0) {
7050 pts_valid = 1;
7051 pts_us64_valid = 1;
7052 } else {
7053 pts_valid = 0;
7054 pts_us64_valid = 0;
7055 }
7056 } else
7057 #endif
7058 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7059 * stream_offset, &vf->pts, 0) != 0) {
7060 */
7061 if (pts_lookup_offset_us64
7062 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7063 &frame_size, 0,
7064 &vf->pts_us64) != 0) {
7065 #ifdef DEBUG_PTS
7066 pbi->pts_missed++;
7067 #endif
7068 vf->pts = 0;
7069 vf->pts_us64 = 0;
7070 pts_valid = 0;
7071 pts_us64_valid = 0;
7072 } else {
7073 #ifdef DEBUG_PTS
7074 pbi->pts_hit++;
7075 #endif
7076 pts_valid = 1;
7077 pts_us64_valid = 1;
7078 }
7079
7080 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7081
7082 pts_save = vf->pts;
7083 pts_us64_save = vf->pts_us64;
7084 if (pbi->pts_unstable) {
7085 frame_duration_adapt(pbi, vf, pts_valid);
7086 if (pbi->duration_from_pts_done) {
7087 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7088 } else {
7089 if (pts_valid || pts_us64_valid)
7090 pbi->pts_mode = PTS_NORMAL;
7091 }
7092 }
7093
7094 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7095 && pbi->get_frame_dur) {
7096 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7097
7098 if (pts_diff < 0) {
7099 pbi->pts_mode_switching_count++;
7100 pbi->pts_mode_recovery_count = 0;
7101
7102 if (pbi->pts_mode_switching_count >=
7103 PTS_MODE_SWITCHING_THRESHOLD) {
7104 pbi->pts_mode =
7105 PTS_NONE_REF_USE_DURATION;
7106 pr_info
7107 ("HEVC: switch to n_d mode.\n");
7108 }
7109
7110 } else {
7111 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7112
7113 pbi->pts_mode_recovery_count++;
7114 if (pbi->pts_mode_recovery_count > p) {
7115 pbi->pts_mode_switching_count = 0;
7116 pbi->pts_mode_recovery_count = 0;
7117 }
7118 }
7119 }
7120
7121 if (vf->pts != 0)
7122 pbi->last_lookup_pts = vf->pts;
7123
7124 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7125 && (slice_type != KEY_FRAME))
7126 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7127 pbi->last_pts = vf->pts;
7128
7129 if (vf->pts_us64 != 0)
7130 pbi->last_lookup_pts_us64 = vf->pts_us64;
7131
7132 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7133 && (slice_type != KEY_FRAME)) {
7134 vf->pts_us64 =
7135 pbi->last_pts_us64 +
7136 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7137 }
7138 pbi->last_pts_us64 = vf->pts_us64;
7139 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7140 pr_info
7141 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7142 pbi->pts_mode, pbi->frame_dur, vf->pts,
7143 vf->pts_us64, pts_save, pts_us64_save);
7144 }
7145
7146 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7147 vf->disp_pts = vf->pts;
7148 vf->disp_pts_us64 = vf->pts_us64;
7149 vf->pts = pts_save;
7150 vf->pts_us64 = pts_us64_save;
7151 } else {
7152 vf->disp_pts = 0;
7153 vf->disp_pts_us64 = 0;
7154 }
7155
7156 vf->index = 0xff00 | pic_config->index;
7157
7158 if (pic_config->double_write_mode & 0x10) {
7159 /* double write only */
7160 vf->compBodyAddr = 0;
7161 vf->compHeadAddr = 0;
7162 } else {
7163 if (pbi->mmu_enable) {
7164 vf->compBodyAddr = 0;
7165 vf->compHeadAddr = pic_config->header_adr;
7166 } else {
7167 /*vf->compBodyAddr = pic_config->mc_y_adr;
7168 *vf->compHeadAddr = pic_config->mc_y_adr +
7169 *pic_config->comp_body_size; */
7170 /*head adr*/
7171 }
7172 vf->canvas0Addr = vf->canvas1Addr = 0;
7173 }
7174 if (pic_config->double_write_mode) {
7175 vf->type = VIDTYPE_PROGRESSIVE |
7176 VIDTYPE_VIU_FIELD;
7177 vf->type |= VIDTYPE_VIU_NV21;
7178 if ((pic_config->double_write_mode == 3) &&
7179 (!IS_8K_SIZE(pic_config->y_crop_width,
7180 pic_config->y_crop_height))) {
7181 vf->type |= VIDTYPE_COMPRESS;
7182 if (pbi->mmu_enable)
7183 vf->type |= VIDTYPE_SCATTER;
7184 }
7185 #ifdef MULTI_INSTANCE_SUPPORT
7186 if (pbi->m_ins_flag) {
7187 vf->canvas0Addr = vf->canvas1Addr = -1;
7188 vf->plane_num = 2;
7189 vf->canvas0_config[0] =
7190 pic_config->canvas_config[0];
7191 vf->canvas0_config[1] =
7192 pic_config->canvas_config[1];
7193 vf->canvas1_config[0] =
7194 pic_config->canvas_config[0];
7195 vf->canvas1_config[1] =
7196 pic_config->canvas_config[1];
7197
7198 } else
7199 #endif
7200 vf->canvas0Addr = vf->canvas1Addr =
7201 spec2canvas(pic_config);
7202 } else {
7203 vf->canvas0Addr = vf->canvas1Addr = 0;
7204 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7205 if (pbi->mmu_enable)
7206 vf->type |= VIDTYPE_SCATTER;
7207 }
7208
7209 switch (pic_config->bit_depth) {
7210 case VPX_BITS_8:
7211 vf->bitdepth = BITDEPTH_Y8 |
7212 BITDEPTH_U8 | BITDEPTH_V8;
7213 break;
7214 case VPX_BITS_10:
7215 case VPX_BITS_12:
7216 vf->bitdepth = BITDEPTH_Y10 |
7217 BITDEPTH_U10 | BITDEPTH_V10;
7218 break;
7219 default:
7220 vf->bitdepth = BITDEPTH_Y10 |
7221 BITDEPTH_U10 | BITDEPTH_V10;
7222 break;
7223 }
7224 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7225 vf->bitdepth =
7226 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7227 if (pic_config->bit_depth == VPX_BITS_8)
7228 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7229
7230 /* if((vf->width!=pic_config->width)|
7231 * (vf->height!=pic_config->height))
7232 */
7233 /* pr_info("aaa: %d/%d, %d/%d\n",
7234 vf->width,vf->height, pic_config->width,
7235 pic_config->height); */
7236 vf->width = pic_config->y_crop_width /
7237 get_double_write_ratio(pbi,
7238 pic_config->double_write_mode);
7239 vf->height = pic_config->y_crop_height /
7240 get_double_write_ratio(pbi,
7241 pic_config->double_write_mode);
7242 if (force_w_h != 0) {
7243 vf->width = (force_w_h >> 16) & 0xffff;
7244 vf->height = force_w_h & 0xffff;
7245 }
7246 vf->compWidth = pic_config->y_crop_width;
7247 vf->compHeight = pic_config->y_crop_height;
7248 set_frame_info(pbi, vf);
7249 if (force_fps & 0x100) {
7250 u32 rate = force_fps & 0xff;
7251
7252 if (rate)
7253 vf->duration = 96000/rate;
7254 else
7255 vf->duration = 0;
7256 }
7257 update_vf_memhandle(pbi, vf, pic_config);
7258 if (!(pic_config->y_crop_width == 196
7259 && pic_config->y_crop_height == 196
7260 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7261 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7262 inc_vf_ref(pbi, pic_config->index);
7263 decoder_do_frame_check(hw_to_vdec(pbi), vf);
7264 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7265 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7266 pbi->vf_pre_count++;
7267 #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7268 /*count info*/
7269 gvs->frame_dur = pbi->frame_dur;
7270 vdec_count_info(gvs, 0, stream_offset);
7271 #endif
7272 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7273 if (without_display_mode == 0) {
7274 vf_notify_receiver(pbi->provider_name,
7275 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7276 } else
7277 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7278 } else {
7279 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7280 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7281 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7282 __func__, __LINE__, vf->width,
7283 vf->height, pbi->stat);
7284 }
7285 }
7286
7287 return 0;
7288 }
7289
7290 static int notify_v4l_eos(struct vdec_s *vdec)
7291 {
7292 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7293 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7294 struct vframe_s *vf = &hw->vframe_dummy;
7295 struct vdec_v4l2_buffer *fb = NULL;
7296 int index = INVALID_IDX;
7297 ulong expires;
7298
7299 if (hw->is_used_v4l && hw->eos) {
7300 expires = jiffies + msecs_to_jiffies(2000);
7301 while (INVALID_IDX == (index = v4l_get_free_fb(hw))) {
7302 if (time_after(jiffies, expires) ||
7303 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
7304 break;
7305 }
7306
7307 if (index == INVALID_IDX) {
7308 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7309 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7310 return -1;
7311 }
7312 }
7313
7314 vf->type |= VIDTYPE_V4L_EOS;
7315 vf->timestamp = ULONG_MAX;
7316 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7317 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7318 hw->m_BUF[index].v4l_ref_buf_addr;
7319
7320 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7321 vf_notify_receiver(vdec->vf_provider_name,
7322 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7323
7324 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7325 }
7326
7327 return 0;
7328 }
7329
7330 static void get_rpm_param(union param_u *params)
7331 {
7332 int i;
7333 unsigned int data32;
7334
7335 if (debug & VP9_DEBUG_BUFMGR)
7336 pr_info("enter %s\r\n", __func__);
7337 for (i = 0; i < 128; i++) {
7338 do {
7339 data32 = READ_VREG(RPM_CMD_REG);
7340 /*pr_info("%x\n", data32);*/
7341 } while ((data32 & 0x10000) == 0);
7342 params->l.data[i] = data32&0xffff;
7343 /*pr_info("%x\n", data32);*/
7344 WRITE_VREG(RPM_CMD_REG, 0);
7345 }
7346 if (debug & VP9_DEBUG_BUFMGR)
7347 pr_info("leave %s\r\n", __func__);
7348 }
7349 static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7350 {
7351 int i;
7352
7353 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7354 return;
7355 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7356 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7357 pr_info("%04x ", vp9_param.l.data[i]);
7358 if (((i + 1) & 0xf) == 0)
7359 pr_info("\n");
7360 }
7361 pr_info("=============param==========\r\n");
7362 pr_info("profile %x\r\n", vp9_param.p.profile);
7363 pr_info("show_existing_frame %x\r\n",
7364 vp9_param.p.show_existing_frame);
7365 pr_info("frame_to_show_idx %x\r\n",
7366 vp9_param.p.frame_to_show_idx);
7367 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7368 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7369 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7370 vp9_param.p.error_resilient_mode);
7371 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7372 pr_info("display_size_present %x\r\n",
7373 vp9_param.p.display_size_present);
7374 pr_info("reset_frame_context %x\r\n",
7375 vp9_param.p.reset_frame_context);
7376 pr_info("refresh_frame_flags %x\r\n",
7377 vp9_param.p.refresh_frame_flags);
7378 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7379 pr_info("width %x\r\n", vp9_param.p.width);
7380 pr_info("height %x\r\n", vp9_param.p.height);
7381 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7382 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7383 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7384 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7385 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7386 return;
7387 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7388 vp9_param.p.mode_ref_delta_enabled);
7389 pr_info("sharpness_level: 0x%x\r\n",
7390 vp9_param.p.sharpness_level);
7391 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7392 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7393 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7394 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7395 vp9_param.p.mode_deltas[1]);
7396 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7397 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7398 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7399 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7400 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7401 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7402 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7403 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7404 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7405 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7406 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7407 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7408 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7409 (vp9_param.p.seg_lf_info[0] & 0x13f),
7410 (vp9_param.p.seg_lf_info[1] & 0x13f),
7411 (vp9_param.p.seg_lf_info[2] & 0x13f),
7412 (vp9_param.p.seg_lf_info[3] & 0x13f),
7413 (vp9_param.p.seg_lf_info[4] & 0x13f),
7414 (vp9_param.p.seg_lf_info[5] & 0x13f),
7415 (vp9_param.p.seg_lf_info[6] & 0x13f),
7416 (vp9_param.p.seg_lf_info[7] & 0x13f));
7417
7418 }
7419
7420
7421 static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7422 {
7423 struct VP9_Common_s *const cm = &pbi->common;
7424 if (pbi->double_write_mode & 0x10)
7425 return;
7426 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7427 if (pbi->used_4k_num == -1) {
7428 pbi->used_4k_num =
7429 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7430 if (pbi->m_ins_flag)
7431 hevc_mmu_dma_check(hw_to_vdec(pbi));
7432 }
7433 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7434 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7435 cm->cur_fb_idx_mmu = INVALID_IDX;
7436 pbi->used_4k_num = -1;
7437 }
7438 }
7439
7440 #ifdef MULTI_INSTANCE_SUPPORT
7441 static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7442 {
7443 struct VP9_Common_s *const cm = &pbi->common;
7444 if (pbi->double_write_mode & 0x10)
7445 return;
7446 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7447 decoder_mmu_box_free_idx(pbi->mmu_box,
7448 cm->cur_fb_idx_mmu);
7449
7450 cm->cur_fb_idx_mmu = INVALID_IDX;
7451 pbi->used_4k_num = -1;
7452 }
7453 }
7454
7455 void vp9_recycle_mmu_work(struct work_struct *work)
7456 {
7457 struct VP9Decoder_s *pbi = container_of(work,
7458 struct VP9Decoder_s, recycle_mmu_work);
7459
7460 vp9_recycle_mmu_buf(pbi);
7461 }
7462 #endif
7463
7464
7465 static void dec_again_process(struct VP9Decoder_s *pbi)
7466 {
7467 amhevc_stop();
7468 pbi->dec_result = DEC_RESULT_AGAIN;
7469 if (pbi->process_state ==
7470 PROC_STATE_DECODESLICE) {
7471 pbi->process_state =
7472 PROC_STATE_SENDAGAIN;
7473 if (pbi->mmu_enable) {
7474 /*
7475 * Because vp9_recycle_mmu_buf has sleep function,we can't
7476 * call it directly. Use a recycle_mmu_work to substitude it.
7477 */
7478 vdec_schedule_work(&pbi->recycle_mmu_work);
7479 }
7480 }
7481 reset_process_time(pbi);
7482 vdec_schedule_work(&pbi->work);
7483 }
7484
7485 int continue_decoding(struct VP9Decoder_s *pbi)
7486 {
7487 int ret;
7488 int i;
7489 struct VP9_Common_s *const cm = &pbi->common;
7490 debug_buffer_mgr_more(pbi);
7491
7492 bit_depth_luma = vp9_param.p.bit_depth;
7493 bit_depth_chroma = vp9_param.p.bit_depth;
7494
7495 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7496 (get_double_write_mode(pbi) == 0x10)) {
7497 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7498 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7499 vp9_param.p.bit_depth);
7500 return -1;
7501 }
7502
7503 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7504 ret = vp9_bufmgr_process(pbi, &vp9_param);
7505 if (!pbi->m_ins_flag)
7506 pbi->slice_idx++;
7507 } else {
7508 union param_u *params = &vp9_param;
7509 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7510 ret = vp9_alloc_mmu(pbi,
7511 cm->new_fb_idx,
7512 params->p.width,
7513 params->p.height,
7514 params->p.bit_depth,
7515 pbi->frame_mmu_map_addr);
7516 if (ret >= 0)
7517 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7518 else
7519 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7520 cm->new_fb_idx,
7521 ret);
7522 } else {
7523 ret = 0;
7524 }
7525 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7526 (params->p.height << 16) | params->p.width);
7527 }
7528 if (ret < 0) {
7529 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7530 ret);
7531 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7532 cm->show_frame = 0;
7533 if (pbi->mmu_enable)
7534 vp9_recycle_mmu_buf(pbi);
7535 #ifdef MULTI_INSTANCE_SUPPORT
7536 if (pbi->m_ins_flag) {
7537 pbi->dec_result = DEC_RESULT_DONE;
7538 #ifdef SUPPORT_FB_DECODING
7539 if (pbi->used_stage_buf_num == 0)
7540 #endif
7541 amhevc_stop();
7542 vdec_schedule_work(&pbi->work);
7543 }
7544 #endif
7545 return ret;
7546 } else if (ret == 0) {
7547 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7548 = &cm->cur_frame->buf;
7549 cur_pic_config->decode_idx = pbi->frame_count;
7550
7551 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7552 if (!pbi->m_ins_flag) {
7553 pbi->frame_count++;
7554 decode_frame_count[pbi->index]
7555 = pbi->frame_count;
7556 }
7557 #ifdef MULTI_INSTANCE_SUPPORT
7558 if (pbi->chunk) {
7559 cur_pic_config->pts = pbi->chunk->pts;
7560 cur_pic_config->pts64 = pbi->chunk->pts64;
7561 cur_pic_config->timestamp = pbi->chunk->timestamp;
7562 }
7563 #endif
7564 }
7565 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7566 config_pic_size(pbi, vp9_param.p.bit_depth);
7567
7568 if ((pbi->common.frame_type != KEY_FRAME)
7569 && (!pbi->common.intra_only)) {
7570 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7571 #ifdef SUPPORT_FB_DECODING
7572 if (pbi->used_stage_buf_num == 0)
7573 #endif
7574 config_mpred_hw(pbi);
7575 } else {
7576 #ifdef SUPPORT_FB_DECODING
7577 if (pbi->used_stage_buf_num == 0)
7578 #endif
7579 clear_mpred_hw(pbi);
7580 }
7581 #ifdef MCRCC_ENABLE
7582 if (mcrcc_cache_alg_flag)
7583 config_mcrcc_axi_hw_new(pbi);
7584 else
7585 config_mcrcc_axi_hw(pbi);
7586 #endif
7587 config_sao_hw(pbi, &vp9_param);
7588
7589 #ifdef VP9_LPF_LVL_UPDATE
7590 /*
7591 * Get loop filter related picture level parameters from Parser
7592 */
7593 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7594 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7595 for (i = 0; i < 4; i++)
7596 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7597 for (i = 0; i < 2; i++)
7598 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7599 pbi->default_filt_lvl = vp9_param.p.filter_level;
7600 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7601 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7602 for (i = 0; i < MAX_SEGMENTS; i++)
7603 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7604 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7605 for (i = 0; i < MAX_SEGMENTS; i++)
7606 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7607 = (vp9_param.p.seg_lf_info[i]
7608 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7609 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7610 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7611 /*Set pipeline mode*/
7612 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7613 /*dblk pipeline mode=1 for performance*/
7614 if (vp9_param.p.width >= 1280)
7615 lpf_data32 |= (0x1 << 4);
7616 else
7617 lpf_data32 &= ~(0x3 << 4);
7618 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7619 }
7620 /*
7621 * Update loop filter Thr/Lvl table for every frame
7622 */
7623 /*pr_info
7624 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7625 vp9_loop_filter_frame_init(pbi->seg_4lf,
7626 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7627 #endif
7628 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7629 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7630 } else {
7631 pr_info("Skip search next start code\n");
7632 cm->prev_fb_idx = INVALID_IDX;
7633 /*skip, search next start code*/
7634 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7635 }
7636 pbi->process_state = PROC_STATE_DECODESLICE;
7637 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7638 if (pbi->last_put_idx < pbi->used_buf_num) {
7639 struct RefCntBuffer_s *frame_bufs =
7640 cm->buffer_pool->frame_bufs;
7641 int i = pbi->last_put_idx;
7642 /*free not used buffers.*/
7643 if ((frame_bufs[i].ref_count == 0) &&
7644 (frame_bufs[i].buf.vf_ref == 0) &&
7645 (frame_bufs[i].buf.index != -1)) {
7646 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7647 }
7648 pbi->last_put_idx = -1;
7649 }
7650 }
7651 return ret;
7652 }
7653
7654 static void fill_frame_info(struct VP9Decoder_s *pbi,
7655 struct PIC_BUFFER_CONFIG_s *frame,
7656 unsigned int framesize,
7657 unsigned int pts)
7658 {
7659 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7660
7661 if (frame->slice_type == KEY_FRAME)
7662 vframe_qos->type = 1;
7663 else if (frame->slice_type == INTER_FRAME)
7664 vframe_qos->type = 2;
7665 /*
7666 #define SHOW_QOS_INFO
7667 */
7668 vframe_qos->size = framesize;
7669 vframe_qos->pts = pts;
7670 #ifdef SHOW_QOS_INFO
7671 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7672 #endif
7673 vframe_qos->max_mv = frame->max_mv;
7674 vframe_qos->avg_mv = frame->avg_mv;
7675 vframe_qos->min_mv = frame->min_mv;
7676 #ifdef SHOW_QOS_INFO
7677 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7678 vframe_qos->max_mv,
7679 vframe_qos->avg_mv,
7680 vframe_qos->min_mv);
7681 #endif
7682 vframe_qos->max_qp = frame->max_qp;
7683 vframe_qos->avg_qp = frame->avg_qp;
7684 vframe_qos->min_qp = frame->min_qp;
7685 #ifdef SHOW_QOS_INFO
7686 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7687 vframe_qos->max_qp,
7688 vframe_qos->avg_qp,
7689 vframe_qos->min_qp);
7690 #endif
7691 vframe_qos->max_skip = frame->max_skip;
7692 vframe_qos->avg_skip = frame->avg_skip;
7693 vframe_qos->min_skip = frame->min_skip;
7694 #ifdef SHOW_QOS_INFO
7695 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7696 vframe_qos->max_skip,
7697 vframe_qos->avg_skip,
7698 vframe_qos->min_skip);
7699 #endif
7700 vframe_qos->num++;
7701
7702 if (pbi->frameinfo_enable)
7703 vdec_fill_frame_info(vframe_qos, 1);
7704 }
7705
7706 /* only when we decoded one field or one frame,
7707 we can call this function to get qos info*/
7708 static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7709 {
7710 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7711
7712 if (!frame)
7713 return;
7714
7715 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7716 unsigned char a[3];
7717 unsigned char i, j, t;
7718 unsigned long data;
7719
7720 data = READ_VREG(HEVC_MV_INFO);
7721 if (frame->slice_type == KEY_FRAME)
7722 data = 0;
7723 a[0] = data & 0xff;
7724 a[1] = (data >> 8) & 0xff;
7725 a[2] = (data >> 16) & 0xff;
7726
7727 for (i = 0; i < 3; i++) {
7728 for (j = i+1; j < 3; j++) {
7729 if (a[j] < a[i]) {
7730 t = a[j];
7731 a[j] = a[i];
7732 a[i] = t;
7733 } else if (a[j] == a[i]) {
7734 a[i]++;
7735 t = a[j];
7736 a[j] = a[i];
7737 a[i] = t;
7738 }
7739 }
7740 }
7741 frame->max_mv = a[2];
7742 frame->avg_mv = a[1];
7743 frame->min_mv = a[0];
7744
7745 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7746 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7747 data, a[0], a[1], a[2]);
7748
7749 data = READ_VREG(HEVC_QP_INFO);
7750 a[0] = data & 0x1f;
7751 a[1] = (data >> 8) & 0x3f;
7752 a[2] = (data >> 16) & 0x7f;
7753
7754 for (i = 0; i < 3; i++) {
7755 for (j = i+1; j < 3; j++) {
7756 if (a[j] < a[i]) {
7757 t = a[j];
7758 a[j] = a[i];
7759 a[i] = t;
7760 } else if (a[j] == a[i]) {
7761 a[i]++;
7762 t = a[j];
7763 a[j] = a[i];
7764 a[i] = t;
7765 }
7766 }
7767 }
7768 frame->max_qp = a[2];
7769 frame->avg_qp = a[1];
7770 frame->min_qp = a[0];
7771
7772 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7773 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7774 data, a[0], a[1], a[2]);
7775
7776 data = READ_VREG(HEVC_SKIP_INFO);
7777 a[0] = data & 0x1f;
7778 a[1] = (data >> 8) & 0x3f;
7779 a[2] = (data >> 16) & 0x7f;
7780
7781 for (i = 0; i < 3; i++) {
7782 for (j = i+1; j < 3; j++) {
7783 if (a[j] < a[i]) {
7784 t = a[j];
7785 a[j] = a[i];
7786 a[i] = t;
7787 } else if (a[j] == a[i]) {
7788 a[i]++;
7789 t = a[j];
7790 a[j] = a[i];
7791 a[i] = t;
7792 }
7793 }
7794 }
7795 frame->max_skip = a[2];
7796 frame->avg_skip = a[1];
7797 frame->min_skip = a[0];
7798
7799 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7800 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7801 data, a[0], a[1], a[2]);
7802 } else {
7803 uint32_t blk88_y_count;
7804 uint32_t blk88_c_count;
7805 uint32_t blk22_mv_count;
7806 uint32_t rdata32;
7807 int32_t mv_hi;
7808 int32_t mv_lo;
7809 uint32_t rdata32_l;
7810 uint32_t mvx_L0_hi;
7811 uint32_t mvy_L0_hi;
7812 uint32_t mvx_L1_hi;
7813 uint32_t mvy_L1_hi;
7814 int64_t value;
7815 uint64_t temp_value;
7816 int pic_number = frame->decode_idx;
7817
7818 frame->max_mv = 0;
7819 frame->avg_mv = 0;
7820 frame->min_mv = 0;
7821
7822 frame->max_skip = 0;
7823 frame->avg_skip = 0;
7824 frame->min_skip = 0;
7825
7826 frame->max_qp = 0;
7827 frame->avg_qp = 0;
7828 frame->min_qp = 0;
7829
7830 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7831 frame->slice_type,
7832 pic_number);
7833
7834 /* set rd_idx to 0 */
7835 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7836
7837 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7838 if (blk88_y_count == 0) {
7839
7840 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7841 "[Picture %d Quality] NO Data yet.\n",
7842 pic_number);
7843
7844 /* reset all counts */
7845 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7846 return;
7847 }
7848 /* qp_y_sum */
7849 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7850
7851 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7852 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7853 pic_number, rdata32/blk88_y_count,
7854 rdata32, blk88_y_count);
7855
7856 frame->avg_qp = rdata32/blk88_y_count;
7857 /* intra_y_count */
7858 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7859
7860 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7861 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7862 pic_number, rdata32*100/blk88_y_count,
7863 '%', rdata32);
7864
7865 /* skipped_y_count */
7866 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7867
7868 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7869 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7870 pic_number, rdata32*100/blk88_y_count,
7871 '%', rdata32);
7872
7873 frame->avg_skip = rdata32*100/blk88_y_count;
7874 /* coeff_non_zero_y_count */
7875 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7876
7877 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7878 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7879 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7880 '%', rdata32);
7881
7882 /* blk66_c_count */
7883 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7884 if (blk88_c_count == 0) {
7885 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7886 "[Picture %d Quality] NO Data yet.\n",
7887 pic_number);
7888 /* reset all counts */
7889 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7890 return;
7891 }
7892 /* qp_c_sum */
7893 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7894
7895 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7896 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7897 pic_number, rdata32/blk88_c_count,
7898 rdata32, blk88_c_count);
7899
7900 /* intra_c_count */
7901 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7902
7903 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7904 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7905 pic_number, rdata32*100/blk88_c_count,
7906 '%', rdata32);
7907
7908 /* skipped_cu_c_count */
7909 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7910
7911 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7912 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7913 pic_number, rdata32*100/blk88_c_count,
7914 '%', rdata32);
7915
7916 /* coeff_non_zero_c_count */
7917 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7918
7919 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7920 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7921 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7922 '%', rdata32);
7923
7924 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7925 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7926 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7927
7928 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7929 "[Picture %d Quality] Y QP min : %d\n",
7930 pic_number, (rdata32>>0)&0xff);
7931
7932 frame->min_qp = (rdata32>>0)&0xff;
7933
7934 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7935 "[Picture %d Quality] Y QP max : %d\n",
7936 pic_number, (rdata32>>8)&0xff);
7937
7938 frame->max_qp = (rdata32>>8)&0xff;
7939
7940 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7941 "[Picture %d Quality] C QP min : %d\n",
7942 pic_number, (rdata32>>16)&0xff);
7943 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7944 "[Picture %d Quality] C QP max : %d\n",
7945 pic_number, (rdata32>>24)&0xff);
7946
7947 /* blk22_mv_count */
7948 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7949 if (blk22_mv_count == 0) {
7950 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7951 "[Picture %d Quality] NO MV Data yet.\n",
7952 pic_number);
7953 /* reset all counts */
7954 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7955 return;
7956 }
7957 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7958 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7959 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7960 /* should all be 0x00 or 0xff */
7961 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7962 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7963 pic_number, rdata32);
7964
7965 mvx_L0_hi = ((rdata32>>0)&0xff);
7966 mvy_L0_hi = ((rdata32>>8)&0xff);
7967 mvx_L1_hi = ((rdata32>>16)&0xff);
7968 mvy_L1_hi = ((rdata32>>24)&0xff);
7969
7970 /* mvx_L0_count[31:0] */
7971 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7972 temp_value = mvx_L0_hi;
7973 temp_value = (temp_value << 32) | rdata32_l;
7974
7975 if (mvx_L0_hi & 0x80)
7976 value = 0xFFFFFFF000000000 | temp_value;
7977 else
7978 value = temp_value;
7979
7980 value = div_s64(value, blk22_mv_count);
7981
7982 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7983 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7984 pic_number, (int)value,
7985 value, blk22_mv_count);
7986
7987 frame->avg_mv = value;
7988
7989 /* mvy_L0_count[31:0] */
7990 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7991 temp_value = mvy_L0_hi;
7992 temp_value = (temp_value << 32) | rdata32_l;
7993
7994 if (mvy_L0_hi & 0x80)
7995 value = 0xFFFFFFF000000000 | temp_value;
7996 else
7997 value = temp_value;
7998
7999 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8000 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
8001 pic_number, rdata32_l/blk22_mv_count,
8002 value, blk22_mv_count);
8003
8004 /* mvx_L1_count[31:0] */
8005 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8006 temp_value = mvx_L1_hi;
8007 temp_value = (temp_value << 32) | rdata32_l;
8008 if (mvx_L1_hi & 0x80)
8009 value = 0xFFFFFFF000000000 | temp_value;
8010 else
8011 value = temp_value;
8012
8013 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8014 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
8015 pic_number, rdata32_l/blk22_mv_count,
8016 value, blk22_mv_count);
8017
8018 /* mvy_L1_count[31:0] */
8019 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8020 temp_value = mvy_L1_hi;
8021 temp_value = (temp_value << 32) | rdata32_l;
8022 if (mvy_L1_hi & 0x80)
8023 value = 0xFFFFFFF000000000 | temp_value;
8024 else
8025 value = temp_value;
8026
8027 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8028 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
8029 pic_number, rdata32_l/blk22_mv_count,
8030 value, blk22_mv_count);
8031
8032 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
8033 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8034 mv_hi = (rdata32>>16)&0xffff;
8035 if (mv_hi & 0x8000)
8036 mv_hi = 0x8000 - mv_hi;
8037
8038 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8039 "[Picture %d Quality] MVX_L0 MAX : %d\n",
8040 pic_number, mv_hi);
8041
8042 frame->max_mv = mv_hi;
8043
8044 mv_lo = (rdata32>>0)&0xffff;
8045 if (mv_lo & 0x8000)
8046 mv_lo = 0x8000 - mv_lo;
8047
8048 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8049 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8050 pic_number, mv_lo);
8051
8052 frame->min_mv = mv_lo;
8053
8054 /* {mvy_L0_max, mvy_L0_min} */
8055 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8056 mv_hi = (rdata32>>16)&0xffff;
8057 if (mv_hi & 0x8000)
8058 mv_hi = 0x8000 - mv_hi;
8059
8060 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8061 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8062 pic_number, mv_hi);
8063
8064 mv_lo = (rdata32>>0)&0xffff;
8065 if (mv_lo & 0x8000)
8066 mv_lo = 0x8000 - mv_lo;
8067
8068 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8069 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8070 pic_number, mv_lo);
8071
8072 /* {mvx_L1_max, mvx_L1_min} */
8073 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8074 mv_hi = (rdata32>>16)&0xffff;
8075 if (mv_hi & 0x8000)
8076 mv_hi = 0x8000 - mv_hi;
8077
8078 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8079 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8080 pic_number, mv_hi);
8081
8082 mv_lo = (rdata32>>0)&0xffff;
8083 if (mv_lo & 0x8000)
8084 mv_lo = 0x8000 - mv_lo;
8085
8086 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8087 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8088 pic_number, mv_lo);
8089
8090 /* {mvy_L1_max, mvy_L1_min} */
8091 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8092 mv_hi = (rdata32>>16)&0xffff;
8093 if (mv_hi & 0x8000)
8094 mv_hi = 0x8000 - mv_hi;
8095
8096 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8097 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8098 pic_number, mv_hi);
8099
8100 mv_lo = (rdata32>>0)&0xffff;
8101 if (mv_lo & 0x8000)
8102 mv_lo = 0x8000 - mv_lo;
8103
8104 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8105 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8106 pic_number, mv_lo);
8107
8108 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8109
8110 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8111 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8112 pic_number, rdata32);
8113
8114 /* reset all counts */
8115 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8116 }
8117 }
8118
8119 static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8120 {
8121 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8122 unsigned int dec_status = pbi->dec_status;
8123 int i;
8124
8125 /*if (pbi->wait_buf)
8126 * pr_info("set wait_buf to 0\r\n");
8127 */
8128 if (pbi->eos)
8129 return IRQ_HANDLED;
8130 pbi->wait_buf = 0;
8131 #ifdef MULTI_INSTANCE_SUPPORT
8132 #ifdef SUPPORT_FB_DECODING
8133 #ifdef FB_DECODING_TEST_SCHEDULE
8134 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8135 dec_status = HEVC_DECPIC_DATA_DONE;
8136 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8137 && dec_status == HEVC_DECPIC_DATA_DONE)
8138 dec_status = HEVC_S2_DECODING_DONE;
8139 pbi->s1_test_cmd = TEST_SET_NONE;
8140 #else
8141 /*if (irq != VDEC_IRQ_0)
8142 dec_status = HEVC_S2_DECODING_DONE;*/
8143 #endif
8144 if (dec_status == HEVC_S2_DECODING_DONE) {
8145 pbi->dec_result = DEC_RESULT_DONE;
8146 vdec_schedule_work(&pbi->work);
8147 #ifdef FB_DECODING_TEST_SCHEDULE
8148 amhevc_stop();
8149 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8150 vdec_schedule_work(&pbi->s1_work);
8151 #endif
8152 } else
8153 #endif
8154 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8155 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8156 (dec_status == HEVC_DECODE_BUFEMPTY)
8157 ) {
8158 if (pbi->m_ins_flag) {
8159 reset_process_time(pbi);
8160 if (!vdec_frame_based(hw_to_vdec(pbi)))
8161 dec_again_process(pbi);
8162 else {
8163 pbi->dec_result = DEC_RESULT_GET_DATA;
8164 vdec_schedule_work(&pbi->work);
8165 }
8166 }
8167 pbi->process_busy = 0;
8168 return IRQ_HANDLED;
8169 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8170 if (pbi->m_ins_flag) {
8171 get_picture_qos_info(pbi);
8172 #ifdef SUPPORT_FB_DECODING
8173 if (pbi->used_stage_buf_num > 0) {
8174 reset_process_time(pbi);
8175 inc_s1_pos(pbi);
8176 trigger_schedule(pbi);
8177 #ifdef FB_DECODING_TEST_SCHEDULE
8178 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8179 #else
8180 amhevc_stop();
8181 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8182 vdec_schedule_work(&pbi->s1_work);
8183 #endif
8184 } else
8185 #endif
8186 {
8187 reset_process_time(pbi);
8188 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8189 vp9_bufmgr_postproc(pbi);
8190
8191 pbi->dec_result = DEC_RESULT_DONE;
8192 amhevc_stop();
8193 if (mcrcc_cache_alg_flag)
8194 dump_hit_rate(pbi);
8195 vdec_schedule_work(&pbi->work);
8196 }
8197 } else {
8198 if (pbi->low_latency_flag) {
8199 vp9_bufmgr_postproc(pbi);
8200 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8201 #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8202 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8203 if (debug & PRINT_FLAG_VDEC_DETAIL)
8204 pr_info("%s VP9 frame done \n", __func__);
8205 #endif
8206 }
8207 }
8208
8209 pbi->process_busy = 0;
8210 return IRQ_HANDLED;
8211 }
8212 #endif
8213
8214 if (dec_status == VP9_EOS) {
8215 #ifdef MULTI_INSTANCE_SUPPORT
8216 if (pbi->m_ins_flag)
8217 reset_process_time(pbi);
8218 #endif
8219
8220 pr_info("VP9_EOS, flush buffer\r\n");
8221
8222 vp9_bufmgr_postproc(pbi);
8223
8224 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8225 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8226 pbi->process_busy = 0;
8227 #ifdef MULTI_INSTANCE_SUPPORT
8228 if (pbi->m_ins_flag) {
8229 pbi->dec_result = DEC_RESULT_DONE;
8230 amhevc_stop();
8231 vdec_schedule_work(&pbi->work);
8232 }
8233 #endif
8234 return IRQ_HANDLED;
8235 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8236 pr_info("vp9 decode oversize !!\n");
8237 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8238 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8239 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8240 #ifdef MULTI_INSTANCE_SUPPORT
8241 if (pbi->m_ins_flag)
8242 reset_process_time(pbi);
8243 #endif
8244 return IRQ_HANDLED;
8245 }
8246
8247 if (dec_status != VP9_HEAD_PARSER_DONE) {
8248 pbi->process_busy = 0;
8249 return IRQ_HANDLED;
8250 }
8251
8252
8253 #ifdef MULTI_INSTANCE_SUPPORT
8254 #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8255 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8256 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8257 if (debug & PRINT_FLAG_VDEC_DETAIL)
8258 pr_info("%s VP9 frame header found \n", __func__);
8259 }
8260 #endif
8261 if (pbi->m_ins_flag)
8262 reset_process_time(pbi);
8263 #endif
8264 if (pbi->process_state != PROC_STATE_SENDAGAIN
8265 #ifdef SUPPORT_FB_DECODING
8266 && pbi->used_stage_buf_num == 0
8267 #endif
8268 ) {
8269 if (pbi->mmu_enable)
8270 vp9_recycle_mmu_buf_tail(pbi);
8271
8272
8273 if (pbi->frame_count > 0)
8274 vp9_bufmgr_postproc(pbi);
8275 }
8276
8277 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8278 get_rpm_param(&vp9_param);
8279 } else {
8280 #ifdef SUPPORT_FB_DECODING
8281 if (pbi->used_stage_buf_num > 0) {
8282 reset_process_time(pbi);
8283 get_s1_buf(pbi);
8284
8285 if (get_mv_buf(pbi,
8286 &pbi->s1_mv_buf_index,
8287 &pbi->s1_mpred_mv_wr_start_addr
8288 ) < 0) {
8289 vp9_print(pbi, 0,
8290 "%s: Error get_mv_buf fail\n",
8291 __func__);
8292 }
8293
8294 if (pbi->s1_buf == NULL) {
8295 vp9_print(pbi, 0,
8296 "%s: Error get_s1_buf fail\n",
8297 __func__);
8298 pbi->process_busy = 0;
8299 return IRQ_HANDLED;
8300 }
8301
8302 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8303 int ii;
8304 for (ii = 0; ii < 4; ii++) {
8305 pbi->s1_buf->rpm[i + 3 - ii] =
8306 pbi->rpm_ptr[i + 3 - ii];
8307 pbi->s1_param.l.data[i + ii] =
8308 pbi->rpm_ptr[i + 3 - ii];
8309 }
8310 }
8311
8312 mpred_process(pbi);
8313 #ifdef FB_DECODING_TEST_SCHEDULE
8314 pbi->dec_s1_result =
8315 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8316 vdec_schedule_work(&pbi->s1_work);
8317 #else
8318 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8319 pbi->stage_mmu_map_phy_addr +
8320 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8321
8322 start_s1_decoding(pbi);
8323 #endif
8324 start_process_time(pbi);
8325 pbi->process_busy = 0;
8326 return IRQ_HANDLED;
8327 } else
8328 #endif
8329 {
8330 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8331 int ii;
8332 for (ii = 0; ii < 4; ii++)
8333 vp9_param.l.data[i + ii] =
8334 pbi->rpm_ptr[i + 3 - ii];
8335 }
8336 }
8337 }
8338
8339 if (pbi->is_used_v4l) {
8340 struct aml_vcodec_ctx *ctx =
8341 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8342
8343 pbi->frame_width = vp9_param.p.width;
8344 pbi->frame_height = vp9_param.p.height;
8345 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8346 struct aml_vdec_ps_infos ps;
8347
8348 ps.visible_width = pbi->frame_width;
8349 ps.visible_height = pbi->frame_height;
8350 ps.coded_width = ALIGN(pbi->frame_width, 32);
8351 ps.coded_height = ALIGN(pbi->frame_height, 32);
8352 ps.dpb_size = pbi->used_buf_num;
8353 pbi->v4l_params_parsed = true;
8354 vdec_v4l_set_ps_infos(ctx, &ps);
8355 }
8356 }
8357
8358 if (pbi->is_used_v4l) {
8359 pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8360 vdec_schedule_work(&pbi->work);
8361 } else {
8362 continue_decoding(pbi);
8363 pbi->postproc_done = 0;
8364 pbi->process_busy = 0;
8365 }
8366
8367 #ifdef MULTI_INSTANCE_SUPPORT
8368 if (pbi->m_ins_flag)
8369 start_process_time(pbi);
8370 #endif
8371
8372 return IRQ_HANDLED;
8373 }
8374
8375 static irqreturn_t vvp9_isr(int irq, void *data)
8376 {
8377 int i;
8378 unsigned int dec_status;
8379 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8380 unsigned int adapt_prob_status;
8381 struct VP9_Common_s *const cm = &pbi->common;
8382 uint debug_tag;
8383
8384 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8385
8386 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8387 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8388 if (!pbi)
8389 return IRQ_HANDLED;
8390 if (pbi->init_flag == 0)
8391 return IRQ_HANDLED;
8392 if (pbi->process_busy)/*on process.*/
8393 return IRQ_HANDLED;
8394 pbi->dec_status = dec_status;
8395 pbi->process_busy = 1;
8396 if (debug & VP9_DEBUG_BUFMGR)
8397 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8398 irq,
8399 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8400 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8401 READ_VREG(HEVC_STREAM_START_ADDR),
8402 READ_VREG(HEVC_STREAM_END_ADDR),
8403 READ_VREG(HEVC_STREAM_LEVEL),
8404 READ_VREG(HEVC_STREAM_WR_PTR),
8405 READ_VREG(HEVC_STREAM_RD_PTR)
8406 );
8407 #ifdef SUPPORT_FB_DECODING
8408 /*if (irq != VDEC_IRQ_0)
8409 return IRQ_WAKE_THREAD;*/
8410 #endif
8411
8412 debug_tag = READ_HREG(DEBUG_REG1);
8413 if (debug_tag & 0x10000) {
8414 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8415 for (i = 0; i < 0x400; i += 4) {
8416 int ii;
8417 if ((i & 0xf) == 0)
8418 pr_info("%03x: ", i);
8419 for (ii = 0; ii < 4; ii++) {
8420 pr_info("%04x ",
8421 pbi->lmem_ptr[i + 3 - ii]);
8422 }
8423 if (((i + ii) & 0xf) == 0)
8424 pr_info("\n");
8425 }
8426
8427 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8428 (udebug_pause_decode_idx == 0 ||
8429 udebug_pause_decode_idx == pbi->slice_idx) &&
8430 (udebug_pause_val == 0 ||
8431 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8432 pbi->ucode_pause_pos = udebug_pause_pos;
8433 else if (debug_tag & 0x20000)
8434 pbi->ucode_pause_pos = 0xffffffff;
8435 if (pbi->ucode_pause_pos)
8436 reset_process_time(pbi);
8437 else
8438 WRITE_HREG(DEBUG_REG1, 0);
8439 } else if (debug_tag != 0) {
8440 pr_info(
8441 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8442 READ_HREG(DEBUG_REG2),
8443 READ_VREG(HEVC_PARSER_LCU_START));
8444 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8445 (udebug_pause_decode_idx == 0 ||
8446 udebug_pause_decode_idx == pbi->slice_idx) &&
8447 (udebug_pause_val == 0 ||
8448 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8449 pbi->ucode_pause_pos = udebug_pause_pos;
8450 if (pbi->ucode_pause_pos)
8451 reset_process_time(pbi);
8452 else
8453 WRITE_HREG(DEBUG_REG1, 0);
8454 pbi->process_busy = 0;
8455 return IRQ_HANDLED;
8456 }
8457
8458 #ifdef MULTI_INSTANCE_SUPPORT
8459 if (!pbi->m_ins_flag) {
8460 #endif
8461 if (pbi->error_flag == 1) {
8462 pbi->error_flag = 2;
8463 pbi->process_busy = 0;
8464 return IRQ_HANDLED;
8465 } else if (pbi->error_flag == 3) {
8466 pbi->process_busy = 0;
8467 return IRQ_HANDLED;
8468 }
8469
8470 if (get_free_buf_count(pbi) <= 0) {
8471 /*
8472 if (pbi->wait_buf == 0)
8473 pr_info("set wait_buf to 1\r\n");
8474 */
8475 pbi->wait_buf = 1;
8476 pbi->process_busy = 0;
8477 return IRQ_HANDLED;
8478 }
8479 #ifdef MULTI_INSTANCE_SUPPORT
8480 }
8481 #endif
8482 if ((adapt_prob_status & 0xff) == 0xfd) {
8483 /*VP9_REQ_ADAPT_PROB*/
8484 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8485 uint8_t *prev_prob_b =
8486 ((uint8_t *)pbi->prob_buffer_addr) +
8487 ((adapt_prob_status >> 8) * 0x1000);
8488 uint8_t *cur_prob_b =
8489 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8490 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8491 #ifdef MULTI_INSTANCE_SUPPORT
8492 if (pbi->m_ins_flag)
8493 reset_process_time(pbi);
8494 #endif
8495 adapt_coef_probs(pbi->pic_count,
8496 (cm->last_frame_type == KEY_FRAME),
8497 pre_fc, (adapt_prob_status >> 8),
8498 (unsigned int *)prev_prob_b,
8499 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8500
8501 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8502 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8503 pbi->pic_count += 1;
8504 #ifdef MULTI_INSTANCE_SUPPORT
8505 if (pbi->m_ins_flag)
8506 start_process_time(pbi);
8507 #endif
8508
8509 /*return IRQ_HANDLED;*/
8510 }
8511 return IRQ_WAKE_THREAD;
8512 }
8513
8514 static void vp9_set_clk(struct work_struct *work)
8515 {
8516 struct VP9Decoder_s *pbi = container_of(work,
8517 struct VP9Decoder_s, set_clk_work);
8518 int fps = 96000 / pbi->frame_dur;
8519
8520 if (hevc_source_changed(VFORMAT_VP9,
8521 frame_width, frame_height, fps) > 0)
8522 pbi->saved_resolution = frame_width *
8523 frame_height * fps;
8524 }
8525
8526 static void vvp9_put_timer_func(unsigned long arg)
8527 {
8528 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8529 struct timer_list *timer = &pbi->timer;
8530 uint8_t empty_flag;
8531 unsigned int buf_level;
8532
8533 enum receviver_start_e state = RECEIVER_INACTIVE;
8534
8535 if (pbi->m_ins_flag) {
8536 if (hw_to_vdec(pbi)->next_status
8537 == VDEC_STATUS_DISCONNECTED) {
8538 #ifdef SUPPORT_FB_DECODING
8539 if (pbi->run2_busy)
8540 return;
8541
8542 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8543 vdec_schedule_work(&pbi->s1_work);
8544 #endif
8545 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8546 vdec_schedule_work(&pbi->work);
8547 pr_debug(
8548 "vdec requested to be disconnected\n");
8549 return;
8550 }
8551 }
8552 if (pbi->init_flag == 0) {
8553 if (pbi->stat & STAT_TIMER_ARM) {
8554 timer->expires = jiffies + PUT_INTERVAL;
8555 add_timer(&pbi->timer);
8556 }
8557 return;
8558 }
8559 if (pbi->m_ins_flag == 0) {
8560 if (vf_get_receiver(pbi->provider_name)) {
8561 state =
8562 vf_notify_receiver(pbi->provider_name,
8563 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8564 NULL);
8565 if ((state == RECEIVER_STATE_NULL)
8566 || (state == RECEIVER_STATE_NONE))
8567 state = RECEIVER_INACTIVE;
8568 } else
8569 state = RECEIVER_INACTIVE;
8570
8571 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8572 /* error watchdog */
8573 if (empty_flag == 0) {
8574 /* decoder has input */
8575 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8576
8577 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8578 /* receiver has no buffer to recycle */
8579 if ((state == RECEIVER_INACTIVE) &&
8580 (kfifo_is_empty(&pbi->display_q) &&
8581 buf_level > 0x200)
8582 ) {
8583 WRITE_VREG
8584 (HEVC_ASSIST_MBOX0_IRQ_REG,
8585 0x1);
8586 }
8587 }
8588
8589 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8590 /* receiver has no buffer to recycle */
8591 /*if ((state == RECEIVER_INACTIVE) &&
8592 * (kfifo_is_empty(&pbi->display_q))) {
8593 *pr_info("vp9 something error,need reset\n");
8594 *}
8595 */
8596 }
8597 }
8598 }
8599 #ifdef MULTI_INSTANCE_SUPPORT
8600 else {
8601 if (
8602 (decode_timeout_val > 0) &&
8603 (pbi->start_process_time > 0) &&
8604 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8605 > decode_timeout_val)
8606 ) {
8607 int current_lcu_idx =
8608 READ_VREG(HEVC_PARSER_LCU_START)
8609 & 0xffffff;
8610 if (pbi->last_lcu_idx == current_lcu_idx) {
8611 if (pbi->decode_timeout_count > 0)
8612 pbi->decode_timeout_count--;
8613 if (pbi->decode_timeout_count == 0) {
8614 if (input_frame_based(
8615 hw_to_vdec(pbi)) ||
8616 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8617 timeout_process(pbi);
8618 else {
8619 vp9_print(pbi, 0,
8620 "timeout & empty, again\n");
8621 dec_again_process(pbi);
8622 }
8623 }
8624 } else {
8625 start_process_time(pbi);
8626 pbi->last_lcu_idx = current_lcu_idx;
8627 }
8628 }
8629 }
8630 #endif
8631
8632 if ((pbi->ucode_pause_pos != 0) &&
8633 (pbi->ucode_pause_pos != 0xffffffff) &&
8634 udebug_pause_pos != pbi->ucode_pause_pos) {
8635 pbi->ucode_pause_pos = 0;
8636 WRITE_HREG(DEBUG_REG1, 0);
8637 }
8638 #ifdef MULTI_INSTANCE_SUPPORT
8639 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8640 pr_info(
8641 "Force Send Again\r\n");
8642 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8643 reset_process_time(pbi);
8644 pbi->dec_result = DEC_RESULT_AGAIN;
8645 if (pbi->process_state ==
8646 PROC_STATE_DECODESLICE) {
8647 if (pbi->mmu_enable)
8648 vp9_recycle_mmu_buf(pbi);
8649 pbi->process_state =
8650 PROC_STATE_SENDAGAIN;
8651 }
8652 amhevc_stop();
8653
8654 vdec_schedule_work(&pbi->work);
8655 }
8656
8657 if (debug & VP9_DEBUG_DUMP_DATA) {
8658 debug &= ~VP9_DEBUG_DUMP_DATA;
8659 vp9_print(pbi, 0,
8660 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8661 __func__,
8662 pbi->chunk->size,
8663 pbi->chunk->offset,
8664 get_data_check_sum(pbi, pbi->chunk->size)
8665 );
8666 dump_data(pbi, pbi->chunk->size);
8667 }
8668 #endif
8669 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8670 dump_pic_list(pbi);
8671 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8672 }
8673 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8674 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8675 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8676 }
8677 /*if (debug & VP9_DEBUG_HW_RESET) {
8678 }*/
8679
8680 if (radr != 0) {
8681 if (rval != 0) {
8682 WRITE_VREG(radr, rval);
8683 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8684 } else
8685 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8686 rval = 0;
8687 radr = 0;
8688 }
8689 if (pop_shorts != 0) {
8690 int i;
8691 u32 sum = 0;
8692
8693 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8694 for (i = 0; i < pop_shorts; i++) {
8695 u32 data =
8696 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8697 WRITE_HREG(HEVC_SHIFT_COMMAND,
8698 (1<<7)|16);
8699 if ((i & 0xf) == 0)
8700 pr_info("%04x:", i);
8701 pr_info("%04x ", data);
8702 if (((i + 1) & 0xf) == 0)
8703 pr_info("\r\n");
8704 sum += data;
8705 }
8706 pr_info("\r\nsum = %x\r\n", sum);
8707 pop_shorts = 0;
8708 }
8709 if (dbg_cmd != 0) {
8710 if (dbg_cmd == 1) {
8711 u32 disp_laddr;
8712
8713 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8714 get_double_write_mode(pbi) == 0) {
8715 disp_laddr =
8716 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8717 } else {
8718 struct canvas_s cur_canvas;
8719
8720 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8721 & 0xff), &cur_canvas);
8722 disp_laddr = cur_canvas.addr;
8723 }
8724 pr_info("current displayed buffer address %x\r\n",
8725 disp_laddr);
8726 }
8727 dbg_cmd = 0;
8728 }
8729 /*don't changed at start.*/
8730 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8731 pbi->frame_dur > 0 && pbi->saved_resolution !=
8732 frame_width * frame_height *
8733 (96000 / pbi->frame_dur))
8734 vdec_schedule_work(&pbi->set_clk_work);
8735
8736 timer->expires = jiffies + PUT_INTERVAL;
8737 add_timer(timer);
8738 }
8739
8740
8741 int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8742 {
8743 struct VP9Decoder_s *vp9 =
8744 (struct VP9Decoder_s *)vdec->private;
8745
8746 if (!vp9)
8747 return -1;
8748
8749 vstatus->frame_width = frame_width;
8750 vstatus->frame_height = frame_height;
8751 if (vp9->frame_dur != 0)
8752 vstatus->frame_rate = 96000 / vp9->frame_dur;
8753 else
8754 vstatus->frame_rate = -1;
8755 vstatus->error_count = 0;
8756 vstatus->status = vp9->stat | vp9->fatal_error;
8757 vstatus->frame_dur = vp9->frame_dur;
8758 #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8759 vstatus->bit_rate = gvs->bit_rate;
8760 vstatus->frame_data = gvs->frame_data;
8761 vstatus->total_data = gvs->total_data;
8762 vstatus->frame_count = gvs->frame_count;
8763 vstatus->error_frame_count = gvs->error_frame_count;
8764 vstatus->drop_frame_count = gvs->drop_frame_count;
8765 vstatus->total_data = gvs->total_data;
8766 vstatus->samp_cnt = gvs->samp_cnt;
8767 vstatus->offset = gvs->offset;
8768 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8769 "%s", DRIVER_NAME);
8770 #endif
8771 return 0;
8772 }
8773
8774 int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8775 {
8776 is_reset = isreset;
8777 return 0;
8778 }
8779
8780 #if 0
8781 static void VP9_DECODE_INIT(void)
8782 {
8783 /* enable vp9 clocks */
8784 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8785 /* *************************************************************** */
8786 /* Power ON HEVC */
8787 /* *************************************************************** */
8788 /* Powerup HEVC */
8789 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8790 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8791 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8792 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8793 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8794 /* remove isolations */
8795 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8796 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8797
8798 }
8799 #endif
8800
8801 static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8802 {
8803 unsigned int data32;
8804 /* VP9_DECODE_INIT(); */
8805 vp9_config_work_space_hw(pbi, mask);
8806 if (mask & HW_MASK_BACK)
8807 init_pic_list_hw(pbi);
8808
8809 vp9_init_decoder_hw(pbi, mask);
8810
8811 #ifdef VP9_LPF_LVL_UPDATE
8812 if (mask & HW_MASK_BACK)
8813 vp9_loop_filter_init(pbi);
8814 #endif
8815
8816 if ((mask & HW_MASK_FRONT) == 0)
8817 return;
8818 #if 1
8819 if (debug & VP9_DEBUG_BUFMGR_MORE)
8820 pr_info("%s\n", __func__);
8821 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8822 data32 = data32 |
8823 (1 << 0)/*stream_fetch_enable*/
8824 ;
8825 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8826
8827 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8828 if (debug & VP9_DEBUG_BUFMGR)
8829 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8830 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8831 data32 = data32 |
8832 (1 << 29) // stream_fifo_hole
8833 ;
8834 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8835 }
8836 #if 0
8837 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8838 if (data32 != 0x00000100) {
8839 pr_info("vp9 prot init error %d\n", __LINE__);
8840 return;
8841 }
8842 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8843 if (data32 != 0x00000300) {
8844 pr_info("vp9 prot init error %d\n", __LINE__);
8845 return;
8846 }
8847 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8848 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8849 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8850 if (data32 != 0x12345678) {
8851 pr_info("vp9 prot init error %d\n", __LINE__);
8852 return;
8853 }
8854 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8855 if (data32 != 0x9abcdef0) {
8856 pr_info("vp9 prot init error %d\n", __LINE__);
8857 return;
8858 }
8859 #endif
8860 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8861 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8862 #endif
8863
8864
8865
8866 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8867
8868 /* WRITE_VREG(HEVC_MPSR, 1); */
8869
8870 /* clear mailbox interrupt */
8871 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8872
8873 /* enable mailbox interrupt */
8874 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8875
8876 /* disable PSCALE for hardware sharing */
8877 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8878
8879 WRITE_VREG(DEBUG_REG1, 0x0);
8880 /*check vps/sps/pps/i-slice in ucode*/
8881 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8882
8883 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8884 #ifdef SUPPORT_FB_DECODING
8885 #ifndef FB_DECODING_TEST_SCHEDULE
8886 if (pbi->used_stage_buf_num > 0) {
8887 if (mask & HW_MASK_FRONT) {
8888 data32 = READ_VREG(
8889 HEVC_ASSIST_HED_FB_W_CTL);
8890 data32 = data32 |
8891 (1 << 0) /*hed_fb_wr_en*/
8892 ;
8893 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8894 data32);
8895 }
8896 if (mask & HW_MASK_BACK) {
8897 data32 = READ_VREG(
8898 HEVC_ASSIST_HED_FB_R_CTL);
8899 while (data32 & (1 << 7)) {
8900 /*wait finish*/
8901 data32 = READ_VREG(
8902 HEVC_ASSIST_HED_FB_R_CTL);
8903 }
8904 data32 &= (~(0x1 << 0));
8905 /*hed_fb_rd_addr_auto_rd*/
8906 data32 &= (~(0x1 << 1));
8907 /*rd_id = 0, hed_rd_map_auto_halt_num,
8908 after wr 2 ready, then start reading*/
8909 data32 |= (0x2 << 16);
8910 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8911 data32);
8912
8913 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8914 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8915 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8916 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8917 data32);
8918 }
8919
8920 }
8921 #endif
8922 #endif
8923 }
8924
8925 static int vvp9_local_init(struct VP9Decoder_s *pbi)
8926 {
8927 int i;
8928 int ret;
8929 int width, height;
8930 if (alloc_lf_buf(pbi) < 0)
8931 return -1;
8932
8933 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8934 if (NULL == pbi->gvs) {
8935 pr_info("the struct of vdec status malloc failed.\n");
8936 return -1;
8937 }
8938 #ifdef DEBUG_PTS
8939 pbi->pts_missed = 0;
8940 pbi->pts_hit = 0;
8941 #endif
8942 pbi->new_frame_displayed = 0;
8943 pbi->last_put_idx = -1;
8944 pbi->saved_resolution = 0;
8945 pbi->get_frame_dur = false;
8946 on_no_keyframe_skiped = 0;
8947 pbi->duration_from_pts_done = 0;
8948 pbi->vp9_first_pts_ready = 0;
8949 pbi->frame_cnt_window = 0;
8950 width = pbi->vvp9_amstream_dec_info.width;
8951 height = pbi->vvp9_amstream_dec_info.height;
8952 pbi->frame_dur =
8953 (pbi->vvp9_amstream_dec_info.rate ==
8954 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8955 if (width && height)
8956 pbi->frame_ar = height * 0x100 / width;
8957 /*
8958 *TODO:FOR VERSION
8959 */
8960 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8961 0, width, height, pbi->frame_dur);
8962
8963 if (pbi->frame_dur == 0)
8964 pbi->frame_dur = 96000 / 24;
8965
8966 INIT_KFIFO(pbi->display_q);
8967 INIT_KFIFO(pbi->newframe_q);
8968
8969
8970 for (i = 0; i < VF_POOL_SIZE; i++) {
8971 const struct vframe_s *vf = &pbi->vfpool[i];
8972
8973 pbi->vfpool[i].index = -1;
8974 kfifo_put(&pbi->newframe_q, vf);
8975 }
8976
8977
8978 ret = vp9_local_init(pbi);
8979
8980 if (!pbi->pts_unstable) {
8981 pbi->pts_unstable =
8982 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8983 pr_info("set pts unstable\n");
8984 }
8985
8986 return ret;
8987 }
8988
8989
8990 #ifdef MULTI_INSTANCE_SUPPORT
8991 static s32 vvp9_init(struct vdec_s *vdec)
8992 {
8993 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8994 #else
8995 static s32 vvp9_init(struct VP9Decoder_s *pbi)
8996 {
8997 #endif
8998 int ret;
8999 int fw_size = 0x1000 * 16;
9000 struct firmware_s *fw = NULL;
9001
9002 pbi->stat |= STAT_TIMER_INIT;
9003
9004 if (vvp9_local_init(pbi) < 0)
9005 return -EBUSY;
9006
9007 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
9008 if (IS_ERR_OR_NULL(fw))
9009 return -ENOMEM;
9010
9011 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
9012 pr_err("get firmware fail.\n");
9013 vfree(fw);
9014 return -1;
9015 }
9016
9017 fw->len = fw_size;
9018
9019 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
9020 init_timer(&pbi->timer);
9021
9022 #ifdef MULTI_INSTANCE_SUPPORT
9023 if (pbi->m_ins_flag) {
9024 pbi->timer.data = (ulong) pbi;
9025 pbi->timer.function = vvp9_put_timer_func;
9026 pbi->timer.expires = jiffies + PUT_INTERVAL;
9027
9028 /*add_timer(&pbi->timer);
9029
9030 pbi->stat |= STAT_TIMER_ARM;
9031 pbi->stat |= STAT_ISR_REG;*/
9032
9033 INIT_WORK(&pbi->work, vp9_work);
9034 INIT_WORK(&pbi->recycle_mmu_work, vp9_recycle_mmu_work);
9035 #ifdef SUPPORT_FB_DECODING
9036 if (pbi->used_stage_buf_num > 0)
9037 INIT_WORK(&pbi->s1_work, vp9_s1_work);
9038 #endif
9039 pbi->fw = fw;
9040
9041 /* picture list init.*/
9042 pbi->dec_result = DEC_INIT_PICLIST;
9043 vdec_schedule_work(&pbi->work);
9044
9045 return 0;
9046 }
9047 #endif
9048 amhevc_enable();
9049
9050 init_pic_list(pbi);
9051
9052 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9053 if (ret < 0) {
9054 amhevc_disable();
9055 vfree(fw);
9056 pr_err("VP9: the %s fw loading failed, err: %x\n",
9057 tee_enabled() ? "TEE" : "local", ret);
9058 return -EBUSY;
9059 }
9060
9061 vfree(fw);
9062
9063 pbi->stat |= STAT_MC_LOAD;
9064
9065 /* enable AMRISC side protocol */
9066 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9067
9068 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9069 vvp9_isr,
9070 vvp9_isr_thread_fn,
9071 IRQF_ONESHOT,/*run thread on this irq disabled*/
9072 "vvp9-irq", (void *)pbi)) {
9073 pr_info("vvp9 irq register error.\n");
9074 amhevc_disable();
9075 return -ENOENT;
9076 }
9077
9078 pbi->stat |= STAT_ISR_REG;
9079
9080 pbi->provider_name = PROVIDER_NAME;
9081 #ifdef MULTI_INSTANCE_SUPPORT
9082 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9083 &vvp9_vf_provider, pbi);
9084 vf_reg_provider(&vvp9_vf_prov);
9085 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9086 if (pbi->frame_dur != 0) {
9087 if (!is_reset)
9088 vf_notify_receiver(pbi->provider_name,
9089 VFRAME_EVENT_PROVIDER_FR_HINT,
9090 (void *)
9091 ((unsigned long)pbi->frame_dur));
9092 }
9093 #else
9094 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9095 pbi);
9096 vf_reg_provider(&vvp9_vf_prov);
9097 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9098 if (!is_reset)
9099 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9100 (void *)((unsigned long)pbi->frame_dur));
9101 #endif
9102 pbi->stat |= STAT_VF_HOOK;
9103
9104 pbi->timer.data = (ulong)pbi;
9105 pbi->timer.function = vvp9_put_timer_func;
9106 pbi->timer.expires = jiffies + PUT_INTERVAL;
9107
9108 pbi->stat |= STAT_VDEC_RUN;
9109
9110 add_timer(&pbi->timer);
9111
9112 pbi->stat |= STAT_TIMER_ARM;
9113
9114 amhevc_start();
9115
9116 pbi->init_flag = 1;
9117 pbi->process_busy = 0;
9118 pr_info("%d, vvp9_init, RP=0x%x\n",
9119 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9120 return 0;
9121 }
9122
9123 static int vmvp9_stop(struct VP9Decoder_s *pbi)
9124 {
9125 pbi->init_flag = 0;
9126
9127 if (pbi->stat & STAT_VDEC_RUN) {
9128 amhevc_stop();
9129 pbi->stat &= ~STAT_VDEC_RUN;
9130 }
9131 if (pbi->stat & STAT_ISR_REG) {
9132 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9133 pbi->stat &= ~STAT_ISR_REG;
9134 }
9135 if (pbi->stat & STAT_TIMER_ARM) {
9136 del_timer_sync(&pbi->timer);
9137 pbi->stat &= ~STAT_TIMER_ARM;
9138 }
9139
9140 if (pbi->stat & STAT_VF_HOOK) {
9141 if (!is_reset)
9142 vf_notify_receiver(pbi->provider_name,
9143 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9144 NULL);
9145
9146 vf_unreg_provider(&vvp9_vf_prov);
9147 pbi->stat &= ~STAT_VF_HOOK;
9148 }
9149 vp9_local_uninit(pbi);
9150 reset_process_time(pbi);
9151 cancel_work_sync(&pbi->work);
9152 cancel_work_sync(&pbi->recycle_mmu_work);
9153 #ifdef SUPPORT_FB_DECODING
9154 if (pbi->used_stage_buf_num > 0)
9155 cancel_work_sync(&pbi->s1_work);
9156 #endif
9157 cancel_work_sync(&pbi->set_clk_work);
9158 uninit_mmu_buffers(pbi);
9159 if (pbi->fw)
9160 vfree(pbi->fw);
9161 pbi->fw = NULL;
9162 return 0;
9163 }
9164
9165 static int vvp9_stop(struct VP9Decoder_s *pbi)
9166 {
9167
9168 pbi->init_flag = 0;
9169 pbi->first_sc_checked = 0;
9170 if (pbi->stat & STAT_VDEC_RUN) {
9171 amhevc_stop();
9172 pbi->stat &= ~STAT_VDEC_RUN;
9173 }
9174
9175 if (pbi->stat & STAT_ISR_REG) {
9176 #ifdef MULTI_INSTANCE_SUPPORT
9177 if (!pbi->m_ins_flag)
9178 #endif
9179 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9180 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9181 pbi->stat &= ~STAT_ISR_REG;
9182 }
9183
9184 if (pbi->stat & STAT_TIMER_ARM) {
9185 del_timer_sync(&pbi->timer);
9186 pbi->stat &= ~STAT_TIMER_ARM;
9187 }
9188
9189 if (pbi->stat & STAT_VF_HOOK) {
9190 if (!is_reset)
9191 vf_notify_receiver(pbi->provider_name,
9192 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9193 NULL);
9194
9195 vf_unreg_provider(&vvp9_vf_prov);
9196 pbi->stat &= ~STAT_VF_HOOK;
9197 }
9198 vp9_local_uninit(pbi);
9199
9200 cancel_work_sync(&pbi->set_clk_work);
9201 #ifdef MULTI_INSTANCE_SUPPORT
9202 if (pbi->m_ins_flag) {
9203 #ifdef SUPPORT_FB_DECODING
9204 if (pbi->used_stage_buf_num > 0)
9205 cancel_work_sync(&pbi->s1_work);
9206 #endif
9207 cancel_work_sync(&pbi->work);
9208 cancel_work_sync(&pbi->recycle_mmu_work);
9209 } else
9210 amhevc_disable();
9211 #else
9212 amhevc_disable();
9213 #endif
9214 uninit_mmu_buffers(pbi);
9215
9216 vfree(pbi->fw);
9217 pbi->fw = NULL;
9218 return 0;
9219 }
9220 static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9221 {
9222 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9223 CODEC_MM_FLAGS_TVP : 0;
9224 int buf_size = 48;
9225
9226 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9227 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9228 buf_size = 12;
9229 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9230 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9231 buf_size = 4;
9232 }
9233 pbi->need_cache_size = buf_size * SZ_1M;
9234 pbi->sc_start_time = get_jiffies_64();
9235 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9236 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9237 pbi->index, FRAME_BUFFERS,
9238 pbi->need_cache_size,
9239 tvp_flag
9240 );
9241 if (!pbi->mmu_box) {
9242 pr_err("vp9 alloc mmu box failed!!\n");
9243 return -1;
9244 }
9245 }
9246 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9247 DRIVER_NAME,
9248 pbi->index,
9249 MAX_BMMU_BUFFER_NUM,
9250 4 + PAGE_SHIFT,
9251 CODEC_MM_FLAGS_CMA_CLEAR |
9252 CODEC_MM_FLAGS_FOR_VDECODER |
9253 tvp_flag);
9254 if (!pbi->bmmu_box) {
9255 pr_err("vp9 alloc bmmu box failed!!\n");
9256 return -1;
9257 }
9258 return 0;
9259 }
9260
9261 static struct VP9Decoder_s *gHevc;
9262
9263 static int amvdec_vp9_probe(struct platform_device *pdev)
9264 {
9265 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9266 struct BUF_s BUF[MAX_BUF_NUM];
9267 struct VP9Decoder_s *pbi;
9268 int ret;
9269 #ifndef MULTI_INSTANCE_SUPPORT
9270 int i;
9271 #endif
9272 pr_debug("%s\n", __func__);
9273
9274 mutex_lock(&vvp9_mutex);
9275 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9276 if (pbi == NULL) {
9277 pr_info("\namvdec_vp9 device data allocation failed\n");
9278 mutex_unlock(&vvp9_mutex);
9279 return -ENOMEM;
9280 }
9281
9282 gHevc = pbi;
9283 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9284 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9285 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9286
9287 pbi->init_flag = 0;
9288 pbi->first_sc_checked= 0;
9289 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9290 vp9_max_pic_w = 8192;
9291 vp9_max_pic_h = 4608;
9292 }
9293 pbi->max_pic_w = vp9_max_pic_w;
9294 pbi->max_pic_h = vp9_max_pic_h;
9295
9296 #ifdef MULTI_INSTANCE_SUPPORT
9297 pbi->eos = 0;
9298 pbi->start_process_time = 0;
9299 pbi->timeout_num = 0;
9300 #endif
9301 pbi->fatal_error = 0;
9302 pbi->show_frame_num = 0;
9303 if (pdata == NULL) {
9304 pr_info("\namvdec_vp9 memory resource undefined.\n");
9305 vfree(pbi);
9306 mutex_unlock(&vvp9_mutex);
9307 return -EFAULT;
9308 }
9309 pbi->m_ins_flag = 0;
9310 #ifdef MULTI_INSTANCE_SUPPORT
9311 pbi->platform_dev = pdev;
9312 platform_set_drvdata(pdev, pdata);
9313 #endif
9314 pbi->double_write_mode = double_write_mode;
9315 pbi->mmu_enable = 1;
9316 if (amvdec_vp9_mmu_init(pbi) < 0) {
9317 vfree(pbi);
9318 mutex_unlock(&vvp9_mutex);
9319 pr_err("vp9 alloc bmmu box failed!!\n");
9320 return -1;
9321 }
9322
9323 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9324 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9325 if (ret < 0) {
9326 uninit_mmu_buffers(pbi);
9327 vfree(pbi);
9328 mutex_unlock(&vvp9_mutex);
9329 return ret;
9330 }
9331 pbi->buf_size = work_buf_size;
9332
9333 #ifdef MULTI_INSTANCE_SUPPORT
9334 pbi->buf_start = pdata->mem_start;
9335 #else
9336 if (!pbi->mmu_enable)
9337 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9338
9339 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9340 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9341 #endif
9342
9343
9344 if (debug) {
9345 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9346 pdata->mem_start, pbi->buf_size);
9347 }
9348
9349 if (pdata->sys_info)
9350 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9351 else {
9352 pbi->vvp9_amstream_dec_info.width = 0;
9353 pbi->vvp9_amstream_dec_info.height = 0;
9354 pbi->vvp9_amstream_dec_info.rate = 30;
9355 }
9356 pbi->no_head = no_head;
9357 #ifdef MULTI_INSTANCE_SUPPORT
9358 pbi->cma_dev = pdata->cma_dev;
9359 #else
9360 cma_dev = pdata->cma_dev;
9361 #endif
9362
9363 #ifdef MULTI_INSTANCE_SUPPORT
9364 pdata->private = pbi;
9365 pdata->dec_status = vvp9_dec_status;
9366 pdata->set_isreset = vvp9_set_isreset;
9367 is_reset = 0;
9368 if (vvp9_init(pdata) < 0) {
9369 #else
9370 if (vvp9_init(pbi) < 0) {
9371 #endif
9372 pr_info("\namvdec_vp9 init failed.\n");
9373 vp9_local_uninit(pbi);
9374 uninit_mmu_buffers(pbi);
9375 vfree(pbi);
9376 pdata->dec_status = NULL;
9377 mutex_unlock(&vvp9_mutex);
9378 return -ENODEV;
9379 }
9380 /*set the max clk for smooth playing...*/
9381 hevc_source_changed(VFORMAT_VP9,
9382 4096, 2048, 60);
9383 mutex_unlock(&vvp9_mutex);
9384
9385 return 0;
9386 }
9387
9388 static int amvdec_vp9_remove(struct platform_device *pdev)
9389 {
9390 struct VP9Decoder_s *pbi = gHevc;
9391 struct vdec_s *vdec = hw_to_vdec(pbi);
9392 int i;
9393
9394 if (debug)
9395 pr_info("amvdec_vp9_remove\n");
9396
9397 mutex_lock(&vvp9_mutex);
9398
9399 vvp9_stop(pbi);
9400
9401 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9402
9403 if (vdec->parallel_dec == 1) {
9404 for (i = 0; i < FRAME_BUFFERS; i++) {
9405 vdec->free_canvas_ex(pbi->common.buffer_pool->
9406 frame_bufs[i].buf.y_canvas_index, vdec->id);
9407 vdec->free_canvas_ex(pbi->common.buffer_pool->
9408 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9409 }
9410 }
9411
9412 #ifdef DEBUG_PTS
9413 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9414 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9415 #endif
9416 mem_map_mode = 0;
9417
9418 vfree(pbi);
9419 mutex_unlock(&vvp9_mutex);
9420
9421 return 0;
9422 }
9423
9424 /****************************************/
9425 #ifdef CONFIG_PM
9426 static int vp9_suspend(struct device *dev)
9427 {
9428 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9429 return 0;
9430 }
9431
9432 static int vp9_resume(struct device *dev)
9433 {
9434 amhevc_resume(to_platform_device(dev));
9435 return 0;
9436 }
9437
9438 static const struct dev_pm_ops vp9_pm_ops = {
9439 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9440 };
9441 #endif
9442
9443 static struct platform_driver amvdec_vp9_driver = {
9444 .probe = amvdec_vp9_probe,
9445 .remove = amvdec_vp9_remove,
9446 .driver = {
9447 .name = DRIVER_NAME,
9448 #ifdef CONFIG_PM
9449 .pm = &vp9_pm_ops,
9450 #endif
9451 }
9452 };
9453
9454 static struct codec_profile_t amvdec_vp9_profile = {
9455 .name = "vp9",
9456 .profile = ""
9457 };
9458
9459 static struct codec_profile_t amvdec_vp9_profile_mult;
9460
9461 static unsigned char get_data_check_sum
9462 (struct VP9Decoder_s *pbi, int size)
9463 {
9464 int jj;
9465 int sum = 0;
9466 u8 *data = NULL;
9467
9468 if (!pbi->chunk->block->is_mapped)
9469 data = codec_mm_vmap(pbi->chunk->block->start +
9470 pbi->chunk->offset, size);
9471 else
9472 data = ((u8 *)pbi->chunk->block->start_virt) +
9473 pbi->chunk->offset;
9474
9475 for (jj = 0; jj < size; jj++)
9476 sum += data[jj];
9477
9478 if (!pbi->chunk->block->is_mapped)
9479 codec_mm_unmap_phyaddr(data);
9480 return sum;
9481 }
9482
9483 static void dump_data(struct VP9Decoder_s *pbi, int size)
9484 {
9485 int jj;
9486 u8 *data = NULL;
9487 int padding_size = pbi->chunk->offset &
9488 (VDEC_FIFO_ALIGN - 1);
9489
9490 if (!pbi->chunk->block->is_mapped)
9491 data = codec_mm_vmap(pbi->chunk->block->start +
9492 pbi->chunk->offset, size);
9493 else
9494 data = ((u8 *)pbi->chunk->block->start_virt) +
9495 pbi->chunk->offset;
9496
9497 vp9_print(pbi, 0, "padding: ");
9498 for (jj = padding_size; jj > 0; jj--)
9499 vp9_print_cont(pbi,
9500 0,
9501 "%02x ", *(data - jj));
9502 vp9_print_cont(pbi, 0, "data adr %p\n",
9503 data);
9504
9505 for (jj = 0; jj < size; jj++) {
9506 if ((jj & 0xf) == 0)
9507 vp9_print(pbi,
9508 0,
9509 "%06x:", jj);
9510 vp9_print_cont(pbi,
9511 0,
9512 "%02x ", data[jj]);
9513 if (((jj + 1) & 0xf) == 0)
9514 vp9_print(pbi,
9515 0,
9516 "\n");
9517 }
9518 vp9_print(pbi,
9519 0,
9520 "\n");
9521
9522 if (!pbi->chunk->block->is_mapped)
9523 codec_mm_unmap_phyaddr(data);
9524 }
9525
9526 static void vp9_work(struct work_struct *work)
9527 {
9528 struct VP9Decoder_s *pbi = container_of(work,
9529 struct VP9Decoder_s, work);
9530 struct vdec_s *vdec = hw_to_vdec(pbi);
9531 /* finished decoding one frame or error,
9532 * notify vdec core to switch context
9533 */
9534 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9535 "%s dec_result %d %x %x %x\n",
9536 __func__,
9537 pbi->dec_result,
9538 READ_VREG(HEVC_STREAM_LEVEL),
9539 READ_VREG(HEVC_STREAM_WR_PTR),
9540 READ_VREG(HEVC_STREAM_RD_PTR));
9541
9542 if (pbi->dec_result == DEC_INIT_PICLIST) {
9543 init_pic_list(pbi);
9544 pbi->pic_list_init_done = true;
9545 return;
9546 }
9547
9548 if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9549 struct aml_vcodec_ctx *ctx =
9550 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9551
9552 if (ctx->param_sets_from_ucode) {
9553 reset_process_time(pbi);
9554 if (wait_event_interruptible_timeout(ctx->wq,
9555 ctx->v4l_codec_ready,
9556 msecs_to_jiffies(500)) < 0)
9557 return;
9558 }
9559
9560 continue_decoding(pbi);
9561 pbi->postproc_done = 0;
9562 pbi->process_busy = 0;
9563
9564 return;
9565 }
9566
9567 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9568 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9569 && (hw_to_vdec(pbi)->next_status !=
9570 VDEC_STATUS_DISCONNECTED)) {
9571 if (!vdec_has_more_input(vdec)) {
9572 pbi->dec_result = DEC_RESULT_EOS;
9573 vdec_schedule_work(&pbi->work);
9574 return;
9575 }
9576
9577 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9578 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9579 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9580 __func__,
9581 READ_VREG(HEVC_STREAM_LEVEL),
9582 READ_VREG(HEVC_STREAM_WR_PTR),
9583 READ_VREG(HEVC_STREAM_RD_PTR));
9584 vdec_vframe_dirty(vdec, pbi->chunk);
9585 vdec_clean_input(vdec);
9586 }
9587
9588 if (get_free_buf_count(pbi) >=
9589 run_ready_min_buf_num) {
9590 int r;
9591 int decode_size;
9592 r = vdec_prepare_input(vdec, &pbi->chunk);
9593 if (r < 0) {
9594 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9595
9596 vp9_print(pbi,
9597 PRINT_FLAG_VDEC_DETAIL,
9598 "amvdec_vh265: Insufficient data\n");
9599
9600 vdec_schedule_work(&pbi->work);
9601 return;
9602 }
9603 pbi->dec_result = DEC_RESULT_NONE;
9604 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9605 "%s: chunk size 0x%x sum 0x%x\n",
9606 __func__, r,
9607 (debug & PRINT_FLAG_VDEC_STATUS) ?
9608 get_data_check_sum(pbi, r) : 0
9609 );
9610
9611 if (debug & PRINT_FLAG_VDEC_DATA)
9612 dump_data(pbi, pbi->chunk->size);
9613
9614 decode_size = pbi->chunk->size +
9615 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9616
9617 WRITE_VREG(HEVC_DECODE_SIZE,
9618 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9619
9620 vdec_enable_input(vdec);
9621
9622 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9623
9624 start_process_time(pbi);
9625
9626 } else{
9627 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9628
9629 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9630 "amvdec_vh265: Insufficient data\n");
9631
9632 vdec_schedule_work(&pbi->work);
9633 }
9634 return;
9635 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9636 #ifdef SUPPORT_FB_DECODING
9637 if (pbi->used_stage_buf_num > 0) {
9638 #ifndef FB_DECODING_TEST_SCHEDULE
9639 if (!is_s2_decoding_finished(pbi)) {
9640 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9641 "s2 decoding not done, check again later\n");
9642 vdec_schedule_work(&pbi->work);
9643 }
9644 #endif
9645 inc_s2_pos(pbi);
9646 if (mcrcc_cache_alg_flag)
9647 dump_hit_rate(pbi);
9648 }
9649 #endif
9650 /* if (!pbi->ctx_valid)
9651 pbi->ctx_valid = 1; */
9652 pbi->slice_idx++;
9653 pbi->frame_count++;
9654 pbi->process_state = PROC_STATE_INIT;
9655 decode_frame_count[pbi->index] = pbi->frame_count;
9656
9657 if (pbi->mmu_enable)
9658 pbi->used_4k_num =
9659 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9660 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9661 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9662 __func__,
9663 pbi->frame_count,
9664 pbi->dec_result,
9665 READ_VREG(HEVC_STREAM_LEVEL),
9666 READ_VREG(HEVC_STREAM_WR_PTR),
9667 READ_VREG(HEVC_STREAM_RD_PTR),
9668 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9669 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9670 pbi->start_shift_bytes
9671 );
9672 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9673 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9674 /*
9675 stream base: stream buf empty or timeout
9676 frame base: vdec_prepare_input fail
9677 */
9678 if (!vdec_has_more_input(vdec)) {
9679 pbi->dec_result = DEC_RESULT_EOS;
9680 vdec_schedule_work(&pbi->work);
9681 return;
9682 }
9683 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9684 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9685 "%s: end of stream\n",
9686 __func__);
9687 pbi->eos = 1;
9688 vp9_bufmgr_postproc(pbi);
9689
9690 if (pbi->is_used_v4l)
9691 notify_v4l_eos(hw_to_vdec(pbi));
9692
9693 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9694 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9695 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9696 "%s: force exit\n",
9697 __func__);
9698 if (pbi->stat & STAT_VDEC_RUN) {
9699 amhevc_stop();
9700 pbi->stat &= ~STAT_VDEC_RUN;
9701 }
9702
9703 if (pbi->stat & STAT_ISR_REG) {
9704 #ifdef MULTI_INSTANCE_SUPPORT
9705 if (!pbi->m_ins_flag)
9706 #endif
9707 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9708 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9709 pbi->stat &= ~STAT_ISR_REG;
9710 }
9711 }
9712 if (pbi->stat & STAT_VDEC_RUN) {
9713 amhevc_stop();
9714 pbi->stat &= ~STAT_VDEC_RUN;
9715 }
9716
9717 if (pbi->stat & STAT_TIMER_ARM) {
9718 del_timer_sync(&pbi->timer);
9719 pbi->stat &= ~STAT_TIMER_ARM;
9720 }
9721 /* mark itself has all HW resource released and input released */
9722 #ifdef SUPPORT_FB_DECODING
9723 if (pbi->used_stage_buf_num > 0)
9724 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9725 else
9726 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9727 | CORE_MASK_HEVC
9728 | CORE_MASK_HEVC_FRONT
9729 | CORE_MASK_HEVC_BACK
9730 );
9731 #else
9732 if (vdec->parallel_dec == 1)
9733 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9734 else
9735 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9736 | CORE_MASK_HEVC);
9737 #endif
9738 trigger_schedule(pbi);
9739 }
9740
9741 static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9742 {
9743 /* new to do ... */
9744 #if (!defined SUPPORT_FB_DECODING)
9745 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9746 #elif (defined FB_DECODING_TEST_SCHEDULE)
9747 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9748 #else
9749 if (pbi->used_stage_buf_num > 0)
9750 vvp9_prot_init(pbi, HW_MASK_FRONT);
9751 else
9752 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9753 #endif
9754 return 0;
9755 }
9756 static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9757 {
9758 struct VP9Decoder_s *pbi =
9759 (struct VP9Decoder_s *)vdec->private;
9760 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9761 CODEC_MM_FLAGS_TVP : 0;
9762 unsigned long ret = 0;
9763
9764 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9765 return ret;
9766 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9767 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9768 pbi->first_sc_checked = 1;
9769 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9770 size, (pbi->need_cache_size >> PAGE_SHIFT),
9771 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9772 }
9773
9774 #ifdef SUPPORT_FB_DECODING
9775 if (pbi->used_stage_buf_num > 0) {
9776 if (mask & CORE_MASK_HEVC_FRONT) {
9777 if (get_free_stage_buf_num(pbi) > 0
9778 && mv_buf_available(pbi))
9779 ret |= CORE_MASK_HEVC_FRONT;
9780 }
9781 if (mask & CORE_MASK_HEVC_BACK) {
9782 if (s2_buf_available(pbi) &&
9783 (get_free_buf_count(pbi) >=
9784 run_ready_min_buf_num)) {
9785 ret |= CORE_MASK_HEVC_BACK;
9786 pbi->back_not_run_ready = 0;
9787 } else
9788 pbi->back_not_run_ready = 1;
9789 #if 0
9790 if (get_free_buf_count(pbi) <
9791 run_ready_min_buf_num)
9792 dump_pic_list(pbi);
9793 #endif
9794 }
9795 } else if (get_free_buf_count(pbi) >=
9796 run_ready_min_buf_num)
9797 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9798 | CORE_MASK_HEVC_FRONT
9799 | CORE_MASK_HEVC_BACK;
9800
9801 if (ret & CORE_MASK_HEVC_FRONT)
9802 not_run_ready[pbi->index] = 0;
9803 else
9804 not_run_ready[pbi->index]++;
9805
9806 if (ret & CORE_MASK_HEVC_BACK)
9807 not_run2_ready[pbi->index] = 0;
9808 else
9809 not_run2_ready[pbi->index]++;
9810
9811 vp9_print(pbi,
9812 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9813 __func__, mask, ret,
9814 get_free_stage_buf_num(pbi),
9815 mv_buf_available(pbi),
9816 s2_buf_available(pbi),
9817 get_free_buf_count(pbi)
9818 );
9819
9820 return ret;
9821
9822 #else
9823 if (get_free_buf_count(pbi) >=
9824 run_ready_min_buf_num) {
9825 if (vdec->parallel_dec == 1)
9826 ret = CORE_MASK_HEVC;
9827 else
9828 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9829 }
9830
9831 if (pbi->is_used_v4l) {
9832 struct aml_vcodec_ctx *ctx =
9833 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9834
9835 if (ctx->param_sets_from_ucode &&
9836 !ctx->v4l_codec_ready &&
9837 pbi->v4l_params_parsed) {
9838 ret = 0; /*the params has parsed.*/
9839 } else if (!ctx->v4l_codec_dpb_ready) {
9840 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9841 run_ready_min_buf_num)
9842 ret = 0;
9843 }
9844 }
9845
9846 if (ret)
9847 not_run_ready[pbi->index] = 0;
9848 else
9849 not_run_ready[pbi->index]++;
9850
9851 vp9_print(pbi,
9852 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9853 __func__, mask, ret);
9854 return ret;
9855 #endif
9856 }
9857
9858 static void run_front(struct vdec_s *vdec)
9859 {
9860 struct VP9Decoder_s *pbi =
9861 (struct VP9Decoder_s *)vdec->private;
9862 int ret, size;
9863
9864 run_count[pbi->index]++;
9865 /* pbi->chunk = vdec_prepare_input(vdec); */
9866 #if (!defined SUPPORT_FB_DECODING)
9867 hevc_reset_core(vdec);
9868 #elif (defined FB_DECODING_TEST_SCHEDULE)
9869 hevc_reset_core(vdec);
9870 #else
9871 if (pbi->used_stage_buf_num > 0)
9872 fb_reset_core(vdec, HW_MASK_FRONT);
9873 else
9874 hevc_reset_core(vdec);
9875 #endif
9876
9877 size = vdec_prepare_input(vdec, &pbi->chunk);
9878 if (size < 0) {
9879 input_empty[pbi->index]++;
9880
9881 pbi->dec_result = DEC_RESULT_AGAIN;
9882
9883 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9884 "ammvdec_vh265: Insufficient data\n");
9885
9886 vdec_schedule_work(&pbi->work);
9887 return;
9888 }
9889
9890 input_empty[pbi->index] = 0;
9891 pbi->dec_result = DEC_RESULT_NONE;
9892 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9893
9894 if (debug & PRINT_FLAG_VDEC_STATUS) {
9895 int ii;
9896 vp9_print(pbi, 0,
9897 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9898 __func__,
9899 pbi->frame_count, size,
9900 pbi->chunk ? pbi->chunk->size : 0,
9901 pbi->chunk ? pbi->chunk->offset : 0,
9902 pbi->chunk ? ((vdec_frame_based(vdec) &&
9903 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9904 get_data_check_sum(pbi, size) : 0) : 0,
9905 READ_VREG(HEVC_STREAM_START_ADDR),
9906 READ_VREG(HEVC_STREAM_END_ADDR),
9907 READ_VREG(HEVC_STREAM_LEVEL),
9908 READ_VREG(HEVC_STREAM_WR_PTR),
9909 READ_VREG(HEVC_STREAM_RD_PTR),
9910 pbi->start_shift_bytes);
9911 if (vdec_frame_based(vdec) && pbi->chunk) {
9912 u8 *data = NULL;
9913
9914 if (!pbi->chunk->block->is_mapped)
9915 data = codec_mm_vmap(pbi->chunk->block->start +
9916 pbi->chunk->offset, 8);
9917 else
9918 data = ((u8 *)pbi->chunk->block->start_virt) +
9919 pbi->chunk->offset;
9920
9921 vp9_print_cont(pbi, 0, "data adr %p:",
9922 data);
9923 for (ii = 0; ii < 8; ii++)
9924 vp9_print_cont(pbi, 0, "%02x ",
9925 data[ii]);
9926
9927 if (!pbi->chunk->block->is_mapped)
9928 codec_mm_unmap_phyaddr(data);
9929 }
9930 vp9_print_cont(pbi, 0, "\r\n");
9931 }
9932 if (vdec->mc_loaded) {
9933 /*firmware have load before,
9934 and not changes to another.
9935 ignore reload.
9936 */
9937 } else {
9938 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9939 if (ret < 0) {
9940 amhevc_disable();
9941 vp9_print(pbi, PRINT_FLAG_ERROR,
9942 "VP9: the %s fw loading failed, err: %x\n",
9943 tee_enabled() ? "TEE" : "local", ret);
9944 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9945 vdec_schedule_work(&pbi->work);
9946 return;
9947 }
9948 vdec->mc_loaded = 1;
9949 vdec->mc_type = VFORMAT_VP9;
9950 }
9951
9952 if (vp9_hw_ctx_restore(pbi) < 0) {
9953 vdec_schedule_work(&pbi->work);
9954 return;
9955 }
9956
9957 vdec_enable_input(vdec);
9958
9959 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9960
9961 if (vdec_frame_based(vdec)) {
9962 if (debug & PRINT_FLAG_VDEC_DATA)
9963 dump_data(pbi, pbi->chunk->size);
9964
9965 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9966 size = pbi->chunk->size +
9967 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9968 }
9969 WRITE_VREG(HEVC_DECODE_SIZE, size);
9970 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9971 pbi->init_flag = 1;
9972
9973 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9974 "%s: start hevc (%x %x %x)\n",
9975 __func__,
9976 READ_VREG(HEVC_DEC_STATUS_REG),
9977 READ_VREG(HEVC_MPC_E),
9978 READ_VREG(HEVC_MPSR));
9979
9980 start_process_time(pbi);
9981 mod_timer(&pbi->timer, jiffies);
9982 pbi->stat |= STAT_TIMER_ARM;
9983 pbi->stat |= STAT_ISR_REG;
9984 amhevc_start();
9985 pbi->stat |= STAT_VDEC_RUN;
9986 }
9987
9988 #ifdef SUPPORT_FB_DECODING
9989 static void mpred_process(struct VP9Decoder_s *pbi)
9990 {
9991 union param_u *params = &pbi->s1_param;
9992 unsigned char use_prev_frame_mvs =
9993 !params->p.error_resilient_mode &&
9994 params->p.width == pbi->s1_width &&
9995 params->p.height == pbi->s1_height &&
9996 !pbi->s1_intra_only &&
9997 pbi->s1_last_show_frame &&
9998 (pbi->s1_frame_type != KEY_FRAME);
9999 pbi->s1_width = params->p.width;
10000 pbi->s1_height = params->p.height;
10001 pbi->s1_frame_type = params->p.frame_type;
10002 pbi->s1_intra_only =
10003 (params->p.show_frame ||
10004 params->p.show_existing_frame)
10005 ? 0 : params->p.intra_only;
10006 if ((pbi->s1_frame_type != KEY_FRAME)
10007 && (!pbi->s1_intra_only)) {
10008 unsigned int data32;
10009 int mpred_mv_rd_end_addr;
10010
10011 mpred_mv_rd_end_addr =
10012 pbi->s1_mpred_mv_wr_start_addr_pre
10013 + (pbi->lcu_total * MV_MEM_UNIT);
10014
10015 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
10016 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
10017 pbi->work_space_buf->
10018 mpred_above.buf_start);
10019
10020 data32 = READ_VREG(HEVC_MPRED_CTRL4);
10021
10022 data32 &= (~(1 << 6));
10023 data32 |= (use_prev_frame_mvs << 6);
10024 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
10025
10026 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
10027 pbi->s1_mpred_mv_wr_start_addr);
10028 WRITE_VREG(HEVC_MPRED_MV_WPTR,
10029 pbi->s1_mpred_mv_wr_start_addr);
10030
10031 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
10032 pbi->s1_mpred_mv_wr_start_addr_pre);
10033 WRITE_VREG(HEVC_MPRED_MV_RPTR,
10034 pbi->s1_mpred_mv_wr_start_addr_pre);
10035
10036 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
10037 mpred_mv_rd_end_addr);
10038
10039 } else
10040 clear_mpred_hw(pbi);
10041
10042 if (!params->p.show_existing_frame) {
10043 pbi->s1_mpred_mv_wr_start_addr_pre =
10044 pbi->s1_mpred_mv_wr_start_addr;
10045 pbi->s1_last_show_frame =
10046 params->p.show_frame;
10047 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
10048 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10049 pbi->s1_mv_buf_index_pre_pre =
10050 pbi->s1_mv_buf_index_pre;
10051 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10052 } else
10053 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10054 }
10055
10056 static void vp9_s1_work(struct work_struct *s1_work)
10057 {
10058 struct VP9Decoder_s *pbi = container_of(s1_work,
10059 struct VP9Decoder_s, s1_work);
10060 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10061 "%s dec_s1_result %d\n",
10062 __func__,
10063 pbi->dec_s1_result);
10064
10065 #ifdef FB_DECODING_TEST_SCHEDULE
10066 if (pbi->dec_s1_result ==
10067 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10068 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10069 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10070 }
10071 #endif
10072 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10073 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10074
10075 vdec_core_finish_run(hw_to_vdec(pbi),
10076 CORE_MASK_HEVC_FRONT);
10077
10078 trigger_schedule(pbi);
10079 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10080 }
10081
10082 }
10083
10084 static void run_back(struct vdec_s *vdec)
10085 {
10086 struct VP9Decoder_s *pbi =
10087 (struct VP9Decoder_s *)vdec->private;
10088 int i;
10089 run2_count[pbi->index]++;
10090 if (debug & PRINT_FLAG_VDEC_STATUS) {
10091 vp9_print(pbi, 0,
10092 "%s", __func__);
10093 }
10094 pbi->run2_busy = 1;
10095 #ifndef FB_DECODING_TEST_SCHEDULE
10096 fb_reset_core(vdec, HW_MASK_BACK);
10097
10098 vvp9_prot_init(pbi, HW_MASK_BACK);
10099 #endif
10100 vp9_recycle_mmu_buf_tail(pbi);
10101
10102 if (pbi->frame_count > 0)
10103 vp9_bufmgr_postproc(pbi);
10104
10105 if (get_s2_buf(pbi) >= 0) {
10106 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10107 int ii;
10108 for (ii = 0; ii < 4; ii++)
10109 vp9_param.l.data[i + ii] =
10110 pbi->s2_buf->rpm[i + 3 - ii];
10111 }
10112 #ifndef FB_DECODING_TEST_SCHEDULE
10113 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10114 pbi->stage_mmu_map_phy_addr +
10115 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10116 #endif
10117 continue_decoding(pbi);
10118 }
10119 pbi->run2_busy = 0;
10120 }
10121 #endif
10122
10123 static void run(struct vdec_s *vdec, unsigned long mask,
10124 void (*callback)(struct vdec_s *, void *), void *arg)
10125 {
10126 struct VP9Decoder_s *pbi =
10127 (struct VP9Decoder_s *)vdec->private;
10128
10129 vp9_print(pbi,
10130 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10131 __func__, mask);
10132
10133 run_count[pbi->index]++;
10134 pbi->vdec_cb_arg = arg;
10135 pbi->vdec_cb = callback;
10136 #ifdef SUPPORT_FB_DECODING
10137 if ((mask & CORE_MASK_HEVC) ||
10138 (mask & CORE_MASK_HEVC_FRONT))
10139 run_front(vdec);
10140
10141 if ((pbi->used_stage_buf_num > 0)
10142 && (mask & CORE_MASK_HEVC_BACK))
10143 run_back(vdec);
10144 #else
10145 run_front(vdec);
10146 #endif
10147 }
10148
10149 static void init_frame_bufs(struct VP9Decoder_s *pbi)
10150 {
10151 struct vdec_s *vdec = hw_to_vdec(pbi);
10152 struct VP9_Common_s *const cm = &pbi->common;
10153 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10154 int i;
10155
10156 for (i = 0; i < pbi->used_buf_num; ++i) {
10157 frame_bufs[i].ref_count = 0;
10158 frame_bufs[i].buf.vf_ref = 0;
10159 frame_bufs[i].buf.decode_idx = 0;
10160 frame_bufs[i].buf.cma_alloc_addr = 0;
10161 frame_bufs[i].buf.index = i;
10162 }
10163
10164 if (vdec->parallel_dec == 1) {
10165 for (i = 0; i < FRAME_BUFFERS; i++) {
10166 vdec->free_canvas_ex
10167 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10168 vdec->id);
10169 vdec->free_canvas_ex
10170 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10171 vdec->id);
10172 }
10173 }
10174 }
10175
10176 static void reset(struct vdec_s *vdec)
10177 {
10178 struct VP9Decoder_s *pbi =
10179 (struct VP9Decoder_s *)vdec->private;
10180
10181 cancel_work_sync(&pbi->work);
10182 if (pbi->stat & STAT_VDEC_RUN) {
10183 amhevc_stop();
10184 pbi->stat &= ~STAT_VDEC_RUN;
10185 }
10186
10187 if (pbi->stat & STAT_TIMER_ARM) {
10188 del_timer_sync(&pbi->timer);
10189 pbi->stat &= ~STAT_TIMER_ARM;
10190 }
10191 pbi->dec_result = DEC_RESULT_NONE;
10192 reset_process_time(pbi);
10193 vp9_local_uninit(pbi);
10194 if (vvp9_local_init(pbi) < 0)
10195 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10196 init_frame_bufs(pbi);
10197
10198 pbi->eos = 0;
10199
10200 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10201 }
10202
10203 static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10204 {
10205 struct VP9Decoder_s *pbi =
10206 (struct VP9Decoder_s *)vdec->private;
10207 return vvp9_isr(0, pbi);
10208 }
10209
10210 static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10211 {
10212 struct VP9Decoder_s *pbi =
10213 (struct VP9Decoder_s *)vdec->private;
10214 return vvp9_isr_thread_fn(0, pbi);
10215 }
10216
10217 static void vp9_dump_state(struct vdec_s *vdec)
10218 {
10219 struct VP9Decoder_s *pbi =
10220 (struct VP9Decoder_s *)vdec->private;
10221 struct VP9_Common_s *const cm = &pbi->common;
10222 int i;
10223 vp9_print(pbi, 0, "====== %s\n", __func__);
10224
10225 vp9_print(pbi, 0,
10226 "width/height (%d/%d), used_buf_num %d\n",
10227 cm->width,
10228 cm->height,
10229 pbi->used_buf_num
10230 );
10231
10232 vp9_print(pbi, 0,
10233 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10234 input_frame_based(vdec),
10235 pbi->eos,
10236 pbi->dec_result,
10237 decode_frame_count[pbi->index],
10238 display_frame_count[pbi->index],
10239 run_count[pbi->index],
10240 not_run_ready[pbi->index],
10241 input_empty[pbi->index],
10242 pbi->low_latency_flag,
10243 pbi->no_head
10244 );
10245
10246 if (vf_get_receiver(vdec->vf_provider_name)) {
10247 enum receviver_start_e state =
10248 vf_notify_receiver(vdec->vf_provider_name,
10249 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10250 NULL);
10251 vp9_print(pbi, 0,
10252 "\nreceiver(%s) state %d\n",
10253 vdec->vf_provider_name,
10254 state);
10255 }
10256
10257 vp9_print(pbi, 0,
10258 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10259 __func__,
10260 kfifo_len(&pbi->newframe_q),
10261 VF_POOL_SIZE,
10262 kfifo_len(&pbi->display_q),
10263 VF_POOL_SIZE,
10264 pbi->vf_pre_count,
10265 pbi->vf_get_count,
10266 pbi->vf_put_count,
10267 get_free_buf_count(pbi),
10268 run_ready_min_buf_num
10269 );
10270
10271 dump_pic_list(pbi);
10272
10273 for (i = 0; i < MAX_BUF_NUM; i++) {
10274 vp9_print(pbi, 0,
10275 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10276 i,
10277 pbi->m_mv_BUF[i].start_adr,
10278 pbi->m_mv_BUF[i].size,
10279 pbi->m_mv_BUF[i].used_flag);
10280 }
10281
10282 vp9_print(pbi, 0,
10283 "HEVC_DEC_STATUS_REG=0x%x\n",
10284 READ_VREG(HEVC_DEC_STATUS_REG));
10285 vp9_print(pbi, 0,
10286 "HEVC_MPC_E=0x%x\n",
10287 READ_VREG(HEVC_MPC_E));
10288 vp9_print(pbi, 0,
10289 "DECODE_MODE=0x%x\n",
10290 READ_VREG(DECODE_MODE));
10291 vp9_print(pbi, 0,
10292 "NAL_SEARCH_CTL=0x%x\n",
10293 READ_VREG(NAL_SEARCH_CTL));
10294 vp9_print(pbi, 0,
10295 "HEVC_PARSER_LCU_START=0x%x\n",
10296 READ_VREG(HEVC_PARSER_LCU_START));
10297 vp9_print(pbi, 0,
10298 "HEVC_DECODE_SIZE=0x%x\n",
10299 READ_VREG(HEVC_DECODE_SIZE));
10300 vp9_print(pbi, 0,
10301 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10302 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10303 vp9_print(pbi, 0,
10304 "HEVC_STREAM_START_ADDR=0x%x\n",
10305 READ_VREG(HEVC_STREAM_START_ADDR));
10306 vp9_print(pbi, 0,
10307 "HEVC_STREAM_END_ADDR=0x%x\n",
10308 READ_VREG(HEVC_STREAM_END_ADDR));
10309 vp9_print(pbi, 0,
10310 "HEVC_STREAM_LEVEL=0x%x\n",
10311 READ_VREG(HEVC_STREAM_LEVEL));
10312 vp9_print(pbi, 0,
10313 "HEVC_STREAM_WR_PTR=0x%x\n",
10314 READ_VREG(HEVC_STREAM_WR_PTR));
10315 vp9_print(pbi, 0,
10316 "HEVC_STREAM_RD_PTR=0x%x\n",
10317 READ_VREG(HEVC_STREAM_RD_PTR));
10318 vp9_print(pbi, 0,
10319 "PARSER_VIDEO_RP=0x%x\n",
10320 READ_PARSER_REG(PARSER_VIDEO_RP));
10321 vp9_print(pbi, 0,
10322 "PARSER_VIDEO_WP=0x%x\n",
10323 READ_PARSER_REG(PARSER_VIDEO_WP));
10324
10325 if (input_frame_based(vdec) &&
10326 (debug & PRINT_FLAG_VDEC_DATA)
10327 ) {
10328 int jj;
10329 if (pbi->chunk && pbi->chunk->block &&
10330 pbi->chunk->size > 0) {
10331 u8 *data = NULL;
10332
10333 if (!pbi->chunk->block->is_mapped)
10334 data = codec_mm_vmap(
10335 pbi->chunk->block->start +
10336 pbi->chunk->offset,
10337 pbi->chunk->size);
10338 else
10339 data = ((u8 *)pbi->chunk->block->start_virt)
10340 + pbi->chunk->offset;
10341 vp9_print(pbi, 0,
10342 "frame data size 0x%x\n",
10343 pbi->chunk->size);
10344 for (jj = 0; jj < pbi->chunk->size; jj++) {
10345 if ((jj & 0xf) == 0)
10346 vp9_print(pbi, 0,
10347 "%06x:", jj);
10348 vp9_print_cont(pbi, 0,
10349 "%02x ", data[jj]);
10350 if (((jj + 1) & 0xf) == 0)
10351 vp9_print_cont(pbi, 0,
10352 "\n");
10353 }
10354
10355 if (!pbi->chunk->block->is_mapped)
10356 codec_mm_unmap_phyaddr(data);
10357 }
10358 }
10359
10360 }
10361
10362 static int ammvdec_vp9_probe(struct platform_device *pdev)
10363 {
10364 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10365 int ret;
10366 int config_val;
10367 struct vframe_content_light_level_s content_light_level;
10368 struct vframe_master_display_colour_s vf_dp;
10369
10370 struct BUF_s BUF[MAX_BUF_NUM];
10371 struct VP9Decoder_s *pbi = NULL;
10372 pr_debug("%s\n", __func__);
10373
10374 if (pdata == NULL) {
10375 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10376 return -EFAULT;
10377 }
10378 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10379 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10380 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10381 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10382 if (pbi == NULL) {
10383 pr_info("\nammvdec_vp9 device data allocation failed\n");
10384 return -ENOMEM;
10385 }
10386 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10387
10388 /* the ctx from v4l2 driver. */
10389 pbi->v4l2_ctx = pdata->private;
10390
10391 pdata->private = pbi;
10392 pdata->dec_status = vvp9_dec_status;
10393 /* pdata->set_trickmode = set_trickmode; */
10394 pdata->run_ready = run_ready;
10395 pdata->run = run;
10396 pdata->reset = reset;
10397 pdata->irq_handler = vp9_irq_cb;
10398 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10399 pdata->dump_state = vp9_dump_state;
10400
10401 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10402 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10403
10404 pbi->index = pdev->id;
10405
10406 if (pdata->use_vfm_path)
10407 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10408 VFM_DEC_PROVIDER_NAME);
10409 else
10410 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10411 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10412
10413 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10414 &vvp9_vf_provider, pbi);
10415
10416 pbi->provider_name = pdata->vf_provider_name;
10417 platform_set_drvdata(pdev, pdata);
10418
10419 pbi->platform_dev = pdev;
10420 pbi->video_signal_type = 0;
10421 pbi->m_ins_flag = 1;
10422 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10423 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10424
10425 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10426 pbi->max_pic_w = 8192;
10427 pbi->max_pic_h = 4608;
10428 } else {
10429 pbi->max_pic_w = 4096;
10430 pbi->max_pic_h = 2304;
10431 }
10432 #if 1
10433 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10434 pdata->config_len) {
10435 #ifdef MULTI_INSTANCE_SUPPORT
10436 int vp9_buf_width = 0;
10437 int vp9_buf_height = 0;
10438 /*use ptr config for doubel_write_mode, etc*/
10439 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10440 if (get_config_int(pdata->config, "vp9_double_write_mode",
10441 &config_val) == 0)
10442 pbi->double_write_mode = config_val;
10443 else
10444 pbi->double_write_mode = double_write_mode;
10445
10446 if (get_config_int(pdata->config, "save_buffer_mode",
10447 &config_val) == 0)
10448 pbi->save_buffer_mode = config_val;
10449 else
10450 pbi->save_buffer_mode = 0;
10451 if (get_config_int(pdata->config, "vp9_buf_width",
10452 &config_val) == 0) {
10453 vp9_buf_width = config_val;
10454 }
10455 if (get_config_int(pdata->config, "vp9_buf_height",
10456 &config_val) == 0) {
10457 vp9_buf_height = config_val;
10458 }
10459
10460 if (get_config_int(pdata->config, "no_head",
10461 &config_val) == 0)
10462 pbi->no_head = config_val;
10463 else
10464 pbi->no_head = no_head;
10465
10466 /*use ptr config for max_pic_w, etc*/
10467 if (get_config_int(pdata->config, "vp9_max_pic_w",
10468 &config_val) == 0) {
10469 pbi->max_pic_w = config_val;
10470 }
10471 if (get_config_int(pdata->config, "vp9_max_pic_h",
10472 &config_val) == 0) {
10473 pbi->max_pic_h = config_val;
10474 }
10475 if ((pbi->max_pic_w * pbi->max_pic_h)
10476 < (vp9_buf_width * vp9_buf_height)) {
10477 pbi->max_pic_w = vp9_buf_width;
10478 pbi->max_pic_h = vp9_buf_height;
10479 vp9_print(pbi, 0, "use buf resolution\n");
10480 }
10481
10482 if (get_config_int(pdata->config,
10483 "parm_v4l_codec_enable",
10484 &config_val) == 0)
10485 pbi->is_used_v4l = config_val;
10486
10487 if (get_config_int(pdata->config,
10488 "parm_v4l_buffer_margin",
10489 &config_val) == 0)
10490 pbi->dynamic_buf_num_margin = config_val;
10491
10492 if (get_config_int(pdata->config,
10493 "parm_v4l_canvas_mem_mode",
10494 &config_val) == 0)
10495 pbi->mem_map_mode = config_val;
10496 #endif
10497 if (get_config_int(pdata->config, "HDRStaticInfo",
10498 &vf_dp.present_flag) == 0
10499 && vf_dp.present_flag == 1) {
10500 get_config_int(pdata->config, "mG.x",
10501 &vf_dp.primaries[0][0]);
10502 get_config_int(pdata->config, "mG.y",
10503 &vf_dp.primaries[0][1]);
10504 get_config_int(pdata->config, "mB.x",
10505 &vf_dp.primaries[1][0]);
10506 get_config_int(pdata->config, "mB.y",
10507 &vf_dp.primaries[1][1]);
10508 get_config_int(pdata->config, "mR.x",
10509 &vf_dp.primaries[2][0]);
10510 get_config_int(pdata->config, "mR.y",
10511 &vf_dp.primaries[2][1]);
10512 get_config_int(pdata->config, "mW.x",
10513 &vf_dp.white_point[0]);
10514 get_config_int(pdata->config, "mW.y",
10515 &vf_dp.white_point[1]);
10516 get_config_int(pdata->config, "mMaxDL",
10517 &vf_dp.luminance[0]);
10518 get_config_int(pdata->config, "mMinDL",
10519 &vf_dp.luminance[1]);
10520 vf_dp.content_light_level.present_flag = 1;
10521 get_config_int(pdata->config, "mMaxCLL",
10522 &content_light_level.max_content);
10523 get_config_int(pdata->config, "mMaxFALL",
10524 &content_light_level.max_pic_average);
10525 vf_dp.content_light_level = content_light_level;
10526 pbi->video_signal_type = (1 << 29)
10527 | (5 << 26) /* unspecified */
10528 | (0 << 25) /* limit */
10529 | (1 << 24) /* color available */
10530 | (9 << 16) /* 2020 */
10531 | (16 << 8) /* 2084 */
10532 | (9 << 0); /* 2020 */
10533 }
10534 pbi->vf_dp = vf_dp;
10535 } else
10536 #endif
10537 {
10538 /*pbi->vvp9_amstream_dec_info.width = 0;
10539 pbi->vvp9_amstream_dec_info.height = 0;
10540 pbi->vvp9_amstream_dec_info.rate = 30;*/
10541 pbi->double_write_mode = double_write_mode;
10542 }
10543
10544 if (!pbi->is_used_v4l) {
10545 pbi->mem_map_mode = mem_map_mode;
10546 }
10547
10548 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10549 pr_err("over size: %dx%d, probe failed\n",
10550 pbi->max_pic_w, pbi->max_pic_h);
10551 return -1;
10552 }
10553 pbi->mmu_enable = 1;
10554 video_signal_type = pbi->video_signal_type;
10555
10556 if (pdata->sys_info) {
10557 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10558 } else {
10559 pbi->vvp9_amstream_dec_info.width = 0;
10560 pbi->vvp9_amstream_dec_info.height = 0;
10561 pbi->vvp9_amstream_dec_info.rate = 30;
10562 }
10563 pbi->low_latency_flag = 1;
10564
10565 vp9_print(pbi, 0,
10566 "no_head %d low_latency %d\n",
10567 pbi->no_head, pbi->low_latency_flag);
10568 #if 0
10569 pbi->buf_start = pdata->mem_start;
10570 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10571 #else
10572 if (amvdec_vp9_mmu_init(pbi) < 0) {
10573 pr_err("vp9 alloc bmmu box failed!!\n");
10574 /* devm_kfree(&pdev->dev, (void *)pbi); */
10575 vfree((void *)pbi);
10576 pdata->dec_status = NULL;
10577 return -1;
10578 }
10579
10580 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10581 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10582 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10583 &pbi->cma_alloc_addr);
10584 if (ret < 0) {
10585 uninit_mmu_buffers(pbi);
10586 /* devm_kfree(&pdev->dev, (void *)pbi); */
10587 vfree((void *)pbi);
10588 pdata->dec_status = NULL;
10589 return ret;
10590 }
10591 pbi->buf_start = pbi->cma_alloc_addr;
10592 pbi->buf_size = work_buf_size;
10593 #endif
10594
10595 pbi->init_flag = 0;
10596 pbi->first_sc_checked = 0;
10597 pbi->fatal_error = 0;
10598 pbi->show_frame_num = 0;
10599
10600 if (debug) {
10601 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10602 pbi->buf_start,
10603 pbi->buf_size);
10604 }
10605
10606 pbi->cma_dev = pdata->cma_dev;
10607 if (vvp9_init(pdata) < 0) {
10608 pr_info("\namvdec_vp9 init failed.\n");
10609 vp9_local_uninit(pbi);
10610 uninit_mmu_buffers(pbi);
10611 /* devm_kfree(&pdev->dev, (void *)pbi); */
10612 vfree((void *)pbi);
10613 pdata->dec_status = NULL;
10614 return -ENODEV;
10615 }
10616 vdec_set_prepare_level(pdata, start_decode_buf_level);
10617 hevc_source_changed(VFORMAT_VP9,
10618 4096, 2048, 60);
10619 #ifdef SUPPORT_FB_DECODING
10620 if (pbi->used_stage_buf_num > 0)
10621 vdec_core_request(pdata,
10622 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10623 else
10624 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10625 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10626 | CORE_MASK_COMBINE);
10627 #else
10628 if (pdata->parallel_dec == 1)
10629 vdec_core_request(pdata, CORE_MASK_HEVC);
10630 else
10631 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10632 | CORE_MASK_COMBINE);
10633 #endif
10634 pbi->pic_list_init_done2 = true;
10635 return 0;
10636 }
10637
10638 static int ammvdec_vp9_remove(struct platform_device *pdev)
10639 {
10640 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10641 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10642 struct vdec_s *vdec = hw_to_vdec(pbi);
10643 int i;
10644 if (debug)
10645 pr_info("amvdec_vp9_remove\n");
10646
10647 vmvp9_stop(pbi);
10648
10649 #ifdef SUPPORT_FB_DECODING
10650 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10651 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10652 );
10653 #else
10654 if (vdec->parallel_dec == 1)
10655 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10656 else
10657 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10658 #endif
10659 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10660
10661 if (vdec->parallel_dec == 1) {
10662 for (i = 0; i < FRAME_BUFFERS; i++) {
10663 vdec->free_canvas_ex
10664 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10665 vdec->id);
10666 vdec->free_canvas_ex
10667 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10668 vdec->id);
10669 }
10670 }
10671
10672
10673 #ifdef DEBUG_PTS
10674 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10675 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10676 #endif
10677 mem_map_mode = 0;
10678
10679 /* devm_kfree(&pdev->dev, (void *)pbi); */
10680 vfree((void *)pbi);
10681 return 0;
10682 }
10683
10684 static struct platform_driver ammvdec_vp9_driver = {
10685 .probe = ammvdec_vp9_probe,
10686 .remove = ammvdec_vp9_remove,
10687 .driver = {
10688 .name = MULTI_DRIVER_NAME,
10689 #ifdef CONFIG_PM
10690 .pm = &vp9_pm_ops,
10691 #endif
10692 }
10693 };
10694 #endif
10695 static struct mconfig vp9_configs[] = {
10696 MC_PU32("bit_depth_luma", &bit_depth_luma),
10697 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10698 MC_PU32("frame_width", &frame_width),
10699 MC_PU32("frame_height", &frame_height),
10700 MC_PU32("debug", &debug),
10701 MC_PU32("radr", &radr),
10702 MC_PU32("rval", &rval),
10703 MC_PU32("pop_shorts", &pop_shorts),
10704 MC_PU32("dbg_cmd", &dbg_cmd),
10705 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10706 MC_PU32("endian", &endian),
10707 MC_PU32("step", &step),
10708 MC_PU32("udebug_flag", &udebug_flag),
10709 MC_PU32("decode_pic_begin", &decode_pic_begin),
10710 MC_PU32("slice_parse_begin", &slice_parse_begin),
10711 MC_PU32("i_only_flag", &i_only_flag),
10712 MC_PU32("error_handle_policy", &error_handle_policy),
10713 MC_PU32("buf_alloc_width", &buf_alloc_width),
10714 MC_PU32("buf_alloc_height", &buf_alloc_height),
10715 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10716 MC_PU32("buf_alloc_size", &buf_alloc_size),
10717 MC_PU32("buffer_mode", &buffer_mode),
10718 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10719 MC_PU32("max_buf_num", &max_buf_num),
10720 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10721 MC_PU32("mem_map_mode", &mem_map_mode),
10722 MC_PU32("double_write_mode", &double_write_mode),
10723 MC_PU32("enable_mem_saving", &enable_mem_saving),
10724 MC_PU32("force_w_h", &force_w_h),
10725 MC_PU32("force_fps", &force_fps),
10726 MC_PU32("max_decoding_time", &max_decoding_time),
10727 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10728 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10729 MC_PU32("decode_timeout_val", &decode_timeout_val),
10730 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10731 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10732 };
10733 static struct mconfig_node vp9_node;
10734
10735 static int __init amvdec_vp9_driver_init_module(void)
10736 {
10737
10738 struct BuffInfo_s *p_buf_info;
10739
10740 if (vdec_is_support_4k()) {
10741 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10742 p_buf_info = &amvvp9_workbuff_spec[2];
10743 else
10744 p_buf_info = &amvvp9_workbuff_spec[1];
10745 } else
10746 p_buf_info = &amvvp9_workbuff_spec[0];
10747
10748 init_buff_spec(NULL, p_buf_info);
10749 work_buf_size =
10750 (p_buf_info->end_adr - p_buf_info->start_adr
10751 + 0xffff) & (~0xffff);
10752
10753 pr_debug("amvdec_vp9 module init\n");
10754
10755 error_handle_policy = 0;
10756
10757 #ifdef ERROR_HANDLE_DEBUG
10758 dbg_nal_skip_flag = 0;
10759 dbg_nal_skip_count = 0;
10760 #endif
10761 udebug_flag = 0;
10762 decode_pic_begin = 0;
10763 slice_parse_begin = 0;
10764 step = 0;
10765 buf_alloc_size = 0;
10766 #ifdef MULTI_INSTANCE_SUPPORT
10767 if (platform_driver_register(&ammvdec_vp9_driver))
10768 pr_err("failed to register ammvdec_vp9 driver\n");
10769
10770 #endif
10771 if (platform_driver_register(&amvdec_vp9_driver)) {
10772 pr_err("failed to register amvdec_vp9 driver\n");
10773 return -ENODEV;
10774 }
10775
10776 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10777 amvdec_vp9_profile.profile =
10778 "8k, 10bit, dwrite, compressed, no_head";
10779 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10780 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10781 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10782 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10783 if (vdec_is_support_4k())
10784 amvdec_vp9_profile.profile =
10785 "4k, 10bit, dwrite, compressed";
10786 else
10787 amvdec_vp9_profile.profile =
10788 "10bit, dwrite, compressed";
10789 } else {
10790 if (vdec_is_support_4k())
10791 amvdec_vp9_profile.profile =
10792 "4k, 10bit, dwrite, compressed, no_head";
10793 else
10794 amvdec_vp9_profile.profile =
10795 "10bit, dwrite, compressed, no_head";
10796 }
10797
10798 } else {
10799 amvdec_vp9_profile.name = "vp9_unsupport";
10800 }
10801
10802 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10803 max_buf_num = MAX_BUF_NUM_LESS;
10804
10805 vcodec_profile_register(&amvdec_vp9_profile);
10806 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10807 amvdec_vp9_profile_mult.name = "mvp9";
10808 vcodec_profile_register(&amvdec_vp9_profile_mult);
10809 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10810 "vp9", vp9_configs, CONFIG_FOR_RW);
10811
10812 return 0;
10813 }
10814
10815 static void __exit amvdec_vp9_driver_remove_module(void)
10816 {
10817 pr_debug("amvdec_vp9 module remove.\n");
10818 #ifdef MULTI_INSTANCE_SUPPORT
10819 platform_driver_unregister(&ammvdec_vp9_driver);
10820 #endif
10821 platform_driver_unregister(&amvdec_vp9_driver);
10822 }
10823
10824 /****************************************/
10825
10826 module_param(bit_depth_luma, uint, 0664);
10827 MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10828
10829 module_param(bit_depth_chroma, uint, 0664);
10830 MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10831
10832 module_param(frame_width, uint, 0664);
10833 MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10834
10835 module_param(frame_height, uint, 0664);
10836 MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10837
10838 module_param(debug, uint, 0664);
10839 MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10840
10841 module_param(radr, uint, 0664);
10842 MODULE_PARM_DESC(radr, "\n radr\n");
10843
10844 module_param(rval, uint, 0664);
10845 MODULE_PARM_DESC(rval, "\n rval\n");
10846
10847 module_param(pop_shorts, uint, 0664);
10848 MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10849
10850 module_param(dbg_cmd, uint, 0664);
10851 MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10852
10853 module_param(dbg_skip_decode_index, uint, 0664);
10854 MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10855
10856 module_param(endian, uint, 0664);
10857 MODULE_PARM_DESC(endian, "\n rval\n");
10858
10859 module_param(step, uint, 0664);
10860 MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10861
10862 module_param(decode_pic_begin, uint, 0664);
10863 MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10864
10865 module_param(slice_parse_begin, uint, 0664);
10866 MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10867
10868 module_param(i_only_flag, uint, 0664);
10869 MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10870
10871 module_param(low_latency_flag, uint, 0664);
10872 MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10873
10874 module_param(no_head, uint, 0664);
10875 MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10876
10877 module_param(error_handle_policy, uint, 0664);
10878 MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10879
10880 module_param(buf_alloc_width, uint, 0664);
10881 MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10882
10883 module_param(buf_alloc_height, uint, 0664);
10884 MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10885
10886 module_param(buf_alloc_depth, uint, 0664);
10887 MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10888
10889 module_param(buf_alloc_size, uint, 0664);
10890 MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10891
10892 module_param(buffer_mode, uint, 0664);
10893 MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10894
10895 module_param(buffer_mode_dbg, uint, 0664);
10896 MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10897 /*USE_BUF_BLOCK*/
10898 module_param(max_buf_num, uint, 0664);
10899 MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10900
10901 module_param(dynamic_buf_num_margin, uint, 0664);
10902 MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10903
10904 module_param(mv_buf_margin, uint, 0664);
10905 MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10906
10907 module_param(run_ready_min_buf_num, uint, 0664);
10908 MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10909
10910 /**/
10911
10912 module_param(mem_map_mode, uint, 0664);
10913 MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10914
10915 #ifdef SUPPORT_10BIT
10916 module_param(double_write_mode, uint, 0664);
10917 MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10918
10919 module_param(enable_mem_saving, uint, 0664);
10920 MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10921
10922 module_param(force_w_h, uint, 0664);
10923 MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10924 #endif
10925
10926 module_param(force_fps, uint, 0664);
10927 MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10928
10929 module_param(max_decoding_time, uint, 0664);
10930 MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10931
10932 module_param(on_no_keyframe_skiped, uint, 0664);
10933 MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10934
10935 module_param(mcrcc_cache_alg_flag, uint, 0664);
10936 MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10937
10938 #ifdef MULTI_INSTANCE_SUPPORT
10939 module_param(start_decode_buf_level, int, 0664);
10940 MODULE_PARM_DESC(start_decode_buf_level,
10941 "\n vp9 start_decode_buf_level\n");
10942
10943 module_param(decode_timeout_val, uint, 0664);
10944 MODULE_PARM_DESC(decode_timeout_val,
10945 "\n vp9 decode_timeout_val\n");
10946
10947 module_param(vp9_max_pic_w, uint, 0664);
10948 MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10949
10950 module_param(vp9_max_pic_h, uint, 0664);
10951 MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10952
10953 module_param_array(decode_frame_count, uint,
10954 &max_decode_instance_num, 0664);
10955
10956 module_param_array(display_frame_count, uint,
10957 &max_decode_instance_num, 0664);
10958
10959 module_param_array(max_process_time, uint,
10960 &max_decode_instance_num, 0664);
10961
10962 module_param_array(run_count, uint,
10963 &max_decode_instance_num, 0664);
10964
10965 module_param_array(input_empty, uint,
10966 &max_decode_instance_num, 0664);
10967
10968 module_param_array(not_run_ready, uint,
10969 &max_decode_instance_num, 0664);
10970 #endif
10971
10972 #ifdef SUPPORT_FB_DECODING
10973 module_param_array(not_run2_ready, uint,
10974 &max_decode_instance_num, 0664);
10975
10976 module_param_array(run2_count, uint,
10977 &max_decode_instance_num, 0664);
10978
10979 module_param(stage_buf_num, uint, 0664);
10980 MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10981 #endif
10982
10983 module_param(udebug_flag, uint, 0664);
10984 MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10985
10986 module_param(udebug_pause_pos, uint, 0664);
10987 MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10988
10989 module_param(udebug_pause_val, uint, 0664);
10990 MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10991
10992 module_param(udebug_pause_decode_idx, uint, 0664);
10993 MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10994
10995 module_param(without_display_mode, uint, 0664);
10996 MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10997
10998 module_init(amvdec_vp9_driver_init_module);
10999 module_exit(amvdec_vp9_driver_remove_module);
11000
11001 MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
11002 MODULE_LICENSE("GPL");
11003