2 * drivers/amlogic/amports/vavs.c
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/semaphore.h>
22 #include <linux/timer.h>
23 #include <linux/kfifo.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/amlogic/media/utils/amstream.h>
27 #include <linux/amlogic/media/frame_sync/ptsserv.h>
28 #include <linux/amlogic/media/canvas/canvas.h>
29 #include <linux/amlogic/media/vfm/vframe_provider.h>
30 #include <linux/amlogic/media/vfm/vframe_receiver.h>
31 #include <linux/amlogic/media/vfm/vframe.h>
32 #include <linux/amlogic/media/utils/vdec_reg.h>
33 #include "../../../stream_input/amports/streambuf_reg.h"
34 #include "../utils/amvdec.h"
35 #include <linux/amlogic/media/registers/register.h>
36 #include "../../../stream_input/amports/amports_priv.h"
37 #include <linux/dma-mapping.h>
38 #include <linux/amlogic/media/codec_mm/codec_mm.h>
39 #include <linux/slab.h>
40 #include "avs_multi.h"
41 #include <linux/amlogic/media/codec_mm/configs.h>
42 #include "../utils/decoder_mmu_box.h"
43 #include "../utils/decoder_bmmu_box.h"
44 #include "../utils/firmware.h"
45 #include "../../../common/chips/decoder_cpu_ver_info.h"
46 #include <linux/amlogic/tee.h>
48 #define DEBUG_MULTI_FLAG 0
50 #define DEBUG_WITH_SINGLE_MODE
51 #define DEBUG_MULTI_WITH_AUTOMODE
52 #define DEBUG_MULTI_FRAME_INS
56 #define USE_DYNAMIC_BUF_NUM
58 #ifdef DEBUG_WITH_SINGLE_MODE
59 #define DRIVER_NAME "amvdec_avs"
60 #define MODULE_NAME "amvdec_avs"
62 #define DRIVER_NAME "ammvdec_avs"
63 #define MODULE_NAME "ammvdec_avs"
66 #define MULTI_DRIVER_NAME "ammvdec_avs"
68 #define ENABLE_USER_DATA
70 #if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
74 #define USE_AVS_SEQ_INFO
75 #define HANDLE_AVS_IRQ
78 #define CHECK_INTERVAL (HZ/100)
84 #define LMEM_BUF_SIZE (0x500 * 2)
86 /* #define ORI_BUFFER_START_ADDR 0x81000000 */
87 #define ORI_BUFFER_START_ADDR 0x80000000
89 #define INTERLACE_FLAG 0x80
90 #define TOP_FIELD_FIRST_FLAG 0x40
92 /* protocol registers */
93 #define AVS_PIC_RATIO AV_SCRATCH_0
94 #define AVS_PIC_WIDTH AV_SCRATCH_1
95 #define AVS_PIC_HEIGHT AV_SCRATCH_2
96 #define AVS_FRAME_RATE AV_SCRATCH_3
98 /*#define AVS_ERROR_COUNT AV_SCRATCH_6*/
99 #define AVS_SOS_COUNT AV_SCRATCH_7
100 #define AVS_BUFFERIN AV_SCRATCH_8
101 #define AVS_BUFFEROUT AV_SCRATCH_9
102 #define AVS_REPEAT_COUNT AV_SCRATCH_A
103 #define AVS_TIME_STAMP AV_SCRATCH_B
104 #define AVS_OFFSET_REG AV_SCRATCH_C
105 #define MEM_OFFSET_REG AV_SCRATCH_F
106 #define AVS_ERROR_RECOVERY_MODE AV_SCRATCH_G
107 #define DECODE_PIC_COUNT AV_SCRATCH_G
109 #define DECODE_MODE AV_SCRATCH_6
110 #define DECODE_MODE_SINGLE 0x0
111 #define DECODE_MODE_MULTI_FRAMEBASE 0x1
112 #define DECODE_MODE_MULTI_STREAMBASE 0x2
113 #define DECODE_MODE_MULTI_STREAMBASE_CONT 0x3
115 #define DECODE_STATUS AV_SCRATCH_H
116 #define DECODE_STATUS_PIC_DONE 0x1
117 #define DECODE_STATUS_DECODE_BUF_EMPTY 0x2
118 #define DECODE_STATUS_SEARCH_BUF_EMPTY 0x3
119 #define DECODE_STATUS_SKIP_PIC_DONE 0x4
120 #define DECODE_SEARCH_HEAD 0xff
122 #define DECODE_STOP_POS AV_SCRATCH_J
124 #define DECODE_LMEM_BUF_ADR AV_SCRATCH_I
126 #define DECODE_CFG AV_SCRATCH_K
131 #define VF_POOL_SIZE 64
132 #define PUT_INTERVAL (HZ/100)
134 #if 1 /*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/
135 #define INT_AMVENCODER INT_DOS_MAILBOX_1
137 /* #define AMVENC_DEV_VERSION "AML-MT" */
138 #define INT_AMVENCODER INT_MAILBOX_1A
141 #ifdef USE_DYNAMIC_BUF_NUM
142 static unsigned int buf_spec_reg
[] = {
147 AV_SCRATCH_7
, /*AVS_SOS_COUNT*/
148 AV_SCRATCH_D
, /*DEBUG_REG2*/
149 AV_SCRATCH_E
, /*DEBUG_REG1*/
150 AV_SCRATCH_M
/*user_data_poc_number*/
154 #define DEBUG_REG1 AV_SCRATCH_E
155 #define DEBUG_REG2 AV_SCRATCH_D
158 static void check_timer_func(unsigned long arg
);
159 static void vavs_work(struct work_struct
*work
);
161 #define DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE 0x0001
162 static u32 dec_control
= DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE
;
165 #define VPP_VD1_POSTBLEND (1 << 10)
168 static unsigned int debug_mask
= 0xff;
173 bit 0, enable ucode print
174 bit 1, enable ucode more print
175 bit 3, enable ucdode detail print
176 bit [31:16] not 0, pos to dump lmem
177 bit 2, pop bits to lmem
178 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
181 bit [8], disable empty muitl-instance handling
182 bit [9], enable writting of VC1_CONTROL_REG in ucode
184 static u32 udebug_flag
;
186 when udebug_flag[1:0] is not 0
187 udebug_pause_pos not 0,
190 static u32 udebug_pause_pos
;
192 when udebug_flag[1:0] is not 0
193 and udebug_pause_pos is not 0,
194 pause only when DEBUG_REG2 is equal to this val
196 static u32 udebug_pause_val
;
198 static u32 udebug_pause_decode_idx
;
200 static u32 udebug_pause_ins_id
;
202 static u32 force_fps
;
204 #ifdef DEBUG_MULTI_FRAME_INS
210 static u32 start_decoding_delay
;
212 #define AVS_DEV_NUM 9
213 static unsigned int max_decode_instance_num
= AVS_DEV_NUM
;
214 static unsigned int max_process_time
[AVS_DEV_NUM
];
215 static unsigned int max_get_frame_interval
[AVS_DEV_NUM
];
216 static unsigned int run_count
[AVS_DEV_NUM
];
217 static unsigned int ins_udebug_flag
[AVS_DEV_NUM
];
218 #ifdef DEBUG_MULTI_FRAME_INS
219 static unsigned int max_run_count
[AVS_DEV_NUM
];
224 static unsigned int error_handle_policy
= 3;
226 static u32 again_threshold
= 0; /*0x40;*/
228 static unsigned int decode_timeout_val
= 200;
229 static unsigned int start_decode_buf_level
= 0x8000;
231 /********************************
233 0: use avsp_trans long cabac ucode;
234 1: not use avsp_trans long cabac ucode
236 #define USE_EXT_BUFFER_ASSIGNMENT
237 #undef USE_DYNAMIC_BUF_NUM
238 ********************************/
239 static int firmware_sel
;
240 static int disable_longcabac_trans
= 1;
241 static int pre_decode_buf_level
= 0x800;
244 static struct vframe_s
*vavs_vf_peek(void *);
245 static struct vframe_s
*vavs_vf_get(void *);
246 static void vavs_vf_put(struct vframe_s
*, void *);
247 static int vavs_vf_states(struct vframe_states
*states
, void *);
248 static int vavs_event_cb(int type
, void *data
, void *private_data
);
250 static const char vavs_dec_id
[] = "vavs-dev";
252 #define PROVIDER_NAME "decoder.avs"
253 static DEFINE_SPINLOCK(lock
);
254 static DEFINE_MUTEX(vavs_mutex
);
256 static const struct vframe_operations_s vavs_vf_provider
= {
257 .peek
= vavs_vf_peek
,
260 .event_cb
= vavs_event_cb
,
261 .vf_states
= vavs_vf_states
,
264 static void *mm_blk_handle;
266 static struct vframe_provider_s vavs_vf_prov
;
268 #define VF_BUF_NUM_MAX 16
269 #ifdef DEBUG_MULTI_FRAME_INS
270 #define WORKSPACE_SIZE (16 * SZ_1M)
272 #define WORKSPACE_SIZE (4 * SZ_1M)
274 #ifdef AVSP_LONG_CABAC
275 #define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 2)
276 #define WORKSPACE_SIZE_A (MAX_CODED_FRAME_SIZE + LOCAL_HEAP_SIZE)
278 #define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 1)
281 #define RV_AI_BUFF_START_ADDR 0x01a00000
282 #define LONG_CABAC_RV_AI_BUFF_START_ADDR 0x00000000
284 /* 4 buffers not enough for multi inc*/
285 static u32 vf_buf_num
= 8;
286 /*static u32 vf_buf_num_used;*/
287 static u32 canvas_base
= 128;
289 static int canvas_num
= 2; /*NV21*/
291 static int canvas_num
= 3;
295 static struct vframe_s vfpool
[VF_POOL_SIZE
];
296 /*static struct vframe_s vfpool2[VF_POOL_SIZE];*/
297 static struct vframe_s
*cur_vfpool
;
298 static unsigned char recover_flag
;
299 static s32 vfbuf_use
[VF_BUF_NUM_MAX
];
300 static u32 saved_resolution
;
301 static u32 frame_width
, frame_height
, frame_dur
, frame_prog
;
302 static struct timer_list recycle_timer
;
305 static u32 buf_size
= 32 * 1024 * 1024;
307 static u32 buf_offset
;
309 static u32 vavs_ratio
;
312 static u32 pts_by_offset
= 1;
314 static u32 total_frame
;
316 static unsigned char throw_pb_flag
;
318 static u32 pts_hit
, pts_missed
, pts_i_hit
, pts_i_missed
;
321 static u32 radr
, rval
;
324 static struct dec_sysinfo vavs_amstream_dec_info
;
325 static struct vdec_info
*gvs
;
326 static u32 fr_hint_status
;
327 static struct work_struct notify_work
;
328 static struct work_struct set_clk_work
;
329 static bool is_reset
;
331 /*static struct vdec_s *vdec;*/
333 #ifdef AVSP_LONG_CABAC
334 static struct work_struct long_cabac_wd_work
;
335 void *es_write_addr_virt
;
336 dma_addr_t es_write_addr_phy
;
338 void *bitstream_read_tmp
;
339 dma_addr_t bitstream_read_tmp_phy
;
341 static uint long_cabac_busy
;
345 #ifdef ENABLE_USER_DATA
346 static void *user_data_buffer
;
347 static dma_addr_t user_data_buffer_phys
;
349 static DECLARE_KFIFO(newframe_q
, struct vframe_s
*, VF_POOL_SIZE
);
350 static DECLARE_KFIFO(display_q
, struct vframe_s
*, VF_POOL_SIZE
);
351 static DECLARE_KFIFO(recycle_q
, struct vframe_s
*, VF_POOL_SIZE
);
353 static inline u32
index2canvas(u32 index
)
355 const u32 canvas_tab
[VF_BUF_NUM_MAX
] = {
356 0x010100, 0x030302, 0x050504, 0x070706,
357 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e,
358 0x111110, 0x131312, 0x151514, 0x171716,
359 0x191918, 0x1b1b1a, 0x1d1d1c, 0x1f1f1e,
361 const u32 canvas_tab_3
[4] = {
362 0x010100, 0x040403, 0x070706, 0x0a0a09
366 return canvas_tab
[index
] + (canvas_base
<< 16)
367 + (canvas_base
<< 8) + canvas_base
;
369 return canvas_tab_3
[index
] + (canvas_base
<< 16)
370 + (canvas_base
<< 8) + canvas_base
;
373 static const u32 frame_rate_tab
[16] = {
374 96000 / 30, /* forbidden */
375 96000000 / 23976, /* 24000/1001 (23.967) */
378 9600000 / 2997, /* 30000/1001 (29.97) */
381 9600000 / 5994, /* 60000/1001 (59.94) */
383 /* > 8 reserved, use 24 */
384 96000 / 24, 96000 / 24, 96000 / 24, 96000 / 24,
385 96000 / 24, 96000 / 24, 96000 / 24
388 #define DECODE_BUFFER_NUM_MAX VF_BUF_NUM_MAX
389 #define PIC_PTS_NUM 64
395 #define buf_of_vf(vf) container_of(vf, struct buf_pool_s, vf)
401 unsigned short decode_pic_count
;
404 struct vdec_avs_hw_s
{
406 unsigned char m_ins_flag
;
407 struct platform_device
*platform_dev
;
408 DECLARE_KFIFO(newframe_q
, struct vframe_s
*, VF_POOL_SIZE
);
409 DECLARE_KFIFO(display_q
, struct vframe_s
*, VF_POOL_SIZE
);
410 DECLARE_KFIFO(recycle_q
, struct vframe_s
*, VF_POOL_SIZE
);
411 struct buf_pool_s vfpool
[VF_POOL_SIZE
];
412 s32 vfbuf_use
[VF_BUF_NUM_MAX
];
413 unsigned char again_flag
;
414 unsigned char recover_flag
;
419 u32 saved_resolution
;
427 unsigned char throw_pb_flag
;
428 struct pic_pts_s pic_pts
[PIC_PTS_NUM
];
437 #ifdef ENABLE_USER_DATA
438 struct work_struct userdata_push_work
;
439 void *user_data_buffer
;
440 dma_addr_t user_data_buffer_phys
;
442 dma_addr_t lmem_addr
;
447 struct dec_sysinfo vavs_amstream_dec_info
;
448 struct vdec_info
*gvs
;
450 struct work_struct set_clk_work
;
456 u32 decode_pic_count
;
457 u8 reset_decode_flag
;
458 u32 display_frame_count
;
460 u32 pre_parser_wr_ptr
;
462 buffer_status &= ~buf_recycle_status
464 u32 buf_recycle_status
;
469 struct vframe_chunk_s
*chunk
;
472 unsigned long buf_start
;
495 u32 reg_viff_bit_cnt
;
497 u32 reg_dbkr_canvas_addr
;
498 u32 reg_dbkw_canvas_addr
;
499 u32 reg_anc2_canvas_addr
;
500 u32 reg_anc0_canvas_addr
;
501 u32 reg_anc1_canvas_addr
;
502 u32 reg_anc3_canvas_addr
;
503 u32 reg_anc4_canvas_addr
;
504 u32 reg_anc5_canvas_addr
;
505 u32 slice_ver_pos_pic_type
;
507 u32 avs_co_mb_wr_addr
;
508 u32 slice_start_byte_01
;
509 u32 slice_start_byte_23
;
515 u32 avsp_iq_wq_param_01
;
516 u32 avsp_iq_wq_param_23
;
517 u32 avsp_iq_wq_param_45
;
518 u32 avs_co_mb_rd_addr
;
519 u32 dblk_mb_wid_height
;
521 u32 avs_co_mb_rw_ctl
;
522 u32 vld_decode_control
;
524 struct timer_list check_timer
;
525 u32 decode_timeout_count
;
526 unsigned long int start_process_time
;
529 u32 canvas_spec
[DECODE_BUFFER_NUM_MAX
];
530 struct canvas_config_s canvas_config
[DECODE_BUFFER_NUM_MAX
][2];
534 struct timer_list recycle_timer
;
535 struct work_struct work
;
536 struct work_struct notify_work
;
537 atomic_t error_handler_run
;
538 struct work_struct fatal_error_wd_work
;
539 void (*vdec_cb
)(struct vdec_s
*, void *);
541 /* for error handling */
549 u32 drop_frame_count
;
550 u32 buffer_not_ready
;
551 int frameinfo_enable
;
552 struct firmware_s
*fw
;
554 u32 decode_status_skip_pic_done_flag
;
555 u32 decode_decode_cont_start_code
;
558 static void reset_process_time(struct vdec_avs_hw_s
*hw
);
559 static void start_process_time(struct vdec_avs_hw_s
*hw
);
560 static void vavs_save_regs(struct vdec_avs_hw_s
*hw
);
562 struct vdec_avs_hw_s
*ghw
;
564 #define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs"
566 #define DEC_RESULT_NONE 0
567 #define DEC_RESULT_DONE 1
568 #define DEC_RESULT_AGAIN 2
569 #define DEC_RESULT_ERROR 3
570 #define DEC_RESULT_FORCE_EXIT 4
571 #define DEC_RESULT_EOS 5
572 #define DEC_RESULT_GET_DATA 6
573 #define DEC_RESULT_GET_DATA_RETRY 7
574 #define DEC_RESULT_USERDATA 8
576 #define DECODE_ID(hw) (hw->m_ins_flag? hw_to_vdec(hw)->id : 0)
578 #define PRINT_FLAG_ERROR 0x0
579 #define PRINT_FLAG_RUN_FLOW 0X0001
580 #define PRINT_FLAG_DECODING 0x0002
581 #define PRINT_FLAG_PTS 0x0004
582 #define PRINT_FLAG_VFRAME_DETAIL 0x0010
583 #define PRINT_FLAG_VLD_DETAIL 0x0020
584 #define PRINT_FLAG_DEC_DETAIL 0x0040
585 #define PRINT_FLAG_BUFFER_DETAIL 0x0080
586 #define PRINT_FLAG_FORCE_DONE 0x0100
587 #define PRINT_FLAG_COUNTER 0X0200
588 #define PRINT_FRAMEBASE_DATA 0x0400
589 #define PRINT_FLAG_PARA_DATA 0x1000
590 #define DEBUG_FLAG_PREPARE_MORE_INPUT 0x2000
591 #define DEBUG_FLAG_PRINT_REG 0x4000
592 #define DEBUG_FLAG_DISABLE_TIMEOUT 0x10000
593 #define DEBUG_WAIT_DECODE_DONE_WHEN_STOP 0x20000
594 #define DEBUG_PIC_DONE_WHEN_UCODE_PAUSE 0x40000
599 static void WRITE_VREG_DBG2(unsigned adr
, unsigned val
)
601 if (debug
& DEBUG_FLAG_PRINT_REG
)
602 pr_info("%s(%x, %x)\n", __func__
, adr
, val
);
604 WRITE_VREG(adr
, val
);
608 #define WRITE_VREG WRITE_VREG_DBG2
612 #define pr_info printk
613 static int debug_print(struct vdec_avs_hw_s
*hw
,
614 int flag
, const char *fmt
, ...)
616 #define AVS_PRINT_BUF 256
617 unsigned char buf
[AVS_PRINT_BUF
];
621 index
= hw
->m_ins_flag
? DECODE_ID(hw
) : 0;
626 && (debug
& flag
))) {
631 len
= sprintf(buf
, "[%d]", index
);
632 vsnprintf(buf
+ len
, AVS_PRINT_BUF
- len
, fmt
, args
);
639 static int debug_print_cont(struct vdec_avs_hw_s
*hw
,
640 int flag
, const char *fmt
, ...)
642 unsigned char buf
[AVS_PRINT_BUF
];
646 index
= hw
->m_ins_flag
? DECODE_ID(hw
) : 0;
651 && (debug
& flag
))) {
655 vsnprintf(buf
+ len
, AVS_PRINT_BUF
- len
, fmt
, args
);
662 static void avs_pts_check_in(struct vdec_avs_hw_s
*hw
,
663 unsigned short decode_pic_count
, struct vframe_chunk_s
*chunk
)
666 debug_print(hw
, PRINT_FLAG_PTS
,
667 "%s %d (wr pos %d), pts %d pts64 %ld timestamp %ld\n",
668 __func__
, decode_pic_count
, hw
->pic_pts_wr_pos
,
669 chunk
->pts
, (u64
)(chunk
->pts64
), (u64
)(chunk
->timestamp
));
671 debug_print(hw
, PRINT_FLAG_PTS
,
672 "%s %d, chunk is null\n",
673 __func__
, decode_pic_count
);
676 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts
= chunk
->pts
;
677 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts64
= chunk
->pts64
;
678 hw
->pic_pts
[hw
->pic_pts_wr_pos
].timestamp
= chunk
->timestamp
;
680 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts
= 0;
681 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts64
= 0;
682 hw
->pic_pts
[hw
->pic_pts_wr_pos
].timestamp
= 0;
684 hw
->pic_pts
[hw
->pic_pts_wr_pos
].decode_pic_count
686 hw
->pic_pts_wr_pos
++;
687 if (hw
->pic_pts_wr_pos
>= PIC_PTS_NUM
)
688 hw
->pic_pts_wr_pos
= 0;
692 static void clear_pts_buf(struct vdec_avs_hw_s
*hw
)
695 debug_print(hw
, PRINT_FLAG_PTS
,
697 hw
->pic_pts_wr_pos
= 0;
698 for (i
= 0; i
< PIC_PTS_NUM
; i
++) {
699 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts
= 0;
700 hw
->pic_pts
[hw
->pic_pts_wr_pos
].pts64
= 0;
701 hw
->pic_pts
[hw
->pic_pts_wr_pos
].timestamp
= 0;
702 hw
->pic_pts
[hw
->pic_pts_wr_pos
].decode_pic_count
= 0;
706 static int set_vframe_pts(struct vdec_avs_hw_s
*hw
,
707 unsigned short decode_pic_count
, struct vframe_s
*vf
)
711 for (i
= 0; i
< PIC_PTS_NUM
; i
++) {
712 if (hw
->pic_pts
[i
].decode_pic_count
== decode_pic_count
) {
713 vf
->pts
= hw
->pic_pts
[i
].pts
;
714 vf
->pts_us64
= hw
->pic_pts
[i
].pts64
;
715 vf
->timestamp
= hw
->pic_pts
[i
].timestamp
;
717 debug_print(hw
, PRINT_FLAG_PTS
,
718 "%s %d (rd pos %d), pts %d pts64 %ld timestamp %ld\n",
719 __func__
, decode_pic_count
, i
,
720 vf
->pts
, vf
->pts_us64
, vf
->timestamp
);
728 static void avs_vf_notify_receiver(struct vdec_avs_hw_s
*hw
,
729 const char *provider_name
, int event_type
, void *data
)
732 vf_notify_receiver(hw_to_vdec(hw
)->vf_provider_name
,
735 vf_notify_receiver(provider_name
, event_type
, data
);
738 static void set_frame_info(struct vdec_avs_hw_s
*hw
, struct vframe_s
*vf
,
739 unsigned int *duration
)
743 unsigned int pixel_ratio
= READ_VREG(AVS_PIC_RATIO
);
745 #ifndef USE_AVS_SEQ_INFO
746 if (hw
->vavs_amstream_dec_info
.width
> 0
747 && hw
->vavs_amstream_dec_info
.height
> 0) {
748 vf
->width
= hw
->vavs_amstream_dec_info
.width
;
749 vf
->height
= hw
->vavs_amstream_dec_info
.height
;
753 vf
->width
= READ_VREG(AVS_PIC_WIDTH
);
754 vf
->height
= READ_VREG(AVS_PIC_HEIGHT
);
755 hw
->frame_width
= vf
->width
;
756 hw
->frame_height
= vf
->height
;
757 /* pr_info("%s: (%d,%d)\n", __func__,vf->width, vf->height);*/
760 #ifndef USE_AVS_SEQ_INFO
761 if (hw
->vavs_amstream_dec_info
.rate
> 0)
762 *duration
= hw
->vavs_amstream_dec_info
.rate
;
766 *duration
= frame_rate_tab
[READ_VREG(AVS_FRAME_RATE
) & 0xf];
767 /* pr_info("%s: duration = %d\n", __func__, *duration); */
768 hw
->frame_dur
= *duration
;
769 schedule_work(&hw
->notify_work
);
772 if (hw
->vavs_ratio
== 0) {
773 /* always stretch to 16:9 */
774 vf
->ratio_control
|= (0x90 <<
775 DISP_RATIO_ASPECT_RATIO_BIT
);
777 switch (pixel_ratio
) {
779 ar
= (vf
->height
* hw
->vavs_ratio
) / vf
->width
;
782 ar
= (vf
->height
* 3 * hw
->vavs_ratio
) / (vf
->width
* 4);
785 ar
= (vf
->height
* 9 * hw
->vavs_ratio
) / (vf
->width
* 16);
788 ar
= (vf
->height
* 100 * hw
->vavs_ratio
) / (vf
->width
*
792 ar
= (vf
->height
* hw
->vavs_ratio
) / vf
->width
;
797 ar
= min(ar
, DISP_RATIO_ASPECT_RATIO_MAX
);
799 vf
->ratio_control
= (ar
<< DISP_RATIO_ASPECT_RATIO_BIT
);
800 /*vf->ratio_control |= DISP_RATIO_FORCECONFIG | DISP_RATIO_KEEPRATIO; */
803 buf_of_vf(vf
)->detached
= 0;
807 #ifdef ENABLE_USER_DATA
809 /*static struct work_struct userdata_push_work;*/
811 #define DUMP_LAST_REPORTED_USER_DATA
813 static void userdata_push_process(struct vdec_avs_hw_s
*hw
)
815 unsigned int user_data_flags
;
816 unsigned int user_data_wp
;
817 unsigned int user_data_length
;
818 struct userdata_poc_info_t user_data_poc
;
819 #ifdef DUMP_LAST_REPORTED_USER_DATA
822 unsigned char *pdata
;
826 user_data_flags
= READ_VREG(AV_SCRATCH_N
);
827 user_data_wp
= (user_data_flags
>> 16) & 0xffff;
828 user_data_length
= user_data_flags
& 0x7fff;
830 #ifdef DUMP_LAST_REPORTED_USER_DATA
831 dma_sync_single_for_cpu(amports_get_dma_device(),
832 hw
->user_data_buffer_phys
, USER_DATA_SIZE
,
835 if (user_data_length
& 0x07)
836 user_data_len
= (user_data_length
+ 8) & 0xFFFFFFF8;
838 user_data_len
= user_data_length
;
840 if (user_data_wp
>= user_data_len
) {
841 wp_start
= user_data_wp
- user_data_len
;
843 pdata
= (unsigned char *)hw
->user_data_buffer
;
845 nLeft
= user_data_len
;
847 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
848 pdata
[0], pdata
[1], pdata
[2], pdata
[3],
849 pdata
[4], pdata
[5], pdata
[6], pdata
[7]);
854 wp_start
= user_data_wp
+
855 USER_DATA_SIZE
- user_data_len
;
857 pdata
= (unsigned char *)hw
->user_data_buffer
;
859 nLeft
= USER_DATA_SIZE
- wp_start
;
862 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
863 pdata
[0], pdata
[1], pdata
[2], pdata
[3],
864 pdata
[4], pdata
[5], pdata
[6], pdata
[7]);
869 pdata
= (unsigned char *)hw
->user_data_buffer
;
870 nLeft
= user_data_wp
;
872 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
873 pdata
[0], pdata
[1], pdata
[2], pdata
[3],
874 pdata
[4], pdata
[5], pdata
[6], pdata
[7]);
882 pr_info("pocinfo 0x%x, poc %d, wp 0x%x, len %d\n",
883 READ_VREG(AV_SCRATCH_L), READ_VREG(AV_SCRATCH_M),
884 user_data_wp, user_data_length);
886 user_data_poc
.poc_info
= READ_VREG(AV_SCRATCH_L
);
887 user_data_poc
.poc_number
= READ_VREG(AV_SCRATCH_M
);
889 WRITE_VREG(AV_SCRATCH_N
, 0);
891 wakeup_userdata_poll(user_data_poc, user_data_wp,
892 (unsigned long)hw->user_data_buffer,
893 USER_DATA_SIZE, user_data_length);
897 static void userdata_push_do_work(struct work_struct
*work
)
899 struct vdec_avs_hw_s
*hw
=
900 container_of(work
, struct vdec_avs_hw_s
, userdata_push_work
);
901 userdata_push_process(hw
);
904 static u8
UserDataHandler(struct vdec_avs_hw_s
*hw
)
906 unsigned int user_data_flags
;
908 user_data_flags
= READ_VREG(AV_SCRATCH_N
);
909 if (user_data_flags
& (1 << 15)) { /* data ready */
910 if (hw
->m_ins_flag
) {
911 hw
->dec_result
= DEC_RESULT_USERDATA
;
912 vdec_schedule_work(&hw
->work
);
915 schedule_work(&hw
->userdata_push_work
);
922 static inline void avs_update_gvs(struct vdec_avs_hw_s
*hw
)
924 if (hw
->gvs
->frame_height
!= hw
->frame_height
) {
925 hw
->gvs
->frame_width
= hw
->frame_width
;
926 hw
->gvs
->frame_height
= hw
->frame_height
;
928 if (hw
->gvs
->frame_dur
!= hw
->frame_dur
) {
929 hw
->gvs
->frame_dur
= hw
->frame_dur
;
930 if (hw
->frame_dur
!= 0)
931 hw
->gvs
->frame_rate
= ((96000 * 10 / hw
->frame_dur
) % 10) < 5 ?
932 96000 / hw
->frame_dur
: (96000 / hw
->frame_dur
+1);
934 hw
->gvs
->frame_rate
= -1;
937 hw
->gvs
->status
= hw
->stat
;
938 hw
->gvs
->error_count
= READ_VREG(AV_SCRATCH_C
);
939 hw
->gvs
->drop_frame_count
= hw
->drop_frame_count
;
943 #ifdef HANDLE_AVS_IRQ
944 static irqreturn_t
vavs_isr(int irq
, void *dev_id
)
946 static void vavs_isr(void)
949 WRITE_VREG(ASSIST_MBOX1_CLR_REG
, 1);
951 return IRQ_WAKE_THREAD
;
954 *static int run_flag = 1;
955 *static int step_flag;
957 static int error_recovery_mode
; /*0: blocky 1: mosaic*/
959 *static uint error_watchdog_threshold=10;
960 *static uint error_watchdog_count;
961 *static uint error_watchdog_buf_threshold = 0x4000000;
964 static struct vframe_s
*vavs_vf_peek(void *op_arg
)
967 struct vdec_avs_hw_s
*hw
=
968 (struct vdec_avs_hw_s
*)op_arg
;
972 if (hw
->recover_flag
)
975 if (kfifo_peek(&hw
->display_q
, &vf
)) {
977 if (force_fps
& 0x100) {
978 u32 rate
= force_fps
& 0xff;
981 vf
->duration
= 96000/rate
;
994 static struct vframe_s
*vavs_vf_get(void *op_arg
)
997 struct vdec_avs_hw_s
*hw
=
998 (struct vdec_avs_hw_s
*)op_arg
;
1000 if (hw
->recover_flag
)
1008 if (kfifo_get(&hw
->display_q
, &vf
)) {
1011 if (force_fps
& 0x100) {
1012 u32 rate
= force_fps
& 0xff;
1015 vf
->duration
= 96000/rate
;
1020 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
1021 "%s, index = %d, w %d h %d, type 0x%x detached %d\n",
1027 buf_of_vf(vf
)->detached
);
1036 static void vavs_vf_put(struct vframe_s
*vf
, void *op_arg
)
1039 struct vdec_avs_hw_s
*hw
=
1040 (struct vdec_avs_hw_s
*)op_arg
;
1044 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
1045 "%s, index = %d, w %d h %d, type 0x%x detached 0x%x\n",
1051 buf_of_vf(vf
)->detached
);
1053 if (hw
->recover_flag
)
1056 for (i
= 0; i
< VF_POOL_SIZE
; i
++) {
1057 if (vf
== &hw
->vfpool
[i
].vf
)
1060 if (i
< VF_POOL_SIZE
)
1062 kfifo_put(&hw
->recycle_q
, (const struct vframe_s
*)vf
);
1066 static int vavs_event_cb(int type
, void *data
, void *private_data
)
1071 static int vavs_dec_status(struct vdec_s
*vdec
, struct vdec_info
*vstatus
)
1073 struct vdec_avs_hw_s
*hw
=
1074 (struct vdec_avs_hw_s
*)vdec
->private;
1075 /*if (!(hw->stat & STAT_VDEC_RUN))
1080 vstatus
->frame_width
= hw
->frame_width
;
1081 vstatus
->frame_height
= hw
->frame_height
;
1082 if (hw
->frame_dur
!= 0)
1083 vstatus
->frame_rate
= ((96000 * 10 / hw
->frame_dur
) % 10) < 5 ?
1084 96000 / hw
->frame_dur
: (96000 / hw
->frame_dur
+1);
1086 vstatus
->frame_rate
= -1;
1087 vstatus
->error_count
= READ_VREG(AV_SCRATCH_C
);
1088 vstatus
->status
= hw
->stat
;
1089 vstatus
->bit_rate
= hw
->gvs
->bit_rate
;
1090 vstatus
->frame_dur
= hw
->frame_dur
;
1091 vstatus
->frame_data
= hw
->gvs
->frame_data
;
1092 vstatus
->total_data
= hw
->gvs
->total_data
;
1093 vstatus
->frame_count
= hw
->gvs
->frame_count
;
1094 vstatus
->error_frame_count
= hw
->gvs
->error_frame_count
;
1095 vstatus
->drop_frame_count
= hw
->gvs
->drop_frame_count
;
1096 vstatus
->i_decoded_frames
= hw
->gvs
->i_decoded_frames
;
1097 vstatus
->i_lost_frames
= hw
->gvs
->i_lost_frames
;
1098 vstatus
->i_concealed_frames
= hw
->gvs
->i_concealed_frames
;
1099 vstatus
->p_decoded_frames
= hw
->gvs
->p_decoded_frames
;
1100 vstatus
->p_lost_frames
= hw
->gvs
->p_lost_frames
;
1101 vstatus
->p_concealed_frames
= hw
->gvs
->p_concealed_frames
;
1102 vstatus
->b_decoded_frames
= hw
->gvs
->b_decoded_frames
;
1103 vstatus
->b_lost_frames
= hw
->gvs
->b_lost_frames
;
1104 vstatus
->b_concealed_frames
= hw
->gvs
->b_concealed_frames
;
1105 vstatus
->total_data
= hw
->gvs
->total_data
;
1106 vstatus
->samp_cnt
= hw
->gvs
->samp_cnt
;
1107 vstatus
->offset
= hw
->gvs
->offset
;
1108 snprintf(vstatus
->vdec_name
, sizeof(vstatus
->vdec_name
),
1114 static int vavs_set_isreset(struct vdec_s
*vdec
, int isreset
)
1116 struct vdec_avs_hw_s
*hw
=
1117 (struct vdec_avs_hw_s
*)vdec
->private;
1119 hw
->is_reset
= isreset
;
1123 static int vavs_vdec_info_init(struct vdec_avs_hw_s
*hw
)
1126 hw
->gvs
= kzalloc(sizeof(struct vdec_info
), GFP_KERNEL
);
1127 if (NULL
== hw
->gvs
) {
1128 pr_info("the struct of vdec status malloc failed.\n");
1134 /****************************************/
1135 static int vavs_canvas_init(struct vdec_avs_hw_s
*hw
)
1138 u32 canvas_width
, canvas_height
;
1139 u32 decbuf_size
, decbuf_y_size
, decbuf_uv_size
;
1140 unsigned long buf_start
;
1141 int need_alloc_buf_num
;
1142 struct vdec_s
*vdec
= NULL
;
1145 vdec
= hw_to_vdec(hw
);
1147 if (buf_size
<= 0x00400000) {
1150 canvas_height
= 576;
1151 decbuf_y_size
= 0x80000;
1152 decbuf_uv_size
= 0x20000;
1153 decbuf_size
= 0x100000;
1156 canvas_width
= 1920;
1157 canvas_height
= 1088;
1158 decbuf_y_size
= 0x200000;
1159 decbuf_uv_size
= 0x80000;
1160 decbuf_size
= 0x300000;
1163 #ifdef AVSP_LONG_CABAC
1164 need_alloc_buf_num
= hw
->vf_buf_num_used
+ 2;
1166 need_alloc_buf_num
= hw
->vf_buf_num_used
+ 1;
1168 for (i
= 0; i
< need_alloc_buf_num
; i
++) {
1170 if (i
== (need_alloc_buf_num
- 1))
1171 decbuf_size
= WORKSPACE_SIZE
;
1172 #ifdef AVSP_LONG_CABAC
1173 else if (i
== (need_alloc_buf_num
- 2))
1174 decbuf_size
= WORKSPACE_SIZE_A
;
1176 ret
= decoder_bmmu_box_alloc_buf_phy(hw
->mm_blk_handle
, i
,
1177 decbuf_size
, DRIVER_NAME
, &buf_start
);
1180 if (i
== (need_alloc_buf_num
- 1)) {
1181 if (firmware_sel
== 1)
1182 hw
->buf_offset
= buf_start
-
1183 RV_AI_BUFF_START_ADDR
;
1185 hw
->buf_offset
= buf_start
-
1186 LONG_CABAC_RV_AI_BUFF_START_ADDR
;
1189 #ifdef AVSP_LONG_CABAC
1190 else if (i
== (need_alloc_buf_num
- 2)) {
1191 avsp_heap_adr
= codec_mm_phys_to_virt(buf_start
);
1195 if (hw
->m_ins_flag
) {
1198 if (vdec
->parallel_dec
== 1) {
1200 if (canvas_u(hw
->canvas_spec
[i
]) == 0xff) {
1202 vdec
->get_canvas_ex(CORE_MASK_VDEC_1
, vdec
->id
);
1203 hw
->canvas_spec
[i
] &= ~(0xffff << 8);
1204 hw
->canvas_spec
[i
] |= tmp
<< 8;
1205 hw
->canvas_spec
[i
] |= tmp
<< 16;
1207 if (canvas_y(hw
->canvas_spec
[i
]) == 0xff) {
1209 vdec
->get_canvas_ex(CORE_MASK_VDEC_1
, vdec
->id
);
1210 hw
->canvas_spec
[i
] &= ~0xff;
1211 hw
->canvas_spec
[i
] |= tmp
;
1213 canvas
= hw
->canvas_spec
[i
];
1215 canvas
= vdec
->get_canvas(i
, 2);
1216 hw
->canvas_spec
[i
] = canvas
;
1219 hw
->canvas_config
[i
][0].phy_addr
=
1221 hw
->canvas_config
[i
][0].width
=
1223 hw
->canvas_config
[i
][0].height
=
1225 hw
->canvas_config
[i
][0].block_mode
=
1226 CANVAS_BLKMODE_32X32
;
1228 hw
->canvas_config
[i
][1].phy_addr
=
1229 buf_start
+ decbuf_y_size
;
1230 hw
->canvas_config
[i
][1].width
=
1232 hw
->canvas_config
[i
][1].height
=
1234 hw
->canvas_config
[i
][1].block_mode
=
1235 CANVAS_BLKMODE_32X32
;
1239 canvas_config(canvas_base
+ canvas_num
* i
+ 0,
1241 canvas_width
, canvas_height
,
1243 CANVAS_BLKMODE_32X32
);
1244 canvas_config(canvas_base
+ canvas_num
* i
+ 1,
1246 decbuf_y_size
, canvas_width
,
1249 CANVAS_BLKMODE_32X32
);
1251 canvas_config(canvas_num
* i
+ 0,
1253 canvas_width
, canvas_height
,
1255 CANVAS_BLKMODE_32X32
);
1256 canvas_config(canvas_num
* i
+ 1,
1258 decbuf_y_size
, canvas_width
/ 2,
1261 CANVAS_BLKMODE_32X32
);
1262 canvas_config(canvas_num
* i
+ 2,
1264 decbuf_y_size
+ decbuf_uv_size
,
1265 canvas_width
/ 2, canvas_height
/ 2,
1267 CANVAS_BLKMODE_32X32
);
1269 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
1270 "canvas config %d, addr %p\n", i
,
1277 static void vavs_recover(struct vdec_avs_hw_s
*hw
)
1279 vavs_canvas_init(hw
);
1281 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) | (1 << 4));
1282 WRITE_VREG(DOS_SW_RESET0
, 0);
1284 READ_VREG(DOS_SW_RESET0
);
1286 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) | (1 << 4));
1287 WRITE_VREG(DOS_SW_RESET0
, 0);
1289 WRITE_VREG(DOS_SW_RESET0
, (1 << 9) | (1 << 8));
1290 WRITE_VREG(DOS_SW_RESET0
, 0);
1292 if (firmware_sel
== 1) {
1293 WRITE_VREG(POWER_CTL_VLD
, 0x10);
1294 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 2,
1295 MEM_FIFO_CNT_BIT
, 2);
1296 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 8,
1297 MEM_LEVEL_CNT_BIT
, 6);
1301 if (firmware_sel
== 0) {
1302 /* fixed canvas index */
1303 WRITE_VREG(AV_SCRATCH_0
, canvas_base
);
1304 WRITE_VREG(AV_SCRATCH_1
, hw
->vf_buf_num_used
);
1307 #ifndef USE_DYNAMIC_BUF_NUM
1308 for (ii
= 0; ii
< 4; ii
++) {
1309 WRITE_VREG(AV_SCRATCH_0
+ ii
,
1310 (canvas_base
+ canvas_num
* ii
) |
1311 ((canvas_base
+ canvas_num
* ii
+ 1)
1313 ((canvas_base
+ canvas_num
* ii
+ 1)
1318 for (ii
= 0; ii
< hw
->vf_buf_num_used
; ii
+= 2) {
1319 WRITE_VREG(buf_spec_reg
[ii
>> 1],
1320 (canvas_base
+ canvas_num
* ii
) |
1321 ((canvas_base
+ canvas_num
* ii
+ 1)
1323 ((canvas_base
+ canvas_num
* ii
+ 2)
1325 ((canvas_base
+ canvas_num
* ii
+ 3)
1332 /* notify ucode the buffer offset */
1333 WRITE_VREG(AV_SCRATCH_F
, hw
->buf_offset
);
1335 /* disable PSCALE for hardware sharing */
1336 WRITE_VREG(PSCALE_CTRL
, 0);
1338 #ifndef USE_DYNAMIC_BUF_NUM
1339 WRITE_VREG(AVS_SOS_COUNT
, 0);
1341 WRITE_VREG(AVS_BUFFERIN
, 0);
1342 WRITE_VREG(AVS_BUFFEROUT
, 0);
1343 if (error_recovery_mode
)
1344 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 0);
1346 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 1);
1347 /* clear mailbox interrupt */
1348 WRITE_VREG(ASSIST_MBOX1_CLR_REG
, 1);
1350 /* enable mailbox interrupt */
1351 WRITE_VREG(ASSIST_MBOX1_MASK
, 1);
1352 #ifndef USE_DYNAMIC_BUF_NUM /* def DEBUG_UCODE */
1353 WRITE_VREG(AV_SCRATCH_D
, 0);
1357 SET_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 17);
1360 #ifdef PIC_DC_NEED_CLEAR
1361 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 31);
1364 #ifdef AVSP_LONG_CABAC
1365 if (firmware_sel
== 0) {
1366 WRITE_VREG(LONG_CABAC_DES_ADDR
, es_write_addr_phy
);
1367 WRITE_VREG(LONG_CABAC_REQ
, 0);
1368 WRITE_VREG(LONG_CABAC_PIC_SIZE
, 0);
1369 WRITE_VREG(LONG_CABAC_SRC_ADDR
, 0);
1372 WRITE_VREG(AV_SCRATCH_5
, 0);
1376 #define MBY_MBX MB_MOTION_MODE /*0xc07*/
1377 #define AVS_CO_MB_WR_ADDR 0xc38
1378 #define AVS_CO_MB_RW_CTL 0xc3d
1379 #define AVS_CO_MB_RD_ADDR 0xc39
1380 #define AVSP_IQ_WQ_PARAM_01 0x0e19
1381 #define AVSP_IQ_WQ_PARAM_23 0x0e1a
1382 #define AVSP_IQ_WQ_PARAM_45 0x0e1b
1384 static void vavs_save_regs(struct vdec_avs_hw_s
*hw
)
1386 hw
->reg_scratch_0
= READ_VREG(AV_SCRATCH_0
);
1387 hw
->reg_scratch_1
= READ_VREG(AV_SCRATCH_1
);
1388 hw
->reg_scratch_2
= READ_VREG(AV_SCRATCH_2
);
1389 hw
->reg_scratch_3
= READ_VREG(AV_SCRATCH_3
);
1390 hw
->reg_scratch_4
= READ_VREG(AV_SCRATCH_4
);
1391 hw
->reg_scratch_5
= READ_VREG(AV_SCRATCH_5
);
1392 hw
->reg_scratch_6
= READ_VREG(AV_SCRATCH_6
);
1393 hw
->reg_scratch_7
= READ_VREG(AV_SCRATCH_7
);
1394 hw
->reg_scratch_8
= READ_VREG(AV_SCRATCH_8
);
1395 hw
->reg_scratch_9
= READ_VREG(AV_SCRATCH_9
);
1396 hw
->reg_scratch_A
= READ_VREG(AV_SCRATCH_A
);
1397 hw
->reg_scratch_B
= READ_VREG(AV_SCRATCH_B
);
1398 hw
->reg_scratch_C
= READ_VREG(AV_SCRATCH_C
);
1399 hw
->reg_scratch_D
= READ_VREG(AV_SCRATCH_D
);
1400 hw
->reg_scratch_E
= READ_VREG(AV_SCRATCH_E
);
1401 hw
->reg_scratch_F
= READ_VREG(AV_SCRATCH_F
);
1402 hw
->reg_scratch_G
= READ_VREG(AV_SCRATCH_G
);
1403 hw
->reg_scratch_H
= READ_VREG(AV_SCRATCH_H
);
1404 hw
->reg_scratch_I
= READ_VREG(AV_SCRATCH_I
);
1406 hw
->reg_mb_width
= READ_VREG(MB_WIDTH
);
1407 hw
->reg_viff_bit_cnt
= READ_VREG(VIFF_BIT_CNT
);
1409 hw
->reg_canvas_addr
= READ_VREG(REC_CANVAS_ADDR
);
1410 hw
->reg_dbkr_canvas_addr
= READ_VREG(DBKR_CANVAS_ADDR
);
1411 hw
->reg_dbkw_canvas_addr
= READ_VREG(DBKW_CANVAS_ADDR
);
1412 hw
->reg_anc2_canvas_addr
= READ_VREG(ANC2_CANVAS_ADDR
);
1413 hw
->reg_anc0_canvas_addr
= READ_VREG(ANC0_CANVAS_ADDR
);
1414 hw
->reg_anc1_canvas_addr
= READ_VREG(ANC1_CANVAS_ADDR
);
1415 hw
->reg_anc3_canvas_addr
= READ_VREG(ANC3_CANVAS_ADDR
);
1416 hw
->reg_anc4_canvas_addr
= READ_VREG(ANC4_CANVAS_ADDR
);
1417 hw
->reg_anc5_canvas_addr
= READ_VREG(ANC5_CANVAS_ADDR
);
1419 hw
->slice_ver_pos_pic_type
= READ_VREG(SLICE_VER_POS_PIC_TYPE
);
1421 hw
->vc1_control_reg
= READ_VREG(VC1_CONTROL_REG
);
1422 hw
->avs_co_mb_wr_addr
= READ_VREG(AVS_CO_MB_WR_ADDR
);
1423 hw
->slice_start_byte_01
= READ_VREG(SLICE_START_BYTE_01
);
1424 hw
->slice_start_byte_23
= READ_VREG(SLICE_START_BYTE_23
);
1425 hw
->vcop_ctrl_reg
= READ_VREG(VCOP_CTRL_REG
);
1426 hw
->iqidct_control
= READ_VREG(IQIDCT_CONTROL
);
1427 hw
->rv_ai_mb_count
= READ_VREG(RV_AI_MB_COUNT
);
1428 hw
->slice_qp
= READ_VREG(SLICE_QP
);
1430 hw
->dc_scaler
= READ_VREG(DC_SCALER
);
1431 hw
->avsp_iq_wq_param_01
= READ_VREG(AVSP_IQ_WQ_PARAM_01
);
1432 hw
->avsp_iq_wq_param_23
= READ_VREG(AVSP_IQ_WQ_PARAM_23
);
1433 hw
->avsp_iq_wq_param_45
= READ_VREG(AVSP_IQ_WQ_PARAM_45
);
1434 hw
->avs_co_mb_rd_addr
= READ_VREG(AVS_CO_MB_RD_ADDR
);
1435 hw
->dblk_mb_wid_height
= READ_VREG(DBLK_MB_WID_HEIGHT
);
1436 hw
->mc_pic_w_h
= READ_VREG(MC_PIC_W_H
);
1437 hw
->avs_co_mb_rw_ctl
= READ_VREG(AVS_CO_MB_RW_CTL
);
1439 hw
->vld_decode_control
= READ_VREG(VLD_DECODE_CONTROL
);
1442 static void vavs_restore_regs(struct vdec_avs_hw_s
*hw
)
1444 debug_print(hw
, PRINT_FLAG_DECODING
,
1445 "%s scratch_8 (AVS_BUFFERIN) 0x%x, decode_pic_count = %d\n",
1446 __func__
, hw
->reg_scratch_8
, hw
->decode_pic_count
);
1448 WRITE_VREG(AV_SCRATCH_0
, hw
->reg_scratch_0
);
1449 WRITE_VREG(AV_SCRATCH_1
, hw
->reg_scratch_1
);
1450 WRITE_VREG(AV_SCRATCH_2
, hw
->reg_scratch_2
);
1451 WRITE_VREG(AV_SCRATCH_3
, hw
->reg_scratch_3
);
1452 WRITE_VREG(AV_SCRATCH_4
, hw
->reg_scratch_4
);
1453 WRITE_VREG(AV_SCRATCH_5
, hw
->reg_scratch_5
);
1454 WRITE_VREG(AV_SCRATCH_6
, hw
->reg_scratch_6
);
1455 WRITE_VREG(AV_SCRATCH_7
, hw
->reg_scratch_7
);
1456 WRITE_VREG(AV_SCRATCH_8
, hw
->reg_scratch_8
);
1457 WRITE_VREG(AV_SCRATCH_9
, hw
->reg_scratch_9
);
1458 WRITE_VREG(AV_SCRATCH_A
, hw
->reg_scratch_A
);
1459 WRITE_VREG(AV_SCRATCH_B
, hw
->reg_scratch_B
);
1460 WRITE_VREG(AV_SCRATCH_C
, hw
->reg_scratch_C
);
1461 WRITE_VREG(AV_SCRATCH_D
, hw
->reg_scratch_D
);
1462 WRITE_VREG(AV_SCRATCH_E
, hw
->reg_scratch_E
);
1463 WRITE_VREG(AV_SCRATCH_F
, hw
->reg_scratch_F
);
1464 WRITE_VREG(AV_SCRATCH_G
, hw
->reg_scratch_G
);
1465 WRITE_VREG(AV_SCRATCH_H
, hw
->reg_scratch_H
);
1466 WRITE_VREG(AV_SCRATCH_I
, hw
->reg_scratch_I
);
1468 WRITE_VREG(MB_WIDTH
, hw
->reg_mb_width
);
1469 WRITE_VREG(VIFF_BIT_CNT
, hw
->reg_viff_bit_cnt
);
1471 WRITE_VREG(REC_CANVAS_ADDR
, hw
->reg_canvas_addr
);
1472 WRITE_VREG(DBKR_CANVAS_ADDR
, hw
->reg_dbkr_canvas_addr
);
1473 WRITE_VREG(DBKW_CANVAS_ADDR
, hw
->reg_dbkw_canvas_addr
);
1474 WRITE_VREG(ANC2_CANVAS_ADDR
, hw
->reg_anc2_canvas_addr
);
1475 WRITE_VREG(ANC0_CANVAS_ADDR
, hw
->reg_anc0_canvas_addr
);
1476 WRITE_VREG(ANC1_CANVAS_ADDR
, hw
->reg_anc1_canvas_addr
);
1477 WRITE_VREG(ANC3_CANVAS_ADDR
, hw
->reg_anc3_canvas_addr
);
1478 WRITE_VREG(ANC4_CANVAS_ADDR
, hw
->reg_anc4_canvas_addr
);
1479 WRITE_VREG(ANC5_CANVAS_ADDR
, hw
->reg_anc5_canvas_addr
);
1481 WRITE_VREG(SLICE_VER_POS_PIC_TYPE
, hw
->slice_ver_pos_pic_type
);
1483 WRITE_VREG(VC1_CONTROL_REG
, hw
->vc1_control_reg
);
1484 WRITE_VREG(AVS_CO_MB_WR_ADDR
, hw
->avs_co_mb_wr_addr
);
1485 WRITE_VREG(SLICE_START_BYTE_01
, hw
->slice_start_byte_01
);
1486 WRITE_VREG(SLICE_START_BYTE_23
, hw
->slice_start_byte_23
);
1487 WRITE_VREG(VCOP_CTRL_REG
, hw
->vcop_ctrl_reg
);
1488 WRITE_VREG(IQIDCT_CONTROL
, hw
->iqidct_control
);
1489 WRITE_VREG(RV_AI_MB_COUNT
, hw
->rv_ai_mb_count
);
1490 WRITE_VREG(SLICE_QP
, hw
->slice_qp
);
1492 WRITE_VREG(DC_SCALER
, hw
->dc_scaler
);
1493 WRITE_VREG(AVSP_IQ_WQ_PARAM_01
, hw
->avsp_iq_wq_param_01
);
1494 WRITE_VREG(AVSP_IQ_WQ_PARAM_23
, hw
->avsp_iq_wq_param_23
);
1495 WRITE_VREG(AVSP_IQ_WQ_PARAM_45
, hw
->avsp_iq_wq_param_45
);
1496 WRITE_VREG(AVS_CO_MB_RD_ADDR
, hw
->avs_co_mb_rd_addr
);
1497 WRITE_VREG(DBLK_MB_WID_HEIGHT
, hw
->dblk_mb_wid_height
);
1498 WRITE_VREG(MC_PIC_W_H
, hw
->mc_pic_w_h
);
1499 WRITE_VREG(AVS_CO_MB_RW_CTL
, hw
->avs_co_mb_rw_ctl
);
1501 WRITE_VREG(VLD_DECODE_CONTROL
, hw
->vld_decode_control
);
1505 static int vavs_prot_init(struct vdec_avs_hw_s
*hw
)
1508 #if DEBUG_MULTI_FLAG > 0
1509 if (hw
->decode_pic_count
== 0) {
1511 #if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
1512 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) | (1 << 4));
1513 WRITE_VREG(DOS_SW_RESET0
, 0);
1515 READ_VREG(DOS_SW_RESET0
);
1517 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) | (1 << 4));
1518 WRITE_VREG(DOS_SW_RESET0
, 0);
1520 WRITE_VREG(DOS_SW_RESET0
, (1 << 9) | (1 << 8));
1521 WRITE_VREG(DOS_SW_RESET0
, 0);
1524 WRITE_RESET_REG(RESET0_REGISTER
,
1525 RESET_IQIDCT
| RESET_MC
| RESET_VLD_PART
);
1526 READ_RESET_REG(RESET0_REGISTER
);
1527 WRITE_RESET_REG(RESET0_REGISTER
,
1528 RESET_IQIDCT
| RESET_MC
| RESET_VLD_PART
);
1530 WRITE_RESET_REG(RESET2_REGISTER
, RESET_PIC_DC
| RESET_DBLK
);
1532 #if DEBUG_MULTI_FLAG > 0
1535 /***************** reset vld **********************************/
1536 WRITE_VREG(POWER_CTL_VLD
, 0x10);
1537 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 2, MEM_FIFO_CNT_BIT
, 2);
1538 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 8, MEM_LEVEL_CNT_BIT
, 6);
1539 /*************************************************************/
1540 if (hw
->m_ins_flag
) {
1542 if (hw
->decode_pic_count
== 0) {
1543 r
= vavs_canvas_init(hw
);
1544 #ifndef USE_DYNAMIC_BUF_NUM
1545 for (i
= 0; i
< 4; i
++) {
1546 WRITE_VREG(AV_SCRATCH_0
+ i
,
1551 for (i
= 0; i
< hw
->vf_buf_num_used
; i
++)
1552 WRITE_VREG(buf_spec_reg
[i
], 0);
1553 for (i
= 0; i
< hw
->vf_buf_num_used
; i
+= 2) {
1554 WRITE_VREG(buf_spec_reg
[i
>> 1],
1555 (hw
->canvas_spec
[i
] & 0xffff) |
1556 ((hw
->canvas_spec
[i
+ 1] & 0xffff)
1559 debug_print(hw
, PRINT_FLAG_DECODING
,
1560 "%s WRITE_VREG(0x%x, 0x%x)\n",
1561 __func__
, buf_spec_reg
[i
>> 1], READ_VREG(buf_spec_reg
[i
>> 1]));
1565 vavs_restore_regs(hw
);
1567 for (i
= 0; i
< hw
->vf_buf_num_used
; i
++) {
1568 canvas_config_ex(canvas_y(hw
->canvas_spec
[i
]),
1569 hw
->canvas_config
[i
][0].phy_addr
,
1570 hw
->canvas_config
[i
][0].width
,
1571 hw
->canvas_config
[i
][0].height
,
1573 hw
->canvas_config
[i
][0].block_mode
,
1576 canvas_config_ex(canvas_u(hw
->canvas_spec
[i
]),
1577 hw
->canvas_config
[i
][1].phy_addr
,
1578 hw
->canvas_config
[i
][1].width
,
1579 hw
->canvas_config
[i
][1].height
,
1581 hw
->canvas_config
[i
][1].block_mode
,
1585 r
= vavs_canvas_init(hw
);
1587 if (firmware_sel
== 0) {
1588 /* fixed canvas index */
1589 WRITE_VREG(AV_SCRATCH_0
, canvas_base
);
1590 WRITE_VREG(AV_SCRATCH_1
, hw
->vf_buf_num_used
);
1593 #ifndef USE_DYNAMIC_BUF_NUM
1594 for (ii
= 0; ii
< 4; ii
++) {
1595 WRITE_VREG(AV_SCRATCH_0
+ ii
,
1596 (canvas_base
+ canvas_num
* ii
) |
1597 ((canvas_base
+ canvas_num
* ii
+ 1)
1599 ((canvas_base
+ canvas_num
* ii
+ 1)
1604 for (ii
= 0; ii
< hw
->vf_buf_num_used
; ii
+= 2) {
1605 WRITE_VREG(buf_spec_reg
[ii
>> 1],
1606 (canvas_base
+ canvas_num
* ii
) |
1607 ((canvas_base
+ canvas_num
* ii
+ 1)
1609 ((canvas_base
+ canvas_num
* ii
+ 2)
1611 ((canvas_base
+ canvas_num
* ii
+ 3)
1617 *WRITE_VREG(AV_SCRATCH_0, 0x010100);
1618 *WRITE_VREG(AV_SCRATCH_1, 0x040403);
1619 *WRITE_VREG(AV_SCRATCH_2, 0x070706);
1620 *WRITE_VREG(AV_SCRATCH_3, 0x0a0a09);
1624 /* index v << 16 | u << 8 | y */
1625 WRITE_VREG(AV_SCRATCH_0
, 0x020100);
1626 WRITE_VREG(AV_SCRATCH_1
, 0x050403);
1627 WRITE_VREG(AV_SCRATCH_2
, 0x080706);
1628 WRITE_VREG(AV_SCRATCH_3
, 0x0b0a09);
1631 /* notify ucode the buffer offset */
1632 if (hw
->decode_pic_count
== 0)
1633 WRITE_VREG(AV_SCRATCH_F
, hw
->buf_offset
);
1635 /* disable PSCALE for hardware sharing */
1636 WRITE_VREG(PSCALE_CTRL
, 0);
1638 if (hw
->decode_pic_count
== 0) {
1639 #ifndef USE_DYNAMIC_BUF_NUM
1640 WRITE_VREG(AVS_SOS_COUNT
, 0);
1642 WRITE_VREG(AVS_BUFFERIN
, 0);
1643 WRITE_VREG(AVS_BUFFEROUT
, 0);
1645 if (error_recovery_mode
)
1646 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 0);
1648 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 1);
1649 /* clear mailbox interrupt */
1650 WRITE_VREG(ASSIST_MBOX1_CLR_REG
, 1);
1652 /* enable mailbox interrupt */
1653 WRITE_VREG(ASSIST_MBOX1_MASK
, 1);
1654 #ifndef USE_DYNAMIC_BUF_NUM /* def DEBUG_UCODE */
1655 if (hw
->decode_pic_count
== 0)
1656 WRITE_VREG(AV_SCRATCH_D
, 0);
1660 SET_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 17);
1663 #ifdef PIC_DC_NEED_CLEAR
1664 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 31);
1666 if (hw
->m_ins_flag
&& start_decoding_delay
> 0)
1667 msleep(start_decoding_delay
);
1669 //pr_info("+++++++++++++++++++++++++++++++\n");
1670 //pr_info("+++++++++++++++++++++++++++++++\n");
1671 //pr_info("+++++++++++++++++++++++++++++++\n");
1672 #ifdef AVSP_LONG_CABAC
1673 if (firmware_sel
== 0) {
1674 WRITE_VREG(LONG_CABAC_DES_ADDR
, es_write_addr_phy
);
1675 WRITE_VREG(LONG_CABAC_REQ
, 0);
1676 WRITE_VREG(LONG_CABAC_PIC_SIZE
, 0);
1677 WRITE_VREG(LONG_CABAC_SRC_ADDR
, 0);
1681 #ifdef ENABLE_USER_DATA
1682 if (hw
->decode_pic_count
== 0) {
1683 WRITE_VREG(AV_SCRATCH_N
, (u32
)(hw
->user_data_buffer_phys
- hw
->buf_offset
));
1684 pr_debug("AV_SCRATCH_N = 0x%x\n", READ_VREG(AV_SCRATCH_N
));
1686 WRITE_VREG(AV_SCRATCH_N
, 0);
1688 if (hw
->m_ins_flag
) {
1689 if (vdec_frame_based(hw_to_vdec(hw
)))
1690 WRITE_VREG(DECODE_MODE
, DECODE_MODE_MULTI_FRAMEBASE
);
1692 if (hw
->decode_status_skip_pic_done_flag
) {
1693 WRITE_VREG(DECODE_CFG
, hw
->decode_decode_cont_start_code
);
1694 WRITE_VREG(DECODE_MODE
, DECODE_MODE_MULTI_STREAMBASE_CONT
);
1696 WRITE_VREG(DECODE_MODE
, DECODE_MODE_MULTI_STREAMBASE
);
1698 WRITE_VREG(DECODE_LMEM_BUF_ADR
, (u32
)hw
->lmem_phy_addr
);
1700 WRITE_VREG(DECODE_MODE
, DECODE_MODE_SINGLE
);
1702 if (ins_udebug_flag
[DECODE_ID(hw
)] &&
1703 (ins_udebug_flag
[DECODE_ID(hw
)] >> 16) == hw
->decode_pic_count
) {
1704 WRITE_VREG(DECODE_STOP_POS
,
1705 ins_udebug_flag
[DECODE_ID(hw
)] & 0xffff);
1708 WRITE_VREG(DECODE_STOP_POS
, udebug_flag
);
1709 hw
->old_udebug_flag
= udebug_flag
;
1715 #ifdef AVSP_LONG_CABAC
1716 static unsigned char es_write_addr
[MAX_CODED_FRAME_SIZE
] __aligned(64);
1718 static void vavs_local_init(struct vdec_avs_hw_s
*hw
)
1722 hw
->vf_buf_num_used
= vf_buf_num
;
1724 hw
->vavs_ratio
= hw
->vavs_amstream_dec_info
.ratio
;
1726 hw
->avi_flag
= (unsigned long) hw
->vavs_amstream_dec_info
.param
;
1728 hw
->frame_width
= hw
->frame_height
= hw
->frame_dur
= hw
->frame_prog
= 0;
1730 hw
->throw_pb_flag
= 1;
1732 hw
->total_frame
= 0;
1733 hw
->saved_resolution
= 0;
1737 hw
->pts_hit
= hw
->pts_missed
= hw
->pts_i_hit
= hw
->pts_i_missed
= 0;
1739 INIT_KFIFO(hw
->display_q
);
1740 INIT_KFIFO(hw
->recycle_q
);
1741 INIT_KFIFO(hw
->newframe_q
);
1743 for (i
= 0; i
< VF_POOL_SIZE
; i
++) {
1744 const struct vframe_s
*vf
= &hw
->vfpool
[i
].vf
;
1746 hw
->vfpool
[i
].vf
.index
= hw
->vf_buf_num_used
;
1747 hw
->vfpool
[i
].vf
.bufWidth
= 1920;
1748 hw
->vfpool
[i
].detached
= 0;
1749 kfifo_put(&hw
->newframe_q
, vf
);
1751 for (i
= 0; i
< hw
->vf_buf_num_used
; i
++)
1752 hw
->vfbuf_use
[i
] = 0;
1754 /*cur_vfpool = vfpool;*/
1756 if (hw
->recover_flag
== 1)
1759 if (hw
->mm_blk_handle
) {
1760 pr_info("decoder_bmmu_box_free\n");
1761 decoder_bmmu_box_free(hw
->mm_blk_handle
);
1762 hw
->mm_blk_handle
= NULL
;
1765 hw
->mm_blk_handle
= decoder_bmmu_box_alloc_box(
1768 MAX_BMMU_BUFFER_NUM
,
1770 CODEC_MM_FLAGS_CMA_CLEAR
|
1771 CODEC_MM_FLAGS_FOR_VDECODER
);
1772 if (hw
->mm_blk_handle
== NULL
)
1773 pr_info("Error, decoder_bmmu_box_alloc_box fail\n");
1777 static int vavs_vf_states(struct vframe_states
*states
, void *op_arg
)
1779 unsigned long flags
;
1780 struct vdec_avs_hw_s
*hw
=
1781 (struct vdec_avs_hw_s
*)op_arg
;
1784 spin_lock_irqsave(&lock
, flags
);
1785 states
->vf_pool_size
= VF_POOL_SIZE
;
1786 states
->buf_free_num
= kfifo_len(&hw
->newframe_q
);
1787 states
->buf_avail_num
= kfifo_len(&hw
->display_q
);
1788 states
->buf_recycle_num
= kfifo_len(&hw
->recycle_q
);
1790 states
->buf_avail_num
= 0;
1791 spin_unlock_irqrestore(&lock
, flags
);
1795 #ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1796 static void vavs_ppmgr_reset(void)
1798 vf_notify_receiver(PROVIDER_NAME
, VFRAME_EVENT_PROVIDER_RESET
, NULL
);
1800 vavs_local_init(ghw
);
1802 pr_info("vavs: vf_ppmgr_reset\n");
1806 static void vavs_local_reset(struct vdec_avs_hw_s
*hw
)
1808 mutex_lock(&vavs_mutex
);
1809 hw
->recover_flag
= 1;
1810 pr_info("error, local reset\n");
1813 avs_vf_notify_receiver(hw
, PROVIDER_NAME
, VFRAME_EVENT_PROVIDER_RESET
, NULL
);
1814 vavs_local_init(hw
);
1817 #ifdef ENABLE_USER_DATA
1818 reset_userdata_fifo(1);
1822 hw
->recover_flag
= 0;
1824 error_watchdog_count
= 0;
1826 pr_info("pc %x stream buf wp %x rp %x level %x\n",
1828 READ_VREG(VLD_MEM_VIFIFO_WP
),
1829 READ_VREG(VLD_MEM_VIFIFO_RP
),
1830 READ_VREG(VLD_MEM_VIFIFO_LEVEL
));
1835 mutex_unlock(&vavs_mutex
);
1839 static struct work_struct fatal_error_wd_work
;
1840 static struct work_struct notify_work
;
1841 static atomic_t error_handler_run
= ATOMIC_INIT(0);
1843 static void vavs_fatal_error_handler(struct work_struct
*work
)
1845 struct vdec_avs_hw_s
*hw
=
1846 container_of(work
, struct vdec_avs_hw_s
, fatal_error_wd_work
);
1847 if (debug
& AVS_DEBUG_OLD_ERROR_HANDLE
) {
1848 mutex_lock(&vavs_mutex
);
1849 pr_info("vavs fatal error reset !\n");
1851 #ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1854 vf_light_unreg_provider(&vavs_vf_prov
);
1855 vavs_local_init(hw
);
1856 vf_reg_provider(&vavs_vf_prov
);
1860 mutex_unlock(&vavs_mutex
);
1862 pr_info("avs fatal_error_handler\n");
1863 vavs_local_reset(hw
);
1865 atomic_set(&hw
->error_handler_run
, 0);
1868 static void vavs_notify_work(struct work_struct
*work
)
1870 struct vdec_avs_hw_s
*hw
=
1871 container_of(work
, struct vdec_avs_hw_s
, notify_work
);
1872 if (hw
->fr_hint_status
== VDEC_NEED_HINT
) {
1873 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
1874 VFRAME_EVENT_PROVIDER_FR_HINT
,
1875 (void *)((unsigned long)hw
->frame_dur
));
1876 hw
->fr_hint_status
= VDEC_HINTED
;
1881 static void avs_set_clk(struct work_struct
*work
)
1883 struct vdec_avs_hw_s
*hw
=
1884 container_of(work
, struct vdec_avs_hw_s
, set_clk_work
);
1885 if (hw
->frame_dur
> 0 && hw
->saved_resolution
!=
1886 hw
->frame_width
* hw
->frame_height
* (96000 / hw
->frame_dur
)) {
1887 int fps
= 96000 / hw
->frame_dur
;
1889 hw
->saved_resolution
= hw
->frame_width
* hw
->frame_height
* fps
;
1890 if (firmware_sel
== 0 &&
1891 (debug
& AVS_DEBUG_USE_FULL_SPEED
)) {
1892 vdec_source_changed(VFORMAT_AVS
,
1895 vdec_source_changed(VFORMAT_AVS
,
1896 hw
->frame_width
, hw
->frame_height
, fps
);
1902 #ifdef DEBUG_MULTI_WITH_AUTOMODE
1903 int delay_count
= 0;
1905 static void vavs_put_timer_func(unsigned long arg
)
1907 struct vdec_avs_hw_s
*hw
= (struct vdec_avs_hw_s
*)arg
;
1908 struct timer_list
*timer
= &hw
->recycle_timer
;
1910 #ifndef HANDLE_AVS_IRQ
1913 #ifdef DEBUG_MULTI_WITH_AUTOMODE
1914 if (delay_count
> 0) {
1915 if (delay_count
== 1)
1920 if (READ_VREG(AVS_SOS_COUNT
)) {
1921 if (!error_recovery_mode
) {
1923 if (debug
& AVS_DEBUG_OLD_ERROR_HANDLE
) {
1924 mutex_lock(&vavs_mutex
);
1925 pr_info("vavs fatal error reset !\n");
1927 #ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
1930 vf_light_unreg_provider(&vavs_vf_prov
);
1932 vf_reg_provider(&vavs_vf_prov
);
1936 mutex_unlock(&vavs_mutex
);
1941 if (!atomic_read(&hw
->error_handler_run
)) {
1942 atomic_set(&hw
->error_handler_run
, 1);
1943 pr_info("AVS_SOS_COUNT = %d\n",
1944 READ_VREG(AVS_SOS_COUNT
));
1945 pr_info("WP = 0x%x, RP = 0x%x, LEVEL = 0x%x, AVAIL = 0x%x, CUR_PTR = 0x%x\n",
1946 READ_VREG(VLD_MEM_VIFIFO_WP
),
1947 READ_VREG(VLD_MEM_VIFIFO_RP
),
1948 READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
1949 READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL
),
1950 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR
));
1951 schedule_work(&hw
->fatal_error_wd_work
);
1957 if (long_cabac_busy
== 0 &&
1958 error_watchdog_threshold
> 0 &&
1959 kfifo_len(&hw
->display_q
) == 0 &&
1960 READ_VREG(VLD_MEM_VIFIFO_LEVEL
) >
1961 error_watchdog_buf_threshold
) {
1962 pr_info("newq %d dispq %d recyq %d\r\n",
1963 kfifo_len(&hw
->newframe_q
),
1964 kfifo_len(&hw
->display_q
),
1965 kfifo_len(&hw
->recycle_q
));
1966 pr_info("pc %x stream buf wp %x rp %x level %x\n",
1968 READ_VREG(VLD_MEM_VIFIFO_WP
),
1969 READ_VREG(VLD_MEM_VIFIFO_RP
),
1970 READ_VREG(VLD_MEM_VIFIFO_LEVEL
));
1971 error_watchdog_count
++;
1972 if (error_watchdog_count
>= error_watchdog_threshold
)
1975 error_watchdog_count
= 0;
1979 WRITE_VREG(radr
, rval
);
1980 pr_info("WRITE_VREG(%x,%x)\n", radr
, rval
);
1982 pr_info("READ_VREG(%x)=%x\n", radr
, READ_VREG(radr
));
1986 if ((hw
->ucode_pause_pos
!= 0) &&
1987 (hw
->ucode_pause_pos
!= 0xffffffff) &&
1988 udebug_pause_pos
!= hw
->ucode_pause_pos
) {
1989 hw
->ucode_pause_pos
= 0;
1990 WRITE_VREG(DEBUG_REG1
, 0);
1993 if (!kfifo_is_empty(&hw
->recycle_q
) && (READ_VREG(AVS_BUFFERIN
) == 0)) {
1994 struct vframe_s
*vf
;
1996 if (kfifo_get(&hw
->recycle_q
, &vf
)) {
1997 if ((vf
->index
< hw
->vf_buf_num_used
) &&
1998 (--hw
->vfbuf_use
[vf
->index
] == 0)) {
1999 debug_print(hw
, PRINT_FLAG_DECODING
,
2000 "%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for vf index of %d\n",
2002 ~(1 << vf
->index
), vf
->index
);
2003 WRITE_VREG(AVS_BUFFERIN
, ~(1 << vf
->index
));
2004 vf
->index
= hw
->vf_buf_num_used
;
2006 kfifo_put(&hw
->newframe_q
,
2007 (const struct vframe_s
*)vf
);
2012 schedule_work(&hw
->set_clk_work
);
2014 timer
->expires
= jiffies
+ PUT_INTERVAL
;
2019 #ifdef AVSP_LONG_CABAC
2021 static void long_cabac_do_work(struct work_struct
*work
)
2024 struct vdec_avs_hw_s
*hw
= gw
;
2025 #ifdef PERFORMANCE_DEBUG
2026 pr_info("enter %s buf level (new %d, display %d, recycle %d)\r\n",
2028 kfifo_len(&hw
->newframe_q
),
2029 kfifo_len(&hw
->display_q
),
2030 kfifo_len(&hw
->recycle_q
)
2033 mutex_lock(&vavs_mutex
);
2034 long_cabac_busy
= 1;
2035 while (READ_VREG(LONG_CABAC_REQ
)) {
2036 if (process_long_cabac() < 0) {
2041 long_cabac_busy
= 0;
2042 mutex_unlock(&vavs_mutex
);
2043 #ifdef PERFORMANCE_DEBUG
2044 pr_info("exit %s buf level (new %d, display %d, recycle %d)\r\n",
2046 kfifo_len(&hw
->newframe_q
),
2047 kfifo_len(&hw
->display_q
),
2048 kfifo_len(&hw
->recycle_q
)
2052 pr_info("transcoding error, local reset\r\n");
2053 vavs_local_reset(hw
);
2059 #ifdef AVSP_LONG_CABAC
2060 static void init_avsp_long_cabac_buf(void)
2063 es_write_addr_phy
= (unsigned long)codec_mm_alloc_for_dma(
2065 PAGE_ALIGN(MAX_CODED_FRAME_SIZE
)/PAGE_SIZE
,
2066 0, CODEC_MM_FLAGS_DMA_CPU
);
2067 es_write_addr_virt
= codec_mm_phys_to_virt(es_write_addr_phy
);
2070 es_write_addr_virt
=
2071 (void *)dma_alloc_coherent(amports_get_dma_device(),
2072 MAX_CODED_FRAME_SIZE
, &es_write_addr_phy
,
2075 /*es_write_addr_virt = kmalloc(MAX_CODED_FRAME_SIZE, GFP_KERNEL);
2076 * es_write_addr_virt = (void *)__get_free_pages(GFP_KERNEL,
2077 * get_order(MAX_CODED_FRAME_SIZE));
2079 es_write_addr_virt
= &es_write_addr
[0];
2080 if (es_write_addr_virt
== NULL
) {
2081 pr_err("%s: failed to alloc es_write_addr_virt buffer\n",
2086 es_write_addr_phy
= dma_map_single(amports_get_dma_device(),
2088 MAX_CODED_FRAME_SIZE
, DMA_BIDIRECTIONAL
);
2089 if (dma_mapping_error(amports_get_dma_device(),
2090 es_write_addr_phy
)) {
2091 pr_err("%s: failed to map es_write_addr_virt buffer\n",
2093 /*kfree(es_write_addr_virt);*/
2094 es_write_addr_virt
= NULL
;
2100 #ifdef BITSTREAM_READ_TMP_NO_CACHE
2101 bitstream_read_tmp
=
2102 (void *)dma_alloc_coherent(amports_get_dma_device(),
2103 SVA_STREAM_BUF_SIZE
, &bitstream_read_tmp_phy
,
2108 bitstream_read_tmp
= kmalloc(SVA_STREAM_BUF_SIZE
, GFP_KERNEL
);
2109 /*bitstream_read_tmp = (void *)__get_free_pages(GFP_KERNEL,
2110 *get_order(MAX_CODED_FRAME_SIZE));
2112 if (bitstream_read_tmp
== NULL
) {
2113 pr_err("%s: failed to alloc bitstream_read_tmp buffer\n",
2118 bitstream_read_tmp_phy
= dma_map_single(amports_get_dma_device(),
2120 SVA_STREAM_BUF_SIZE
, DMA_FROM_DEVICE
);
2121 if (dma_mapping_error(amports_get_dma_device(),
2122 bitstream_read_tmp_phy
)) {
2123 pr_err("%s: failed to map rpm buffer\n", __func__
);
2124 kfree(bitstream_read_tmp
);
2125 bitstream_read_tmp
= NULL
;
2133 static s32
vavs_init(struct vdec_avs_hw_s
*hw
)
2136 struct firmware_s
*fw
;
2137 u32 fw_size
= 0x1000 * 16;
2138 /*char *buf = vmalloc(0x1000 * 16);
2140 if (IS_ERR_OR_NULL(buf))
2143 fw
= vmalloc(sizeof(struct firmware_s
) + fw_size
);
2144 if (IS_ERR_OR_NULL(fw
))
2147 pr_info("vavs_init\n");
2148 //init_timer(&hw->recycle_timer);
2150 //hw->stat |= STAT_TIMER_INIT;
2154 //vdec_enable_DMC(NULL);
2156 vavs_local_init(hw
);
2158 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
)
2159 size
= get_firmware_data(VIDEO_DEC_AVS_MULTI
, fw
->data
);
2161 if (firmware_sel
== 1)
2162 size
= get_firmware_data(VIDEO_DEC_AVS_NOCABAC
, fw
->data
);
2163 #ifdef AVSP_LONG_CABAC
2165 init_avsp_long_cabac_buf();
2166 size
= get_firmware_data(VIDEO_DEC_AVS_MULTI
, fw
->data
);
2173 pr_err("get firmware fail.");
2181 if (hw
->m_ins_flag
) {
2182 init_timer(&hw
->check_timer
);
2183 hw
->check_timer
.data
= (ulong
) hw
;
2184 hw
->check_timer
.function
= check_timer_func
;
2185 hw
->check_timer
.expires
= jiffies
+ CHECK_INTERVAL
;
2188 //add_timer(&hw->check_timer);
2189 hw
->stat
|= STAT_TIMER_ARM
;
2191 INIT_WORK(&hw
->work
, vavs_work
);
2197 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
)
2198 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, NULL
, fw
->data
);
2199 else if (firmware_sel
== 1)
2200 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, "avs_no_cabac", fw
->data
);
2202 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, NULL
, fw
->data
);
2207 pr_err("AVS: the %s fw loading failed, err: %x\n",
2208 tee_enabled() ? "TEE" : "local", ret
);
2214 hw
->stat
|= STAT_MC_LOAD
;
2217 /* enable AMRISC side protocol */
2218 ret
= vavs_prot_init(hw
);
2222 #ifdef HANDLE_AVS_IRQ
2223 if (vdec_request_irq(VDEC_IRQ_1
, vavs_isr
,
2224 "vavs-irq", (void *)hw
)) {
2226 pr_info("vavs irq register error.\n");
2231 hw
->stat
|= STAT_ISR_REG
;
2233 #ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2234 vf_provider_init(&vavs_vf_prov
, PROVIDER_NAME
, &vavs_vf_provider
, hw
);
2235 vf_reg_provider(&vavs_vf_prov
);
2236 avs_vf_notify_receiver(hw
, PROVIDER_NAME
, VFRAME_EVENT_PROVIDER_START
, NULL
);
2238 vf_provider_init(&vavs_vf_prov
, PROVIDER_NAME
, &vavs_vf_provider
, hw
);
2239 vf_reg_provider(&vavs_vf_prov
);
2242 if (hw
->vavs_amstream_dec_info
.rate
!= 0) {
2244 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
2245 VFRAME_EVENT_PROVIDER_FR_HINT
,
2246 (void *)((unsigned long)
2247 hw
->vavs_amstream_dec_info
.rate
));
2248 hw
->fr_hint_status
= VDEC_HINTED
;
2250 hw
->fr_hint_status
= VDEC_NEED_HINT
;
2252 hw
->stat
|= STAT_VF_HOOK
;
2254 hw
->recycle_timer
.data
= (ulong
)(hw
);
2255 hw
->recycle_timer
.function
= vavs_put_timer_func
;
2256 hw
->recycle_timer
.expires
= jiffies
+ PUT_INTERVAL
;
2258 add_timer(&hw
->recycle_timer
);
2260 hw
->stat
|= STAT_TIMER_ARM
;
2262 #ifdef AVSP_LONG_CABAC
2263 if (firmware_sel
== 0)
2264 INIT_WORK(&long_cabac_wd_work
, long_cabac_do_work
);
2266 vdec_source_changed(VFORMAT_AVS
,
2268 #ifdef DEBUG_MULTI_WITH_AUTOMODE
2269 if (start_decoding_delay
== 0)
2272 delay_count
= start_decoding_delay
/10;
2276 hw
->stat
|= STAT_VDEC_RUN
;
2280 static int amvdec_avs_probe(struct platform_device
*pdev
)
2282 struct vdec_s
*pdata
= *(struct vdec_s
**)pdev
->dev
.platform_data
;
2283 struct vdec_avs_hw_s
*hw
= NULL
;
2285 if (pdata
== NULL
) {
2286 pr_info("amvdec_avs memory resource undefined.\n");
2290 hw
= (struct vdec_avs_hw_s
*)devm_kzalloc(&pdev
->dev
,
2291 sizeof(struct vdec_avs_hw_s
), GFP_KERNEL
);
2293 pr_info("\nammvdec_avs decoder driver alloc failed\n");
2296 pdata
->private = hw
;
2298 atomic_set(&hw
->error_handler_run
, 0);
2301 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
|| disable_longcabac_trans
)
2304 if (firmware_sel
== 1) {
2305 #ifndef USE_DYNAMIC_BUF_NUM
2313 canvas_num
= 2; /*NV21*/
2317 if (pdata
->sys_info
)
2318 hw
->vavs_amstream_dec_info
= *pdata
->sys_info
;
2320 pr_info("%s (%d,%d) %d\n", __func__
, hw
->vavs_amstream_dec_info
.width
,
2321 hw
->vavs_amstream_dec_info
.height
, hw
->vavs_amstream_dec_info
.rate
);
2323 pdata
->dec_status
= vavs_dec_status
;
2324 pdata
->set_isreset
= vavs_set_isreset
;
2327 pdata
->user_data_read
= NULL
;
2328 pdata
->reset_userdata_fifo
= NULL
;
2330 vavs_vdec_info_init(hw
);
2332 #ifdef ENABLE_USER_DATA
2333 if (NULL
== hw
->user_data_buffer
) {
2334 hw
->user_data_buffer
=
2335 dma_alloc_coherent(amports_get_dma_device(),
2337 &hw
->user_data_buffer_phys
, GFP_KERNEL
);
2338 if (!hw
->user_data_buffer
) {
2339 pr_info("%s: Can not allocate hw->user_data_buffer\n",
2343 pr_debug("hw->user_data_buffer = 0x%p, hw->user_data_buffer_phys = 0x%x\n",
2344 hw
->user_data_buffer
, (u32
)hw
->user_data_buffer_phys
);
2347 INIT_WORK(&hw
->set_clk_work
, avs_set_clk
);
2348 if (vavs_init(hw
) < 0) {
2349 pr_info("amvdec_avs init failed.\n");
2352 pdata
->dec_status
= NULL
;
2360 INIT_WORK(&hw
->fatal_error_wd_work
, vavs_fatal_error_handler
);
2361 atomic_set(&hw
->error_handler_run
, 0);
2362 #ifdef ENABLE_USER_DATA
2363 INIT_WORK(&hw
->userdata_push_work
, userdata_push_do_work
);
2365 INIT_WORK(&hw
->notify_work
, vavs_notify_work
);
2370 static int amvdec_avs_remove(struct platform_device
*pdev
)
2372 struct vdec_avs_hw_s
*hw
= ghw
;
2374 cancel_work_sync(&hw
->fatal_error_wd_work
);
2375 atomic_set(&hw
->error_handler_run
, 0);
2376 #ifdef ENABLE_USER_DATA
2377 cancel_work_sync(&hw
->userdata_push_work
);
2379 cancel_work_sync(&hw
->notify_work
);
2380 cancel_work_sync(&hw
->set_clk_work
);
2381 if (hw
->stat
& STAT_VDEC_RUN
) {
2383 hw
->stat
&= ~STAT_VDEC_RUN
;
2386 if (hw
->stat
& STAT_ISR_REG
) {
2387 vdec_free_irq(VDEC_IRQ_1
, (void *)vavs_dec_id
);
2388 hw
->stat
&= ~STAT_ISR_REG
;
2391 if (hw
->stat
& STAT_TIMER_ARM
) {
2392 del_timer_sync(&hw
->recycle_timer
);
2393 hw
->stat
&= ~STAT_TIMER_ARM
;
2395 #ifdef AVSP_LONG_CABAC
2396 if (firmware_sel
== 0) {
2397 mutex_lock(&vavs_mutex
);
2398 cancel_work_sync(&long_cabac_wd_work
);
2399 mutex_unlock(&vavs_mutex
);
2401 if (es_write_addr_virt
) {
2403 codec_mm_free_for_dma("vavs", es_write_addr_phy
);
2405 dma_unmap_single(amports_get_dma_device(),
2407 MAX_CODED_FRAME_SIZE
, DMA_FROM_DEVICE
);
2408 /*kfree(es_write_addr_virt);*/
2409 es_write_addr_virt
= NULL
;
2413 #ifdef BITSTREAM_READ_TMP_NO_CACHE
2414 if (bitstream_read_tmp
) {
2415 dma_free_coherent(amports_get_dma_device(),
2416 SVA_STREAM_BUF_SIZE
, bitstream_read_tmp
,
2417 bitstream_read_tmp_phy
);
2418 bitstream_read_tmp
= NULL
;
2421 if (bitstream_read_tmp
) {
2422 dma_unmap_single(amports_get_dma_device(),
2423 bitstream_read_tmp_phy
,
2424 SVA_STREAM_BUF_SIZE
, DMA_FROM_DEVICE
);
2425 kfree(bitstream_read_tmp
);
2426 bitstream_read_tmp
= NULL
;
2431 if (hw
->stat
& STAT_VF_HOOK
) {
2432 if (hw
->fr_hint_status
== VDEC_HINTED
&& !hw
->is_reset
)
2433 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
2434 VFRAME_EVENT_PROVIDER_FR_END_HINT
, NULL
);
2435 hw
->fr_hint_status
= VDEC_NO_NEED_HINT
;
2436 vf_unreg_provider(&vavs_vf_prov
);
2437 hw
->stat
&= ~STAT_VF_HOOK
;
2440 #ifdef ENABLE_USER_DATA
2441 if (hw
->user_data_buffer
!= NULL
) {
2443 amports_get_dma_device(),
2445 hw
->user_data_buffer
,
2446 hw
->user_data_buffer_phys
);
2447 hw
->user_data_buffer
= NULL
;
2448 hw
->user_data_buffer_phys
= 0;
2458 //vdec_disable_DMC(NULL);
2461 if (hw
->mm_blk_handle
) {
2462 decoder_bmmu_box_free(hw
->mm_blk_handle
);
2463 hw
->mm_blk_handle
= NULL
;
2466 pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", hw
->pts_hit
,
2467 hw
->pts_missed
, hw
->pts_i_hit
, hw
->pts_i_missed
);
2468 pr_debug("total frame %d, hw->avi_flag %d, rate %d\n", hw
->total_frame
, hw
->avi_flag
,
2469 hw
->vavs_amstream_dec_info
.rate
);
2477 /****************************************/
2479 static struct platform_driver amvdec_avs_driver
= {
2480 .probe
= amvdec_avs_probe
,
2481 .remove
= amvdec_avs_remove
,
2483 .name
= DRIVER_NAME
,
2487 static void recycle_frames(struct vdec_avs_hw_s
*hw
);
2489 static unsigned long run_ready(struct vdec_s
*vdec
, unsigned long mask
)
2491 struct vdec_avs_hw_s
*hw
=
2492 (struct vdec_avs_hw_s
*)vdec
->private;
2494 unsigned buf_busy_mask
= (1 << hw
->vf_buf_num_used
) - 1;
2496 if (work_pending(&hw
->work
) ||
2497 work_busy(&hw
->work
)) {
2498 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,
2499 "avs work pending,not ready for run.\n");
2503 #ifdef DEBUG_MULTI_FRAME_INS
2504 if ((DECODE_ID(hw
) == 0) && run_count
[0] > run_count
[1] &&
2505 run_count
[1] < max_run_count
[1])
2508 if ((DECODE_ID(hw
) == 1) && run_count
[1] >= run_count
[0] &&
2509 run_count
[0] < max_run_count
[0])
2512 if (max_run_count
[DECODE_ID(hw
)] > 0 &&
2513 run_count
[DECODE_ID(hw
)] >= max_run_count
[DECODE_ID(hw
)])
2516 if (vdec_stream_based(vdec
) && (hw
->init_flag
== 0)
2517 && pre_decode_buf_level
!= 0) {
2520 rp
= STBUF_READ(&vdec
->vbuf
, get_rp
);
2521 wp
= STBUF_READ(&vdec
->vbuf
, get_wp
);
2523 level
= vdec
->input
.size
+ wp
- rp
;
2527 if (level
< pre_decode_buf_level
) {
2528 hw
->not_run_ready
++;
2533 if (hw
->reset_decode_flag
== 0 &&
2534 hw
->again_flag
== 0 &&
2535 (hw
->buf_status
& buf_busy_mask
) == buf_busy_mask
) {
2537 if (hw
->buf_recycle_status
== 0)
2541 if (again_threshold
> 0 &&
2542 hw
->pre_parser_wr_ptr
!= 0 &&
2544 (!vdec_frame_based(vdec
))) {
2546 STBUF_READ(&vdec
->vbuf
, get_rp
);
2547 if (parser_wr_ptr
>= hw
->pre_parser_wr_ptr
&&
2548 (parser_wr_ptr
- hw
->pre_parser_wr_ptr
) <
2550 int r
= vdec_sync_input(vdec
);
2551 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
2552 "%s buf lelvel:%x\n", __func__
, r
);
2558 hw
->not_run_ready
= 0;
2560 hw
->not_run_ready
++;
2563 if (vdec
->parallel_dec
== 1)
2564 return (unsigned long)(CORE_MASK_VDEC_1
);
2566 return (unsigned long)(CORE_MASK_VDEC_1
| CORE_MASK_HEVC
);
2571 static void vavs_work(struct work_struct
*work
)
2573 struct vdec_avs_hw_s
*hw
=
2574 container_of(work
, struct vdec_avs_hw_s
, work
);
2575 struct vdec_s
*vdec
= hw_to_vdec(hw
);
2576 if (hw
->dec_result
!= DEC_RESULT_AGAIN
)
2577 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,
2578 "ammvdec_avs: vavs_work,result=%d,status=%d\n",
2579 hw
->dec_result
, hw_to_vdec(hw
)->next_status
);
2581 if (hw
->dec_result
== DEC_RESULT_USERDATA
) {
2582 userdata_push_process(hw
);
2584 } else if (hw
->dec_result
== DEC_RESULT_DONE
) {
2588 #ifdef DEBUG_MULTI_FRAME_INS
2591 vdec_vframe_dirty(hw_to_vdec(hw
), hw
->chunk
);
2592 } else if (hw
->dec_result
== DEC_RESULT_AGAIN
2593 && (hw_to_vdec(hw
)->next_status
!=
2594 VDEC_STATUS_DISCONNECTED
)) {
2596 stream base: stream buf empty or timeout
2597 frame base: vdec_prepare_input fail
2600 if (!vdec_has_more_input(hw_to_vdec(hw
))) {
2601 hw
->dec_result
= DEC_RESULT_EOS
;
2602 vdec_schedule_work(&hw
->work
);
2605 } else if (hw
->dec_result
== DEC_RESULT_GET_DATA
2606 && (hw_to_vdec(hw
)->next_status
!=
2607 VDEC_STATUS_DISCONNECTED
)) {
2608 if (!vdec_has_more_input(hw_to_vdec(hw
))) {
2609 hw
->dec_result
= DEC_RESULT_EOS
;
2610 vdec_schedule_work(&hw
->work
);
2613 debug_print(hw
, PRINT_FLAG_VLD_DETAIL
,
2614 "%s DEC_RESULT_GET_DATA %x %x %x\n",
2616 READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
2617 READ_VREG(VLD_MEM_VIFIFO_WP
),
2618 READ_VREG(VLD_MEM_VIFIFO_RP
));
2619 vdec_vframe_dirty(hw_to_vdec(hw
), hw
->chunk
);
2620 vdec_clean_input(hw_to_vdec(hw
));
2622 } else if (hw
->dec_result
== DEC_RESULT_FORCE_EXIT
) {
2623 debug_print(hw
, PRINT_FLAG_ERROR
,
2624 "%s: force exit\n", __func__
);
2625 if (hw
->stat
& STAT_ISR_REG
) {
2627 /*disable mbox interrupt */
2628 WRITE_VREG(ASSIST_MBOX1_MASK
, 0);
2629 vdec_free_irq(VDEC_IRQ_1
, (void *)hw
);
2630 hw
->stat
&= ~STAT_ISR_REG
;
2632 } else if (hw
->dec_result
== DEC_RESULT_EOS
) {
2633 debug_print(hw
, PRINT_FLAG_DECODING
,
2634 "%s: end of stream\n", __func__
);
2635 if (hw
->stat
& STAT_VDEC_RUN
) {
2637 hw
->stat
&= ~STAT_VDEC_RUN
;
2640 vdec_vframe_dirty(hw_to_vdec(hw
), hw
->chunk
);
2641 vdec_clean_input(hw_to_vdec(hw
));
2643 if (hw
->stat
& STAT_VDEC_RUN
) {
2644 #if DEBUG_MULTI_FLAG == 1
2648 hw
->stat
&= ~STAT_VDEC_RUN
;
2650 /*wait_vmmpeg12_search_done(hw);*/
2651 if (hw
->stat
& STAT_TIMER_ARM
) {
2652 del_timer_sync(&hw
->check_timer
);
2653 hw
->stat
&= ~STAT_TIMER_ARM
;
2655 if (hw
->dec_result
== DEC_RESULT_DONE
)
2656 hw
->buf_recycle_status
= 0;
2657 debug_print(hw
, PRINT_FLAG_RUN_FLOW
, "work end %d\n", hw
->dec_result
);
2658 if (vdec
->parallel_dec
== 1)
2659 vdec_core_finish_run(hw_to_vdec(hw
), CORE_MASK_VDEC_1
);
2661 vdec_core_finish_run(hw_to_vdec(hw
), CORE_MASK_VDEC_1
| CORE_MASK_HEVC
);
2664 hw
->vdec_cb(hw_to_vdec(hw
), hw
->vdec_cb_arg
);
2665 debug_print(hw
, 0x80000,
2671 static void reset_process_time(struct vdec_avs_hw_s
*hw
)
2673 if (!hw
->m_ins_flag
)
2675 if (hw
->start_process_time
) {
2676 unsigned process_time
=
2677 1000 * (jiffies
- hw
->start_process_time
) / HZ
;
2678 hw
->start_process_time
= 0;
2679 if (process_time
> max_process_time
[DECODE_ID(hw
)])
2680 max_process_time
[DECODE_ID(hw
)] = process_time
;
2683 static void start_process_time(struct vdec_avs_hw_s
*hw
)
2685 hw
->decode_timeout_count
= 2;
2686 hw
->start_process_time
= jiffies
;
2689 static void handle_decoding_error(struct vdec_avs_hw_s
*hw
)
2692 unsigned long flags
;
2693 struct vframe_s
*vf
;
2694 spin_lock_irqsave(&lock
, flags
);
2695 for (i
= 0; i
< VF_POOL_SIZE
; i
++) {
2696 vf
= &hw
->vfpool
[i
].vf
;
2697 if (vf
->index
< hw
->vf_buf_num_used
) {
2698 hw
->vfpool
[i
].detached
= 1;
2699 hw
->vfbuf_use
[vf
->index
] = 0;
2702 if (error_handle_policy
& 0x2) {
2703 while (!kfifo_is_empty(&hw
->display_q
)) {
2704 if (kfifo_get(&hw
->display_q
, &vf
)) {
2705 if (buf_of_vf(vf
)->detached
!=0) {
2706 debug_print(hw
, PRINT_FLAG_DECODING
,
2707 "%s recycle %d => newframe_q\n",
2710 vf
->index
= hw
->vf_buf_num_used
;
2711 buf_of_vf(vf
)->detached
= 0;
2712 kfifo_put(&hw
->newframe_q
,
2713 (const struct vframe_s
*)vf
);
2720 hw
->decode_pic_count
= 0;
2721 hw
->reset_decode_flag
= 1;
2722 hw
->pre_parser_wr_ptr
= 0;
2724 hw
->throw_pb_flag
= 1;
2725 spin_unlock_irqrestore(&lock
, flags
);
2728 static void timeout_process(struct vdec_avs_hw_s
*hw
)
2730 struct vdec_s
*vdec
= hw_to_vdec(hw
);
2732 if (error_handle_policy
& 0x1) {
2733 handle_decoding_error(hw
);
2737 if (hw
->decode_pic_count
== 0)
2738 hw
->decode_pic_count
++;
2740 hw
->dec_result
= DEC_RESULT_DONE
;
2742 debug_print(hw
, PRINT_FLAG_ERROR
,
2743 "%s decoder timeout, status=%d, level=%d, bit_cnt=0x%x\n",
2744 __func__
, vdec
->status
, READ_VREG(VLD_MEM_VIFIFO_LEVEL
), READ_VREG(VIFF_BIT_CNT
));
2745 reset_process_time(hw
);
2746 vdec_schedule_work(&hw
->work
);
2750 static void recycle_frame_bufferin(struct vdec_avs_hw_s
*hw
)
2752 if (!kfifo_is_empty(&hw
->recycle_q
) && (READ_VREG(AVS_BUFFERIN
) == 0)) {
2753 struct vframe_s
*vf
;
2755 if (kfifo_get(&hw
->recycle_q
, &vf
)) {
2756 if (buf_of_vf(vf
)->detached
) {
2758 "%s recycle detached vf, index=%d detched %d used %d\n",
2759 __func__
, vf
->index
,
2760 buf_of_vf(vf
)->detached
,
2761 hw
->vfbuf_use
[vf
->index
]);
2763 if ((vf
->index
< hw
->vf_buf_num_used
) &&
2764 (buf_of_vf(vf
)->detached
== 0) &&
2765 (--hw
->vfbuf_use
[vf
->index
] == 0)) {
2766 hw
->buf_recycle_status
|= (1 << vf
->index
);
2767 WRITE_VREG(AVS_BUFFERIN
, ~(1 << vf
->index
));
2768 debug_print(hw
, PRINT_FLAG_DECODING
,
2769 "%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for vf index of %d => buf_recycle_status 0x%x\n",
2771 READ_VREG(AVS_BUFFERIN
), vf
->index
,
2772 hw
->buf_recycle_status
);
2774 vf
->index
= hw
->vf_buf_num_used
;
2775 buf_of_vf(vf
)->detached
= 0;
2776 kfifo_put(&hw
->newframe_q
,
2777 (const struct vframe_s
*)vf
);
2784 static void recycle_frames(struct vdec_avs_hw_s
*hw
)
2786 while (!kfifo_is_empty(&hw
->recycle_q
)) {
2787 struct vframe_s
*vf
;
2789 if (kfifo_get(&hw
->recycle_q
, &vf
)) {
2790 if (buf_of_vf(vf
)->detached
) {
2792 "%s recycle detached vf, index=%d detched %d used %d\n",
2793 __func__
, vf
->index
,
2794 buf_of_vf(vf
)->detached
,
2795 hw
->vfbuf_use
[vf
->index
]);
2799 if ((vf
->index
< hw
->vf_buf_num_used
) &&
2800 (buf_of_vf(vf
)->detached
== 0) &&
2801 (--hw
->vfbuf_use
[vf
->index
] == 0)) {
2802 hw
->buf_recycle_status
|= (1 << vf
->index
);
2803 debug_print(hw
, PRINT_FLAG_DECODING
,
2804 "%s for vf index of %d => buf_recycle_status 0x%x\n",
2807 hw
->buf_recycle_status
);
2809 vf
->index
= hw
->vf_buf_num_used
;
2810 buf_of_vf(vf
)->detached
= 0;
2811 kfifo_put(&hw
->newframe_q
,
2812 (const struct vframe_s
*)vf
);
2820 static void check_timer_func(unsigned long arg
)
2822 struct vdec_avs_hw_s
*hw
= (struct vdec_avs_hw_s
*)arg
;
2823 struct vdec_s
*vdec
= hw_to_vdec(hw
);
2824 unsigned int timeout_val
= decode_timeout_val
;
2825 unsigned long flags
;
2827 if (hw
->m_ins_flag
&&
2829 DEBUG_WAIT_DECODE_DONE_WHEN_STOP
) == 0 &&
2830 vdec
->next_status
==
2831 VDEC_STATUS_DISCONNECTED
) {
2832 hw
->dec_result
= DEC_RESULT_FORCE_EXIT
;
2833 vdec_schedule_work(&hw
->work
);
2835 0, "vdec requested to be disconnected\n");
2840 if (!hw
->m_ins_flag
) {
2841 spin_lock_irqsave(&lock
, flags
);
2842 recycle_frame_bufferin(hw
);
2843 spin_unlock_irqrestore(&lock
, flags
);
2846 if (hw
->m_ins_flag
) {
2847 if ((READ_VREG(AV_SCRATCH_5
) & 0xf) != 0 &&
2848 (READ_VREG(AV_SCRATCH_5
) & 0xff00) != 0){
2849 /*ucode buffer empty*/
2850 if ((kfifo_len(&hw
->recycle_q
) == 0) &&
2851 (kfifo_len(&hw
->display_q
) == 0)) {
2853 0, "AV_SCRATCH_5=0x%x, recover ucode buffer_status\n",
2854 READ_VREG(AV_SCRATCH_5
));
2855 WRITE_VREG(AV_SCRATCH_5
, 0x10);
2856 /*let ucode to recover buffer_status*/
2862 WRITE_VREG(radr
, rval
);
2863 pr_info("WRITE_VREG(%x,%x)\n", radr
, rval
);
2865 pr_info("READ_VREG(%x)=%x\n", radr
, READ_VREG(radr
));
2870 if (udebug_flag
!= hw
->old_udebug_flag
) {
2871 WRITE_VREG(DECODE_STOP_POS
, udebug_flag
);
2872 hw
->old_udebug_flag
= udebug_flag
;
2876 int r
= vdec_sync_input(vdec
);
2879 "vdec_sync_input=>0x%x, (lev %x, wp %x rp %x, prp %x, pwp %x)\n",
2881 READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
2882 READ_VREG(VLD_MEM_VIFIFO_WP
),
2883 READ_VREG(VLD_MEM_VIFIFO_RP
),
2884 STBUF_READ(&vdec
->vbuf
, get_rp
),
2885 STBUF_READ(&vdec
->vbuf
, get_wp
));
2889 if ((debug
& DEBUG_FLAG_DISABLE_TIMEOUT
) == 0 &&
2890 (timeout_val
> 0) &&
2891 (hw
->start_process_time
> 0) &&
2892 ((1000 * (jiffies
- hw
->start_process_time
) / HZ
)
2894 if (hw
->last_vld_level
== READ_VREG(VLD_MEM_VIFIFO_LEVEL
)) {
2895 if (hw
->decode_timeout_count
> 0)
2896 hw
->decode_timeout_count
--;
2897 if (hw
->decode_timeout_count
== 0)
2898 timeout_process(hw
);
2900 hw
->last_vld_level
= READ_VREG(VLD_MEM_VIFIFO_LEVEL
);
2903 if (READ_VREG(AVS_SOS_COUNT
)) {
2904 if (!error_recovery_mode
) {
2906 if (error_handle_policy
& 0x1) {
2907 handle_decoding_error(hw
);
2911 if (hw
->decode_pic_count
== 0)
2912 hw
->decode_pic_count
++;
2914 hw
->dec_result
= DEC_RESULT_DONE
;
2916 debug_print(hw
, PRINT_FLAG_ERROR
,
2917 "%s decoder error, status=%d, level=%d, AVS_SOS_COUNT=0x%x\n",
2918 __func__
, vdec
->status
, READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
2919 READ_VREG(AVS_SOS_COUNT
));
2920 reset_process_time(hw
);
2921 vdec_schedule_work(&hw
->work
);
2925 if ((hw
->ucode_pause_pos
!= 0) &&
2926 (hw
->ucode_pause_pos
!= 0xffffffff) &&
2927 udebug_pause_pos
!= hw
->ucode_pause_pos
) {
2928 hw
->ucode_pause_pos
= 0;
2929 WRITE_VREG(DEBUG_REG1
, 0);
2932 if (vdec
->next_status
== VDEC_STATUS_DISCONNECTED
) {
2933 hw
->dec_result
= DEC_RESULT_FORCE_EXIT
;
2934 vdec_schedule_work(&hw
->work
);
2935 pr_info("vdec requested to be disconnected\n");
2939 mod_timer(&hw
->check_timer
, jiffies
+ CHECK_INTERVAL
);
2942 static int avs_hw_ctx_restore(struct vdec_avs_hw_s
*hw
)
2950 static unsigned char get_data_check_sum
2951 (struct vdec_avs_hw_s
*hw
, int size
)
2957 if (!hw
->chunk
->block
->is_mapped
)
2958 data
= codec_mm_vmap(hw
->chunk
->block
->start
+
2959 hw
->chunk
->offset
, size
);
2961 data
= ((u8
*)hw
->chunk
->block
->start_virt
) +
2964 for (jj
= 0; jj
< size
; jj
++)
2967 if (!hw
->chunk
->block
->is_mapped
)
2968 codec_mm_unmap_phyaddr(data
);
2972 static void run(struct vdec_s
*vdec
, unsigned long mask
,
2973 void (*callback
)(struct vdec_s
*, void *),
2976 struct vdec_avs_hw_s
*hw
=
2977 (struct vdec_avs_hw_s
*)vdec
->private;
2978 int save_reg
= READ_VREG(POWER_CTL_VLD
);
2980 /* reset everything except DOS_TOP[1] and APB_CBUS[0]*/
2981 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,"run in\n");
2982 if (vdec_stream_based(vdec
)) {
2983 hw
->pre_parser_wr_ptr
=
2984 STBUF_READ(&vdec
->vbuf
, get_wp
);
2987 #if DEBUG_MULTI_FLAG > 0
2988 if (hw
->decode_pic_count
== 0) {
2990 WRITE_VREG(DOS_SW_RESET0
, 0xfffffff0);
2991 WRITE_VREG(DOS_SW_RESET0
, 0);
2992 WRITE_VREG(POWER_CTL_VLD
, save_reg
);
2994 run_count
[DECODE_ID(hw
)] = hw
->run_count
;
2995 vdec_reset_core(vdec
);
2996 #if DEBUG_MULTI_FLAG > 0
3000 vdec_reset_core(vdec
);
3002 hw
->vdec_cb_arg
= arg
;
3003 hw
->vdec_cb
= callback
;
3005 size
= vdec_prepare_input(vdec
, &hw
->chunk
);
3006 if (debug
& DEBUG_FLAG_PREPARE_MORE_INPUT
) {
3007 if (size
< start_decode_buf_level
) {
3008 /*debug_print(hw, PRINT_FLAG_VLD_DETAIL,
3009 "DEC_RESULT_AGAIN %x %x %x\n",
3010 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
3011 READ_VREG(VLD_MEM_VIFIFO_WP),
3012 READ_VREG(VLD_MEM_VIFIFO_RP));*/
3015 hw
->dec_result
= DEC_RESULT_AGAIN
;
3016 vdec_schedule_work(&hw
->work
);
3022 hw
->dec_result
= DEC_RESULT_AGAIN
;
3023 vdec_schedule_work(&hw
->work
);
3027 if (input_frame_based(vdec
)) {
3030 if (!hw
->chunk
->block
->is_mapped
)
3031 data
= codec_mm_vmap(hw
->chunk
->block
->start
+
3032 hw
->chunk
->offset
, size
);
3034 data
= ((u8
*)hw
->chunk
->block
->start_virt
) +
3037 if (debug
& PRINT_FLAG_RUN_FLOW
3040 "%s decode_pic_count %d buf_recycle_status 0x%x: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
3041 __func__
, hw
->decode_pic_count
,
3042 hw
->buf_recycle_status
,
3043 size
, get_data_check_sum(hw
, size
),
3044 data
[0], data
[1], data
[2], data
[3],
3045 data
[4], data
[5], data
[size
- 4],
3046 data
[size
- 3], data
[size
- 2],
3049 if (debug
& PRINT_FRAMEBASE_DATA
3053 for (jj
= 0; jj
< size
; jj
++) {
3054 if ((jj
& 0xf) == 0)
3056 PRINT_FRAMEBASE_DATA
,
3059 PRINT_FRAMEBASE_DATA
,
3061 if (((jj
+ 1) & 0xf) == 0)
3063 PRINT_FRAMEBASE_DATA
,
3068 if (!hw
->chunk
->block
->is_mapped
)
3069 codec_mm_unmap_phyaddr(data
);
3071 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,
3072 "%s decode_pic_count %d buf_recycle_status 0x%x: %x %x %x %x %x size 0x%x\n",
3074 hw
->decode_pic_count
,
3075 hw
->buf_recycle_status
,
3076 READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
3077 READ_VREG(VLD_MEM_VIFIFO_WP
),
3078 READ_VREG(VLD_MEM_VIFIFO_RP
),
3079 STBUF_READ(&vdec
->vbuf
, get_rp
),
3080 STBUF_READ(&vdec
->vbuf
, get_wp
),
3084 hw
->input_empty
= 0;
3085 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,
3086 "%s,%d, size=%d\n", __func__
, __LINE__
, size
);
3088 /*vdec_enable_input(vdec);
3089 need run after VC1_CONTROL_REG is configured
3094 debug_print(hw
, PRINT_FLAG_RUN_FLOW
,
3095 "input chunk offset %d, size %d\n",
3096 hw
->chunk
->offset
, hw
->chunk
->size
);
3098 hw
->dec_result
= DEC_RESULT_NONE
;
3099 /*vdec->mc_loaded = 0;*/
3100 if (vdec
->mc_loaded
) {
3101 /*firmware have load before,
3102 and not changes to another.
3106 ret
= amvdec_vdec_loadmc_buf_ex(VFORMAT_AVS
, "avs_multi", vdec
,
3107 hw
->fw
->data
, hw
->fw
->len
);
3109 pr_err("[%d] %s: the %s fw loading failed, err: %x\n", vdec
->id
,
3110 hw
->fw
->name
, tee_enabled() ? "TEE" : "local", ret
);
3111 hw
->dec_result
= DEC_RESULT_FORCE_EXIT
;
3112 vdec_schedule_work(&hw
->work
);
3115 vdec
->mc_loaded
= 1;
3116 vdec
->mc_type
= VFORMAT_AVS
;
3118 if (avs_hw_ctx_restore(hw
) < 0) {
3119 hw
->dec_result
= DEC_RESULT_ERROR
;
3120 debug_print(hw
, PRINT_FLAG_ERROR
,
3121 "ammvdec_avs: error HW context restore\n");
3122 vdec_schedule_work(&hw
->work
);
3127 This configureation of VC1_CONTROL_REG will
3128 pop bits (even no data in the stream buffer) if input is enabled,
3129 so it can only be configured before vdec_enable_input() is called.
3130 So move this code from ucode to here
3132 #define DISABLE_DBLK_HCMD 0
3133 #define DISABLE_MC_HCMD 0
3134 WRITE_VREG(VC1_CONTROL_REG
, (DISABLE_DBLK_HCMD
<<6) |
3135 (DISABLE_MC_HCMD
<<5) | (1 << 7) | (0xc <<8) | (1<<14));
3136 if (vdec_frame_based(vdec
)) {
3137 size
= hw
->chunk
->size
+
3138 (hw
->chunk
->offset
& (VDEC_FIFO_ALIGN
- 1));
3142 vdec_enable_input(vdec
);
3146 hw
->stat
|= STAT_MC_LOAD
;
3147 hw
->last_vld_level
= 0;
3149 debug_print(hw
, PRINT_FLAG_DECODING
,
3150 "%s READ_VREG(AVS_BUFFERIN)=0x%x, recycle_q num %d\n",
3151 __func__
, READ_VREG(AVS_BUFFERIN
),
3152 kfifo_len(&hw
->recycle_q
));
3153 WRITE_VREG(VIFF_BIT_CNT
, size
* 8);
3155 if (hw
->reset_decode_flag
)
3156 WRITE_VREG(DECODE_STATUS
, 0);
3159 avs_pts_check_in(hw
,
3160 hw
->decode_pic_count
& 0xffff,
3163 WRITE_VREG(DECODE_STATUS
,
3164 (hw
->decode_pic_count
& 0xffff) |
3165 ((~hw
->buf_recycle_status
) << 16));
3168 hw
->reset_decode_flag
= 0;
3169 //hw->decode_status_skip_pic_done_flag = 0;
3170 start_process_time(hw
);
3171 #if DEBUG_MULTI_FLAG == 1
3172 if (hw
->decode_pic_count
> 0)
3173 WRITE_VREG(DECODE_STATUS
, 0xff);
3177 hw
->stat
|= STAT_VDEC_RUN
;
3179 hw
->stat
|= STAT_TIMER_ARM
;
3181 mod_timer(&hw
->check_timer
, jiffies
+ CHECK_INTERVAL
);
3184 static void reset(struct vdec_s
*vdec
)
3188 static irqreturn_t
vmavs_isr_thread_fn(struct vdec_s
*vdec
, int irq
)
3190 struct vdec_avs_hw_s
*hw
=
3191 (struct vdec_avs_hw_s
*)vdec
->private;
3193 struct vframe_s
*vf
= NULL
;
3199 bool force_interlaced_frame
= false;
3200 unsigned int pts
, pts_valid
= 0, offset
= 0;
3203 u32 buffer_status_debug
;
3204 //struct vdec_avs_hw_s *hw = (struct vdec_avs_hw_s *)dev_id;
3206 /*if (debug & AVS_DEBUG_UCODE) {
3207 if (READ_VREG(AV_SCRATCH_E) != 0) {
3208 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_E),
3209 READ_VREG(AV_SCRATCH_D));
3210 WRITE_VREG(AV_SCRATCH_E, 0);
3214 debug_print(hw
, PRINT_FLAG_RUN_FLOW
, "READ_VREG(AVS_BUFFEROUT) 0x%x, READ_VREG(DECODE_STATUS) 0x%x READ_VREG(AV_SCRATCH_N) 0x%x, READ_VREG(DEBUG_REG1) 0x%x\n",
3215 READ_VREG(AVS_BUFFEROUT
),READ_VREG(DECODE_STATUS
), READ_VREG(AV_SCRATCH_N
), READ_VREG(DEBUG_REG1
));
3217 debug_tag
= READ_VREG(DEBUG_REG1
);
3218 buffer_status_debug
= debug_tag
>> 16;
3219 debug_tag
&= 0xffff;
3220 /* if (debug_tag & 0x10000) {
3222 dma_sync_single_for_cpu(
3223 amports_get_dma_device(),
3229 "LMEM<tag %x>:\n", debug_tag);
3231 for (i = 0; i < 0x400; i += 4) {
3233 unsigned short *lmem_ptr = hw->lmem_addr;
3235 debug_print_cont(hw, 0, "%03x: ", i);
3236 for (ii = 0; ii < 4; ii++) {
3237 debug_print_cont(hw, 0, "%04x ",
3238 lmem_ptr[i + 3 - ii]);
3240 if (((i + ii) & 0xf) == 0)
3241 debug_print_cont(hw, 0, "\n");
3244 if (((udebug_pause_pos & 0xffff)
3245 == (debug_tag & 0xffff)) &&
3246 (udebug_pause_decode_idx == 0 ||
3247 udebug_pause_decode_idx == hw->decode_pic_count) &&
3248 (udebug_pause_val == 0 ||
3249 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
3250 udebug_pause_pos &= 0xffff;
3251 hw->ucode_pause_pos = udebug_pause_pos;
3253 else if (debug_tag & 0x20000)
3254 hw->ucode_pause_pos = 0xffffffff;
3255 if (hw->ucode_pause_pos)
3256 reset_process_time(hw);
3258 WRITE_VREG(DEBUG_REG1, 0);
3259 } else*/ if (debug_tag
!= 0) {
3261 "dbg%x: %x buffer_status 0x%x l/w/r %x %x %x bitcnt %x AVAIL %x\n",
3263 READ_VREG(DEBUG_REG2
),
3264 buffer_status_debug
,
3265 READ_VREG(VLD_MEM_VIFIFO_LEVEL
),
3266 READ_VREG(VLD_MEM_VIFIFO_WP
),
3267 READ_VREG(VLD_MEM_VIFIFO_RP
),
3268 READ_VREG(VIFF_BIT_CNT
),
3269 READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL
));
3271 if (((udebug_pause_pos
& 0xffff)
3272 == (debug_tag
& 0xffff)) &&
3273 (udebug_pause_decode_idx
== 0 ||
3274 udebug_pause_decode_idx
== hw
->decode_pic_count
) &&
3275 (udebug_pause_val
== 0 ||
3276 udebug_pause_val
== READ_VREG(DEBUG_REG2
)) &&
3277 (udebug_pause_ins_id
== 0 ||
3278 DECODE_ID(hw
) == (udebug_pause_ins_id
-1))) {
3279 udebug_pause_pos
&= 0xffff;
3280 hw
->ucode_pause_pos
= udebug_pause_pos
;
3281 if (debug
& DEBUG_PIC_DONE_WHEN_UCODE_PAUSE
) {
3282 hw
->decode_pic_count
++;
3283 if ((hw
->decode_pic_count
& 0xffff) == 0) {
3284 /*make ucode do not handle it as first picture*/
3285 hw
->decode_pic_count
++;
3287 reset_process_time(hw
);
3288 hw
->dec_result
= DEC_RESULT_DONE
;
3291 debug_print(hw
, PRINT_FLAG_DECODING
,
3292 "%s ucode pause, force done, decode_pic_count = %d, bit_cnt=0x%x\n",
3294 hw
->decode_pic_count
,
3295 READ_VREG(VIFF_BIT_CNT
));
3296 vdec_schedule_work(&hw
->work
);
3300 if (hw
->ucode_pause_pos
)
3301 reset_process_time(hw
);
3303 WRITE_VREG(DEBUG_REG1
, 0);
3306 debug_print(hw
, PRINT_FLAG_DECODING
,
3307 "%s decode_status 0x%x, buffer_status 0x%x\n",
3309 READ_VREG(DECODE_STATUS
),
3310 buffer_status_debug
);
3313 #ifdef AVSP_LONG_CABAC
3314 if (firmware_sel
== 0 && READ_VREG(LONG_CABAC_REQ
)) {
3315 #ifdef PERFORMANCE_DEBUG
3316 pr_info("%s:schedule long_cabac_wd_work\r\n", __func__
);
3318 pr_info("schedule long_cabac_wd_work and requested from %d\n",
3319 (READ_VREG(LONG_CABAC_REQ
) >> 8)&0xFF);
3320 schedule_work(&long_cabac_wd_work
);
3324 #ifdef ENABLE_USER_DATA
3325 if (UserDataHandler(hw
))
3328 reg
= READ_VREG(AVS_BUFFEROUT
);
3330 unsigned short decode_pic_count
3331 = READ_VREG(DECODE_PIC_COUNT
);
3332 debug_print(hw
, PRINT_FLAG_DECODING
, "AVS_BUFFEROUT=0x%x decode_pic_count %d\n",
3333 reg
, decode_pic_count
);
3334 if (pts_by_offset
) {
3335 offset
= READ_VREG(AVS_OFFSET_REG
);
3336 debug_print(hw
, PRINT_FLAG_DECODING
, "AVS OFFSET=%x\n", offset
);
3337 if ((vdec
->vbuf
.no_parser
== 0) || (vdec
->vbuf
.use_ptsserv
)) {
3338 if (pts_lookup_offset_us64(PTS_TYPE_VIDEO
, offset
, &pts
,
3339 &frame_size
, 0, &pts_us64
) == 0) {
3352 repeat_count
= READ_VREG(AVS_REPEAT_COUNT
);
3353 #ifdef USE_DYNAMIC_BUF_NUM
3356 (((reg
>> 8) & 0x3) << 3) - 1) & 0x1f;
3358 if (firmware_sel
== 0)
3361 (((reg
>> 8) & 0x3) << 3) - 1) & 0x1f;
3364 ((reg
& 0x7) - 1) & 3;
3366 picture_type
= (reg
>> 3) & 7;
3368 if (picture_type
== I_PICTURE
) {
3369 /* pr_info("I offset 0x%x, pts_valid %d\n",
3370 * offset, pts_valid);
3379 if ((dec_control
& DEC_CONTROL_FLAG_FORCE_2500_1080P_INTERLACE
)
3380 && hw
->frame_width
== 1920 && hw
->frame_height
== 1080) {
3381 force_interlaced_frame
= true;
3384 if (hw
->throw_pb_flag
&& picture_type
!= I_PICTURE
) {
3386 debug_print(hw
, PRINT_FLAG_DECODING
,
3387 "%s WRITE_VREG(AVS_BUFFERIN, 0x%x) for throwing picture with type of %d\n",
3389 ~(1 << buffer_index
), picture_type
);
3391 WRITE_VREG(AVS_BUFFERIN
, ~(1 << buffer_index
));
3392 } else if (reg
& INTERLACE_FLAG
|| force_interlaced_frame
) { /* interlace */
3393 hw
->throw_pb_flag
= 0;
3395 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
3396 "interlace, picture type %d\n",
3399 if (kfifo_get(&hw
->newframe_q
, &vf
) == 0) {
3401 ("fatal error, no available buffer slot.");
3404 set_frame_info(hw
, vf
, &dur
);
3405 vf
->bufWidth
= 1920;
3407 if ((picture_type
== I_PICTURE
) && pts_valid
) {
3409 vf
->pts_us64
= pts_us64
;
3410 if ((repeat_count
> 1) && hw
->avi_flag
) {
3411 /* hw->next_pts = pts +
3412 * (hw->vavs_amstream_dec_info.rate *
3413 * repeat_count >> 1)*15/16;
3417 (dur
* repeat_count
>> 1) *
3422 vf
->pts
= hw
->next_pts
;
3426 if ((repeat_count
> 1) && hw
->avi_flag
) {
3428 * hw->vavs_amstream_dec_info.rate *
3429 * repeat_count >> 1;
3431 vf
->duration
= dur
* repeat_count
>> 1;
3432 if (hw
->next_pts
!= 0) {
3435 ((vf
->duration
) >> 4));
3439 * hw->vavs_amstream_dec_info.rate >> 1;
3441 vf
->duration
= dur
>> 1;
3445 vf
->signal_type
= 0;
3446 vf
->index
= buffer_index
;
3447 vf
->duration_pulldown
= 0;
3448 if (force_interlaced_frame
) {
3449 vf
->type
= VIDTYPE_INTERLACE_TOP
;
3452 (reg
& TOP_FIELD_FIRST_FLAG
)
3453 ? VIDTYPE_INTERLACE_TOP
3454 : VIDTYPE_INTERLACE_BOTTOM
;
3457 vf
->type
|= VIDTYPE_VIU_NV21
;
3459 if (hw
->m_ins_flag
) {
3460 vf
->canvas0Addr
= vf
->canvas1Addr
= -1;
3463 vf
->canvas0_config
[0] = hw
->canvas_config
[buffer_index
][0];
3464 vf
->canvas0_config
[1] = hw
->canvas_config
[buffer_index
][1];
3466 vf
->canvas1_config
[0] = hw
->canvas_config
[buffer_index
][0];
3467 vf
->canvas1_config
[1] = hw
->canvas_config
[buffer_index
][1];
3469 vf
->canvas0Addr
= vf
->canvas1Addr
=
3470 index2canvas(buffer_index
);
3471 vf
->type_original
= vf
->type
;
3473 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
3474 "buffer_index %d, canvas addr %x\n",
3475 buffer_index
, vf
->canvas0Addr
);
3476 vf
->pts
= (pts_valid
)?pts
:0;
3477 //vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
3478 hw
->vfbuf_use
[buffer_index
]++;
3480 decoder_bmmu_box_get_mem_handle(
3484 if (hw
->m_ins_flag
&& vdec_frame_based(hw_to_vdec(hw
)))
3485 set_vframe_pts(hw
, decode_pic_count
, vf
);
3487 if (vdec_stream_based(vdec
) && (!vdec
->vbuf
.use_ptsserv
)) {
3488 vf
->pts_us64
= offset
;
3492 debug_print(hw
, PRINT_FLAG_PTS
,
3493 "interlace1 vf->pts = %d, vf->pts_us64 = %lld, pts_valid = %d\n", vf
->pts
, vf
->pts_us64
, pts_valid
);
3494 kfifo_put(&hw
->display_q
,
3495 (const struct vframe_s
*)vf
);
3496 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
3497 VFRAME_EVENT_PROVIDER_VFRAME_READY
,
3500 if (kfifo_get(&hw
->newframe_q
, &vf
) == 0) {
3501 pr_info("fatal error, no available buffer slot.");
3504 set_frame_info(hw
, vf
, &dur
);
3505 vf
->bufWidth
= 1920;
3506 if (force_interlaced_frame
)
3509 vf
->pts
= hw
->next_pts
;
3515 if ((repeat_count
> 1) && hw
->avi_flag
) {
3516 /* vf->duration = hw->vavs_amstream_dec_info.rate *
3517 * repeat_count >> 1;
3519 vf
->duration
= dur
* repeat_count
>> 1;
3520 if (hw
->next_pts
!= 0) {
3523 ((vf
->duration
) >> 4));
3526 /* vf->duration = hw->vavs_amstream_dec_info.rate
3529 vf
->duration
= dur
>> 1;
3532 vf
->signal_type
= 0;
3533 vf
->index
= buffer_index
;
3534 vf
->duration_pulldown
= 0;
3535 if (force_interlaced_frame
) {
3536 vf
->type
= VIDTYPE_INTERLACE_BOTTOM
;
3539 (reg
& TOP_FIELD_FIRST_FLAG
) ?
3540 VIDTYPE_INTERLACE_BOTTOM
:
3541 VIDTYPE_INTERLACE_TOP
;
3544 vf
->type
|= VIDTYPE_VIU_NV21
;
3546 if (hw
->m_ins_flag
) {
3547 vf
->canvas0Addr
= vf
->canvas1Addr
= -1;
3550 vf
->canvas0_config
[0] = hw
->canvas_config
[buffer_index
][0];
3551 vf
->canvas0_config
[1] = hw
->canvas_config
[buffer_index
][1];
3553 vf
->canvas1_config
[0] = hw
->canvas_config
[buffer_index
][0];
3554 vf
->canvas1_config
[1] = hw
->canvas_config
[buffer_index
][1];
3556 vf
->canvas0Addr
= vf
->canvas1Addr
=
3557 index2canvas(buffer_index
);
3558 vf
->type_original
= vf
->type
;
3560 hw
->vfbuf_use
[buffer_index
]++;
3562 decoder_bmmu_box_get_mem_handle(
3566 if (hw
->m_ins_flag
&& vdec_frame_based(hw_to_vdec(hw
)))
3567 set_vframe_pts(hw
, decode_pic_count
, vf
);
3569 if (vdec_stream_based(vdec
) && (!vdec
->vbuf
.use_ptsserv
)) {
3570 vf
->pts_us64
= offset
;
3573 debug_print(hw
, PRINT_FLAG_PTS
,
3574 "interlace2 vf->pts = %d, vf->pts_us64 = %lld, pts_valid = %d\n", vf
->pts
, vf
->pts_us64
, pts_valid
);
3575 kfifo_put(&hw
->display_q
,
3576 (const struct vframe_s
*)vf
);
3577 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
3578 VFRAME_EVENT_PROVIDER_VFRAME_READY
,
3581 } else { /* progressive */
3582 hw
->throw_pb_flag
= 0;
3584 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
3585 "progressive picture type %d\n",
3587 if (kfifo_get(&hw
->newframe_q
, &vf
) == 0) {
3589 ("fatal error, no available buffer slot.");
3592 set_frame_info(hw
, vf
, &dur
);
3593 vf
->bufWidth
= 1920;
3596 if ((picture_type
== I_PICTURE
) && pts_valid
) {
3598 if ((repeat_count
> 1) && hw
->avi_flag
) {
3599 /* hw->next_pts = pts +
3600 * (hw->vavs_amstream_dec_info.rate *
3601 * repeat_count)*15/16;
3605 (dur
* repeat_count
) * 15 / 16;
3609 vf
->pts
= hw
->next_pts
;
3613 if ((repeat_count
> 1) && hw
->avi_flag
) {
3615 * hw->vavs_amstream_dec_info.rate *
3618 vf
->duration
= dur
* repeat_count
;
3619 if (hw
->next_pts
!= 0) {
3622 ((vf
->duration
) >> 4));
3626 * hw->vavs_amstream_dec_info.rate;
3632 vf
->signal_type
= 0;
3633 vf
->index
= buffer_index
;
3634 vf
->duration_pulldown
= 0;
3635 vf
->type
= VIDTYPE_PROGRESSIVE
| VIDTYPE_VIU_FIELD
;
3637 vf
->type
|= VIDTYPE_VIU_NV21
;
3639 if (hw
->m_ins_flag
) {
3640 vf
->canvas0Addr
= vf
->canvas1Addr
= -1;
3643 vf
->canvas0_config
[0] = hw
->canvas_config
[buffer_index
][0];
3644 vf
->canvas0_config
[1] = hw
->canvas_config
[buffer_index
][1];
3646 vf
->canvas1_config
[0] = hw
->canvas_config
[buffer_index
][0];
3647 vf
->canvas1_config
[1] = hw
->canvas_config
[buffer_index
][1];
3649 vf
->canvas0Addr
= vf
->canvas1Addr
=
3650 index2canvas(buffer_index
);
3651 vf
->type_original
= vf
->type
;
3653 vf
->pts
= (pts_valid
)?pts
:0;
3654 //vf->pts_us64 = (pts_valid) ? pts_us64 : 0;
3655 debug_print(hw
, PRINT_FLAG_VFRAME_DETAIL
,
3656 "buffer_index %d, canvas addr %x\n",
3657 buffer_index
, vf
->canvas0Addr
);
3658 debug_print(hw
, PRINT_FLAG_PTS
,
3659 "progressive vf->pts = %d, vf->pts_us64 = %lld, pts_valid = %d\n", vf
->pts
, vf
->pts_us64
, pts_valid
);
3660 hw
->vfbuf_use
[buffer_index
]++;
3662 decoder_bmmu_box_get_mem_handle(
3666 if (hw
->m_ins_flag
&& vdec_frame_based(hw_to_vdec(hw
)))
3667 set_vframe_pts(hw
, decode_pic_count
, vf
);
3669 if (vdec_stream_based(vdec
) && (!vdec
->vbuf
.use_ptsserv
)) {
3670 vf
->pts_us64
= offset
;
3673 vdec_vframe_ready(hw_to_vdec(hw
), vf
);
3674 kfifo_put(&hw
->display_q
,
3675 (const struct vframe_s
*)vf
);
3676 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
3677 VFRAME_EVENT_PROVIDER_VFRAME_READY
,
3683 vdec_count_info(hw
->gvs
, 0, offset
);
3685 if (picture_type
== I_PICTURE
) {
3686 hw
->gvs
->i_decoded_frames
++;
3687 } else if (picture_type
== P_PICTURE
) {
3688 hw
->gvs
->p_decoded_frames
++;
3689 } else if (picture_type
== B_PICTURE
) {
3690 hw
->gvs
->b_decoded_frames
++;
3694 vdec_fill_vdec_frame(hw_to_vdec(hw
), NULL
, hw
->gvs
, vf
, 0);
3696 /* pr_info("PicType = %d, PTS = 0x%x\n",
3697 * picture_type, vf->pts);
3699 WRITE_VREG(AVS_BUFFEROUT
, 0);
3701 //WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
3704 if (hw
->m_ins_flag
) {
3705 u32 status_reg
= READ_VREG(DECODE_STATUS
);
3706 u32 decode_status
= status_reg
& 0xff;
3707 if (hw
->dec_result
== DEC_RESULT_DONE
||
3708 hw
->dec_result
== DEC_RESULT_AGAIN
) {
3709 debug_print(hw
, PRINT_FLAG_DECODING
,
3710 "%s !!! READ_VREG(DECODE_STATUS) = 0x%x, decode_status 0x%x, buf_status 0x%x, dec_result = 0x%x, decode_pic_count = %d bit_cnt=0x%x\n",
3711 __func__
, status_reg
, decode_status
,
3713 hw
->dec_result
, hw
->decode_pic_count
,
3714 READ_VREG(VIFF_BIT_CNT
));
3716 } else if (decode_status
== DECODE_STATUS_PIC_DONE
||
3717 decode_status
== DECODE_STATUS_SKIP_PIC_DONE
) {
3718 hw
->buf_status
= (status_reg
>> 16) & 0xffff;
3719 if (decode_status
== DECODE_STATUS_SKIP_PIC_DONE
) {
3720 hw
->decode_status_skip_pic_done_flag
= 1;
3721 hw
->decode_decode_cont_start_code
= (status_reg
>> 8) & 0xff;
3723 hw
->decode_status_skip_pic_done_flag
= 0;
3724 hw
->decode_pic_count
++;
3725 if ((hw
->decode_pic_count
& 0xffff) == 0) {
3726 /*make ucode do not handle it as first picture*/
3727 hw
->decode_pic_count
++;
3729 reset_process_time(hw
);
3730 hw
->dec_result
= DEC_RESULT_DONE
;
3731 #if DEBUG_MULTI_FLAG == 1
3732 WRITE_VREG(DECODE_STATUS
, 0);
3737 debug_print(hw
, PRINT_FLAG_DECODING
,
3738 "%s %s, READ_VREG(DECODE_STATUS) = 0x%x, decode_status 0x%x, buf_status 0x%x, dec_result = 0x%x, decode_pic_count = %d, bit_cnt=0x%x\n",
3740 (decode_status
== DECODE_STATUS_PIC_DONE
) ?
3741 "DECODE_STATUS_PIC_DONE" : "DECODE_STATUS_SKIP_PIC_DONE",
3742 status_reg
, decode_status
,
3744 hw
->dec_result
, hw
->decode_pic_count
,
3745 READ_VREG(VIFF_BIT_CNT
));
3746 vdec_schedule_work(&hw
->work
);
3748 } else if (decode_status
== DECODE_STATUS_DECODE_BUF_EMPTY
||
3749 decode_status
== DECODE_STATUS_SEARCH_BUF_EMPTY
) {
3750 hw
->buf_status
= (status_reg
>> 16) & 0xffff;
3751 reset_process_time(hw
);
3752 #if DEBUG_MULTI_FLAG == 1
3753 WRITE_VREG(DECODE_STATUS
, 0);
3757 if (vdec_frame_based(hw_to_vdec(hw
))) {
3758 hw
->dec_result
= DEC_RESULT_DONE
;
3759 if (hw
->decode_pic_count
== 0) {
3760 hw
->decode_pic_count
++;
3764 hw
->dec_result
= DEC_RESULT_AGAIN
;
3766 debug_print(hw
, PRINT_FLAG_DECODING
,
3767 "%s BUF_EMPTY, READ_VREG(DECODE_STATUS) = 0x%x, decode_status 0x%x, buf_status 0x%x, scratch_8 (AVS_BUFFERIN) 0x%x, dec_result = 0x%x, decode_pic_count = %d, bit_cnt=0x%x, hw->decode_status_skip_pic_done_flag = %d, hw->decode_decode_cont_start_code = 0x%x\n",
3768 __func__
, status_reg
, decode_status
,
3771 hw
->dec_result
, hw
->decode_pic_count
,
3772 READ_VREG(VIFF_BIT_CNT
), hw
->decode_status_skip_pic_done_flag
, hw
->decode_decode_cont_start_code
);
3773 vdec_schedule_work(&hw
->work
);
3779 #ifdef HANDLE_AVS_IRQ
3787 static irqreturn_t
vmavs_isr(struct vdec_s
*vdec
, int irq
)
3790 WRITE_VREG(ASSIST_MBOX1_CLR_REG
, 1);
3792 return IRQ_WAKE_THREAD
;
3793 //return vavs_isr(0, hw);
3797 static void vmavs_dump_state(struct vdec_s
*vdec
)
3799 struct vdec_avs_hw_s
*hw
=
3800 (struct vdec_avs_hw_s
*)vdec
->private;
3803 "====== %s\n", __func__
);
3806 "width/height (%d/%d), dur %d\n",
3813 "is_framebase(%d), decode_status 0x%x, buf_status 0x%x, buf_recycle_status 0x%x, throw %d, eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
3814 vdec_frame_based(vdec
),
3815 READ_VREG(DECODE_STATUS
) & 0xff,
3817 hw
->buf_recycle_status
,
3822 hw
->decode_pic_count
,
3823 hw
->display_frame_count
,
3829 if (vf_get_receiver(vdec
->vf_provider_name
)) {
3830 enum receviver_start_e state
=
3831 vf_notify_receiver(vdec
->vf_provider_name
,
3832 VFRAME_EVENT_PROVIDER_QUREY_STATE
,
3835 "\nreceiver(%s) state %d\n",
3836 vdec
->vf_provider_name
,
3841 "%s, newq(%d/%d), dispq(%d/%d)recycleq(%d/%d) drop %d vf peek %d, prepare/get/put (%d/%d/%d)\n",
3843 kfifo_len(&hw
->newframe_q
),
3845 kfifo_len(&hw
->display_q
),
3847 kfifo_len(&hw
->recycle_q
),
3849 hw
->drop_frame_count
,
3856 debug_print(hw
, 0, "vfbuf_use:\n");
3857 for (i
= 0; i
< hw
->vf_buf_num_used
; i
++)
3858 debug_print(hw
, 0, "%d: vf_buf_use %d\n",
3859 i
, hw
->vfbuf_use
[i
]);
3862 "DECODE_STATUS=0x%x\n",
3863 READ_VREG(DECODE_STATUS
));
3868 "DECODE_MODE=0x%x\n",
3869 READ_VREG(DECODE_MODE
));
3871 "wait_buf_status, AV_SCRATCH_5=0x%x\n",
3872 READ_VREG(AV_SCRATCH_5
));
3875 READ_VREG(MBY_MBX
));
3877 "VIFF_BIT_CNT=0x%x\n",
3878 READ_VREG(VIFF_BIT_CNT
));
3880 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
3881 READ_VREG(VLD_MEM_VIFIFO_LEVEL
));
3883 "VLD_MEM_VIFIFO_WP=0x%x\n",
3884 READ_VREG(VLD_MEM_VIFIFO_WP
));
3886 "VLD_MEM_VIFIFO_RP=0x%x\n",
3887 READ_VREG(VLD_MEM_VIFIFO_RP
));
3889 "PARSER_VIDEO_RP=0x%x\n",
3890 STBUF_READ(&vdec
->vbuf
, get_rp
));
3892 "PARSER_VIDEO_WP=0x%x\n",
3893 STBUF_READ(&vdec
->vbuf
, get_wp
));
3895 if (vdec_frame_based(vdec
) &&
3896 (debug
& PRINT_FRAMEBASE_DATA
)
3899 if (hw
->chunk
&& hw
->chunk
->block
&&
3900 hw
->chunk
->size
> 0) {
3903 if (!hw
->chunk
->block
->is_mapped
)
3904 data
= codec_mm_vmap(hw
->chunk
->block
->start
+
3905 hw
->chunk
->offset
, hw
->chunk
->size
);
3907 data
= ((u8
*)hw
->chunk
->block
->start_virt
)
3908 + hw
->chunk
->offset
;
3911 "frame data size 0x%x\n",
3913 for (jj
= 0; jj
< hw
->chunk
->size
; jj
++) {
3914 if ((jj
& 0xf) == 0)
3916 PRINT_FRAMEBASE_DATA
,
3918 debug_print_cont(hw
,
3919 PRINT_FRAMEBASE_DATA
,
3921 if (((jj
+ 1) & 0xf) == 0)
3922 debug_print_cont(hw
,
3923 PRINT_FRAMEBASE_DATA
,
3927 if (!hw
->chunk
->block
->is_mapped
)
3928 codec_mm_unmap_phyaddr(data
);
3934 int ammvdec_avs_probe(struct platform_device
*pdev
)
3936 struct vdec_s
*pdata
= *(struct vdec_s
**)pdev
->dev
.platform_data
;
3937 struct vdec_avs_hw_s
*hw
= NULL
;
3939 if (vdec_get_debug_flags() & 0x8)
3940 return amvdec_avs_probe(pdev
);
3942 pr_info("ammvdec_avs probe start.\n");
3944 if (pdata
== NULL
) {
3945 pr_info("ammvdec_avs platform data undefined.\n");
3949 hw
= (struct vdec_avs_hw_s
*)devm_kzalloc(&pdev
->dev
,
3950 sizeof(struct vdec_avs_hw_s
), GFP_KERNEL
);
3952 pr_info("\nammvdec_avs decoder driver alloc failed\n");
3955 /*atomic_set(&hw->error_handler_run, 0);*/
3958 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
|| disable_longcabac_trans
)
3961 if (firmware_sel
== 1) {
3962 #ifndef USE_DYNAMIC_BUF_NUM
3968 pr_info("Error, do not support longcabac work around!!!");
3972 if (pdata
->sys_info
)
3973 hw
->vavs_amstream_dec_info
= *pdata
->sys_info
;
3976 pdata
->user_data_read
= NULL
;
3977 pdata
->reset_userdata_fifo
= NULL
;
3979 pdata
->private = hw
;
3980 pdata
->dec_status
= vavs_dec_status
;
3981 pdata
->set_isreset
= vavs_set_isreset
;
3982 pdata
->run_ready
= run_ready
;
3984 pdata
->reset
= reset
;
3985 pdata
->irq_handler
= vmavs_isr
;
3986 pdata
->threaded_irq_handler
= vmavs_isr_thread_fn
;
3987 pdata
->dump_state
= vmavs_dump_state
;
3989 vavs_vdec_info_init(hw
);
3991 #ifdef ENABLE_USER_DATA
3992 if (NULL
== hw
->user_data_buffer
) {
3993 hw
->user_data_buffer
=
3994 dma_alloc_coherent(amports_get_dma_device(),
3996 &hw
->user_data_buffer_phys
, GFP_KERNEL
);
3997 if (!hw
->user_data_buffer
) {
3998 pr_info("%s: Can not allocate hw->user_data_buffer\n",
4002 pr_debug("hw->user_data_buffer = 0x%p, hw->user_data_buffer_phys = 0x%x\n",
4003 hw
->user_data_buffer
, (u32
)hw
->user_data_buffer_phys
);
4006 /*hw->lmem_addr = kmalloc(LMEM_BUF_SIZE, GFP_KERNEL);
4007 if (hw->lmem_addr == NULL) {
4008 pr_err("%s: failed to alloc lmem buffer\n", __func__);
4011 hw->lmem_phy_addr = dma_map_single(amports_get_dma_device(),
4012 hw->lmem_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE);
4013 if (dma_mapping_error(amports_get_dma_device(),
4014 hw->lmem_phy_addr)) {
4015 pr_err("%s: failed to map lmem buffer\n", __func__);
4016 kfree(hw->lmem_addr);
4017 hw->lmem_addr = NULL;
4020 /*INIT_WORK(&hw->set_clk_work, avs_set_clk);*/
4021 hw
->lmem_addr
= (dma_addr_t
)dma_alloc_coherent(amports_get_dma_device(),
4022 LMEM_BUF_SIZE
, (dma_addr_t
*)&hw
->lmem_phy_addr
, GFP_KERNEL
);
4023 if (hw
->lmem_addr
== 0) {
4024 pr_err("%s: failed to alloc lmem buffer\n", __func__
);
4028 if (vavs_init(hw
) < 0) {
4029 pr_info("amvdec_avs init failed.\n");
4032 pdata
->dec_status
= NULL
;
4036 /*INIT_WORK(&hw->fatal_error_wd_work, vavs_fatal_error_handler);
4037 atomic_set(&hw->error_handler_run, 0);*/
4039 #ifdef ENABLE_USER_DATA
4040 INIT_WORK(&hw
->userdata_push_work
, userdata_push_do_work
);
4043 INIT_WORK(&hw
->notify_work
, vavs_notify_work
);
4045 if (pdata
->use_vfm_path
) {
4046 snprintf(pdata
->vf_provider_name
, VDEC_PROVIDER_NAME_SIZE
,
4047 VFM_DEC_PROVIDER_NAME
);
4048 hw
->frameinfo_enable
= 1;
4051 snprintf(pdata
->vf_provider_name
, VDEC_PROVIDER_NAME_SIZE
,
4052 MULTI_INSTANCE_PROVIDER_NAME
".%02x", pdev
->id
& 0xff);
4053 if (pdata
->parallel_dec
== 1) {
4055 for (i
= 0; i
< DECODE_BUFFER_NUM_MAX
; i
++)
4056 hw
->canvas_spec
[i
] = 0xffffff;
4058 vf_provider_init(&pdata
->vframe_provider
, pdata
->vf_provider_name
,
4059 &vavs_vf_provider
, hw
);
4061 platform_set_drvdata(pdev
, pdata
);
4063 hw
->platform_dev
= pdev
;
4065 vdec_set_prepare_level(pdata
, start_decode_buf_level
);
4067 vdec_set_vframe_comm(pdata
, DRIVER_NAME
);
4069 if (pdata
->parallel_dec
== 1)
4070 vdec_core_request(pdata
, CORE_MASK_VDEC_1
);
4072 vdec_core_request(pdata
, CORE_MASK_VDEC_1
| CORE_MASK_HEVC
4073 | CORE_MASK_COMBINE
);
4076 /*INIT_WORK(&hw->userdata_push_work, userdata_push_do_work);*/
4082 int ammvdec_avs_remove(struct platform_device
*pdev
)
4085 if (vdec_get_debug_flags() & 0x8)
4086 return amvdec_avs_remove(pdev
);
4088 struct vdec_avs_hw_s
*hw
=
4089 (struct vdec_avs_hw_s
*)
4090 (((struct vdec_s
*)(platform_get_drvdata(pdev
)))->private);
4091 struct vdec_s
*vdec
= hw_to_vdec(hw
);
4094 if (hw
->stat
& STAT_VDEC_RUN
) {
4096 hw
->stat
&= ~STAT_VDEC_RUN
;
4099 if (hw
->stat
& STAT_ISR_REG
) {
4100 vdec_free_irq(VDEC_IRQ_1
, (void *)hw
);
4101 hw
->stat
&= ~STAT_ISR_REG
;
4104 if (hw
->stat
& STAT_TIMER_ARM
) {
4105 del_timer_sync(&hw
->check_timer
);
4106 hw
->stat
&= ~STAT_TIMER_ARM
;
4109 cancel_work_sync(&hw
->work
);
4110 cancel_work_sync(&hw
->notify_work
);
4112 if (hw
->mm_blk_handle
) {
4113 decoder_bmmu_box_free(hw
->mm_blk_handle
);
4114 hw
->mm_blk_handle
= NULL
;
4116 if (vdec
->parallel_dec
== 1)
4117 vdec_core_release(hw_to_vdec(hw
), CORE_MASK_VDEC_1
);
4119 vdec_core_release(hw_to_vdec(hw
), CORE_MASK_VDEC_1
| CORE_MASK_HEVC
);
4120 vdec_set_status(hw_to_vdec(hw
), VDEC_STATUS_DISCONNECTED
);
4122 if (vdec
->parallel_dec
== 1) {
4123 for (i
= 0; i
< DECODE_BUFFER_NUM_MAX
; i
++) {
4124 vdec
->free_canvas_ex(canvas_y(hw
->canvas_spec
[i
]), vdec
->id
);
4125 vdec
->free_canvas_ex(canvas_u(hw
->canvas_spec
[i
]), vdec
->id
);
4128 #ifdef ENABLE_USER_DATA
4129 if (hw
->user_data_buffer
!= NULL
) {
4131 amports_get_dma_device(),
4133 hw
->user_data_buffer
,
4134 hw
->user_data_buffer_phys
);
4135 hw
->user_data_buffer
= NULL
;
4136 hw
->user_data_buffer_phys
= 0;
4139 /*if (hw->lmem_addr) {
4140 dma_unmap_single(amports_get_dma_device(),
4141 hw->lmem_phy_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE);
4142 kfree(hw->lmem_addr);
4143 hw->lmem_addr = NULL;
4145 if (hw
->lmem_addr
) {
4146 dma_free_coherent(amports_get_dma_device(),
4147 LMEM_BUF_SIZE
, (void *)hw
->lmem_addr
,
4157 pr_info("ammvdec_avs removed.\n");
4168 #ifdef DEBUG_MULTI_WITH_AUTOMODE
4169 struct stream_buf_s
*get_vbuf(void);
4170 s32
esparser_init(struct stream_buf_s
*buf
, struct vdec_s
*vdec
);
4173 static s32
vavs_init2(struct vdec_avs_hw_s
*hw
)
4176 struct firmware_s
*fw
;
4177 u32 fw_size
= 0x1000 * 16;
4179 fw
= vmalloc(sizeof(struct firmware_s
) + fw_size
);
4180 if (IS_ERR_OR_NULL(fw
))
4183 pr_info("vavs_init\n");
4188 vavs_local_init(hw
);
4190 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
)
4191 size
= get_firmware_data(VIDEO_DEC_AVS_MULTI
, fw
->data
);
4193 if (firmware_sel
== 1)
4194 size
= get_firmware_data(VIDEO_DEC_AVS_NOCABAC
, fw
->data
);
4195 #ifdef AVSP_LONG_CABAC
4197 init_avsp_long_cabac_buf();
4198 size
= get_firmware_data(VIDEO_DEC_AVS_MULTI
, fw
->data
);
4205 pr_err("get firmware fail.");
4212 if (hw
->m_ins_flag
) {
4213 init_timer(&hw
->check_timer
);
4214 hw
->check_timer
.data
= (ulong
) hw
;
4215 hw
->check_timer
.function
= check_timer_func
;
4216 hw
->check_timer
.expires
= jiffies
+ CHECK_INTERVAL
;
4219 //add_timer(&hw->check_timer);
4220 hw
->stat
|= STAT_TIMER_ARM
;
4222 INIT_WORK(&hw
->work
, vavs_work
);
4229 unsigned int debug_flag2
;
4230 static int vavs_prot_init2(struct vdec_avs_hw_s
*hw
, unsigned char post_flag
)
4248 unsigned char run_flag
;
4250 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) /*| (1 << 4)*/);
4251 WRITE_VREG(DOS_SW_RESET0
, 0);
4253 READ_VREG(DOS_SW_RESET0
);
4255 WRITE_VREG(DOS_SW_RESET0
, (1 << 7) | (1 << 6) /*| (1 << 4)*/);
4256 WRITE_VREG(DOS_SW_RESET0
, 0);
4258 WRITE_VREG(DOS_SW_RESET0
, (1 << 9) | (1 << 8));
4259 WRITE_VREG(DOS_SW_RESET0
, 0);
4261 /***************** reset vld **********************************/
4263 WRITE_VREG(POWER_CTL_VLD
, 0x10);
4264 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 2, MEM_FIFO_CNT_BIT
, 2);
4265 WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL
, 8, MEM_LEVEL_CNT_BIT
, 6);
4267 if (start_decoding_delay
& 0x80000)
4268 msleep(start_decoding_delay
&0xffff);
4270 if (debug_flag2
& 0x1)
4271 run_flag
= post_flag
;
4273 run_flag
= !post_flag
;
4275 if (hw
->m_ins_flag
) {
4277 if (hw
->decode_pic_count
== 0) {
4278 r
= vavs_canvas_init(hw
);
4279 #ifndef USE_DYNAMIC_BUF_NUM
4280 for (i
= 0; i
< 4; i
++) {
4281 WRITE_VREG(AV_SCRATCH_0
+ i
,
4286 for (i
= 0; i
< hw
->vf_buf_num_used
; i
+= 2) {
4287 WRITE_VREG(buf_spec_reg
[i
>> 1],
4288 (hw
->canvas_spec
[i
] & 0xffff) |
4289 ((hw
->canvas_spec
[i
+ 1] & 0xffff)
4295 vavs_restore_regs(hw
);
4297 for (i
= 0; i
< hw
->vf_buf_num_used
; i
++) {
4298 canvas_config_ex(canvas_y(hw
->canvas_spec
[i
]),
4299 hw
->canvas_config
[i
][0].phy_addr
,
4300 hw
->canvas_config
[i
][0].width
,
4301 hw
->canvas_config
[i
][0].height
,
4303 hw
->canvas_config
[i
][0].block_mode
,
4306 canvas_config_ex(canvas_u(hw
->canvas_spec
[i
]),
4307 hw
->canvas_config
[i
][1].phy_addr
,
4308 hw
->canvas_config
[i
][1].width
,
4309 hw
->canvas_config
[i
][1].height
,
4311 hw
->canvas_config
[i
][1].block_mode
,
4317 if (debug_flag2
& 0x2)
4318 run_flag
= post_flag
;
4320 run_flag
= !post_flag
;
4323 /* notify ucode the buffer offset */
4324 if (hw
->decode_pic_count
== 0)
4325 WRITE_VREG(AV_SCRATCH_F
, hw
->buf_offset
);
4327 /* disable PSCALE for hardware sharing */
4328 WRITE_VREG(PSCALE_CTRL
, 0);
4331 if (start_decoding_delay
& 0x40000)
4332 msleep(start_decoding_delay
&0xffff);
4334 if (debug_flag2
& 0x4)
4335 run_flag
= post_flag
;
4337 run_flag
= !post_flag
;
4339 if (hw
->decode_pic_count
== 0) {
4340 #ifndef USE_DYNAMIC_BUF_NUM
4341 WRITE_VREG(AVS_SOS_COUNT
, 0);
4343 WRITE_VREG(AVS_BUFFERIN
, 0);
4344 WRITE_VREG(AVS_BUFFEROUT
, 0);
4346 if (error_recovery_mode
)
4347 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 0);
4349 WRITE_VREG(AVS_ERROR_RECOVERY_MODE
, 1);
4350 /* clear mailbox interrupt */
4351 WRITE_VREG(ASSIST_MBOX1_CLR_REG
, 1);
4353 /* enable mailbox interrupt */
4354 WRITE_VREG(ASSIST_MBOX1_MASK
, 1);
4357 if (debug_flag2
& 0x8)
4358 run_flag
= post_flag
;
4360 run_flag
= !post_flag
;
4363 #ifndef USE_DYNAMIC_BUF_NUM /* def DEBUG_UCODE */
4364 if (hw
->decode_pic_count
== 0)
4365 WRITE_VREG(AV_SCRATCH_D
, 0);
4367 if (start_decoding_delay
& 0x10000)
4368 msleep(start_decoding_delay
&0xffff);
4370 SET_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 17);
4372 if (start_decoding_delay
& 0x20000)
4373 msleep(start_decoding_delay
&0xffff);
4376 #ifdef PIC_DC_NEED_CLEAR
4377 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL
, 1 << 31);
4380 if (debug_flag2
& 0x10)
4381 run_flag
= post_flag
;
4383 run_flag
= !post_flag
;
4385 #ifdef ENABLE_USER_DATA
4386 if (firmware_sel
== 0) {
4387 pr_info("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! firmware_sel is 0\n");
4388 WRITE_VREG(AV_SCRATCH_N
, (u32
)(hw
->user_data_buffer_phys
- hw
->buf_offset
));
4389 pr_debug("AV_SCRATCH_N = 0x%x\n", READ_VREG(AV_SCRATCH_N
));
4394 if (debug_flag2
& 0x20)
4395 run_flag
= post_flag
;
4397 run_flag
= !post_flag
;
4399 if (hw
->m_ins_flag
) {
4400 if (vdec_frame_based(hw_to_vdec(hw
)))
4401 WRITE_VREG(DECODE_MODE
, DECODE_MODE_MULTI_FRAMEBASE
);
4403 WRITE_VREG(DECODE_MODE
, DECODE_MODE_MULTI_STREAMBASE
);
4404 WRITE_VREG(DECODE_LMEM_BUF_ADR
, (u32
)hw
->lmem_phy_addr
);
4406 WRITE_VREG(DECODE_MODE
, DECODE_MODE_SINGLE
);
4407 WRITE_VREG(DECODE_STOP_POS
, udebug_flag
);
4408 hw
->old_udebug_flag
= udebug_flag
;
4413 static void init_hw(struct vdec_s
*vdec
)
4415 struct vdec_avs_hw_s
*hw
=
4416 (struct vdec_avs_hw_s
*)vdec
->private;
4418 pr_info("%s, %d\n", __func__
, __LINE__
);
4419 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
)
4420 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, NULL
, hw
->fw
->data
);
4421 else if (firmware_sel
== 1)
4422 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, "avs_no_cabac", hw
->fw
->data
);
4424 ret
= amvdec_loadmc_ex(VFORMAT_AVS
, NULL
, hw
->fw
->data
);
4429 pr_err("AVS: the %s fw loading failed, err: %x\n",
4430 tee_enabled() ? "TEE" : "local", ret
);
4432 pr_info("%s, %d\n", __func__
, __LINE__
);
4436 hw
->stat
|= STAT_MC_LOAD
;
4438 /* enable AMRISC side protocol */
4439 ret
= vavs_prot_init2(hw
, 0);
4442 pr_info("%s, %d\n", __func__
, __LINE__
);
4447 static unsigned long run_ready2(struct vdec_s
*vdec
, unsigned long mask
)
4452 static void run2(struct vdec_s
*vdec
, unsigned long mask
,
4453 void (*callback
)(struct vdec_s
*, void *),
4456 struct vdec_avs_hw_s
*hw
=
4457 (struct vdec_avs_hw_s
*)vdec
->private;
4458 pr_info("%s, %d\n", __func__
, __LINE__
);
4460 vavs_prot_init2(hw
, 1);
4462 vdec_source_changed(VFORMAT_AVS
,
4467 hw
->stat
|= STAT_VDEC_RUN
;
4468 pr_info("%s %d\n", __func__
, __LINE__
);
4472 static int ammvdec_avs_probe2(struct platform_device
*pdev
)
4474 struct vdec_s
*pdata
= *(struct vdec_s
**)pdev
->dev
.platform_data
;
4475 struct vdec_avs_hw_s
*hw
= NULL
;
4477 pr_info("ammvdec_avs probe start.\n");
4479 if (pdata
== NULL
) {
4480 pr_info("ammvdec_avs platform data undefined.\n");
4483 pr_info("%s %d\n", __func__
, __LINE__
);
4485 hw
= (struct vdec_avs_hw_s
*)devm_kzalloc(&pdev
->dev
,
4486 sizeof(struct vdec_avs_hw_s
), GFP_KERNEL
);
4488 pr_info("\nammvdec_avs decoder driver alloc failed\n");
4491 pr_info("%s %d\n", __func__
, __LINE__
);
4492 /*atomic_set(&hw->error_handler_run, 0);*/
4494 pr_info("%s %d\n", __func__
, __LINE__
);
4496 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXM
|| disable_longcabac_trans
)
4498 pr_info("%s %d\n", __func__
, __LINE__
);
4500 if (firmware_sel
== 1) {
4501 #ifndef USE_DYNAMIC_BUF_NUM
4507 pr_info("Error, do not support longcabac work around!!!");
4510 pr_info("%s %d\n", __func__
, __LINE__
);
4512 if (pdata
->sys_info
)
4513 hw
->vavs_amstream_dec_info
= *pdata
->sys_info
;
4514 pr_info("%s %d\n", __func__
, __LINE__
);
4517 pdata
->user_data_read
= NULL
;
4518 pdata
->reset_userdata_fifo
= NULL
;
4520 pr_info("%s %d\n", __func__
, __LINE__
);
4522 pdata
->private = hw
;
4523 pdata
->dec_status
= vavs_dec_status
;
4524 pdata
->set_isreset
= vavs_set_isreset
;
4525 pdata
->run_ready
= run_ready2
;
4527 pdata
->reset
= reset
;
4528 pdata
->irq_handler
= vmavs_isr
;
4529 pdata
->threaded_irq_handler
= vmavs_isr_thread_fn
;
4530 pdata
->dump_state
= vmavs_dump_state
;
4532 pr_info("%s %d\n", __func__
, __LINE__
);
4534 vavs_vdec_info_init(hw
);
4536 pr_info("%s %d\n", __func__
, __LINE__
);
4538 #ifdef ENABLE_USER_DATA
4539 if (NULL
== hw
->user_data_buffer
) {
4540 hw
->user_data_buffer
=
4541 dma_alloc_coherent(amports_get_dma_device(),
4543 &hw
->user_data_buffer_phys
, GFP_KERNEL
);
4544 if (!hw
->user_data_buffer
) {
4545 pr_info("%s: Can not allocate hw->user_data_buffer\n",
4549 pr_debug("hw->user_data_buffer = 0x%p, hw->user_data_buffer_phys = 0x%x\n",
4550 hw
->user_data_buffer
, (u32
)hw
->user_data_buffer_phys
);
4553 hw
->lmem_addr
= kmalloc(LMEM_BUF_SIZE
, GFP_KERNEL
);
4554 if (hw
->lmem_addr
== NULL
) {
4555 pr_err("%s: failed to alloc lmem buffer\n", __func__
);
4558 hw
->lmem_phy_addr
= dma_map_single(amports_get_dma_device(),
4559 hw
->lmem_addr
, LMEM_BUF_SIZE
, DMA_FROM_DEVICE
);
4560 if (dma_mapping_error(amports_get_dma_device(),
4561 hw
->lmem_phy_addr
)) {
4562 pr_err("%s: failed to map lmem buffer\n", __func__
);
4563 kfree(hw
->lmem_addr
);
4564 hw
->lmem_addr
= NULL
;
4568 pr_info("%s %d\n", __func__
, __LINE__
);
4570 /*INIT_WORK(&hw->set_clk_work, avs_set_clk);*/
4572 pr_info("%s %d\n", __func__
, __LINE__
);
4574 if (vavs_init2(hw
) < 0) {
4575 pr_info("amvdec_avs init failed.\n");
4578 pdata
->dec_status
= NULL
;
4582 pr_info("%s, %d\n", __func__
, __LINE__
);
4584 if (hw
->m_ins_flag
) {
4585 INIT_WORK(&hw
->notify_work
, vavs_notify_work
);
4587 if (pdata
->use_vfm_path
) {
4588 snprintf(pdata
->vf_provider_name
, VDEC_PROVIDER_NAME_SIZE
,
4589 VFM_DEC_PROVIDER_NAME
);
4590 hw
->frameinfo_enable
= 1;
4593 snprintf(pdata
->vf_provider_name
, VDEC_PROVIDER_NAME_SIZE
,
4594 MULTI_INSTANCE_PROVIDER_NAME
".%02x", pdev
->id
& 0xff);
4595 if (pdata
->parallel_dec
== 1) {
4597 for (i
= 0; i
< DECODE_BUFFER_NUM_MAX
; i
++)
4598 hw
->canvas_spec
[i
] = 0xffffff;
4600 vf_provider_init(&pdata
->vframe_provider
, pdata
->vf_provider_name
,
4601 &vavs_vf_provider
, hw
);
4603 platform_set_drvdata(pdev
, pdata
);
4605 hw
->platform_dev
= pdev
;
4607 vdec_set_prepare_level(pdata
, start_decode_buf_level
);
4609 if (pdata
->parallel_dec
== 1)
4610 vdec_core_request(pdata
, CORE_MASK_VDEC_1
);
4612 vdec_core_request(pdata
, CORE_MASK_VDEC_1
| CORE_MASK_HEVC
4613 | CORE_MASK_COMBINE
);
4615 pr_info("%s, %d\n", __func__
, __LINE__
);
4618 /*INIT_WORK(&hw->fatal_error_wd_work, vavs_fatal_error_handler);
4619 atomic_set(&hw->error_handler_run, 0);*/
4620 #ifdef ENABLE_USER_DATA
4621 INIT_WORK(&hw
->userdata_push_work
, userdata_push_do_work
);
4623 INIT_WORK(&hw
->notify_work
, vavs_notify_work
);
4630 static int ammvdec_avs_remove2(struct platform_device
*pdev
)
4632 struct vdec_avs_hw_s
*hw
= ghw
;
4634 cancel_work_sync(&hw
->fatal_error_wd_work
);
4635 atomic_set(&hw
->error_handler_run
, 0);
4636 #ifdef ENABLE_USER_DATA
4637 cancel_work_sync(&hw
->userdata_push_work
);
4639 cancel_work_sync(&hw
->notify_work
);
4640 cancel_work_sync(&hw
->set_clk_work
);
4641 if (hw
->stat
& STAT_VDEC_RUN
) {
4643 hw
->stat
&= ~STAT_VDEC_RUN
;
4646 if (hw
->stat
& STAT_ISR_REG
) {
4647 vdec_free_irq(VDEC_IRQ_1
, (void *)vavs_dec_id
);
4648 hw
->stat
&= ~STAT_ISR_REG
;
4651 if (hw
->stat
& STAT_TIMER_ARM
) {
4652 del_timer_sync(&hw
->recycle_timer
);
4653 hw
->stat
&= ~STAT_TIMER_ARM
;
4655 #ifdef AVSP_LONG_CABAC
4656 if (firmware_sel
== 0) {
4657 mutex_lock(&vavs_mutex
);
4658 cancel_work_sync(&long_cabac_wd_work
);
4659 mutex_unlock(&vavs_mutex
);
4661 if (es_write_addr_virt
) {
4663 codec_mm_free_for_dma("vavs", es_write_addr_phy
);
4665 dma_unmap_single(amports_get_dma_device(),
4667 MAX_CODED_FRAME_SIZE
, DMA_FROM_DEVICE
);
4668 /*kfree(es_write_addr_virt);*/
4669 es_write_addr_virt
= NULL
;
4673 #ifdef BITSTREAM_READ_TMP_NO_CACHE
4674 if (bitstream_read_tmp
) {
4675 dma_free_coherent(amports_get_dma_device(),
4676 SVA_STREAM_BUF_SIZE
, bitstream_read_tmp
,
4677 bitstream_read_tmp_phy
);
4678 bitstream_read_tmp
= NULL
;
4681 if (bitstream_read_tmp
) {
4682 dma_unmap_single(amports_get_dma_device(),
4683 bitstream_read_tmp_phy
,
4684 SVA_STREAM_BUF_SIZE
, DMA_FROM_DEVICE
);
4685 kfree(bitstream_read_tmp
);
4686 bitstream_read_tmp
= NULL
;
4691 if (hw
->stat
& STAT_VF_HOOK
) {
4692 if (hw
->fr_hint_status
== VDEC_HINTED
&& !hw
->is_reset
)
4693 avs_vf_notify_receiver(hw
, PROVIDER_NAME
,
4694 VFRAME_EVENT_PROVIDER_FR_END_HINT
, NULL
);
4695 hw
->fr_hint_status
= VDEC_NO_NEED_HINT
;
4696 vf_unreg_provider(&vavs_vf_prov
);
4697 hw
->stat
&= ~STAT_VF_HOOK
;
4700 #ifdef ENABLE_USER_DATA
4701 if (hw
->user_data_buffer
!= NULL
) {
4703 amports_get_dma_device(),
4705 hw
->user_data_buffer
,
4706 hw
->user_data_buffer_phys
);
4707 hw
->user_data_buffer
= NULL
;
4708 hw
->user_data_buffer_phys
= 0;
4718 /*vdec_disable_DMC(NULL);*/
4721 if (hw
->mm_blk_handle
) {
4722 decoder_bmmu_box_free(hw
->mm_blk_handle
);
4723 hw
->mm_blk_handle
= NULL
;
4726 pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", hw
->pts_hit
,
4727 hw
->pts_missed
, hw
->pts_i_hit
, hw
->pts_i_missed
);
4728 pr_debug("total frame %d, hw->avi_flag %d, rate %d\n", hw
->total_frame
, hw
->avi_flag
,
4729 hw
->vavs_amstream_dec_info
.rate
);
4738 static struct platform_driver ammvdec_avs_driver
= {
4739 #ifdef DEBUG_MULTI_WITH_AUTOMODE
4740 .probe
= ammvdec_avs_probe2
,
4741 .remove
= ammvdec_avs_remove2
,
4743 .probe
= ammvdec_avs_probe
,
4744 .remove
= ammvdec_avs_remove
,
4747 .suspend
= amvdec_suspend
,
4748 .resume
= amvdec_resume
,
4751 .name
= MULTI_DRIVER_NAME
,
4755 static struct codec_profile_t ammvdec_avs_profile
= {
4760 static struct mconfig mavs_configs
[] = {
4761 /*MC_PU32("stat", &stat),
4762 MC_PU32("debug_flag", &debug_flag),
4763 MC_PU32("error_recovery_mode", &error_recovery_mode),
4764 MC_PU32("hw->pic_type", &hw->pic_type),
4765 MC_PU32("radr", &radr),
4766 MC_PU32("vf_buf_num", &vf_buf_num),
4767 MC_PU32("vf_buf_num_used", &vf_buf_num_used),
4768 MC_PU32("canvas_base", &canvas_base),
4769 MC_PU32("firmware_sel", &firmware_sel),
4772 static struct mconfig_node mavs_node
;
4775 static int __init
ammvdec_avs_driver_init_module(void)
4777 pr_debug("ammvdec_avs module init\n");
4779 if (platform_driver_register(&ammvdec_avs_driver
))
4780 pr_err("failed to register ammvdec_avs driver\n");
4781 #ifdef DEBUG_WITH_SINGLE_MODE
4782 if (platform_driver_register(&amvdec_avs_driver
)) {
4783 pr_info("failed to register amvdec_avs driver\n");
4787 amvdec_avs_driver
= amvdec_avs_driver
;
4789 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB
)
4790 ammvdec_avs_profile
.profile
= "avs+";
4792 //vcodec_profile_register(&ammvdec_avs_profile);
4793 INIT_REG_NODE_CONFIGS("media.decoder", &mavs_node
,
4794 "mavs", mavs_configs
, CONFIG_FOR_RW
);
4800 static void __exit
ammvdec_avs_driver_remove_module(void)
4802 pr_debug("ammvdec_avs module remove.\n");
4804 platform_driver_unregister(&ammvdec_avs_driver
);
4805 #ifdef DEBUG_WITH_SINGLE_MODE
4806 platform_driver_unregister(&amvdec_avs_driver
);
4810 /****************************************/
4812 module_param(stat, uint, 0664);
4813 MODULE_PARM_DESC(stat, "\n amvdec_avs stat\n");
4815 /******************************************
4816 *module_param(run_flag, uint, 0664);
4817 *MODULE_PARM_DESC(run_flag, "\n run_flag\n");
4819 *module_param(step_flag, uint, 0664);
4820 *MODULE_PARM_DESC(step_flag, "\n step_flag\n");
4821 *******************************************
4823 module_param(step
, uint
, 0664);
4824 MODULE_PARM_DESC(step
, "\n step\n");
4826 module_param(debug
, uint
, 0664);
4827 MODULE_PARM_DESC(debug
, "\n debug\n");
4829 module_param(debug_mask
, uint
, 0664);
4830 MODULE_PARM_DESC(debug_mask
, "\n debug_mask\n");
4832 module_param(error_recovery_mode
, uint
, 0664);
4833 MODULE_PARM_DESC(error_recovery_mode
, "\n error_recovery_mode\n");
4835 /******************************************
4836 *module_param(error_watchdog_threshold, uint, 0664);
4837 *MODULE_PARM_DESC(error_watchdog_threshold, "\n error_watchdog_threshold\n");
4839 *module_param(error_watchdog_buf_threshold, uint, 0664);
4840 *MODULE_PARM_DESC(error_watchdog_buf_threshold,
4841 * "\n error_watchdog_buf_threshold\n");
4842 *******************************************
4845 module_param(pic_type, uint, 0444);
4846 MODULE_PARM_DESC(pic_type, "\n amdec_vas picture type\n");
4848 module_param(radr
, uint
, 0664);
4849 MODULE_PARM_DESC(radr
, "\nradr\n");
4851 module_param(rval
, uint
, 0664);
4852 MODULE_PARM_DESC(rval
, "\nrval\n");
4854 module_param(dbg_cmd
, uint
, 0664);
4855 MODULE_PARM_DESC(dbg_cmd
, "\n dbg_cmd\n");
4857 module_param(vf_buf_num
, uint
, 0664);
4858 MODULE_PARM_DESC(vf_buf_num
, "\nvf_buf_num\n");
4861 module_param(vf_buf_num_used, uint, 0664);
4862 MODULE_PARM_DESC(vf_buf_num_used, "\nvf_buf_num_used\n");
4864 module_param(canvas_base
, uint
, 0664);
4865 MODULE_PARM_DESC(canvas_base
, "\ncanvas_base\n");
4868 module_param(firmware_sel
, uint
, 0664);
4869 MODULE_PARM_DESC(firmware_sel
, "\n firmware_sel\n");
4871 module_param(disable_longcabac_trans
, uint
, 0664);
4872 MODULE_PARM_DESC(disable_longcabac_trans
, "\n disable_longcabac_trans\n");
4874 module_param(dec_control
, uint
, 0664);
4875 MODULE_PARM_DESC(dec_control
, "\n amvdec_vavs decoder control\n");
4877 module_param(start_decode_buf_level
, int, 0664);
4878 MODULE_PARM_DESC(start_decode_buf_level
,
4879 "\n avs start_decode_buf_level\n");
4881 module_param(decode_timeout_val
, uint
, 0664);
4882 MODULE_PARM_DESC(decode_timeout_val
,
4883 "\n avs decode_timeout_val\n");
4885 module_param(error_handle_policy
, uint
, 0664);
4886 MODULE_PARM_DESC(error_handle_policy
,
4887 "\n avs error_handle_policy\n");
4889 module_param(again_threshold
, uint
, 0664);
4890 MODULE_PARM_DESC(again_threshold
, "\n again_threshold\n");
4892 module_param(udebug_flag
, uint
, 0664);
4893 MODULE_PARM_DESC(udebug_flag
, "\n amvdec_h265 udebug_flag\n");
4895 module_param(udebug_pause_pos
, uint
, 0664);
4896 MODULE_PARM_DESC(udebug_pause_pos
, "\n udebug_pause_pos\n");
4898 module_param(udebug_pause_val
, uint
, 0664);
4899 MODULE_PARM_DESC(udebug_pause_val
, "\n udebug_pause_val\n");
4901 module_param(udebug_pause_decode_idx
, uint
, 0664);
4902 MODULE_PARM_DESC(udebug_pause_decode_idx
, "\n udebug_pause_decode_idx\n");
4904 module_param(udebug_pause_ins_id
, uint
, 0664);
4905 MODULE_PARM_DESC(udebug_pause_ins_id
, "\n udebug_pause_ins_id\n");
4908 module_param(start_decoding_delay
, uint
, 0664);
4909 MODULE_PARM_DESC(start_decoding_delay
, "\n start_decoding_delay\n");
4911 module_param(pre_decode_buf_level
, int, 0664);
4912 MODULE_PARM_DESC(pre_decode_buf_level
,
4913 "\n ammvdec_mavs pre_decode_buf_level\n");
4916 #ifdef DEBUG_MULTI_WITH_AUTOMODE
4917 module_param(debug_flag2
, uint
, 0664);
4918 MODULE_PARM_DESC(debug_flag2
, "\n debug_flag2\n");
4920 module_param(force_fps
, uint
, 0664);
4921 MODULE_PARM_DESC(force_fps
, "\n force_fps\n");
4923 #ifdef DEBUG_MULTI_FRAME_INS
4924 module_param(delay
, uint
, 0664);
4925 MODULE_PARM_DESC(delay
, "\n delay\n");
4927 module_param_array(max_run_count
, uint
, &max_decode_instance_num
, 0664);
4931 module_param_array(ins_udebug_flag
, uint
, &max_decode_instance_num
, 0664);
4933 module_param_array(max_process_time
, uint
, &max_decode_instance_num
, 0664);
4935 module_param_array(run_count
, uint
, &max_decode_instance_num
, 0664);
4937 module_param_array(max_get_frame_interval
, uint
,
4938 &max_decode_instance_num
, 0664);
4941 module_init(ammvdec_avs_driver_init_module
);
4942 module_exit(ammvdec_avs_driver_remove_module
);
4944 MODULE_DESCRIPTION("AMLOGIC AVS Video Decoder Driver");
4945 MODULE_LICENSE("GPL");
4946 MODULE_AUTHOR("Qi Wang <qi.wang@amlogic.com>");