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i7core_edac: Print an error message if pci register fails
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / edac / i7core_edac.c
1 /* Intel 7 core Memory Controller kernel module (Nehalem)
2 *
3 * This file may be distributed under the terms of the
4 * GNU General Public License version 2 only.
5 *
6 * Copyright (c) 2009 by:
7 * Mauro Carvalho Chehab <mchehab@redhat.com>
8 *
9 * Red Hat Inc. http://www.redhat.com
10 *
11 * Forked and adapted from the i5400_edac driver
12 *
13 * Based on the following public Intel datasheets:
14 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
15 * Datasheet, Volume 2:
16 * http://download.intel.com/design/processor/datashts/320835.pdf
17 * Intel Xeon Processor 5500 Series Datasheet Volume 2
18 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
19 * also available at:
20 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
21 */
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/slab.h>
28 #include <linux/edac.h>
29 #include <linux/mmzone.h>
30 #include <linux/edac_mce.h>
31 #include <linux/spinlock.h>
32
33 #include "edac_core.h"
34
35 /*
36 * Alter this version for the module when modifications are made
37 */
38 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
39 #define EDAC_MOD_STR "i7core_edac"
40
41 /*
42 * Debug macros
43 */
44 #define i7core_printk(level, fmt, arg...) \
45 edac_printk(level, "i7core", fmt, ##arg)
46
47 #define i7core_mc_printk(mci, level, fmt, arg...) \
48 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
49
50 /*
51 * i7core Memory Controller Registers
52 */
53
54 /* OFFSETS for Device 0 Function 0 */
55
56 #define MC_CFG_CONTROL 0x90
57
58 /* OFFSETS for Device 3 Function 0 */
59
60 #define MC_CONTROL 0x48
61 #define MC_STATUS 0x4c
62 #define MC_MAX_DOD 0x64
63
64 /*
65 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
66 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
67 */
68
69 #define MC_TEST_ERR_RCV1 0x60
70 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
71
72 #define MC_TEST_ERR_RCV0 0x64
73 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
74 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
75
76 /* OFFSETS for Devices 4,5 and 6 Function 0 */
77
78 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
79 #define THREE_DIMMS_PRESENT (1 << 24)
80 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
81 #define QUAD_RANK_PRESENT (1 << 22)
82 #define REGISTERED_DIMM (1 << 15)
83
84 #define MC_CHANNEL_MAPPER 0x60
85 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
86 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
87
88 #define MC_CHANNEL_RANK_PRESENT 0x7c
89 #define RANK_PRESENT_MASK 0xffff
90
91 #define MC_CHANNEL_ADDR_MATCH 0xf0
92 #define MC_CHANNEL_ERROR_MASK 0xf8
93 #define MC_CHANNEL_ERROR_INJECT 0xfc
94 #define INJECT_ADDR_PARITY 0x10
95 #define INJECT_ECC 0x08
96 #define MASK_CACHELINE 0x06
97 #define MASK_FULL_CACHELINE 0x06
98 #define MASK_MSB32_CACHELINE 0x04
99 #define MASK_LSB32_CACHELINE 0x02
100 #define NO_MASK_CACHELINE 0x00
101 #define REPEAT_EN 0x01
102
103 /* OFFSETS for Devices 4,5 and 6 Function 1 */
104
105 #define MC_DOD_CH_DIMM0 0x48
106 #define MC_DOD_CH_DIMM1 0x4c
107 #define MC_DOD_CH_DIMM2 0x50
108 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
109 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
110 #define DIMM_PRESENT_MASK (1 << 9)
111 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
112 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
113 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
114 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
115 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
116 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
117 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
118 #define MC_DOD_NUMCOL_MASK 3
119 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
120
121 #define MC_RANK_PRESENT 0x7c
122
123 #define MC_SAG_CH_0 0x80
124 #define MC_SAG_CH_1 0x84
125 #define MC_SAG_CH_2 0x88
126 #define MC_SAG_CH_3 0x8c
127 #define MC_SAG_CH_4 0x90
128 #define MC_SAG_CH_5 0x94
129 #define MC_SAG_CH_6 0x98
130 #define MC_SAG_CH_7 0x9c
131
132 #define MC_RIR_LIMIT_CH_0 0x40
133 #define MC_RIR_LIMIT_CH_1 0x44
134 #define MC_RIR_LIMIT_CH_2 0x48
135 #define MC_RIR_LIMIT_CH_3 0x4C
136 #define MC_RIR_LIMIT_CH_4 0x50
137 #define MC_RIR_LIMIT_CH_5 0x54
138 #define MC_RIR_LIMIT_CH_6 0x58
139 #define MC_RIR_LIMIT_CH_7 0x5C
140 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
141
142 #define MC_RIR_WAY_CH 0x80
143 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
144 #define MC_RIR_WAY_RANK_MASK 0x7
145
146 /*
147 * i7core structs
148 */
149
150 #define NUM_CHANS 3
151 #define MAX_DIMMS 3 /* Max DIMMS per channel */
152 #define NUM_SOCKETS 2 /* Max number of MC sockets */
153 #define MAX_MCR_FUNC 4
154 #define MAX_CHAN_FUNC 3
155
156 struct i7core_info {
157 u32 mc_control;
158 u32 mc_status;
159 u32 max_dod;
160 u32 ch_map;
161 };
162
163
164 struct i7core_inject {
165 int enable;
166
167 u8 socket;
168 u32 section;
169 u32 type;
170 u32 eccmask;
171
172 /* Error address mask */
173 int channel, dimm, rank, bank, page, col;
174 };
175
176 struct i7core_channel {
177 u32 ranks;
178 u32 dimms;
179 };
180
181 struct pci_id_descr {
182 int dev;
183 int func;
184 int dev_id;
185 struct pci_dev *pdev[NUM_SOCKETS];
186 };
187
188 struct i7core_pvt {
189 struct pci_dev *pci_noncore[NUM_SOCKETS];
190 struct pci_dev *pci_mcr[NUM_SOCKETS][MAX_MCR_FUNC + 1];
191 struct pci_dev *pci_ch[NUM_SOCKETS][NUM_CHANS][MAX_CHAN_FUNC + 1];
192
193 struct i7core_info info;
194 struct i7core_inject inject;
195 struct i7core_channel channel[NUM_SOCKETS][NUM_CHANS];
196
197 int sockets; /* Number of sockets */
198 int channels; /* Number of active channels */
199
200 int ce_count_available[NUM_SOCKETS];
201 /* ECC corrected errors counts per dimm */
202 unsigned long ce_count[NUM_SOCKETS][MAX_DIMMS];
203 int last_ce_count[NUM_SOCKETS][MAX_DIMMS];
204
205 /* mcelog glue */
206 struct edac_mce edac_mce;
207 struct mce mce_entry[MCE_LOG_LEN];
208 unsigned mce_count;
209 spinlock_t mce_lock;
210 };
211
212 /* Device name and register DID (Device ID) */
213 struct i7core_dev_info {
214 const char *ctl_name; /* name for this device */
215 u16 fsb_mapping_errors; /* DID for the branchmap,control */
216 };
217
218 #define PCI_DESCR(device, function, device_id) \
219 .dev = (device), \
220 .func = (function), \
221 .dev_id = (device_id)
222
223 struct pci_id_descr pci_devs[] = {
224 /* Memory controller */
225 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
226 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
227 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM */
228 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
229
230 /* Channel 0 */
231 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
232 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
233 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
234 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
235
236 /* Channel 1 */
237 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
238 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
239 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
240 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
241
242 /* Channel 2 */
243 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
244 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
245 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
246 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
247
248 /* Generic Non-core registers */
249 /*
250 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
251 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
252 * the probing code needs to test for the other address in case of
253 * failure of this one
254 */
255 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
256
257 };
258 #define N_DEVS ARRAY_SIZE(pci_devs)
259
260 /*
261 * pci_device_id table for which devices we are looking for
262 * This should match the first device at pci_devs table
263 */
264 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
265 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
266 {0,} /* 0 terminated list. */
267 };
268
269
270 /* Table of devices attributes supported by this driver */
271 static const struct i7core_dev_info i7core_devs[] = {
272 {
273 .ctl_name = "i7 Core",
274 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
275 },
276 };
277
278 static struct edac_pci_ctl_info *i7core_pci;
279
280 /****************************************************************************
281 Anciliary status routines
282 ****************************************************************************/
283
284 /* MC_CONTROL bits */
285 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
286 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
287
288 /* MC_STATUS bits */
289 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 3))
290 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
291
292 /* MC_MAX_DOD read functions */
293 static inline int numdimms(u32 dimms)
294 {
295 return (dimms & 0x3) + 1;
296 }
297
298 static inline int numrank(u32 rank)
299 {
300 static int ranks[4] = { 1, 2, 4, -EINVAL };
301
302 return ranks[rank & 0x3];
303 }
304
305 static inline int numbank(u32 bank)
306 {
307 static int banks[4] = { 4, 8, 16, -EINVAL };
308
309 return banks[bank & 0x3];
310 }
311
312 static inline int numrow(u32 row)
313 {
314 static int rows[8] = {
315 1 << 12, 1 << 13, 1 << 14, 1 << 15,
316 1 << 16, -EINVAL, -EINVAL, -EINVAL,
317 };
318
319 return rows[row & 0x7];
320 }
321
322 static inline int numcol(u32 col)
323 {
324 static int cols[8] = {
325 1 << 10, 1 << 11, 1 << 12, -EINVAL,
326 };
327 return cols[col & 0x3];
328 }
329
330 /****************************************************************************
331 Memory check routines
332 ****************************************************************************/
333 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
334 unsigned func)
335 {
336 int i;
337
338 for (i = 0; i < N_DEVS; i++) {
339 if (!pci_devs[i].pdev[socket])
340 continue;
341
342 if (PCI_SLOT(pci_devs[i].pdev[socket]->devfn) == slot &&
343 PCI_FUNC(pci_devs[i].pdev[socket]->devfn) == func) {
344 return pci_devs[i].pdev[socket];
345 }
346 }
347
348 return NULL;
349 }
350
351 /**
352 * i7core_get_active_channels() - gets the number of channels and csrows
353 * @socket: Quick Path Interconnect socket
354 * @channels: Number of channels that will be returned
355 * @csrows: Number of csrows found
356 *
357 * Since EDAC core needs to know in advance the number of available channels
358 * and csrows, in order to allocate memory for csrows/channels, it is needed
359 * to run two similar steps. At the first step, implemented on this function,
360 * it checks the number of csrows/channels present at one socket.
361 * this is used in order to properly allocate the size of mci components.
362 *
363 * It should be noticed that none of the current available datasheets explain
364 * or even mention how csrows are seen by the memory controller. So, we need
365 * to add a fake description for csrows.
366 * So, this driver is attributing one DIMM memory for one csrow.
367 */
368 static int i7core_get_active_channels(u8 socket, unsigned *channels,
369 unsigned *csrows)
370 {
371 struct pci_dev *pdev = NULL;
372 int i, j;
373 u32 status, control;
374
375 *channels = 0;
376 *csrows = 0;
377
378 pdev = get_pdev_slot_func(socket, 3, 0);
379 if (!pdev) {
380 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
381 socket);
382 return -ENODEV;
383 }
384
385 /* Device 3 function 0 reads */
386 pci_read_config_dword(pdev, MC_STATUS, &status);
387 pci_read_config_dword(pdev, MC_CONTROL, &control);
388
389 for (i = 0; i < NUM_CHANS; i++) {
390 u32 dimm_dod[3];
391 /* Check if the channel is active */
392 if (!(control & (1 << (8 + i))))
393 continue;
394
395 /* Check if the channel is disabled */
396 if (status & (1 << i))
397 continue;
398
399 pdev = get_pdev_slot_func(socket, i + 4, 1);
400 if (!pdev) {
401 i7core_printk(KERN_ERR, "Couldn't find socket %d "
402 "fn %d.%d!!!\n",
403 socket, i + 4, 1);
404 return -ENODEV;
405 }
406 /* Devices 4-6 function 1 */
407 pci_read_config_dword(pdev,
408 MC_DOD_CH_DIMM0, &dimm_dod[0]);
409 pci_read_config_dword(pdev,
410 MC_DOD_CH_DIMM1, &dimm_dod[1]);
411 pci_read_config_dword(pdev,
412 MC_DOD_CH_DIMM2, &dimm_dod[2]);
413
414 (*channels)++;
415
416 for (j = 0; j < 3; j++) {
417 if (!DIMM_PRESENT(dimm_dod[j]))
418 continue;
419 (*csrows)++;
420 }
421 }
422
423 debugf0("Number of active channels on socket %d: %d\n",
424 socket, *channels);
425
426 return 0;
427 }
428
429 static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
430 {
431 struct i7core_pvt *pvt = mci->pvt_info;
432 struct csrow_info *csr;
433 struct pci_dev *pdev;
434 int i, j;
435 unsigned long last_page = 0;
436 enum edac_type mode;
437 enum mem_type mtype;
438
439 /* Get data from the MC register, function 0 */
440 pdev = pvt->pci_mcr[socket][0];
441 if (!pdev)
442 return -ENODEV;
443
444 /* Device 3 function 0 reads */
445 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
446 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
447 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
448 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
449
450 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
451 socket, pvt->info.mc_control, pvt->info.mc_status,
452 pvt->info.max_dod, pvt->info.ch_map);
453
454 if (ECC_ENABLED(pvt)) {
455 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
456 if (ECCx8(pvt))
457 mode = EDAC_S8ECD8ED;
458 else
459 mode = EDAC_S4ECD4ED;
460 } else {
461 debugf0("ECC disabled\n");
462 mode = EDAC_NONE;
463 }
464
465 /* FIXME: need to handle the error codes */
466 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
467 "x%x x 0x%x\n",
468 numdimms(pvt->info.max_dod),
469 numrank(pvt->info.max_dod >> 2),
470 numbank(pvt->info.max_dod >> 4),
471 numrow(pvt->info.max_dod >> 6),
472 numcol(pvt->info.max_dod >> 9));
473
474 for (i = 0; i < NUM_CHANS; i++) {
475 u32 data, dimm_dod[3], value[8];
476
477 if (!CH_ACTIVE(pvt, i)) {
478 debugf0("Channel %i is not active\n", i);
479 continue;
480 }
481 if (CH_DISABLED(pvt, i)) {
482 debugf0("Channel %i is disabled\n", i);
483 continue;
484 }
485
486 /* Devices 4-6 function 0 */
487 pci_read_config_dword(pvt->pci_ch[socket][i][0],
488 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
489
490 pvt->channel[socket][i].ranks = (data & QUAD_RANK_PRESENT) ?
491 4 : 2;
492
493 if (data & REGISTERED_DIMM)
494 mtype = MEM_RDDR3;
495 else
496 mtype = MEM_DDR3;
497 #if 0
498 if (data & THREE_DIMMS_PRESENT)
499 pvt->channel[i].dimms = 3;
500 else if (data & SINGLE_QUAD_RANK_PRESENT)
501 pvt->channel[i].dimms = 1;
502 else
503 pvt->channel[i].dimms = 2;
504 #endif
505
506 /* Devices 4-6 function 1 */
507 pci_read_config_dword(pvt->pci_ch[socket][i][1],
508 MC_DOD_CH_DIMM0, &dimm_dod[0]);
509 pci_read_config_dword(pvt->pci_ch[socket][i][1],
510 MC_DOD_CH_DIMM1, &dimm_dod[1]);
511 pci_read_config_dword(pvt->pci_ch[socket][i][1],
512 MC_DOD_CH_DIMM2, &dimm_dod[2]);
513
514 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
515 "%d ranks, %cDIMMs\n",
516 i,
517 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
518 data,
519 pvt->channel[socket][i].ranks,
520 (data & REGISTERED_DIMM) ? 'R' : 'U');
521
522 for (j = 0; j < 3; j++) {
523 u32 banks, ranks, rows, cols;
524 u32 size, npages;
525
526 if (!DIMM_PRESENT(dimm_dod[j]))
527 continue;
528
529 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
530 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
531 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
532 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
533
534 /* DDR3 has 8 I/O banks */
535 size = (rows * cols * banks * ranks) >> (20 - 3);
536
537 pvt->channel[socket][i].dimms++;
538
539 debugf0("\tdimm %d %d Mb offset: %x, "
540 "bank: %d, rank: %d, row: %#x, col: %#x\n",
541 j, size,
542 RANKOFFSET(dimm_dod[j]),
543 banks, ranks, rows, cols);
544
545 #if PAGE_SHIFT > 20
546 npages = size >> (PAGE_SHIFT - 20);
547 #else
548 npages = size << (20 - PAGE_SHIFT);
549 #endif
550
551 csr = &mci->csrows[*csrow];
552 csr->first_page = last_page + 1;
553 last_page += npages;
554 csr->last_page = last_page;
555 csr->nr_pages = npages;
556
557 csr->page_mask = 0;
558 csr->grain = 8;
559 csr->csrow_idx = *csrow;
560 csr->nr_channels = 1;
561
562 csr->channels[0].chan_idx = i;
563 csr->channels[0].ce_count = 0;
564
565 switch (banks) {
566 case 4:
567 csr->dtype = DEV_X4;
568 break;
569 case 8:
570 csr->dtype = DEV_X8;
571 break;
572 case 16:
573 csr->dtype = DEV_X16;
574 break;
575 default:
576 csr->dtype = DEV_UNKNOWN;
577 }
578
579 csr->edac_mode = mode;
580 csr->mtype = mtype;
581
582 (*csrow)++;
583 }
584
585 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
586 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
587 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
588 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
589 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
590 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
591 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
592 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
593 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
594 for (j = 0; j < 8; j++)
595 debugf1("\t\t%#x\t%#x\t%#x\n",
596 (value[j] >> 27) & 0x1,
597 (value[j] >> 24) & 0x7,
598 (value[j] && ((1 << 24) - 1)));
599 }
600
601 return 0;
602 }
603
604 /****************************************************************************
605 Error insertion routines
606 ****************************************************************************/
607
608 /* The i7core has independent error injection features per channel.
609 However, to have a simpler code, we don't allow enabling error injection
610 on more than one channel.
611 Also, since a change at an inject parameter will be applied only at enable,
612 we're disabling error injection on all write calls to the sysfs nodes that
613 controls the error code injection.
614 */
615 static int disable_inject(struct mem_ctl_info *mci)
616 {
617 struct i7core_pvt *pvt = mci->pvt_info;
618
619 pvt->inject.enable = 0;
620
621 if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
622 return -ENODEV;
623
624 pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
625 MC_CHANNEL_ERROR_INJECT, 0);
626
627 return 0;
628 }
629
630 /*
631 * i7core inject inject.socket
632 *
633 * accept and store error injection inject.socket value
634 */
635 static ssize_t i7core_inject_socket_store(struct mem_ctl_info *mci,
636 const char *data, size_t count)
637 {
638 struct i7core_pvt *pvt = mci->pvt_info;
639 unsigned long value;
640 int rc;
641
642 rc = strict_strtoul(data, 10, &value);
643 if ((rc < 0) || (value >= pvt->sockets))
644 return -EIO;
645
646 pvt->inject.socket = (u32) value;
647 return count;
648 }
649
650 static ssize_t i7core_inject_socket_show(struct mem_ctl_info *mci,
651 char *data)
652 {
653 struct i7core_pvt *pvt = mci->pvt_info;
654 return sprintf(data, "%d\n", pvt->inject.socket);
655 }
656
657 /*
658 * i7core inject inject.section
659 *
660 * accept and store error injection inject.section value
661 * bit 0 - refers to the lower 32-byte half cacheline
662 * bit 1 - refers to the upper 32-byte half cacheline
663 */
664 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
665 const char *data, size_t count)
666 {
667 struct i7core_pvt *pvt = mci->pvt_info;
668 unsigned long value;
669 int rc;
670
671 if (pvt->inject.enable)
672 disable_inject(mci);
673
674 rc = strict_strtoul(data, 10, &value);
675 if ((rc < 0) || (value > 3))
676 return -EIO;
677
678 pvt->inject.section = (u32) value;
679 return count;
680 }
681
682 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
683 char *data)
684 {
685 struct i7core_pvt *pvt = mci->pvt_info;
686 return sprintf(data, "0x%08x\n", pvt->inject.section);
687 }
688
689 /*
690 * i7core inject.type
691 *
692 * accept and store error injection inject.section value
693 * bit 0 - repeat enable - Enable error repetition
694 * bit 1 - inject ECC error
695 * bit 2 - inject parity error
696 */
697 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
698 const char *data, size_t count)
699 {
700 struct i7core_pvt *pvt = mci->pvt_info;
701 unsigned long value;
702 int rc;
703
704 if (pvt->inject.enable)
705 disable_inject(mci);
706
707 rc = strict_strtoul(data, 10, &value);
708 if ((rc < 0) || (value > 7))
709 return -EIO;
710
711 pvt->inject.type = (u32) value;
712 return count;
713 }
714
715 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
716 char *data)
717 {
718 struct i7core_pvt *pvt = mci->pvt_info;
719 return sprintf(data, "0x%08x\n", pvt->inject.type);
720 }
721
722 /*
723 * i7core_inject_inject.eccmask_store
724 *
725 * The type of error (UE/CE) will depend on the inject.eccmask value:
726 * Any bits set to a 1 will flip the corresponding ECC bit
727 * Correctable errors can be injected by flipping 1 bit or the bits within
728 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
729 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
730 * uncorrectable error to be injected.
731 */
732 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
733 const char *data, size_t count)
734 {
735 struct i7core_pvt *pvt = mci->pvt_info;
736 unsigned long value;
737 int rc;
738
739 if (pvt->inject.enable)
740 disable_inject(mci);
741
742 rc = strict_strtoul(data, 10, &value);
743 if (rc < 0)
744 return -EIO;
745
746 pvt->inject.eccmask = (u32) value;
747 return count;
748 }
749
750 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
751 char *data)
752 {
753 struct i7core_pvt *pvt = mci->pvt_info;
754 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
755 }
756
757 /*
758 * i7core_addrmatch
759 *
760 * The type of error (UE/CE) will depend on the inject.eccmask value:
761 * Any bits set to a 1 will flip the corresponding ECC bit
762 * Correctable errors can be injected by flipping 1 bit or the bits within
763 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
764 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
765 * uncorrectable error to be injected.
766 */
767 static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
768 const char *data, size_t count)
769 {
770 struct i7core_pvt *pvt = mci->pvt_info;
771 char *cmd, *val;
772 long value;
773 int rc;
774
775 if (pvt->inject.enable)
776 disable_inject(mci);
777
778 do {
779 cmd = strsep((char **) &data, ":");
780 if (!cmd)
781 break;
782 val = strsep((char **) &data, " \n\t");
783 if (!val)
784 return cmd - data;
785
786 if (!strcasecmp(val, "any"))
787 value = -1;
788 else {
789 rc = strict_strtol(val, 10, &value);
790 if ((rc < 0) || (value < 0))
791 return cmd - data;
792 }
793
794 if (!strcasecmp(cmd, "channel")) {
795 if (value < 3)
796 pvt->inject.channel = value;
797 else
798 return cmd - data;
799 } else if (!strcasecmp(cmd, "dimm")) {
800 if (value < 3)
801 pvt->inject.dimm = value;
802 else
803 return cmd - data;
804 } else if (!strcasecmp(cmd, "rank")) {
805 if (value < 4)
806 pvt->inject.rank = value;
807 else
808 return cmd - data;
809 } else if (!strcasecmp(cmd, "bank")) {
810 if (value < 32)
811 pvt->inject.bank = value;
812 else
813 return cmd - data;
814 } else if (!strcasecmp(cmd, "page")) {
815 if (value <= 0xffff)
816 pvt->inject.page = value;
817 else
818 return cmd - data;
819 } else if (!strcasecmp(cmd, "col") ||
820 !strcasecmp(cmd, "column")) {
821 if (value <= 0x3fff)
822 pvt->inject.col = value;
823 else
824 return cmd - data;
825 }
826 } while (1);
827
828 return count;
829 }
830
831 static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
832 char *data)
833 {
834 struct i7core_pvt *pvt = mci->pvt_info;
835 char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];
836
837 if (pvt->inject.channel < 0)
838 sprintf(channel, "any");
839 else
840 sprintf(channel, "%d", pvt->inject.channel);
841 if (pvt->inject.dimm < 0)
842 sprintf(dimm, "any");
843 else
844 sprintf(dimm, "%d", pvt->inject.dimm);
845 if (pvt->inject.bank < 0)
846 sprintf(bank, "any");
847 else
848 sprintf(bank, "%d", pvt->inject.bank);
849 if (pvt->inject.rank < 0)
850 sprintf(rank, "any");
851 else
852 sprintf(rank, "%d", pvt->inject.rank);
853 if (pvt->inject.page < 0)
854 sprintf(page, "any");
855 else
856 sprintf(page, "0x%04x", pvt->inject.page);
857 if (pvt->inject.col < 0)
858 sprintf(col, "any");
859 else
860 sprintf(col, "0x%04x", pvt->inject.col);
861
862 return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
863 "rank: %s\npage: %s\ncolumn: %s\n",
864 channel, dimm, bank, rank, page, col);
865 }
866
867 static int write_and_test(struct pci_dev *dev, int where, u32 val)
868 {
869 u32 read;
870 int count;
871
872 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
873 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
874 where, val);
875
876 for (count = 0; count < 10; count++) {
877 if (count)
878 msleep(100);
879 pci_write_config_dword(dev, where, val);
880 pci_read_config_dword(dev, where, &read);
881
882 if (read == val)
883 return 0;
884 }
885
886 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
887 "write=%08x. Read=%08x\n",
888 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
889 where, val, read);
890
891 return -EINVAL;
892 }
893
894 /*
895 * This routine prepares the Memory Controller for error injection.
896 * The error will be injected when some process tries to write to the
897 * memory that matches the given criteria.
898 * The criteria can be set in terms of a mask where dimm, rank, bank, page
899 * and col can be specified.
900 * A -1 value for any of the mask items will make the MCU to ignore
901 * that matching criteria for error injection.
902 *
903 * It should be noticed that the error will only happen after a write operation
904 * on a memory that matches the condition. if REPEAT_EN is not enabled at
905 * inject mask, then it will produce just one error. Otherwise, it will repeat
906 * until the injectmask would be cleaned.
907 *
908 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
909 * is reliable enough to check if the MC is using the
910 * three channels. However, this is not clear at the datasheet.
911 */
912 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
913 const char *data, size_t count)
914 {
915 struct i7core_pvt *pvt = mci->pvt_info;
916 u32 injectmask;
917 u64 mask = 0;
918 int rc;
919 long enable;
920
921 if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
922 return 0;
923
924 rc = strict_strtoul(data, 10, &enable);
925 if ((rc < 0))
926 return 0;
927
928 if (enable) {
929 pvt->inject.enable = 1;
930 } else {
931 disable_inject(mci);
932 return count;
933 }
934
935 /* Sets pvt->inject.dimm mask */
936 if (pvt->inject.dimm < 0)
937 mask |= 1L << 41;
938 else {
939 if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
940 mask |= (pvt->inject.dimm & 0x3L) << 35;
941 else
942 mask |= (pvt->inject.dimm & 0x1L) << 36;
943 }
944
945 /* Sets pvt->inject.rank mask */
946 if (pvt->inject.rank < 0)
947 mask |= 1L << 40;
948 else {
949 if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
950 mask |= (pvt->inject.rank & 0x1L) << 34;
951 else
952 mask |= (pvt->inject.rank & 0x3L) << 34;
953 }
954
955 /* Sets pvt->inject.bank mask */
956 if (pvt->inject.bank < 0)
957 mask |= 1L << 39;
958 else
959 mask |= (pvt->inject.bank & 0x15L) << 30;
960
961 /* Sets pvt->inject.page mask */
962 if (pvt->inject.page < 0)
963 mask |= 1L << 38;
964 else
965 mask |= (pvt->inject.page & 0xffffL) << 14;
966
967 /* Sets pvt->inject.column mask */
968 if (pvt->inject.col < 0)
969 mask |= 1L << 37;
970 else
971 mask |= (pvt->inject.col & 0x3fffL);
972
973 /*
974 * bit 0: REPEAT_EN
975 * bits 1-2: MASK_HALF_CACHELINE
976 * bit 3: INJECT_ECC
977 * bit 4: INJECT_ADDR_PARITY
978 */
979
980 injectmask = (pvt->inject.type & 1) |
981 (pvt->inject.section & 0x3) << 1 |
982 (pvt->inject.type & 0x6) << (3 - 1);
983
984 /* Unlock writes to registers - this register is write only */
985 pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
986 MC_CFG_CONTROL, 0x2);
987
988 write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
989 MC_CHANNEL_ADDR_MATCH, mask);
990 write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
991 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
992
993 write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
994 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
995
996 write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
997 MC_CHANNEL_ERROR_INJECT, injectmask);
998
999 /*
1000 * This is something undocumented, based on my tests
1001 * Without writing 8 to this register, errors aren't injected. Not sure
1002 * why.
1003 */
1004 pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
1005 MC_CFG_CONTROL, 8);
1006
1007 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1008 " inject 0x%08x\n",
1009 mask, pvt->inject.eccmask, injectmask);
1010
1011
1012 return count;
1013 }
1014
1015 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1016 char *data)
1017 {
1018 struct i7core_pvt *pvt = mci->pvt_info;
1019 u32 injectmask;
1020
1021 pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
1022 MC_CHANNEL_ERROR_INJECT, &injectmask);
1023
1024 debugf0("Inject error read: 0x%018x\n", injectmask);
1025
1026 if (injectmask & 0x0c)
1027 pvt->inject.enable = 1;
1028
1029 return sprintf(data, "%d\n", pvt->inject.enable);
1030 }
1031
1032 static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
1033 {
1034 unsigned i, count, total = 0;
1035 struct i7core_pvt *pvt = mci->pvt_info;
1036
1037 for (i = 0; i < pvt->sockets; i++) {
1038 if (!pvt->ce_count_available[i])
1039 count = sprintf(data, "socket 0 data unavailable\n");
1040 else
1041 count = sprintf(data, "socket %d, dimm0: %lu\n"
1042 "dimm1: %lu\ndimm2: %lu\n",
1043 i,
1044 pvt->ce_count[i][0],
1045 pvt->ce_count[i][1],
1046 pvt->ce_count[i][2]);
1047 data += count;
1048 total += count;
1049 }
1050
1051 return total;
1052 }
1053
1054 /*
1055 * Sysfs struct
1056 */
1057 static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
1058 {
1059 .attr = {
1060 .name = "inject_socket",
1061 .mode = (S_IRUGO | S_IWUSR)
1062 },
1063 .show = i7core_inject_socket_show,
1064 .store = i7core_inject_socket_store,
1065 }, {
1066 .attr = {
1067 .name = "inject_section",
1068 .mode = (S_IRUGO | S_IWUSR)
1069 },
1070 .show = i7core_inject_section_show,
1071 .store = i7core_inject_section_store,
1072 }, {
1073 .attr = {
1074 .name = "inject_type",
1075 .mode = (S_IRUGO | S_IWUSR)
1076 },
1077 .show = i7core_inject_type_show,
1078 .store = i7core_inject_type_store,
1079 }, {
1080 .attr = {
1081 .name = "inject_eccmask",
1082 .mode = (S_IRUGO | S_IWUSR)
1083 },
1084 .show = i7core_inject_eccmask_show,
1085 .store = i7core_inject_eccmask_store,
1086 }, {
1087 .attr = {
1088 .name = "inject_addrmatch",
1089 .mode = (S_IRUGO | S_IWUSR)
1090 },
1091 .show = i7core_inject_addrmatch_show,
1092 .store = i7core_inject_addrmatch_store,
1093 }, {
1094 .attr = {
1095 .name = "inject_enable",
1096 .mode = (S_IRUGO | S_IWUSR)
1097 },
1098 .show = i7core_inject_enable_show,
1099 .store = i7core_inject_enable_store,
1100 }, {
1101 .attr = {
1102 .name = "corrected_error_counts",
1103 .mode = (S_IRUGO | S_IWUSR)
1104 },
1105 .show = i7core_ce_regs_show,
1106 .store = NULL,
1107 },
1108 };
1109
1110 /****************************************************************************
1111 Device initialization routines: put/get, init/exit
1112 ****************************************************************************/
1113
1114 /*
1115 * i7core_put_devices 'put' all the devices that we have
1116 * reserved via 'get'
1117 */
1118 static void i7core_put_devices(void)
1119 {
1120 int i, j;
1121
1122 for (i = 0; i < NUM_SOCKETS; i++)
1123 for (j = 0; j < N_DEVS; j++)
1124 pci_dev_put(pci_devs[j].pdev[i]);
1125 }
1126
1127 /*
1128 * i7core_get_devices Find and perform 'get' operation on the MCH's
1129 * device/functions we want to reference for this driver
1130 *
1131 * Need to 'get' device 16 func 1 and func 2
1132 */
1133 int i7core_get_onedevice(struct pci_dev **prev, int devno)
1134 {
1135 struct pci_dev *pdev = NULL;
1136 u8 bus = 0;
1137 u8 socket = 0;
1138
1139 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1140 pci_devs[devno].dev_id, *prev);
1141
1142 /*
1143 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1144 * aren't announced by acpi. So, we need to use a legacy scan probing
1145 * to detect them
1146 */
1147 if (unlikely(!pdev && !devno && !prev)) {
1148 pcibios_scan_specific_bus(254);
1149 pcibios_scan_specific_bus(255);
1150
1151 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1152 pci_devs[devno].dev_id, *prev);
1153 }
1154
1155 /*
1156 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1157 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1158 * to probe for the alternate address in case of failure
1159 */
1160 if (pci_devs[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
1161 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1162 PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
1163
1164 if (!pdev) {
1165 if (*prev) {
1166 *prev = pdev;
1167 return 0;
1168 }
1169
1170 /*
1171 * Dev 3 function 2 only exists on chips with RDIMMs
1172 * so, it is ok to not found it
1173 */
1174 if ((pci_devs[devno].dev == 3) && (pci_devs[devno].func == 2)) {
1175 *prev = pdev;
1176 return 0;
1177 }
1178
1179 i7core_printk(KERN_ERR,
1180 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1181 pci_devs[devno].dev, pci_devs[devno].func,
1182 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1183
1184 /* End of list, leave */
1185 return -ENODEV;
1186 }
1187 bus = pdev->bus->number;
1188
1189 if (bus == 0x3f)
1190 socket = 0;
1191 else
1192 socket = 255 - bus;
1193
1194 if (socket >= NUM_SOCKETS) {
1195 i7core_printk(KERN_ERR,
1196 "Unexpected socket for "
1197 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1198 bus, pci_devs[devno].dev, pci_devs[devno].func,
1199 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1200 pci_dev_put(pdev);
1201 return -ENODEV;
1202 }
1203
1204 if (pci_devs[devno].pdev[socket]) {
1205 i7core_printk(KERN_ERR,
1206 "Duplicated device for "
1207 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1208 bus, pci_devs[devno].dev, pci_devs[devno].func,
1209 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1210 pci_dev_put(pdev);
1211 return -ENODEV;
1212 }
1213
1214 pci_devs[devno].pdev[socket] = pdev;
1215
1216 /* Sanity check */
1217 if (unlikely(PCI_SLOT(pdev->devfn) != pci_devs[devno].dev ||
1218 PCI_FUNC(pdev->devfn) != pci_devs[devno].func)) {
1219 i7core_printk(KERN_ERR,
1220 "Device PCI ID %04x:%04x "
1221 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1222 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id,
1223 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1224 bus, pci_devs[devno].dev, pci_devs[devno].func);
1225 return -ENODEV;
1226 }
1227
1228 /* Be sure that the device is enabled */
1229 if (unlikely(pci_enable_device(pdev) < 0)) {
1230 i7core_printk(KERN_ERR,
1231 "Couldn't enable "
1232 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1233 bus, pci_devs[devno].dev, pci_devs[devno].func,
1234 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1235 return -ENODEV;
1236 }
1237
1238 i7core_printk(KERN_INFO,
1239 "Registered socket %d "
1240 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1241 socket, bus, pci_devs[devno].dev, pci_devs[devno].func,
1242 PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1243
1244 *prev = pdev;
1245
1246 return 0;
1247 }
1248
1249 static int i7core_get_devices(void)
1250 {
1251 int i;
1252 struct pci_dev *pdev = NULL;
1253
1254 for (i = 0; i < N_DEVS; i++) {
1255 pdev = NULL;
1256 do {
1257 if (i7core_get_onedevice(&pdev, i) < 0) {
1258 i7core_put_devices();
1259 return -ENODEV;
1260 }
1261 } while (pdev);
1262 }
1263 return 0;
1264 }
1265
1266 static int mci_bind_devs(struct mem_ctl_info *mci)
1267 {
1268 struct i7core_pvt *pvt = mci->pvt_info;
1269 struct pci_dev *pdev;
1270 int i, j, func, slot;
1271
1272 for (i = 0; i < pvt->sockets; i++) {
1273 for (j = 0; j < N_DEVS; j++) {
1274 pdev = pci_devs[j].pdev[i];
1275 if (!pdev)
1276 continue;
1277
1278 func = PCI_FUNC(pdev->devfn);
1279 slot = PCI_SLOT(pdev->devfn);
1280 if (slot == 3) {
1281 if (unlikely(func > MAX_MCR_FUNC))
1282 goto error;
1283 pvt->pci_mcr[i][func] = pdev;
1284 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1285 if (unlikely(func > MAX_CHAN_FUNC))
1286 goto error;
1287 pvt->pci_ch[i][slot - 4][func] = pdev;
1288 } else if (!slot && !func)
1289 pvt->pci_noncore[i] = pdev;
1290 else
1291 goto error;
1292
1293 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1294 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1295 pdev, i);
1296 }
1297 }
1298
1299 return 0;
1300
1301 error:
1302 i7core_printk(KERN_ERR, "Device %d, function %d "
1303 "is out of the expected range\n",
1304 slot, func);
1305 return -EINVAL;
1306 }
1307
1308 /****************************************************************************
1309 Error check routines
1310 ****************************************************************************/
1311
1312 /* This function is based on the device 3 function 4 registers as described on:
1313 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1314 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1315 * also available at:
1316 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1317 */
1318 static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
1319 {
1320 struct i7core_pvt *pvt = mci->pvt_info;
1321 u32 rcv1, rcv0;
1322 int new0, new1, new2;
1323
1324 if (!pvt->pci_mcr[socket][4]) {
1325 debugf0("%s MCR registers not found\n", __func__);
1326 return;
1327 }
1328
1329 /* Corrected error reads */
1330 pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
1331 pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
1332
1333 /* Store the new values */
1334 new2 = DIMM2_COR_ERR(rcv1);
1335 new1 = DIMM1_COR_ERR(rcv0);
1336 new0 = DIMM0_COR_ERR(rcv0);
1337
1338 #if 0
1339 debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
1340 (pvt->ce_count_available ? "UPDATE" : "READ"),
1341 rcv1, rcv0, new0, new1, new2);
1342 #endif
1343
1344 /* Updates CE counters if it is not the first time here */
1345 if (pvt->ce_count_available[socket]) {
1346 /* Updates CE counters */
1347 int add0, add1, add2;
1348
1349 add2 = new2 - pvt->last_ce_count[socket][2];
1350 add1 = new1 - pvt->last_ce_count[socket][1];
1351 add0 = new0 - pvt->last_ce_count[socket][0];
1352
1353 if (add2 < 0)
1354 add2 += 0x7fff;
1355 pvt->ce_count[socket][2] += add2;
1356
1357 if (add1 < 0)
1358 add1 += 0x7fff;
1359 pvt->ce_count[socket][1] += add1;
1360
1361 if (add0 < 0)
1362 add0 += 0x7fff;
1363 pvt->ce_count[socket][0] += add0;
1364 } else
1365 pvt->ce_count_available[socket] = 1;
1366
1367 /* Store the new values */
1368 pvt->last_ce_count[socket][2] = new2;
1369 pvt->last_ce_count[socket][1] = new1;
1370 pvt->last_ce_count[socket][0] = new0;
1371 }
1372
1373 /*
1374 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1375 * Architectures Software Developer’s Manual Volume 3B.
1376 * Nehalem are defined as family 0x06, model 0x1a
1377 *
1378 * The MCA registers used here are the following ones:
1379 * struct mce field MCA Register
1380 * m->status MSR_IA32_MC8_STATUS
1381 * m->addr MSR_IA32_MC8_ADDR
1382 * m->misc MSR_IA32_MC8_MISC
1383 * In the case of Nehalem, the error information is masked at .status and .misc
1384 * fields
1385 */
1386 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1387 struct mce *m)
1388 {
1389 char *type, *optype, *err, *msg;
1390 unsigned long error = m->status & 0x1ff0000l;
1391 u32 optypenum = (m->status >> 4) & 0x07;
1392 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1393 u32 dimm = (m->misc >> 16) & 0x3;
1394 u32 channel = (m->misc >> 18) & 0x3;
1395 u32 syndrome = m->misc >> 32;
1396 u32 errnum = find_first_bit(&error, 32);
1397
1398 if (m->mcgstatus & 1)
1399 type = "FATAL";
1400 else
1401 type = "NON_FATAL";
1402
1403 switch (optypenum) {
1404 case 0:
1405 optype = "generic undef request";
1406 break;
1407 case 1:
1408 optype = "read error";
1409 break;
1410 case 2:
1411 optype = "write error";
1412 break;
1413 case 3:
1414 optype = "addr/cmd error";
1415 break;
1416 case 4:
1417 optype = "scrubbing error";
1418 break;
1419 default:
1420 optype = "reserved";
1421 break;
1422 }
1423
1424 switch (errnum) {
1425 case 16:
1426 err = "read ECC error";
1427 break;
1428 case 17:
1429 err = "RAS ECC error";
1430 break;
1431 case 18:
1432 err = "write parity error";
1433 break;
1434 case 19:
1435 err = "redundacy loss";
1436 break;
1437 case 20:
1438 err = "reserved";
1439 break;
1440 case 21:
1441 err = "memory range error";
1442 break;
1443 case 22:
1444 err = "RTID out of range";
1445 break;
1446 case 23:
1447 err = "address parity error";
1448 break;
1449 case 24:
1450 err = "byte enable parity error";
1451 break;
1452 default:
1453 err = "unknown";
1454 }
1455
1456 /* FIXME: should convert addr into bank and rank information */
1457 msg = kasprintf(GFP_ATOMIC,
1458 "%s (addr = 0x%08llx, socket=%d, Dimm=%d, Channel=%d, "
1459 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1460 type, (long long) m->addr, m->cpu, dimm, channel,
1461 syndrome, core_err_cnt, (long long)m->status,
1462 (long long)m->misc, optype, err);
1463
1464 debugf0("%s", msg);
1465
1466 /* Call the helper to output message */
1467 edac_mc_handle_fbd_ue(mci, 0 /* FIXME: should be rank here */,
1468 0, 0 /* FIXME: should be channel here */, msg);
1469
1470 kfree(msg);
1471 }
1472
1473 /*
1474 * i7core_check_error Retrieve and process errors reported by the
1475 * hardware. Called by the Core module.
1476 */
1477 static void i7core_check_error(struct mem_ctl_info *mci)
1478 {
1479 struct i7core_pvt *pvt = mci->pvt_info;
1480 int i;
1481 unsigned count = 0;
1482 struct mce *m = NULL;
1483 unsigned long flags;
1484
1485 /* Copy all mce errors into a temporary buffer */
1486 spin_lock_irqsave(&pvt->mce_lock, flags);
1487 if (pvt->mce_count) {
1488 m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC);
1489 if (m) {
1490 count = pvt->mce_count;
1491 memcpy(m, &pvt->mce_entry, sizeof(*m) * count);
1492 }
1493 pvt->mce_count = 0;
1494 }
1495 spin_unlock_irqrestore(&pvt->mce_lock, flags);
1496
1497 /* proccess mcelog errors */
1498 for (i = 0; i < count; i++)
1499 i7core_mce_output_error(mci, &m[i]);
1500
1501 kfree(m);
1502
1503 /* check memory count errors */
1504 for (i = 0; i < pvt->sockets; i++)
1505 check_mc_test_err(mci, i);
1506 }
1507
1508 /*
1509 * i7core_mce_check_error Replicates mcelog routine to get errors
1510 * This routine simply queues mcelog errors, and
1511 * return. The error itself should be handled later
1512 * by i7core_check_error.
1513 */
1514 static int i7core_mce_check_error(void *priv, struct mce *mce)
1515 {
1516 struct mem_ctl_info *mci = priv;
1517 struct i7core_pvt *pvt = mci->pvt_info;
1518 unsigned long flags;
1519
1520 /*
1521 * Just let mcelog handle it if the error is
1522 * outside the memory controller
1523 */
1524 if (((mce->status & 0xffff) >> 7) != 1)
1525 return 0;
1526
1527 /* Bank 8 registers are the only ones that we know how to handle */
1528 if (mce->bank != 8)
1529 return 0;
1530
1531 spin_lock_irqsave(&pvt->mce_lock, flags);
1532 if (pvt->mce_count < MCE_LOG_LEN) {
1533 memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
1534 pvt->mce_count++;
1535 }
1536 spin_unlock_irqrestore(&pvt->mce_lock, flags);
1537
1538 /* Handle fatal errors immediately */
1539 if (mce->mcgstatus & 1)
1540 i7core_check_error(mci);
1541
1542 /* Advice mcelog that the error were handled */
1543 return 1;
1544 }
1545
1546 /*
1547 * i7core_probe Probe for ONE instance of device to see if it is
1548 * present.
1549 * return:
1550 * 0 for FOUND a device
1551 * < 0 for error code
1552 */
1553 static int __devinit i7core_probe(struct pci_dev *pdev,
1554 const struct pci_device_id *id)
1555 {
1556 struct mem_ctl_info *mci;
1557 struct i7core_pvt *pvt;
1558 int num_channels = 0;
1559 int num_csrows = 0;
1560 int csrow = 0;
1561 int dev_idx = id->driver_data;
1562 int rc, i;
1563 u8 sockets;
1564
1565 if (unlikely(dev_idx >= ARRAY_SIZE(i7core_devs)))
1566 return -EINVAL;
1567
1568 /* get the pci devices we want to reserve for our use */
1569 rc = i7core_get_devices();
1570 if (unlikely(rc < 0))
1571 return rc;
1572
1573 sockets = 1;
1574 for (i = NUM_SOCKETS - 1; i > 0; i--)
1575 if (pci_devs[0].pdev[i]) {
1576 sockets = i + 1;
1577 break;
1578 }
1579
1580 for (i = 0; i < sockets; i++) {
1581 int channels;
1582 int csrows;
1583
1584 /* Check the number of active and not disabled channels */
1585 rc = i7core_get_active_channels(i, &channels, &csrows);
1586 if (unlikely(rc < 0))
1587 goto fail0;
1588
1589 num_channels += channels;
1590 num_csrows += csrows;
1591 }
1592
1593 /* allocate a new MC control structure */
1594 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1595 if (unlikely(!mci)) {
1596 rc = -ENOMEM;
1597 goto fail0;
1598 }
1599
1600 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1601
1602 mci->dev = &pdev->dev; /* record ptr to the generic device */
1603 pvt = mci->pvt_info;
1604 memset(pvt, 0, sizeof(*pvt));
1605 pvt->sockets = sockets;
1606 mci->mc_idx = 0;
1607
1608 /*
1609 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1610 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1611 * memory channels
1612 */
1613 mci->mtype_cap = MEM_FLAG_DDR3;
1614 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1615 mci->edac_cap = EDAC_FLAG_NONE;
1616 mci->mod_name = "i7core_edac.c";
1617 mci->mod_ver = I7CORE_REVISION;
1618 mci->ctl_name = i7core_devs[dev_idx].ctl_name;
1619 mci->dev_name = pci_name(pdev);
1620 mci->ctl_page_to_phys = NULL;
1621 mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
1622 /* Set the function pointer to an actual operation function */
1623 mci->edac_check = i7core_check_error;
1624
1625 /* Store pci devices at mci for faster access */
1626 rc = mci_bind_devs(mci);
1627 if (unlikely(rc < 0))
1628 goto fail1;
1629
1630 /* Get dimm basic config */
1631 for (i = 0; i < sockets; i++)
1632 get_dimm_config(mci, &csrow, i);
1633
1634 /* add this new MC control structure to EDAC's list of MCs */
1635 if (unlikely(edac_mc_add_mc(mci))) {
1636 debugf0("MC: " __FILE__
1637 ": %s(): failed edac_mc_add_mc()\n", __func__);
1638 /* FIXME: perhaps some code should go here that disables error
1639 * reporting if we just enabled it
1640 */
1641
1642 rc = -EINVAL;
1643 goto fail1;
1644 }
1645
1646 /* allocating generic PCI control info */
1647 i7core_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1648 if (unlikely(!i7core_pci)) {
1649 printk(KERN_WARNING
1650 "%s(): Unable to create PCI control\n",
1651 __func__);
1652 printk(KERN_WARNING
1653 "%s(): PCI error report via EDAC not setup\n",
1654 __func__);
1655 }
1656
1657 /* Default error mask is any memory */
1658 pvt->inject.channel = 0;
1659 pvt->inject.dimm = -1;
1660 pvt->inject.rank = -1;
1661 pvt->inject.bank = -1;
1662 pvt->inject.page = -1;
1663 pvt->inject.col = -1;
1664
1665 /* Registers on edac_mce in order to receive memory errors */
1666 pvt->edac_mce.priv = mci;
1667 pvt->edac_mce.check_error = i7core_mce_check_error;
1668 spin_lock_init(&pvt->mce_lock);
1669
1670 rc = edac_mce_register(&pvt->edac_mce);
1671 if (unlikely(rc < 0)) {
1672 debugf0("MC: " __FILE__
1673 ": %s(): failed edac_mce_register()\n", __func__);
1674 goto fail1;
1675 }
1676
1677 i7core_printk(KERN_INFO, "Driver loaded.\n");
1678
1679 return 0;
1680
1681 fail1:
1682 edac_mc_free(mci);
1683
1684 fail0:
1685 i7core_put_devices();
1686 return rc;
1687 }
1688
1689 /*
1690 * i7core_remove destructor for one instance of device
1691 *
1692 */
1693 static void __devexit i7core_remove(struct pci_dev *pdev)
1694 {
1695 struct mem_ctl_info *mci;
1696 struct i7core_pvt *pvt;
1697
1698 debugf0(__FILE__ ": %s()\n", __func__);
1699
1700 if (i7core_pci)
1701 edac_pci_release_generic_ctl(i7core_pci);
1702
1703
1704 mci = edac_mc_del_mc(&pdev->dev);
1705 if (!mci)
1706 return;
1707
1708 /* Unregisters on edac_mce in order to receive memory errors */
1709 pvt = mci->pvt_info;
1710 edac_mce_unregister(&pvt->edac_mce);
1711
1712 /* retrieve references to resources, and free those resources */
1713 i7core_put_devices();
1714
1715 edac_mc_free(mci);
1716 }
1717
1718 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
1719
1720 /*
1721 * i7core_driver pci_driver structure for this module
1722 *
1723 */
1724 static struct pci_driver i7core_driver = {
1725 .name = "i7core_edac",
1726 .probe = i7core_probe,
1727 .remove = __devexit_p(i7core_remove),
1728 .id_table = i7core_pci_tbl,
1729 };
1730
1731 /*
1732 * i7core_init Module entry function
1733 * Try to initialize this module for its devices
1734 */
1735 static int __init i7core_init(void)
1736 {
1737 int pci_rc;
1738
1739 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1740
1741 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1742 opstate_init();
1743
1744 pci_rc = pci_register_driver(&i7core_driver);
1745
1746 if (pci_rc >= 0)
1747 return 0;
1748
1749 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
1750 pci_rc);
1751
1752 return pci_rc;
1753 }
1754
1755 /*
1756 * i7core_exit() Module exit function
1757 * Unregister the driver
1758 */
1759 static void __exit i7core_exit(void)
1760 {
1761 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1762 pci_unregister_driver(&i7core_driver);
1763 }
1764
1765 module_init(i7core_init);
1766 module_exit(i7core_exit);
1767
1768 MODULE_LICENSE("GPL");
1769 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1770 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1771 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
1772 I7CORE_REVISION);
1773
1774 module_param(edac_op_state, int, 0444);
1775 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
kernel source for telekom puls (alcatel/mediatek)