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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / edac / i5100_edac.c
1 /*
2 * Intel 5100 Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * This module is based on the following document:
8 *
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
11 *
12 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
14 * rows for each respective channel are laid out one after another,
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
17 */
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
22 #include <linux/edac.h>
23 #include <linux/delay.h>
24 #include <linux/mmzone.h>
25
26 #include "edac_core.h"
27
28 /* register addresses */
29
30 /* device 16, func 1 */
31 #define I5100_MC 0x40 /* Memory Control Register */
32 #define I5100_MC_SCRBEN_MASK (1 << 7)
33 #define I5100_MC_SCRBDONE_MASK (1 << 4)
34 #define I5100_MS 0x44 /* Memory Status Register */
35 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
36 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
37 #define I5100_TOLM 0x6c /* Top of Low Memory */
38 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
39 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
40 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
41 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
42 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
43 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
44 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
45 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
46 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
47 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
48 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
49 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
50 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
51 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
52 #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
53 #define I5100_FERR_NF_MEM_ANY_MASK \
54 (I5100_FERR_NF_MEM_M16ERR_MASK | \
55 I5100_FERR_NF_MEM_M15ERR_MASK | \
56 I5100_FERR_NF_MEM_M14ERR_MASK | \
57 I5100_FERR_NF_MEM_M12ERR_MASK | \
58 I5100_FERR_NF_MEM_M11ERR_MASK | \
59 I5100_FERR_NF_MEM_M10ERR_MASK | \
60 I5100_FERR_NF_MEM_M6ERR_MASK | \
61 I5100_FERR_NF_MEM_M5ERR_MASK | \
62 I5100_FERR_NF_MEM_M4ERR_MASK | \
63 I5100_FERR_NF_MEM_M1ERR_MASK)
64 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
65 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
66
67 /* device 21 and 22, func 0 */
68 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
69 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
70 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */
71 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
72 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
73 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
74 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
75 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
76 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
77 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
78
79 /* bit field accessors */
80
81 static inline u32 i5100_mc_scrben(u32 mc)
82 {
83 return mc >> 7 & 1;
84 }
85
86 static inline u32 i5100_mc_errdeten(u32 mc)
87 {
88 return mc >> 5 & 1;
89 }
90
91 static inline u32 i5100_mc_scrbdone(u32 mc)
92 {
93 return mc >> 4 & 1;
94 }
95
96 static inline u16 i5100_spddata_rdo(u16 a)
97 {
98 return a >> 15 & 1;
99 }
100
101 static inline u16 i5100_spddata_sbe(u16 a)
102 {
103 return a >> 13 & 1;
104 }
105
106 static inline u16 i5100_spddata_busy(u16 a)
107 {
108 return a >> 12 & 1;
109 }
110
111 static inline u16 i5100_spddata_data(u16 a)
112 {
113 return a & ((1 << 8) - 1);
114 }
115
116 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
117 u32 data, u32 cmd)
118 {
119 return ((dti & ((1 << 4) - 1)) << 28) |
120 ((ckovrd & 1) << 27) |
121 ((sa & ((1 << 3) - 1)) << 24) |
122 ((ba & ((1 << 8) - 1)) << 16) |
123 ((data & ((1 << 8) - 1)) << 8) |
124 (cmd & 1);
125 }
126
127 static inline u16 i5100_tolm_tolm(u16 a)
128 {
129 return a >> 12 & ((1 << 4) - 1);
130 }
131
132 static inline u16 i5100_mir_limit(u16 a)
133 {
134 return a >> 4 & ((1 << 12) - 1);
135 }
136
137 static inline u16 i5100_mir_way1(u16 a)
138 {
139 return a >> 1 & 1;
140 }
141
142 static inline u16 i5100_mir_way0(u16 a)
143 {
144 return a & 1;
145 }
146
147 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
148 {
149 return a >> 28 & 1;
150 }
151
152 static inline u32 i5100_ferr_nf_mem_any(u32 a)
153 {
154 return a & I5100_FERR_NF_MEM_ANY_MASK;
155 }
156
157 static inline u32 i5100_nerr_nf_mem_any(u32 a)
158 {
159 return i5100_ferr_nf_mem_any(a);
160 }
161
162 static inline u32 i5100_dmir_limit(u32 a)
163 {
164 return a >> 16 & ((1 << 11) - 1);
165 }
166
167 static inline u32 i5100_dmir_rank(u32 a, u32 i)
168 {
169 return a >> (4 * i) & ((1 << 2) - 1);
170 }
171
172 static inline u16 i5100_mtr_present(u16 a)
173 {
174 return a >> 10 & 1;
175 }
176
177 static inline u16 i5100_mtr_ethrottle(u16 a)
178 {
179 return a >> 9 & 1;
180 }
181
182 static inline u16 i5100_mtr_width(u16 a)
183 {
184 return a >> 8 & 1;
185 }
186
187 static inline u16 i5100_mtr_numbank(u16 a)
188 {
189 return a >> 6 & 1;
190 }
191
192 static inline u16 i5100_mtr_numrow(u16 a)
193 {
194 return a >> 2 & ((1 << 2) - 1);
195 }
196
197 static inline u16 i5100_mtr_numcol(u16 a)
198 {
199 return a & ((1 << 2) - 1);
200 }
201
202
203 static inline u32 i5100_validlog_redmemvalid(u32 a)
204 {
205 return a >> 2 & 1;
206 }
207
208 static inline u32 i5100_validlog_recmemvalid(u32 a)
209 {
210 return a >> 1 & 1;
211 }
212
213 static inline u32 i5100_validlog_nrecmemvalid(u32 a)
214 {
215 return a & 1;
216 }
217
218 static inline u32 i5100_nrecmema_merr(u32 a)
219 {
220 return a >> 15 & ((1 << 5) - 1);
221 }
222
223 static inline u32 i5100_nrecmema_bank(u32 a)
224 {
225 return a >> 12 & ((1 << 3) - 1);
226 }
227
228 static inline u32 i5100_nrecmema_rank(u32 a)
229 {
230 return a >> 8 & ((1 << 3) - 1);
231 }
232
233 static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
234 {
235 return a & ((1 << 8) - 1);
236 }
237
238 static inline u32 i5100_nrecmemb_cas(u32 a)
239 {
240 return a >> 16 & ((1 << 13) - 1);
241 }
242
243 static inline u32 i5100_nrecmemb_ras(u32 a)
244 {
245 return a & ((1 << 16) - 1);
246 }
247
248 static inline u32 i5100_redmemb_ecc_locator(u32 a)
249 {
250 return a & ((1 << 18) - 1);
251 }
252
253 static inline u32 i5100_recmema_merr(u32 a)
254 {
255 return i5100_nrecmema_merr(a);
256 }
257
258 static inline u32 i5100_recmema_bank(u32 a)
259 {
260 return i5100_nrecmema_bank(a);
261 }
262
263 static inline u32 i5100_recmema_rank(u32 a)
264 {
265 return i5100_nrecmema_rank(a);
266 }
267
268 static inline u32 i5100_recmema_dm_buf_id(u32 a)
269 {
270 return i5100_nrecmema_dm_buf_id(a);
271 }
272
273 static inline u32 i5100_recmemb_cas(u32 a)
274 {
275 return i5100_nrecmemb_cas(a);
276 }
277
278 static inline u32 i5100_recmemb_ras(u32 a)
279 {
280 return i5100_nrecmemb_ras(a);
281 }
282
283 /* some generic limits */
284 #define I5100_MAX_RANKS_PER_CHAN 6
285 #define I5100_CHANNELS 2
286 #define I5100_MAX_RANKS_PER_DIMM 4
287 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
288 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
289 #define I5100_MAX_RANK_INTERLEAVE 4
290 #define I5100_MAX_DMIRS 5
291 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
292
293 struct i5100_priv {
294 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
295 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
296
297 /*
298 * mainboard chip select map -- maps i5100 chip selects to
299 * DIMM slot chip selects. In the case of only 4 ranks per
300 * channel, the mapping is fairly obvious but not unique.
301 * we map -1 -> NC and assume both channels use the same
302 * map...
303 *
304 */
305 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
306
307 /* memory interleave range */
308 struct {
309 u64 limit;
310 unsigned way[2];
311 } mir[I5100_CHANNELS];
312
313 /* adjusted memory interleave range register */
314 unsigned amir[I5100_CHANNELS];
315
316 /* dimm interleave range */
317 struct {
318 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
319 u64 limit;
320 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
321
322 /* memory technology registers... */
323 struct {
324 unsigned present; /* 0 or 1 */
325 unsigned ethrottle; /* 0 or 1 */
326 unsigned width; /* 4 or 8 bits */
327 unsigned numbank; /* 2 or 3 lines */
328 unsigned numrow; /* 13 .. 16 lines */
329 unsigned numcol; /* 11 .. 12 lines */
330 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
331
332 u64 tolm; /* top of low memory in bytes */
333 unsigned ranksperchan; /* number of ranks per channel */
334
335 struct pci_dev *mc; /* device 16 func 1 */
336 struct pci_dev *ch0mm; /* device 21 func 0 */
337 struct pci_dev *ch1mm; /* device 22 func 0 */
338
339 struct delayed_work i5100_scrubbing;
340 int scrub_enable;
341 };
342
343 /* map a rank/chan to a slot number on the mainboard */
344 static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
345 int chan, int rank)
346 {
347 const struct i5100_priv *priv = mci->pvt_info;
348 int i;
349
350 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
351 int j;
352 const int numrank = priv->dimm_numrank[chan][i];
353
354 for (j = 0; j < numrank; j++)
355 if (priv->dimm_csmap[i][j] == rank)
356 return i * 2 + chan;
357 }
358
359 return -1;
360 }
361
362 static const char *i5100_err_msg(unsigned err)
363 {
364 static const char *merrs[] = {
365 "unknown", /* 0 */
366 "uncorrectable data ECC on replay", /* 1 */
367 "unknown", /* 2 */
368 "unknown", /* 3 */
369 "aliased uncorrectable demand data ECC", /* 4 */
370 "aliased uncorrectable spare-copy data ECC", /* 5 */
371 "aliased uncorrectable patrol data ECC", /* 6 */
372 "unknown", /* 7 */
373 "unknown", /* 8 */
374 "unknown", /* 9 */
375 "non-aliased uncorrectable demand data ECC", /* 10 */
376 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
377 "non-aliased uncorrectable patrol data ECC", /* 12 */
378 "unknown", /* 13 */
379 "correctable demand data ECC", /* 14 */
380 "correctable spare-copy data ECC", /* 15 */
381 "correctable patrol data ECC", /* 16 */
382 "unknown", /* 17 */
383 "SPD protocol error", /* 18 */
384 "unknown", /* 19 */
385 "spare copy initiated", /* 20 */
386 "spare copy completed", /* 21 */
387 };
388 unsigned i;
389
390 for (i = 0; i < ARRAY_SIZE(merrs); i++)
391 if (1 << i & err)
392 return merrs[i];
393
394 return "none";
395 }
396
397 /* convert csrow index into a rank (per channel -- 0..5) */
398 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
399 {
400 const struct i5100_priv *priv = mci->pvt_info;
401
402 return csrow % priv->ranksperchan;
403 }
404
405 /* convert csrow index into a channel (0..1) */
406 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
407 {
408 const struct i5100_priv *priv = mci->pvt_info;
409
410 return csrow / priv->ranksperchan;
411 }
412
413 static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci,
414 int chan, int rank)
415 {
416 const struct i5100_priv *priv = mci->pvt_info;
417
418 return chan * priv->ranksperchan + rank;
419 }
420
421 static void i5100_handle_ce(struct mem_ctl_info *mci,
422 int chan,
423 unsigned bank,
424 unsigned rank,
425 unsigned long syndrome,
426 unsigned cas,
427 unsigned ras,
428 const char *msg)
429 {
430 const int csrow = i5100_rank_to_csrow(mci, chan, rank);
431
432 printk(KERN_ERR
433 "CE chan %d, bank %u, rank %u, syndrome 0x%lx, "
434 "cas %u, ras %u, csrow %u, label \"%s\": %s\n",
435 chan, bank, rank, syndrome, cas, ras,
436 csrow, mci->csrows[csrow].channels[0].label, msg);
437
438 mci->ce_count++;
439 mci->csrows[csrow].ce_count++;
440 mci->csrows[csrow].channels[0].ce_count++;
441 }
442
443 static void i5100_handle_ue(struct mem_ctl_info *mci,
444 int chan,
445 unsigned bank,
446 unsigned rank,
447 unsigned long syndrome,
448 unsigned cas,
449 unsigned ras,
450 const char *msg)
451 {
452 const int csrow = i5100_rank_to_csrow(mci, chan, rank);
453
454 printk(KERN_ERR
455 "UE chan %d, bank %u, rank %u, syndrome 0x%lx, "
456 "cas %u, ras %u, csrow %u, label \"%s\": %s\n",
457 chan, bank, rank, syndrome, cas, ras,
458 csrow, mci->csrows[csrow].channels[0].label, msg);
459
460 mci->ue_count++;
461 mci->csrows[csrow].ue_count++;
462 }
463
464 static void i5100_read_log(struct mem_ctl_info *mci, int chan,
465 u32 ferr, u32 nerr)
466 {
467 struct i5100_priv *priv = mci->pvt_info;
468 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
469 u32 dw;
470 u32 dw2;
471 unsigned syndrome = 0;
472 unsigned ecc_loc = 0;
473 unsigned merr;
474 unsigned bank;
475 unsigned rank;
476 unsigned cas;
477 unsigned ras;
478
479 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
480
481 if (i5100_validlog_redmemvalid(dw)) {
482 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
483 syndrome = dw2;
484 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
485 ecc_loc = i5100_redmemb_ecc_locator(dw2);
486 }
487
488 if (i5100_validlog_recmemvalid(dw)) {
489 const char *msg;
490
491 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
492 merr = i5100_recmema_merr(dw2);
493 bank = i5100_recmema_bank(dw2);
494 rank = i5100_recmema_rank(dw2);
495
496 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
497 cas = i5100_recmemb_cas(dw2);
498 ras = i5100_recmemb_ras(dw2);
499
500 /* FIXME: not really sure if this is what merr is...
501 */
502 if (!merr)
503 msg = i5100_err_msg(ferr);
504 else
505 msg = i5100_err_msg(nerr);
506
507 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
508 }
509
510 if (i5100_validlog_nrecmemvalid(dw)) {
511 const char *msg;
512
513 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
514 merr = i5100_nrecmema_merr(dw2);
515 bank = i5100_nrecmema_bank(dw2);
516 rank = i5100_nrecmema_rank(dw2);
517
518 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
519 cas = i5100_nrecmemb_cas(dw2);
520 ras = i5100_nrecmemb_ras(dw2);
521
522 /* FIXME: not really sure if this is what merr is...
523 */
524 if (!merr)
525 msg = i5100_err_msg(ferr);
526 else
527 msg = i5100_err_msg(nerr);
528
529 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
530 }
531
532 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
533 }
534
535 static void i5100_check_error(struct mem_ctl_info *mci)
536 {
537 struct i5100_priv *priv = mci->pvt_info;
538 u32 dw, dw2;
539
540 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
541 if (i5100_ferr_nf_mem_any(dw)) {
542
543 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
544
545 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
546 i5100_ferr_nf_mem_any(dw),
547 i5100_nerr_nf_mem_any(dw2));
548
549 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
550 }
551 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
552 }
553
554 /* The i5100 chipset will scrub the entire memory once, then
555 * set a done bit. Continuous scrubbing is achieved by enqueing
556 * delayed work to a workqueue, checking every few minutes if
557 * the scrubbing has completed and if so reinitiating it.
558 */
559
560 static void i5100_refresh_scrubbing(struct work_struct *work)
561 {
562 struct delayed_work *i5100_scrubbing = container_of(work,
563 struct delayed_work,
564 work);
565 struct i5100_priv *priv = container_of(i5100_scrubbing,
566 struct i5100_priv,
567 i5100_scrubbing);
568 u32 dw;
569
570 pci_read_config_dword(priv->mc, I5100_MC, &dw);
571
572 if (priv->scrub_enable) {
573
574 pci_read_config_dword(priv->mc, I5100_MC, &dw);
575
576 if (i5100_mc_scrbdone(dw)) {
577 dw |= I5100_MC_SCRBEN_MASK;
578 pci_write_config_dword(priv->mc, I5100_MC, dw);
579 pci_read_config_dword(priv->mc, I5100_MC, &dw);
580 }
581
582 schedule_delayed_work(&(priv->i5100_scrubbing),
583 I5100_SCRUB_REFRESH_RATE);
584 }
585 }
586 /*
587 * The bandwidth is based on experimentation, feel free to refine it.
588 */
589 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
590 {
591 struct i5100_priv *priv = mci->pvt_info;
592 u32 dw;
593
594 pci_read_config_dword(priv->mc, I5100_MC, &dw);
595 if (bandwidth) {
596 priv->scrub_enable = 1;
597 dw |= I5100_MC_SCRBEN_MASK;
598 schedule_delayed_work(&(priv->i5100_scrubbing),
599 I5100_SCRUB_REFRESH_RATE);
600 } else {
601 priv->scrub_enable = 0;
602 dw &= ~I5100_MC_SCRBEN_MASK;
603 cancel_delayed_work(&(priv->i5100_scrubbing));
604 }
605 pci_write_config_dword(priv->mc, I5100_MC, dw);
606
607 pci_read_config_dword(priv->mc, I5100_MC, &dw);
608
609 bandwidth = 5900000 * i5100_mc_scrben(dw);
610
611 return bandwidth;
612 }
613
614 static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
615 {
616 struct i5100_priv *priv = mci->pvt_info;
617 u32 dw;
618
619 pci_read_config_dword(priv->mc, I5100_MC, &dw);
620
621 return 5900000 * i5100_mc_scrben(dw);
622 }
623
624 static struct pci_dev *pci_get_device_func(unsigned vendor,
625 unsigned device,
626 unsigned func)
627 {
628 struct pci_dev *ret = NULL;
629
630 while (1) {
631 ret = pci_get_device(vendor, device, ret);
632
633 if (!ret)
634 break;
635
636 if (PCI_FUNC(ret->devfn) == func)
637 break;
638 }
639
640 return ret;
641 }
642
643 static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci,
644 int csrow)
645 {
646 struct i5100_priv *priv = mci->pvt_info;
647 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
648 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
649 unsigned addr_lines;
650
651 /* dimm present? */
652 if (!priv->mtr[chan][chan_rank].present)
653 return 0ULL;
654
655 addr_lines =
656 I5100_DIMM_ADDR_LINES +
657 priv->mtr[chan][chan_rank].numcol +
658 priv->mtr[chan][chan_rank].numrow +
659 priv->mtr[chan][chan_rank].numbank;
660
661 return (unsigned long)
662 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
663 }
664
665 static void __devinit i5100_init_mtr(struct mem_ctl_info *mci)
666 {
667 struct i5100_priv *priv = mci->pvt_info;
668 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
669 int i;
670
671 for (i = 0; i < I5100_CHANNELS; i++) {
672 int j;
673 struct pci_dev *pdev = mms[i];
674
675 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
676 const unsigned addr =
677 (j < 4) ? I5100_MTR_0 + j * 2 :
678 I5100_MTR_4 + (j - 4) * 2;
679 u16 w;
680
681 pci_read_config_word(pdev, addr, &w);
682
683 priv->mtr[i][j].present = i5100_mtr_present(w);
684 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
685 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
686 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
687 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
688 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
689 }
690 }
691 }
692
693 /*
694 * FIXME: make this into a real i2c adapter (so that dimm-decode
695 * will work)?
696 */
697 static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
698 u8 ch, u8 slot, u8 addr, u8 *byte)
699 {
700 struct i5100_priv *priv = mci->pvt_info;
701 u16 w;
702 unsigned long et;
703
704 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
705 if (i5100_spddata_busy(w))
706 return -1;
707
708 pci_write_config_dword(priv->mc, I5100_SPDCMD,
709 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
710 0, 0));
711
712 /* wait up to 100ms */
713 et = jiffies + HZ / 10;
714 udelay(100);
715 while (1) {
716 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
717 if (!i5100_spddata_busy(w))
718 break;
719 udelay(100);
720 }
721
722 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
723 return -1;
724
725 *byte = i5100_spddata_data(w);
726
727 return 0;
728 }
729
730 /*
731 * fill dimm chip select map
732 *
733 * FIXME:
734 * o not the only way to may chip selects to dimm slots
735 * o investigate if there is some way to obtain this map from the bios
736 */
737 static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
738 {
739 struct i5100_priv *priv = mci->pvt_info;
740 int i;
741
742 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
743 int j;
744
745 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
746 priv->dimm_csmap[i][j] = -1; /* default NC */
747 }
748
749 /* only 2 chip selects per slot... */
750 if (priv->ranksperchan == 4) {
751 priv->dimm_csmap[0][0] = 0;
752 priv->dimm_csmap[0][1] = 3;
753 priv->dimm_csmap[1][0] = 1;
754 priv->dimm_csmap[1][1] = 2;
755 priv->dimm_csmap[2][0] = 2;
756 priv->dimm_csmap[3][0] = 3;
757 } else {
758 priv->dimm_csmap[0][0] = 0;
759 priv->dimm_csmap[0][1] = 1;
760 priv->dimm_csmap[1][0] = 2;
761 priv->dimm_csmap[1][1] = 3;
762 priv->dimm_csmap[2][0] = 4;
763 priv->dimm_csmap[2][1] = 5;
764 }
765 }
766
767 static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev,
768 struct mem_ctl_info *mci)
769 {
770 struct i5100_priv *priv = mci->pvt_info;
771 int i;
772
773 for (i = 0; i < I5100_CHANNELS; i++) {
774 int j;
775
776 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
777 u8 rank;
778
779 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
780 priv->dimm_numrank[i][j] = 0;
781 else
782 priv->dimm_numrank[i][j] = (rank & 3) + 1;
783 }
784 }
785
786 i5100_init_dimm_csmap(mci);
787 }
788
789 static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
790 struct mem_ctl_info *mci)
791 {
792 u16 w;
793 u32 dw;
794 struct i5100_priv *priv = mci->pvt_info;
795 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
796 int i;
797
798 pci_read_config_word(pdev, I5100_TOLM, &w);
799 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
800
801 pci_read_config_word(pdev, I5100_MIR0, &w);
802 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
803 priv->mir[0].way[1] = i5100_mir_way1(w);
804 priv->mir[0].way[0] = i5100_mir_way0(w);
805
806 pci_read_config_word(pdev, I5100_MIR1, &w);
807 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
808 priv->mir[1].way[1] = i5100_mir_way1(w);
809 priv->mir[1].way[0] = i5100_mir_way0(w);
810
811 pci_read_config_word(pdev, I5100_AMIR_0, &w);
812 priv->amir[0] = w;
813 pci_read_config_word(pdev, I5100_AMIR_1, &w);
814 priv->amir[1] = w;
815
816 for (i = 0; i < I5100_CHANNELS; i++) {
817 int j;
818
819 for (j = 0; j < 5; j++) {
820 int k;
821
822 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
823
824 priv->dmir[i][j].limit =
825 (u64) i5100_dmir_limit(dw) << 28;
826 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
827 priv->dmir[i][j].rank[k] =
828 i5100_dmir_rank(dw, k);
829 }
830 }
831
832 i5100_init_mtr(mci);
833 }
834
835 static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
836 {
837 int i;
838 unsigned long total_pages = 0UL;
839 struct i5100_priv *priv = mci->pvt_info;
840
841 for (i = 0; i < mci->nr_csrows; i++) {
842 const unsigned long npages = i5100_npages(mci, i);
843 const unsigned chan = i5100_csrow_to_chan(mci, i);
844 const unsigned rank = i5100_csrow_to_rank(mci, i);
845
846 if (!npages)
847 continue;
848
849 /*
850 * FIXME: these two are totally bogus -- I don't see how to
851 * map them correctly to this structure...
852 */
853 mci->csrows[i].first_page = total_pages;
854 mci->csrows[i].last_page = total_pages + npages - 1;
855 mci->csrows[i].page_mask = 0UL;
856
857 mci->csrows[i].nr_pages = npages;
858 mci->csrows[i].grain = 32;
859 mci->csrows[i].csrow_idx = i;
860 mci->csrows[i].dtype =
861 (priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8;
862 mci->csrows[i].ue_count = 0;
863 mci->csrows[i].ce_count = 0;
864 mci->csrows[i].mtype = MEM_RDDR2;
865 mci->csrows[i].edac_mode = EDAC_SECDED;
866 mci->csrows[i].mci = mci;
867 mci->csrows[i].nr_channels = 1;
868 mci->csrows[i].channels[0].chan_idx = 0;
869 mci->csrows[i].channels[0].ce_count = 0;
870 mci->csrows[i].channels[0].csrow = mci->csrows + i;
871 snprintf(mci->csrows[i].channels[0].label,
872 sizeof(mci->csrows[i].channels[0].label),
873 "DIMM%u", i5100_rank_to_slot(mci, chan, rank));
874
875 total_pages += npages;
876 }
877 }
878
879 static int __devinit i5100_init_one(struct pci_dev *pdev,
880 const struct pci_device_id *id)
881 {
882 int rc;
883 struct mem_ctl_info *mci;
884 struct i5100_priv *priv;
885 struct pci_dev *ch0mm, *ch1mm;
886 int ret = 0;
887 u32 dw;
888 int ranksperch;
889
890 if (PCI_FUNC(pdev->devfn) != 1)
891 return -ENODEV;
892
893 rc = pci_enable_device(pdev);
894 if (rc < 0) {
895 ret = rc;
896 goto bail;
897 }
898
899 /* ECC enabled? */
900 pci_read_config_dword(pdev, I5100_MC, &dw);
901 if (!i5100_mc_errdeten(dw)) {
902 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
903 ret = -ENODEV;
904 goto bail_pdev;
905 }
906
907 /* figure out how many ranks, from strapped state of 48GB_Mode input */
908 pci_read_config_dword(pdev, I5100_MS, &dw);
909 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
910
911 /* enable error reporting... */
912 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
913 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
914 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
915
916 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
917 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
918 PCI_DEVICE_ID_INTEL_5100_21, 0);
919 if (!ch0mm) {
920 ret = -ENODEV;
921 goto bail_pdev;
922 }
923
924 rc = pci_enable_device(ch0mm);
925 if (rc < 0) {
926 ret = rc;
927 goto bail_ch0;
928 }
929
930 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
931 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
932 PCI_DEVICE_ID_INTEL_5100_22, 0);
933 if (!ch1mm) {
934 ret = -ENODEV;
935 goto bail_disable_ch0;
936 }
937
938 rc = pci_enable_device(ch1mm);
939 if (rc < 0) {
940 ret = rc;
941 goto bail_ch1;
942 }
943
944 mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0);
945 if (!mci) {
946 ret = -ENOMEM;
947 goto bail_disable_ch1;
948 }
949
950 mci->dev = &pdev->dev;
951
952 priv = mci->pvt_info;
953 priv->ranksperchan = ranksperch;
954 priv->mc = pdev;
955 priv->ch0mm = ch0mm;
956 priv->ch1mm = ch1mm;
957
958 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
959
960 /* If scrubbing was already enabled by the bios, start maintaining it */
961 pci_read_config_dword(pdev, I5100_MC, &dw);
962 if (i5100_mc_scrben(dw)) {
963 priv->scrub_enable = 1;
964 schedule_delayed_work(&(priv->i5100_scrubbing),
965 I5100_SCRUB_REFRESH_RATE);
966 }
967
968 i5100_init_dimm_layout(pdev, mci);
969 i5100_init_interleaving(pdev, mci);
970
971 mci->mtype_cap = MEM_FLAG_FB_DDR2;
972 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
973 mci->edac_cap = EDAC_FLAG_SECDED;
974 mci->mod_name = "i5100_edac.c";
975 mci->mod_ver = "not versioned";
976 mci->ctl_name = "i5100";
977 mci->dev_name = pci_name(pdev);
978 mci->ctl_page_to_phys = NULL;
979
980 mci->edac_check = i5100_check_error;
981 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
982 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
983
984 i5100_init_csrows(mci);
985
986 /* this strange construction seems to be in every driver, dunno why */
987 switch (edac_op_state) {
988 case EDAC_OPSTATE_POLL:
989 case EDAC_OPSTATE_NMI:
990 break;
991 default:
992 edac_op_state = EDAC_OPSTATE_POLL;
993 break;
994 }
995
996 if (edac_mc_add_mc(mci)) {
997 ret = -ENODEV;
998 goto bail_scrub;
999 }
1000
1001 return ret;
1002
1003 bail_scrub:
1004 priv->scrub_enable = 0;
1005 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1006 edac_mc_free(mci);
1007
1008 bail_disable_ch1:
1009 pci_disable_device(ch1mm);
1010
1011 bail_ch1:
1012 pci_dev_put(ch1mm);
1013
1014 bail_disable_ch0:
1015 pci_disable_device(ch0mm);
1016
1017 bail_ch0:
1018 pci_dev_put(ch0mm);
1019
1020 bail_pdev:
1021 pci_disable_device(pdev);
1022
1023 bail:
1024 return ret;
1025 }
1026
1027 static void __devexit i5100_remove_one(struct pci_dev *pdev)
1028 {
1029 struct mem_ctl_info *mci;
1030 struct i5100_priv *priv;
1031
1032 mci = edac_mc_del_mc(&pdev->dev);
1033
1034 if (!mci)
1035 return;
1036
1037 priv = mci->pvt_info;
1038
1039 priv->scrub_enable = 0;
1040 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1041
1042 pci_disable_device(pdev);
1043 pci_disable_device(priv->ch0mm);
1044 pci_disable_device(priv->ch1mm);
1045 pci_dev_put(priv->ch0mm);
1046 pci_dev_put(priv->ch1mm);
1047
1048 edac_mc_free(mci);
1049 }
1050
1051 static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
1052 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1054 { 0, }
1055 };
1056 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1057
1058 static struct pci_driver i5100_driver = {
1059 .name = KBUILD_BASENAME,
1060 .probe = i5100_init_one,
1061 .remove = __devexit_p(i5100_remove_one),
1062 .id_table = i5100_pci_tbl,
1063 };
1064
1065 static int __init i5100_init(void)
1066 {
1067 int pci_rc;
1068
1069 pci_rc = pci_register_driver(&i5100_driver);
1070
1071 return (pci_rc < 0) ? pci_rc : 0;
1072 }
1073
1074 static void __exit i5100_exit(void)
1075 {
1076 pci_unregister_driver(&i5100_driver);
1077 }
1078
1079 module_init(i5100_init);
1080 module_exit(i5100_exit);
1081
1082 MODULE_LICENSE("GPL");
1083 MODULE_AUTHOR
1084 ("Arthur Jones <ajones@riverbed.com>");
1085 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");