drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/version.h>
  38
  39 #define EDAC_MC_LABEL_LEN       31
  40 #define EDAC_DEVICE_NAME_LEN    31
  41 #define EDAC_ATTRIB_VALUE_LEN   15
  42 #define MC_PROC_NAME_MAX_LEN    7
  43
  44 #if PAGE_SHIFT < 20
  45 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  46 #else                           /* PAGE_SHIFT > 20 */
  47 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  48 #endif
  49
  50 #define edac_printk(level, prefix, fmt, arg...) \
  51         printk(level "EDAC " prefix ": " fmt, ##arg)
  52
  53 #define edac_mc_printk(mci, level, fmt, arg...) \
  54         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  55
  56 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  57         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 /* edac_device printk */
  60 #define edac_device_printk(ctl, level, fmt, arg...) \
  61         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  62
  63 /* edac_pci printk */
  64 #define edac_pci_printk(ctl, level, fmt, arg...) \
  65         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  66
  67 /* prefixes for edac_printk() and edac_mc_printk() */
  68 #define EDAC_MC "MC"
  69 #define EDAC_PCI "PCI"
  70 #define EDAC_DEBUG "DEBUG"
  71
  72 #ifdef CONFIG_EDAC_DEBUG
  73 extern int edac_debug_level;
  74
  75 #define edac_debug_printk(level, fmt, arg...)                            \
  76         do {                                                             \
  77                 if (level <= edac_debug_level)                           \
  78                         edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \
  79         } while(0)
  80
  81 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  82 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  83 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  84 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  85 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  86
  87 #else                           /* !CONFIG_EDAC_DEBUG */
  88
  89 #define debugf0( ... )
  90 #define debugf1( ... )
  91 #define debugf2( ... )
  92 #define debugf3( ... )
  93 #define debugf4( ... )
  94
  95 #endif                          /* !CONFIG_EDAC_DEBUG */
  96
  97 #define BIT(x) (1 << (x))
  98
  99 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 100         PCI_DEVICE_ID_ ## vend ## _ ## dev
 101
 102 #define dev_name(dev) (dev)->dev_name
 103
 104 /* memory devices */
 105 enum dev_type {
 106         DEV_UNKNOWN = 0,
 107         DEV_X1,
 108         DEV_X2,
 109         DEV_X4,
 110         DEV_X8,
 111         DEV_X16,
 112         DEV_X32,                /* Do these parts exist? */
 113         DEV_X64                 /* Do these parts exist? */
 114 };
 115
 116 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 117 #define DEV_FLAG_X1             BIT(DEV_X1)
 118 #define DEV_FLAG_X2             BIT(DEV_X2)
 119 #define DEV_FLAG_X4             BIT(DEV_X4)
 120 #define DEV_FLAG_X8             BIT(DEV_X8)
 121 #define DEV_FLAG_X16            BIT(DEV_X16)
 122 #define DEV_FLAG_X32            BIT(DEV_X32)
 123 #define DEV_FLAG_X64            BIT(DEV_X64)
 124
 125 /* memory types */
 126 enum mem_type {
 127         MEM_EMPTY = 0,          /* Empty csrow */
 128         MEM_RESERVED,           /* Reserved csrow type */
 129         MEM_UNKNOWN,            /* Unknown csrow type */
 130         MEM_FPM,                /* Fast page mode */
 131         MEM_EDO,                /* Extended data out */
 132         MEM_BEDO,               /* Burst Extended data out */
 133         MEM_SDR,                /* Single data rate SDRAM */
 134         MEM_RDR,                /* Registered single data rate SDRAM */
 135         MEM_DDR,                /* Double data rate SDRAM */
 136         MEM_RDDR,               /* Registered Double data rate SDRAM */
 137         MEM_RMBS,               /* Rambus DRAM */
 138         MEM_DDR2,               /* DDR2 RAM */
 139         MEM_FB_DDR2,            /* fully buffered DDR2 */
 140         MEM_RDDR2,              /* Registered DDR2 RAM */
 141 };
 142
 143 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 144 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 145 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 146 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 147 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 148 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 149 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 150 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 151 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 152 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 153 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 154 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 155 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 156 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 157
 158 /* chipset Error Detection and Correction capabilities and mode */
 159 enum edac_type {
 160         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 161         EDAC_NONE,              /* Doesnt support ECC */
 162         EDAC_RESERVED,          /* Reserved ECC type */
 163         EDAC_PARITY,            /* Detects parity errors */
 164         EDAC_EC,                /* Error Checking - no correction */
 165         EDAC_SECDED,            /* Single bit error correction, Double detection */
 166         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 167         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 168         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 169         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 170 };
 171
 172 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 173 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 174 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 175 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 176 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 177 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 178 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 179 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 180 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 181
 182 /* scrubbing capabilities */
 183 enum scrub_type {
 184         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 185         SCRUB_NONE,             /* No scrubber */
 186         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 187         SCRUB_SW_SRC,           /* Software scrub only errors */
 188         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 189         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 190         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 191         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 192         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 193         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 194 };
 195
 196 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 197 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 198 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 199 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 200 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 201 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 202 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 203 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 204
 205 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 206
 207 /* EDAC internal operation states */
 208 #define OP_ALLOC                0x100
 209 #define OP_RUNNING_POLL         0x201
 210 #define OP_RUNNING_INTERRUPT    0x202
 211 #define OP_RUNNING_POLL_INTR    0x203
 212 #define OP_OFFLINE              0x300
 213
 214 extern char *edac_align_ptr(void *ptr, unsigned size);
 215
 216 /*
 217  * There are several things to be aware of that aren't at all obvious:
 218  *
 219  *
 220  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 221  *
 222  * These are some of the many terms that are thrown about that don't always
 223  * mean what people think they mean (Inconceivable!).  In the interest of
 224  * creating a common ground for discussion, terms and their definitions
 225  * will be established.
 226  *
 227  * Memory devices:      The individual chip on a memory stick.  These devices
 228  *                      commonly output 4 and 8 bits each.  Grouping several
 229  *                      of these in parallel provides 64 bits which is common
 230  *                      for a memory stick.
 231  *
 232  * Memory Stick:        A printed circuit board that agregates multiple
 233  *                      memory devices in parallel.  This is the atomic
 234  *                      memory component that is purchaseable by Joe consumer
 235  *                      and loaded into a memory socket.
 236  *
 237  * Socket:              A physical connector on the motherboard that accepts
 238  *                      a single memory stick.
 239  *
 240  * Channel:             Set of memory devices on a memory stick that must be
 241  *                      grouped in parallel with one or more additional
 242  *                      channels from other memory sticks.  This parallel
 243  *                      grouping of the output from multiple channels are
 244  *                      necessary for the smallest granularity of memory access.
 245  *                      Some memory controllers are capable of single channel -
 246  *                      which means that memory sticks can be loaded
 247  *                      individually.  Other memory controllers are only
 248  *                      capable of dual channel - which means that memory
 249  *                      sticks must be loaded as pairs (see "socket set").
 250  *
 251  * Chip-select row:     All of the memory devices that are selected together.
 252  *                      for a single, minimum grain of memory access.
 253  *                      This selects all of the parallel memory devices across
 254  *                      all of the parallel channels.  Common chip-select rows
 255  *                      for single channel are 64 bits, for dual channel 128
 256  *                      bits.
 257  *
 258  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 259  *                      Motherboards commonly drive two chip-select pins to
 260  *                      a memory stick. A single-ranked stick, will occupy
 261  *                      only one of those rows. The other will be unused.
 262  *
 263  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 264  *                      access different sets of memory devices.  The two
 265  *                      rows cannot be accessed concurrently.
 266  *
 267  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 268  *                      A double-sided stick has two chip-select rows which
 269  *                      access different sets of memory devices.  The two
 270  *                      rows cannot be accessed concurrently.  "Double-sided"
 271  *                      is irrespective of the memory devices being mounted
 272  *                      on both sides of the memory stick.
 273  *
 274  * Socket set:          All of the memory sticks that are required for for
 275  *                      a single memory access or all of the memory sticks
 276  *                      spanned by a chip-select row.  A single socket set
 277  *                      has two chip-select rows and if double-sided sticks
 278  *                      are used these will occupy those chip-select rows.
 279  *
 280  * Bank:                This term is avoided because it is unclear when
 281  *                      needing to distinguish between chip-select rows and
 282  *                      socket sets.
 283  *
 284  * Controller pages:
 285  *
 286  * Physical pages:
 287  *
 288  * Virtual pages:
 289  *
 290  *
 291  * STRUCTURE ORGANIZATION AND CHOICES
 292  *
 293  *
 294  *
 295  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 296  */
 297
 298 struct channel_info {
 299         int chan_idx;           /* channel index */
 300         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 301         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 302         struct csrow_info *csrow;       /* the parent */
 303 };
 304
 305 struct csrow_info {
 306         unsigned long first_page;       /* first page number in dimm */
 307         unsigned long last_page;        /* last page number in dimm */
 308         unsigned long page_mask;        /* used for interleaving -
 309                                          * 0UL for non intlv
 310                                          */
 311         u32 nr_pages;           /* number of pages in csrow */
 312         u32 grain;              /* granularity of reported error in bytes */
 313         int csrow_idx;          /* the chip-select row */
 314         enum dev_type dtype;    /* memory device type */
 315         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 316         u32 ce_count;           /* Correctable Errors for this csrow */
 317         enum mem_type mtype;    /* memory csrow type */
 318         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 319         struct mem_ctl_info *mci;       /* the parent */
 320
 321         struct kobject kobj;    /* sysfs kobject for this csrow */
 322         struct completion kobj_complete;
 323
 324         /* FIXME the number of CHANNELs might need to become dynamic */
 325         u32 nr_channels;
 326         struct channel_info *channels;
 327 };
 328
 329 /* mcidev_sysfs_attribute structure
 330  *      used for driver sysfs attributes and in mem_ctl_info
 331  *      sysfs top level entries
 332  */
 333 struct mcidev_sysfs_attribute {
 334         struct attribute attr;
 335         ssize_t (*show)(struct mem_ctl_info *,char *);
 336         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 337 };
 338
 339 /* MEMORY controller information structure
 340  */
 341 struct mem_ctl_info {
 342         struct list_head link;  /* for global list of mem_ctl_info structs */
 343         unsigned long mtype_cap;        /* memory types supported by mc */
 344         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 345         unsigned long edac_cap; /* configuration capabilities - this is
 346                                  * closely related to edac_ctl_cap.  The
 347                                  * difference is that the controller may be
 348                                  * capable of s4ecd4ed which would be listed
 349                                  * in edac_ctl_cap, but if channels aren't
 350                                  * capable of s4ecd4ed then the edac_cap would
 351                                  * not have that capability.
 352                                  */
 353         unsigned long scrub_cap;        /* chipset scrub capabilities */
 354         enum scrub_type scrub_mode;     /* current scrub mode */
 355
 356         /* Translates sdram memory scrub rate given in bytes/sec to the
 357            internal representation and configures whatever else needs
 358            to be configured.
 359          */
 360         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 361
 362         /* Get the current sdram memory scrub rate from the internal
 363            representation and converts it to the closest matching
 364            bandwith in bytes/sec.
 365          */
 366         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 367
 368
 369         /* pointer to edac checking routine */
 370         void (*edac_check) (struct mem_ctl_info * mci);
 371
 372         /*
 373          * Remaps memory pages: controller pages to physical pages.
 374          * For most MC's, this will be NULL.
 375          */
 376         /* FIXME - why not send the phys page to begin with? */
 377         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 378                                            unsigned long page);
 379         int mc_idx;
 380         int nr_csrows;
 381         struct csrow_info *csrows;
 382         /*
 383          * FIXME - what about controllers on other busses? - IDs must be
 384          * unique.  dev pointer should be sufficiently unique, but
 385          * BUS:SLOT.FUNC numbers may not be unique.
 386          */
 387         struct device *dev;
 388         const char *mod_name;
 389         const char *mod_ver;
 390         const char *ctl_name;
 391         const char *dev_name;
 392         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 393         void *pvt_info;
 394         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 395         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 396         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 397         u32 ce_count;           /* Total Correctable Errors for this MC */
 398         unsigned long start_time;       /* mci load start time (in jiffies) */
 399
 400         /* this stuff is for safe removal of mc devices from global list while
 401          * NMI handlers may be traversing list
 402          */
 403         struct rcu_head rcu;
 404         struct completion complete;
 405
 406         /* edac sysfs device control */
 407         struct kobject edac_mci_kobj;
 408         struct completion kobj_complete;
 409
 410         /* Additional top controller level attributes, but specified
 411          * by the low level driver.
 412          *
 413          * Set by the low level driver to provide attributes at the
 414          * controller level, same level as 'ue_count' and 'ce_count' above.
 415          * An array of structures, NULL terminated
 416          *
 417          * If attributes are desired, then set to array of attributes
 418          * If no attributes are desired, leave NULL
 419          */
 420         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 421
 422         /* work struct for this MC */
 423         struct delayed_work work;
 424
 425         /* the internal state of this controller instance */
 426         int op_state;
 427 };
 428
 429 /*
 430  * The following are the structures to provide for a generic
 431  * or abstract 'edac_device'. This set of structures and the
 432  * code that implements the APIs for the same, provide for
 433  * registering EDAC type devices which are NOT standard memory.
 434  *
 435  * CPU caches (L1 and L2)
 436  * DMA engines
 437  * Core CPU swithces
 438  * Fabric switch units
 439  * PCIe interface controllers
 440  * other EDAC/ECC type devices that can be monitored for
 441  * errors, etc.
 442  *
 443  * It allows for a 2 level set of hiearchry. For example:
 444  *
 445  * cache could be composed of L1, L2 and L3 levels of cache.
 446  * Each CPU core would have its own L1 cache, while sharing
 447  * L2 and maybe L3 caches.
 448  *
 449  * View them arranged, via the sysfs presentation:
 450  * /sys/devices/system/edac/..
 451  *
 452  *      mc/             <existing memory device directory>
 453  *      cpu/cpu0/..     <L1 and L2 block directory>
 454  *              /L1-cache/ce_count
 455  *                       /ue_count
 456  *              /L2-cache/ce_count
 457  *                       /ue_count
 458  *      cpu/cpu1/..     <L1 and L2 block directory>
 459  *              /L1-cache/ce_count
 460  *                       /ue_count
 461  *              /L2-cache/ce_count
 462  *                       /ue_count
 463  *      ...
 464  *
 465  *      the L1 and L2 directories would be "edac_device_block's"
 466  */
 467
 468 struct edac_device_counter {
 469         u32 ue_count;
 470         u32 ce_count;
 471 };
 472
 473 #define INC_COUNTER(cnt)        (cnt++)
 474
 475 /*
 476  * An array of these is passed to the alloc() function
 477  * to specify attributes of the edac_block
 478  */
 479 struct edac_attrib_spec {
 480         char name[EDAC_DEVICE_NAME_LEN + 1];
 481
 482         int type;
 483 #define EDAC_ATTR_INT           0x01
 484 #define EDAC_ATTR_CHAR          0x02
 485 };
 486
 487 /* Attribute control structure
 488  * In this structure is a pointer to the driver's edac_attrib_spec
 489  * The life of this pointer is inclusive in the life of the driver's
 490  * life cycle.
 491  */
 492 struct edac_attrib {
 493         struct edac_device_block *block;        /* Up Pointer */
 494
 495         struct edac_attrib_spec *spec;  /* ptr to module spec entry */
 496
 497         union {                 /* actual value */
 498                 int edac_attrib_int_value;
 499                 char edac_attrib_char_value[EDAC_ATTRIB_VALUE_LEN + 1];
 500         } edac_attrib_value;
 501 };
 502
 503 /* device block control structure */
 504 struct edac_device_block {
 505         struct edac_device_instance *instance;  /* Up Pointer */
 506         char name[EDAC_DEVICE_NAME_LEN + 1];
 507
 508         struct edac_device_counter counters;    /* basic UE and CE counters */
 509
 510         int nr_attribs;         /* how many attributes */
 511         struct edac_attrib *attribs;    /* this block's attributes */
 512
 513         /* edac sysfs device control */
 514         struct kobject kobj;
 515         struct completion kobj_complete;
 516 };
 517
 518 /* device instance control structure */
 519 struct edac_device_instance {
 520         struct edac_device_ctl_info *ctl;       /* Up pointer */
 521         char name[EDAC_DEVICE_NAME_LEN + 4];
 522
 523         struct edac_device_counter counters;    /* instance counters */
 524
 525         u32 nr_blocks;          /* how many blocks */
 526         struct edac_device_block *blocks;       /* block array */
 527
 528         /* edac sysfs device control */
 529         struct kobject kobj;
 530         struct completion kobj_complete;
 531 };
 532
 533 /* edac_dev_sysfs_attribute structure
 534  *     used for driver sysfs attributes and in mem_ctl_info
 535  *     sysfs top level entries
 536  */
 537 struct edac_dev_sysfs_attribute {
 538         struct attribute attr;
 539         ssize_t (*show)(struct edac_device_ctl_info *,char *);
 540         ssize_t (*store)(struct edac_device_ctl_info *, const char *,size_t);
 541 };
 542
 543 /*
 544  * Abstract edac_device control info structure
 545  *
 546  */
 547 struct edac_device_ctl_info {
 548         /* for global list of edac_device_ctl_info structs */
 549         struct list_head link;
 550
 551         int dev_idx;
 552
 553         /* Per instance controls for this edac_device */
 554         int log_ue;             /* boolean for logging UEs */
 555         int log_ce;             /* boolean for logging CEs */
 556         int panic_on_ue;        /* boolean for panic'ing on an UE */
 557         unsigned poll_msec;     /* number of milliseconds to poll interval */
 558         unsigned long delay;    /* number of jiffies for poll_msec */
 559
 560         /* Additional top controller level attributes, but specified
 561          * by the low level driver.
 562          *
 563          * Set by the low level driver to provide attributes at the
 564          * controller level, same level as 'ue_count' and 'ce_count' above.
 565          * An array of structures, NULL terminated
 566          *
 567          * If attributes are desired, then set to array of attributes
 568          * If no attributes are desired, leave NULL
 569          */
 570         struct edac_dev_sysfs_attribute *sysfs_attributes;
 571
 572         /* pointer to main 'edac' class in sysfs */
 573         struct sysdev_class *edac_class;
 574
 575         /* the internal state of this controller instance */
 576         int op_state;
 577         /* work struct for this instance */
 578         struct delayed_work work;
 579
 580         /* pointer to edac polling checking routine:
 581          *      If NOT NULL: points to polling check routine
 582          *      If NULL: Then assumes INTERRUPT operation, where
 583          *              MC driver will receive events
 584          */
 585         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 586
 587         struct device *dev;     /* pointer to device structure */
 588
 589         const char *mod_name;   /* module name */
 590         const char *ctl_name;   /* edac controller  name */
 591         const char *dev_name;   /* pci/platform/etc... name */
 592
 593         void *pvt_info;         /* pointer to 'private driver' info */
 594
 595         unsigned long start_time;       /* edac_device load start time (jiffies) */
 596
 597         /* these are for safe removal of mc devices from global list while
 598          * NMI handlers may be traversing list
 599          */
 600         struct rcu_head rcu;
 601         struct completion complete;
 602
 603         /* sysfs top name under 'edac' directory
 604          * and instance name:
 605          *      cpu/cpu0/...
 606          *      cpu/cpu1/...
 607          *      cpu/cpu2/...
 608          *      ...
 609          */
 610         char name[EDAC_DEVICE_NAME_LEN + 1];
 611
 612         /* Number of instances supported on this control structure
 613          * and the array of those instances
 614          */
 615         u32 nr_instances;
 616         struct edac_device_instance *instances;
 617
 618         /* Event counters for the this whole EDAC Device */
 619         struct edac_device_counter counters;
 620
 621         /* edac sysfs device control for the 'name'
 622          * device this structure controls
 623          */
 624         struct kobject kobj;
 625         struct completion kobj_complete;
 626 };
 627
 628 /* To get from the instance's wq to the beginning of the ctl structure */
 629 #define to_edac_mem_ctl_work(w) \
 630                 container_of(w, struct mem_ctl_info, work)
 631
 632 #define to_edac_device_ctl_work(w) \
 633                 container_of(w,struct edac_device_ctl_info,work)
 634
 635 /* Function to calc the number of delay jiffies from poll_msec */
 636 static inline void edac_device_calc_delay(struct edac_device_ctl_info *edac_dev)
 637 {
 638         /* convert from msec to jiffies */
 639         edac_dev->delay = edac_dev->poll_msec * HZ / 1000;
 640 }
 641
 642 #define edac_calc_delay(dev) dev->delay = dev->poll_msec * HZ / 1000;
 643
 644 /*
 645  * The alloc() and free() functions for the 'edac_device' control info
 646  * structure. A MC driver will allocate one of these for each edac_device
 647  * it is going to control/register with the EDAC CORE.
 648  */
 649 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 650                 unsigned sizeof_private,
 651                 char *edac_device_name,
 652                 unsigned nr_instances,
 653                 char *edac_block_name,
 654                 unsigned nr_blocks,
 655                 unsigned offset_value,
 656                 struct edac_attrib_spec *attrib_spec,
 657                 unsigned nr_attribs);
 658
 659 /* The offset value can be:
 660  *      -1 indicating no offset value
 661  *      0 for zero-based block numbers
 662  *      1 for 1-based block number
 663  *      other for other-based block number
 664  */
 665 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 666
 667 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 668
 669 #ifdef CONFIG_PCI
 670
 671 struct edac_pci_counter {
 672         atomic_t pe_count;
 673         atomic_t npe_count;
 674 };
 675
 676 /*
 677  * Abstract edac_pci control info structure
 678  *
 679  */
 680 struct edac_pci_ctl_info {
 681         /* for global list of edac_pci_ctl_info structs */
 682         struct list_head link;
 683
 684         int pci_idx;
 685
 686         struct sysdev_class *edac_class;        /* pointer to class */
 687
 688         /* the internal state of this controller instance */
 689         int op_state;
 690         /* work struct for this instance */
 691         struct delayed_work work;
 692
 693         /* pointer to edac polling checking routine:
 694          *      If NOT NULL: points to polling check routine
 695          *      If NULL: Then assumes INTERRUPT operation, where
 696          *              MC driver will receive events
 697          */
 698         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 699
 700         struct device *dev;     /* pointer to device structure */
 701
 702         const char *mod_name;   /* module name */
 703         const char *ctl_name;   /* edac controller  name */
 704         const char *dev_name;   /* pci/platform/etc... name */
 705
 706         void *pvt_info;         /* pointer to 'private driver' info */
 707
 708         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 709
 710         /* these are for safe removal of devices from global list while
 711          * NMI handlers may be traversing list
 712          */
 713         struct rcu_head rcu;
 714         struct completion complete;
 715
 716         /* sysfs top name under 'edac' directory
 717          * and instance name:
 718          *      cpu/cpu0/...
 719          *      cpu/cpu1/...
 720          *      cpu/cpu2/...
 721          *      ...
 722          */
 723         char name[EDAC_DEVICE_NAME_LEN + 1];
 724
 725         /* Event counters for the this whole EDAC Device */
 726         struct edac_pci_counter counters;
 727
 728         /* edac sysfs device control for the 'name'
 729          * device this structure controls
 730          */
 731         struct kobject kobj;
 732         struct completion kobj_complete;
 733 };
 734
 735 #define to_edac_pci_ctl_work(w) \
 736                 container_of(w, struct edac_pci_ctl_info,work)
 737
 738 /* write all or some bits in a byte-register*/
 739 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 740                                    u8 mask)
 741 {
 742         if (mask != 0xff) {
 743                 u8 buf;
 744
 745                 pci_read_config_byte(pdev, offset, &buf);
 746                 value &= mask;
 747                 buf &= ~mask;
 748                 value |= buf;
 749         }
 750
 751         pci_write_config_byte(pdev, offset, value);
 752 }
 753
 754 /* write all or some bits in a word-register*/
 755 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 756                                     u16 value, u16 mask)
 757 {
 758         if (mask != 0xffff) {
 759                 u16 buf;
 760
 761                 pci_read_config_word(pdev, offset, &buf);
 762                 value &= mask;
 763                 buf &= ~mask;
 764                 value |= buf;
 765         }
 766
 767         pci_write_config_word(pdev, offset, value);
 768 }
 769
 770 /* write all or some bits in a dword-register*/
 771 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 772                                     u32 value, u32 mask)
 773 {
 774         if (mask != 0xffff) {
 775                 u32 buf;
 776
 777                 pci_read_config_dword(pdev, offset, &buf);
 778                 value &= mask;
 779                 buf &= ~mask;
 780                 value |= buf;
 781         }
 782
 783         pci_write_config_dword(pdev, offset, value);
 784 }
 785
 786 #endif                          /* CONFIG_PCI */
 787
 788 extern struct mem_ctl_info *edac_mc_find(int idx);
 789 extern int edac_mc_add_mc(struct mem_ctl_info *mci, int mc_idx);
 790 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 791 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 792                                       unsigned long page);
 793
 794 /*
 795  * The no info errors are used when error overflows are reported.
 796  * There are a limited number of error logging registers that can
 797  * be exausted.  When all registers are exhausted and an additional
 798  * error occurs then an error overflow register records that an
 799  * error occured and the type of error, but doesn't have any
 800  * further information.  The ce/ue versions make for cleaner
 801  * reporting logic and function interface - reduces conditional
 802  * statement clutter and extra function arguments.
 803  */
 804 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 805                               unsigned long page_frame_number,
 806                               unsigned long offset_in_page,
 807                               unsigned long syndrome, int row, int channel,
 808                               const char *msg);
 809 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 810                                       const char *msg);
 811 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 812                               unsigned long page_frame_number,
 813                               unsigned long offset_in_page, int row,
 814                               const char *msg);
 815 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 816                                       const char *msg);
 817 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 818                                   unsigned int channel0, unsigned int channel1,
 819                                   char *msg);
 820 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 821                                   unsigned int channel, char *msg);
 822
 823 /*
 824  * edac_device APIs
 825  */
 826 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 827                                           unsigned nr_chans);
 828 extern void edac_mc_free(struct mem_ctl_info *mci);
 829 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev,
 830                                   int edac_idx);
 831 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 832 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 833                                   int inst_nr, int block_nr, const char *msg);
 834 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 835                                   int inst_nr, int block_nr, const char *msg);
 836
 837 /*
 838  * edac_pci APIs
 839  */
 840 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt, const char
 841                                                          *edac_pci_name);
 842
 843 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 844
 845 extern void
 846 edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, unsigned long value);
 847
 848 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 849 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 850
 851 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev, const char
 852                                                              *mod_name);
 853
 854 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 855 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 856 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 857
 858 /*
 859  * edac misc APIs
 860  */
 861 extern char *edac_op_state_toString(int op_state);
 862
 863 #endif                          /* _EDAC_CORE_H_ */