drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35
  36 #define EDAC_MC_LABEL_LEN       31
  37 #define MC_PROC_NAME_MAX_LEN 7
  38
  39 #if PAGE_SHIFT < 20
  40 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  41 #else                           /* PAGE_SHIFT > 20 */
  42 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  43 #endif
  44
  45 #define edac_printk(level, prefix, fmt, arg...) \
  46         printk(level "EDAC " prefix ": " fmt, ##arg)
  47
  48 #define edac_mc_printk(mci, level, fmt, arg...) \
  49         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  50
  51 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  52         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  53
  54 /* prefixes for edac_printk() and edac_mc_printk() */
  55 #define EDAC_MC "MC"
  56 #define EDAC_PCI "PCI"
  57 #define EDAC_DEBUG "DEBUG"
  58
  59 #ifdef CONFIG_EDAC_DEBUG
  60 extern int edac_debug_level;
  61
  62 #define edac_debug_printk(level, fmt, arg...)                            \
  63         do {                                                             \
  64                 if (level <= edac_debug_level)                           \
  65                         edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
  66         } while(0)
  67
  68 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  69 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  70 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  71 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  72 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  73
  74 #else  /* !CONFIG_EDAC_DEBUG */
  75
  76 #define debugf0( ... )
  77 #define debugf1( ... )
  78 #define debugf2( ... )
  79 #define debugf3( ... )
  80 #define debugf4( ... )
  81
  82 #endif  /* !CONFIG_EDAC_DEBUG */
  83
  84 #define BIT(x) (1 << (x))
  85
  86 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  87         PCI_DEVICE_ID_ ## vend ## _ ## dev
  88
  89 #if defined(CONFIG_X86) && defined(CONFIG_PCI)
  90 #define dev_name(dev) pci_name(to_pci_dev(dev))
  91 #else
  92 #define dev_name(dev) to_platform_device(dev)->name
  93 #endif
  94
  95 /* memory devices */
  96 enum dev_type {
  97         DEV_UNKNOWN = 0,
  98         DEV_X1,
  99         DEV_X2,
 100         DEV_X4,
 101         DEV_X8,
 102         DEV_X16,
 103         DEV_X32,                /* Do these parts exist? */
 104         DEV_X64                 /* Do these parts exist? */
 105 };
 106
 107 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 108 #define DEV_FLAG_X1             BIT(DEV_X1)
 109 #define DEV_FLAG_X2             BIT(DEV_X2)
 110 #define DEV_FLAG_X4             BIT(DEV_X4)
 111 #define DEV_FLAG_X8             BIT(DEV_X8)
 112 #define DEV_FLAG_X16            BIT(DEV_X16)
 113 #define DEV_FLAG_X32            BIT(DEV_X32)
 114 #define DEV_FLAG_X64            BIT(DEV_X64)
 115
 116 /* memory types */
 117 enum mem_type {
 118         MEM_EMPTY = 0,          /* Empty csrow */
 119         MEM_RESERVED,           /* Reserved csrow type */
 120         MEM_UNKNOWN,            /* Unknown csrow type */
 121         MEM_FPM,                /* Fast page mode */
 122         MEM_EDO,                /* Extended data out */
 123         MEM_BEDO,               /* Burst Extended data out */
 124         MEM_SDR,                /* Single data rate SDRAM */
 125         MEM_RDR,                /* Registered single data rate SDRAM */
 126         MEM_DDR,                /* Double data rate SDRAM */
 127         MEM_RDDR,               /* Registered Double data rate SDRAM */
 128         MEM_RMBS,               /* Rambus DRAM */
 129         MEM_DDR2,               /* DDR2 RAM */
 130         MEM_FB_DDR2,            /* fully buffered DDR2 */
 131         MEM_RDDR2,              /* Registered DDR2 RAM */
 132 };
 133
 134 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 135 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 136 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 137 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 138 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 139 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 140 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 141 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 142 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 143 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 144 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 145 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 146 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 147 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 148
 149 /* chipset Error Detection and Correction capabilities and mode */
 150 enum edac_type {
 151         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 152         EDAC_NONE,              /* Doesnt support ECC */
 153         EDAC_RESERVED,          /* Reserved ECC type */
 154         EDAC_PARITY,            /* Detects parity errors */
 155         EDAC_EC,                /* Error Checking - no correction */
 156         EDAC_SECDED,            /* Single bit error correction, Double detection */
 157         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 158         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 159         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 160         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 161 };
 162
 163 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 164 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 165 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 166 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 167 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 168 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 169 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 170 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 171 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 172
 173 /* scrubbing capabilities */
 174 enum scrub_type {
 175         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 176         SCRUB_NONE,             /* No scrubber */
 177         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 178         SCRUB_SW_SRC,           /* Software scrub only errors */
 179         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 180         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 181         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 182         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 183         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 184         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 185 };
 186
 187 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 188 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC_CORR)
 189 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC_CORR)
 190 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 191 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 192 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC_CORR)
 193 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC_CORR)
 194 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 195
 196 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 197
 198 /*
 199  * There are several things to be aware of that aren't at all obvious:
 200  *
 201  *
 202  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 203  *
 204  * These are some of the many terms that are thrown about that don't always
 205  * mean what people think they mean (Inconceivable!).  In the interest of
 206  * creating a common ground for discussion, terms and their definitions
 207  * will be established.
 208  *
 209  * Memory devices:      The individual chip on a memory stick.  These devices
 210  *                      commonly output 4 and 8 bits each.  Grouping several
 211  *                      of these in parallel provides 64 bits which is common
 212  *                      for a memory stick.
 213  *
 214  * Memory Stick:        A printed circuit board that agregates multiple
 215  *                      memory devices in parallel.  This is the atomic
 216  *                      memory component that is purchaseable by Joe consumer
 217  *                      and loaded into a memory socket.
 218  *
 219  * Socket:              A physical connector on the motherboard that accepts
 220  *                      a single memory stick.
 221  *
 222  * Channel:             Set of memory devices on a memory stick that must be
 223  *                      grouped in parallel with one or more additional
 224  *                      channels from other memory sticks.  This parallel
 225  *                      grouping of the output from multiple channels are
 226  *                      necessary for the smallest granularity of memory access.
 227  *                      Some memory controllers are capable of single channel -
 228  *                      which means that memory sticks can be loaded
 229  *                      individually.  Other memory controllers are only
 230  *                      capable of dual channel - which means that memory
 231  *                      sticks must be loaded as pairs (see "socket set").
 232  *
 233  * Chip-select row:     All of the memory devices that are selected together.
 234  *                      for a single, minimum grain of memory access.
 235  *                      This selects all of the parallel memory devices across
 236  *                      all of the parallel channels.  Common chip-select rows
 237  *                      for single channel are 64 bits, for dual channel 128
 238  *                      bits.
 239  *
 240  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 241  *                      Motherboards commonly drive two chip-select pins to
 242  *                      a memory stick. A single-ranked stick, will occupy
 243  *                      only one of those rows. The other will be unused.
 244  *
 245  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 246  *                      access different sets of memory devices.  The two
 247  *                      rows cannot be accessed concurrently.
 248  *
 249  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 250  *                      A double-sided stick has two chip-select rows which
 251  *                      access different sets of memory devices.  The two
 252  *                      rows cannot be accessed concurrently.  "Double-sided"
 253  *                      is irrespective of the memory devices being mounted
 254  *                      on both sides of the memory stick.
 255  *
 256  * Socket set:          All of the memory sticks that are required for for
 257  *                      a single memory access or all of the memory sticks
 258  *                      spanned by a chip-select row.  A single socket set
 259  *                      has two chip-select rows and if double-sided sticks
 260  *                      are used these will occupy those chip-select rows.
 261  *
 262  * Bank:                This term is avoided because it is unclear when
 263  *                      needing to distinguish between chip-select rows and
 264  *                      socket sets.
 265  *
 266  * Controller pages:
 267  *
 268  * Physical pages:
 269  *
 270  * Virtual pages:
 271  *
 272  *
 273  * STRUCTURE ORGANIZATION AND CHOICES
 274  *
 275  *
 276  *
 277  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 278  */
 279
 280 struct channel_info {
 281         int chan_idx;           /* channel index */
 282         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 283         char label[EDAC_MC_LABEL_LEN + 1];  /* DIMM label on motherboard */
 284         struct csrow_info *csrow;       /* the parent */
 285 };
 286
 287 struct csrow_info {
 288         unsigned long first_page;       /* first page number in dimm */
 289         unsigned long last_page;        /* last page number in dimm */
 290         unsigned long page_mask;        /* used for interleaving -
 291                                          * 0UL for non intlv
 292                                          */
 293         u32 nr_pages;           /* number of pages in csrow */
 294         u32 grain;              /* granularity of reported error in bytes */
 295         int csrow_idx;          /* the chip-select row */
 296         enum dev_type dtype;    /* memory device type */
 297         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 298         u32 ce_count;           /* Correctable Errors for this csrow */
 299         enum mem_type mtype;    /* memory csrow type */
 300         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 301         struct mem_ctl_info *mci;       /* the parent */
 302
 303         struct kobject kobj;    /* sysfs kobject for this csrow */
 304         struct completion kobj_complete;
 305
 306         /* FIXME the number of CHANNELs might need to become dynamic */
 307         u32 nr_channels;
 308         struct channel_info *channels;
 309 };
 310
 311 struct mem_ctl_info {
 312         struct list_head link;  /* for global list of mem_ctl_info structs */
 313         unsigned long mtype_cap;        /* memory types supported by mc */
 314         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 315         unsigned long edac_cap; /* configuration capabilities - this is
 316                                  * closely related to edac_ctl_cap.  The
 317                                  * difference is that the controller may be
 318                                  * capable of s4ecd4ed which would be listed
 319                                  * in edac_ctl_cap, but if channels aren't
 320                                  * capable of s4ecd4ed then the edac_cap would
 321                                  * not have that capability.
 322                                  */
 323         unsigned long scrub_cap;        /* chipset scrub capabilities */
 324         enum scrub_type scrub_mode;     /* current scrub mode */
 325
 326         /* Translates sdram memory scrub rate given in bytes/sec to the
 327            internal representation and configures whatever else needs
 328            to be configured.
 329         */
 330         int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 331
 332         /* Get the current sdram memory scrub rate from the internal
 333            representation and converts it to the closest matching
 334            bandwith in bytes/sec.
 335         */
 336         int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 337
 338         /* pointer to edac checking routine */
 339         void (*edac_check) (struct mem_ctl_info * mci);
 340
 341         /*
 342          * Remaps memory pages: controller pages to physical pages.
 343          * For most MC's, this will be NULL.
 344          */
 345         /* FIXME - why not send the phys page to begin with? */
 346         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 347                                         unsigned long page);
 348         int mc_idx;
 349         int nr_csrows;
 350         struct csrow_info *csrows;
 351         /*
 352          * FIXME - what about controllers on other busses? - IDs must be
 353          * unique.  dev pointer should be sufficiently unique, but
 354          * BUS:SLOT.FUNC numbers may not be unique.
 355          */
 356         struct device *dev;
 357         const char *mod_name;
 358         const char *mod_ver;
 359         const char *ctl_name;
 360         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 361         void *pvt_info;
 362         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 363         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 364         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 365         u32 ce_count;           /* Total Correctable Errors for this MC */
 366         unsigned long start_time;       /* mci load start time (in jiffies) */
 367
 368         /* this stuff is for safe removal of mc devices from global list while
 369          * NMI handlers may be traversing list
 370          */
 371         struct rcu_head rcu;
 372         struct completion complete;
 373
 374         /* edac sysfs device control */
 375         struct kobject edac_mci_kobj;
 376         struct completion kobj_complete;
 377 };
 378
 379 #ifdef CONFIG_PCI
 380
 381 /* write all or some bits in a byte-register*/
 382 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 383                 u8 mask)
 384 {
 385         if (mask != 0xff) {
 386                 u8 buf;
 387
 388                 pci_read_config_byte(pdev, offset, &buf);
 389                 value &= mask;
 390                 buf &= ~mask;
 391                 value |= buf;
 392         }
 393
 394         pci_write_config_byte(pdev, offset, value);
 395 }
 396
 397 /* write all or some bits in a word-register*/
 398 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 399                 u16 value, u16 mask)
 400 {
 401         if (mask != 0xffff) {
 402                 u16 buf;
 403
 404                 pci_read_config_word(pdev, offset, &buf);
 405                 value &= mask;
 406                 buf &= ~mask;
 407                 value |= buf;
 408         }
 409
 410         pci_write_config_word(pdev, offset, value);
 411 }
 412
 413 /* write all or some bits in a dword-register*/
 414 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 415                 u32 value, u32 mask)
 416 {
 417         if (mask != 0xffff) {
 418                 u32 buf;
 419
 420                 pci_read_config_dword(pdev, offset, &buf);
 421                 value &= mask;
 422                 buf &= ~mask;
 423                 value |= buf;
 424         }
 425
 426         pci_write_config_dword(pdev, offset, value);
 427 }
 428
 429 #endif /* CONFIG_PCI */
 430
 431 extern struct mem_ctl_info * edac_mc_find(int idx);
 432 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
 433 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
 434 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 435                                         unsigned long page);
 436
 437 /*
 438  * The no info errors are used when error overflows are reported.
 439  * There are a limited number of error logging registers that can
 440  * be exausted.  When all registers are exhausted and an additional
 441  * error occurs then an error overflow register records that an
 442  * error occured and the type of error, but doesn't have any
 443  * further information.  The ce/ue versions make for cleaner
 444  * reporting logic and function interface - reduces conditional
 445  * statement clutter and extra function arguments.
 446  */
 447 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 448                 unsigned long page_frame_number, unsigned long offset_in_page,
 449                 unsigned long syndrome, int row, int channel,
 450                 const char *msg);
 451 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 452                 const char *msg);
 453 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 454                 unsigned long page_frame_number, unsigned long offset_in_page,
 455                 int row, const char *msg);
 456 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 457                 const char *msg);
 458 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci,
 459                 unsigned int csrow,
 460                 unsigned int channel0,
 461                 unsigned int channel1,
 462                 char *msg);
 463 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci,
 464                 unsigned int csrow,
 465                 unsigned int channel,
 466                 char *msg);
 467
 468 /*
 469  * This kmalloc's and initializes all the structures.
 470  * Can't be used if all structures don't have the same lifetime.
 471  */
 472 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 473                 unsigned nr_chans);
 474
 475 /* Free an mc previously allocated by edac_mc_alloc() */
 476 extern void edac_mc_free(struct mem_ctl_info *mci);
 477
 478 #endif                          /* _EDAC_CORE_H_ */