drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/version.h>
  38
  39 #define EDAC_MC_LABEL_LEN       31
  40 #define EDAC_DEVICE_NAME_LEN    31
  41 #define EDAC_ATTRIB_VALUE_LEN   15
  42 #define MC_PROC_NAME_MAX_LEN    7
  43
  44 #if PAGE_SHIFT < 20
  45 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  46 #else                           /* PAGE_SHIFT > 20 */
  47 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  48 #endif
  49
  50 #define edac_printk(level, prefix, fmt, arg...) \
  51         printk(level "EDAC " prefix ": " fmt, ##arg)
  52
  53 #define edac_mc_printk(mci, level, fmt, arg...) \
  54         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  55
  56 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  57         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 /* edac_device printk */
  60 #define edac_device_printk(ctl, level, fmt, arg...) \
  61         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  62
  63 /* edac_pci printk */
  64 #define edac_pci_printk(ctl, level, fmt, arg...) \
  65         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  66
  67 /* prefixes for edac_printk() and edac_mc_printk() */
  68 #define EDAC_MC "MC"
  69 #define EDAC_PCI "PCI"
  70 #define EDAC_DEBUG "DEBUG"
  71
  72 #ifdef CONFIG_EDAC_DEBUG
  73 extern int edac_debug_level;
  74
  75 #define edac_debug_printk(level, fmt, arg...)                            \
  76         do {                                                             \
  77                 if (level <= edac_debug_level)                           \
  78                         edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
  79         } while(0)
  80
  81 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  82 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  83 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  84 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  85 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  86
  87 #else                           /* !CONFIG_EDAC_DEBUG */
  88
  89 #define debugf0( ... )
  90 #define debugf1( ... )
  91 #define debugf2( ... )
  92 #define debugf3( ... )
  93 #define debugf4( ... )
  94
  95 #endif                          /* !CONFIG_EDAC_DEBUG */
  96
  97 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  98         PCI_DEVICE_ID_ ## vend ## _ ## dev
  99
 100 #define dev_name(dev) (dev)->dev_name
 101
 102 /* memory devices */
 103 enum dev_type {
 104         DEV_UNKNOWN = 0,
 105         DEV_X1,
 106         DEV_X2,
 107         DEV_X4,
 108         DEV_X8,
 109         DEV_X16,
 110         DEV_X32,                /* Do these parts exist? */
 111         DEV_X64                 /* Do these parts exist? */
 112 };
 113
 114 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 115 #define DEV_FLAG_X1             BIT(DEV_X1)
 116 #define DEV_FLAG_X2             BIT(DEV_X2)
 117 #define DEV_FLAG_X4             BIT(DEV_X4)
 118 #define DEV_FLAG_X8             BIT(DEV_X8)
 119 #define DEV_FLAG_X16            BIT(DEV_X16)
 120 #define DEV_FLAG_X32            BIT(DEV_X32)
 121 #define DEV_FLAG_X64            BIT(DEV_X64)
 122
 123 /* memory types */
 124 enum mem_type {
 125         MEM_EMPTY = 0,          /* Empty csrow */
 126         MEM_RESERVED,           /* Reserved csrow type */
 127         MEM_UNKNOWN,            /* Unknown csrow type */
 128         MEM_FPM,                /* Fast page mode */
 129         MEM_EDO,                /* Extended data out */
 130         MEM_BEDO,               /* Burst Extended data out */
 131         MEM_SDR,                /* Single data rate SDRAM */
 132         MEM_RDR,                /* Registered single data rate SDRAM */
 133         MEM_DDR,                /* Double data rate SDRAM */
 134         MEM_RDDR,               /* Registered Double data rate SDRAM */
 135         MEM_RMBS,               /* Rambus DRAM */
 136         MEM_DDR2,               /* DDR2 RAM */
 137         MEM_FB_DDR2,            /* fully buffered DDR2 */
 138         MEM_RDDR2,              /* Registered DDR2 RAM */
 139 };
 140
 141 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 142 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 143 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 144 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 145 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 146 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 147 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 148 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 149 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 150 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 151 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 152 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 153 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 154 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 155
 156 /* chipset Error Detection and Correction capabilities and mode */
 157 enum edac_type {
 158         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 159         EDAC_NONE,              /* Doesnt support ECC */
 160         EDAC_RESERVED,          /* Reserved ECC type */
 161         EDAC_PARITY,            /* Detects parity errors */
 162         EDAC_EC,                /* Error Checking - no correction */
 163         EDAC_SECDED,            /* Single bit error correction, Double detection */
 164         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 165         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 166         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 167         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 168 };
 169
 170 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 171 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 172 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 173 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 174 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 175 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 176 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 177 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 178 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 179
 180 /* scrubbing capabilities */
 181 enum scrub_type {
 182         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 183         SCRUB_NONE,             /* No scrubber */
 184         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 185         SCRUB_SW_SRC,           /* Software scrub only errors */
 186         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 187         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 188         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 189         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 190         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 191         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 192 };
 193
 194 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 195 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 196 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 197 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 198 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 199 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 200 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 201 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 202
 203 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 204
 205 /* EDAC internal operation states */
 206 #define OP_ALLOC                0x100
 207 #define OP_RUNNING_POLL         0x201
 208 #define OP_RUNNING_INTERRUPT    0x202
 209 #define OP_RUNNING_POLL_INTR    0x203
 210 #define OP_OFFLINE              0x300
 211
 212 /*
 213  * There are several things to be aware of that aren't at all obvious:
 214  *
 215  *
 216  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 217  *
 218  * These are some of the many terms that are thrown about that don't always
 219  * mean what people think they mean (Inconceivable!).  In the interest of
 220  * creating a common ground for discussion, terms and their definitions
 221  * will be established.
 222  *
 223  * Memory devices:      The individual chip on a memory stick.  These devices
 224  *                      commonly output 4 and 8 bits each.  Grouping several
 225  *                      of these in parallel provides 64 bits which is common
 226  *                      for a memory stick.
 227  *
 228  * Memory Stick:        A printed circuit board that agregates multiple
 229  *                      memory devices in parallel.  This is the atomic
 230  *                      memory component that is purchaseable by Joe consumer
 231  *                      and loaded into a memory socket.
 232  *
 233  * Socket:              A physical connector on the motherboard that accepts
 234  *                      a single memory stick.
 235  *
 236  * Channel:             Set of memory devices on a memory stick that must be
 237  *                      grouped in parallel with one or more additional
 238  *                      channels from other memory sticks.  This parallel
 239  *                      grouping of the output from multiple channels are
 240  *                      necessary for the smallest granularity of memory access.
 241  *                      Some memory controllers are capable of single channel -
 242  *                      which means that memory sticks can be loaded
 243  *                      individually.  Other memory controllers are only
 244  *                      capable of dual channel - which means that memory
 245  *                      sticks must be loaded as pairs (see "socket set").
 246  *
 247  * Chip-select row:     All of the memory devices that are selected together.
 248  *                      for a single, minimum grain of memory access.
 249  *                      This selects all of the parallel memory devices across
 250  *                      all of the parallel channels.  Common chip-select rows
 251  *                      for single channel are 64 bits, for dual channel 128
 252  *                      bits.
 253  *
 254  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 255  *                      Motherboards commonly drive two chip-select pins to
 256  *                      a memory stick. A single-ranked stick, will occupy
 257  *                      only one of those rows. The other will be unused.
 258  *
 259  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 260  *                      access different sets of memory devices.  The two
 261  *                      rows cannot be accessed concurrently.
 262  *
 263  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 264  *                      A double-sided stick has two chip-select rows which
 265  *                      access different sets of memory devices.  The two
 266  *                      rows cannot be accessed concurrently.  "Double-sided"
 267  *                      is irrespective of the memory devices being mounted
 268  *                      on both sides of the memory stick.
 269  *
 270  * Socket set:          All of the memory sticks that are required for for
 271  *                      a single memory access or all of the memory sticks
 272  *                      spanned by a chip-select row.  A single socket set
 273  *                      has two chip-select rows and if double-sided sticks
 274  *                      are used these will occupy those chip-select rows.
 275  *
 276  * Bank:                This term is avoided because it is unclear when
 277  *                      needing to distinguish between chip-select rows and
 278  *                      socket sets.
 279  *
 280  * Controller pages:
 281  *
 282  * Physical pages:
 283  *
 284  * Virtual pages:
 285  *
 286  *
 287  * STRUCTURE ORGANIZATION AND CHOICES
 288  *
 289  *
 290  *
 291  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 292  */
 293
 294 struct channel_info {
 295         int chan_idx;           /* channel index */
 296         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 297         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 298         struct csrow_info *csrow;       /* the parent */
 299 };
 300
 301 struct csrow_info {
 302         unsigned long first_page;       /* first page number in dimm */
 303         unsigned long last_page;        /* last page number in dimm */
 304         unsigned long page_mask;        /* used for interleaving -
 305                                          * 0UL for non intlv
 306                                          */
 307         u32 nr_pages;           /* number of pages in csrow */
 308         u32 grain;              /* granularity of reported error in bytes */
 309         int csrow_idx;          /* the chip-select row */
 310         enum dev_type dtype;    /* memory device type */
 311         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 312         u32 ce_count;           /* Correctable Errors for this csrow */
 313         enum mem_type mtype;    /* memory csrow type */
 314         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 315         struct mem_ctl_info *mci;       /* the parent */
 316
 317         struct kobject kobj;    /* sysfs kobject for this csrow */
 318
 319         /* channel information for this csrow */
 320         u32 nr_channels;
 321         struct channel_info *channels;
 322 };
 323
 324 /* mcidev_sysfs_attribute structure
 325  *      used for driver sysfs attributes and in mem_ctl_info
 326  *      sysfs top level entries
 327  */
 328 struct mcidev_sysfs_attribute {
 329         struct attribute attr;
 330         ssize_t (*show)(struct mem_ctl_info *,char *);
 331         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 332 };
 333
 334 /* MEMORY controller information structure
 335  */
 336 struct mem_ctl_info {
 337         struct list_head link;  /* for global list of mem_ctl_info structs */
 338
 339         struct module *owner;   /* Module owner of this control struct */
 340
 341         unsigned long mtype_cap;        /* memory types supported by mc */
 342         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 343         unsigned long edac_cap; /* configuration capabilities - this is
 344                                  * closely related to edac_ctl_cap.  The
 345                                  * difference is that the controller may be
 346                                  * capable of s4ecd4ed which would be listed
 347                                  * in edac_ctl_cap, but if channels aren't
 348                                  * capable of s4ecd4ed then the edac_cap would
 349                                  * not have that capability.
 350                                  */
 351         unsigned long scrub_cap;        /* chipset scrub capabilities */
 352         enum scrub_type scrub_mode;     /* current scrub mode */
 353
 354         /* Translates sdram memory scrub rate given in bytes/sec to the
 355            internal representation and configures whatever else needs
 356            to be configured.
 357          */
 358         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 359
 360         /* Get the current sdram memory scrub rate from the internal
 361            representation and converts it to the closest matching
 362            bandwith in bytes/sec.
 363          */
 364         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 365
 366
 367         /* pointer to edac checking routine */
 368         void (*edac_check) (struct mem_ctl_info * mci);
 369
 370         /*
 371          * Remaps memory pages: controller pages to physical pages.
 372          * For most MC's, this will be NULL.
 373          */
 374         /* FIXME - why not send the phys page to begin with? */
 375         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 376                                            unsigned long page);
 377         int mc_idx;
 378         int nr_csrows;
 379         struct csrow_info *csrows;
 380         /*
 381          * FIXME - what about controllers on other busses? - IDs must be
 382          * unique.  dev pointer should be sufficiently unique, but
 383          * BUS:SLOT.FUNC numbers may not be unique.
 384          */
 385         struct device *dev;
 386         const char *mod_name;
 387         const char *mod_ver;
 388         const char *ctl_name;
 389         const char *dev_name;
 390         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 391         void *pvt_info;
 392         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 393         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 394         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 395         u32 ce_count;           /* Total Correctable Errors for this MC */
 396         unsigned long start_time;       /* mci load start time (in jiffies) */
 397
 398         /* this stuff is for safe removal of mc devices from global list while
 399          * NMI handlers may be traversing list
 400          */
 401         struct rcu_head rcu;
 402         struct completion complete;
 403
 404         /* edac sysfs device control */
 405         struct kobject edac_mci_kobj;
 406
 407         /* Additional top controller level attributes, but specified
 408          * by the low level driver.
 409          *
 410          * Set by the low level driver to provide attributes at the
 411          * controller level, same level as 'ue_count' and 'ce_count' above.
 412          * An array of structures, NULL terminated
 413          *
 414          * If attributes are desired, then set to array of attributes
 415          * If no attributes are desired, leave NULL
 416          */
 417         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 418
 419         /* work struct for this MC */
 420         struct delayed_work work;
 421
 422         /* the internal state of this controller instance */
 423         int op_state;
 424 };
 425
 426 /*
 427  * The following are the structures to provide for a generic
 428  * or abstract 'edac_device'. This set of structures and the
 429  * code that implements the APIs for the same, provide for
 430  * registering EDAC type devices which are NOT standard memory.
 431  *
 432  * CPU caches (L1 and L2)
 433  * DMA engines
 434  * Core CPU swithces
 435  * Fabric switch units
 436  * PCIe interface controllers
 437  * other EDAC/ECC type devices that can be monitored for
 438  * errors, etc.
 439  *
 440  * It allows for a 2 level set of hiearchry. For example:
 441  *
 442  * cache could be composed of L1, L2 and L3 levels of cache.
 443  * Each CPU core would have its own L1 cache, while sharing
 444  * L2 and maybe L3 caches.
 445  *
 446  * View them arranged, via the sysfs presentation:
 447  * /sys/devices/system/edac/..
 448  *
 449  *      mc/             <existing memory device directory>
 450  *      cpu/cpu0/..     <L1 and L2 block directory>
 451  *              /L1-cache/ce_count
 452  *                       /ue_count
 453  *              /L2-cache/ce_count
 454  *                       /ue_count
 455  *      cpu/cpu1/..     <L1 and L2 block directory>
 456  *              /L1-cache/ce_count
 457  *                       /ue_count
 458  *              /L2-cache/ce_count
 459  *                       /ue_count
 460  *      ...
 461  *
 462  *      the L1 and L2 directories would be "edac_device_block's"
 463  */
 464
 465 struct edac_device_counter {
 466         u32 ue_count;
 467         u32 ce_count;
 468 };
 469
 470 /* forward reference */
 471 struct edac_device_ctl_info;
 472 struct edac_device_block;
 473
 474 /* edac_dev_sysfs_attribute structure
 475  *      used for driver sysfs attributes in mem_ctl_info
 476  *      for extra controls and attributes:
 477  *              like high level error Injection controls
 478  */
 479 struct edac_dev_sysfs_attribute {
 480         struct attribute attr;
 481         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 482         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 483 };
 484
 485 /* edac_dev_sysfs_block_attribute structure
 486  *
 487  *      used in leaf 'block' nodes for adding controls/attributes
 488  *
 489  *      each block in each instance of the containing control structure
 490  *      can have an array of the following. The show and store functions
 491  *      will be filled in with the show/store function in the
 492  *      low level driver.
 493  *
 494  *      The 'value' field will be the actual value field used for
 495  *      counting
 496  */
 497 struct edac_dev_sysfs_block_attribute {
 498         struct attribute attr;
 499         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 500         ssize_t (*store)(struct kobject *, struct attribute *,
 501                         const char *, size_t);
 502         struct edac_device_block *block;
 503
 504         unsigned int value;
 505 };
 506
 507 /* device block control structure */
 508 struct edac_device_block {
 509         struct edac_device_instance *instance;  /* Up Pointer */
 510         char name[EDAC_DEVICE_NAME_LEN + 1];
 511
 512         struct edac_device_counter counters;    /* basic UE and CE counters */
 513
 514         int nr_attribs;         /* how many attributes */
 515
 516         /* this block's attributes, could be NULL */
 517         struct edac_dev_sysfs_block_attribute *block_attributes;
 518
 519         /* edac sysfs device control */
 520         struct kobject kobj;
 521 };
 522
 523 /* device instance control structure */
 524 struct edac_device_instance {
 525         struct edac_device_ctl_info *ctl;       /* Up pointer */
 526         char name[EDAC_DEVICE_NAME_LEN + 4];
 527
 528         struct edac_device_counter counters;    /* instance counters */
 529
 530         u32 nr_blocks;          /* how many blocks */
 531         struct edac_device_block *blocks;       /* block array */
 532
 533         /* edac sysfs device control */
 534         struct kobject kobj;
 535 };
 536
 537
 538 /*
 539  * Abstract edac_device control info structure
 540  *
 541  */
 542 struct edac_device_ctl_info {
 543         /* for global list of edac_device_ctl_info structs */
 544         struct list_head link;
 545
 546         struct module *owner;   /* Module owner of this control struct */
 547
 548         int dev_idx;
 549
 550         /* Per instance controls for this edac_device */
 551         int log_ue;             /* boolean for logging UEs */
 552         int log_ce;             /* boolean for logging CEs */
 553         int panic_on_ue;        /* boolean for panic'ing on an UE */
 554         unsigned poll_msec;     /* number of milliseconds to poll interval */
 555         unsigned long delay;    /* number of jiffies for poll_msec */
 556
 557         /* Additional top controller level attributes, but specified
 558          * by the low level driver.
 559          *
 560          * Set by the low level driver to provide attributes at the
 561          * controller level, same level as 'ue_count' and 'ce_count' above.
 562          * An array of structures, NULL terminated
 563          *
 564          * If attributes are desired, then set to array of attributes
 565          * If no attributes are desired, leave NULL
 566          */
 567         struct edac_dev_sysfs_attribute *sysfs_attributes;
 568
 569         /* pointer to main 'edac' class in sysfs */
 570         struct sysdev_class *edac_class;
 571
 572         /* the internal state of this controller instance */
 573         int op_state;
 574         /* work struct for this instance */
 575         struct delayed_work work;
 576
 577         /* pointer to edac polling checking routine:
 578          *      If NOT NULL: points to polling check routine
 579          *      If NULL: Then assumes INTERRUPT operation, where
 580          *              MC driver will receive events
 581          */
 582         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 583
 584         struct device *dev;     /* pointer to device structure */
 585
 586         const char *mod_name;   /* module name */
 587         const char *ctl_name;   /* edac controller  name */
 588         const char *dev_name;   /* pci/platform/etc... name */
 589
 590         void *pvt_info;         /* pointer to 'private driver' info */
 591
 592         unsigned long start_time;       /* edac_device load start time (jiffies) */
 593
 594         /* these are for safe removal of mc devices from global list while
 595          * NMI handlers may be traversing list
 596          */
 597         struct rcu_head rcu;
 598         struct completion removal_complete;
 599
 600         /* sysfs top name under 'edac' directory
 601          * and instance name:
 602          *      cpu/cpu0/...
 603          *      cpu/cpu1/...
 604          *      cpu/cpu2/...
 605          *      ...
 606          */
 607         char name[EDAC_DEVICE_NAME_LEN + 1];
 608
 609         /* Number of instances supported on this control structure
 610          * and the array of those instances
 611          */
 612         u32 nr_instances;
 613         struct edac_device_instance *instances;
 614
 615         /* Event counters for the this whole EDAC Device */
 616         struct edac_device_counter counters;
 617
 618         /* edac sysfs device control for the 'name'
 619          * device this structure controls
 620          */
 621         struct kobject kobj;
 622 };
 623
 624 /* To get from the instance's wq to the beginning of the ctl structure */
 625 #define to_edac_mem_ctl_work(w) \
 626                 container_of(w, struct mem_ctl_info, work)
 627
 628 #define to_edac_device_ctl_work(w) \
 629                 container_of(w,struct edac_device_ctl_info,work)
 630
 631 /*
 632  * The alloc() and free() functions for the 'edac_device' control info
 633  * structure. A MC driver will allocate one of these for each edac_device
 634  * it is going to control/register with the EDAC CORE.
 635  */
 636 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 637                 unsigned sizeof_private,
 638                 char *edac_device_name, unsigned nr_instances,
 639                 char *edac_block_name, unsigned nr_blocks,
 640                 unsigned offset_value,
 641                 struct edac_dev_sysfs_block_attribute *block_attributes,
 642                 unsigned nr_attribs,
 643                 int device_index);
 644
 645 /* The offset value can be:
 646  *      -1 indicating no offset value
 647  *      0 for zero-based block numbers
 648  *      1 for 1-based block number
 649  *      other for other-based block number
 650  */
 651 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 652
 653 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 654
 655 #ifdef CONFIG_PCI
 656
 657 struct edac_pci_counter {
 658         atomic_t pe_count;
 659         atomic_t npe_count;
 660 };
 661
 662 /*
 663  * Abstract edac_pci control info structure
 664  *
 665  */
 666 struct edac_pci_ctl_info {
 667         /* for global list of edac_pci_ctl_info structs */
 668         struct list_head link;
 669
 670         int pci_idx;
 671
 672         struct sysdev_class *edac_class;        /* pointer to class */
 673
 674         /* the internal state of this controller instance */
 675         int op_state;
 676         /* work struct for this instance */
 677         struct delayed_work work;
 678
 679         /* pointer to edac polling checking routine:
 680          *      If NOT NULL: points to polling check routine
 681          *      If NULL: Then assumes INTERRUPT operation, where
 682          *              MC driver will receive events
 683          */
 684         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 685
 686         struct device *dev;     /* pointer to device structure */
 687
 688         const char *mod_name;   /* module name */
 689         const char *ctl_name;   /* edac controller  name */
 690         const char *dev_name;   /* pci/platform/etc... name */
 691
 692         void *pvt_info;         /* pointer to 'private driver' info */
 693
 694         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 695
 696         /* these are for safe removal of devices from global list while
 697          * NMI handlers may be traversing list
 698          */
 699         struct rcu_head rcu;
 700         struct completion complete;
 701
 702         /* sysfs top name under 'edac' directory
 703          * and instance name:
 704          *      cpu/cpu0/...
 705          *      cpu/cpu1/...
 706          *      cpu/cpu2/...
 707          *      ...
 708          */
 709         char name[EDAC_DEVICE_NAME_LEN + 1];
 710
 711         /* Event counters for the this whole EDAC Device */
 712         struct edac_pci_counter counters;
 713
 714         /* edac sysfs device control for the 'name'
 715          * device this structure controls
 716          */
 717         struct kobject kobj;
 718         struct completion kobj_complete;
 719 };
 720
 721 #define to_edac_pci_ctl_work(w) \
 722                 container_of(w, struct edac_pci_ctl_info,work)
 723
 724 /* write all or some bits in a byte-register*/
 725 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 726                                    u8 mask)
 727 {
 728         if (mask != 0xff) {
 729                 u8 buf;
 730
 731                 pci_read_config_byte(pdev, offset, &buf);
 732                 value &= mask;
 733                 buf &= ~mask;
 734                 value |= buf;
 735         }
 736
 737         pci_write_config_byte(pdev, offset, value);
 738 }
 739
 740 /* write all or some bits in a word-register*/
 741 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 742                                     u16 value, u16 mask)
 743 {
 744         if (mask != 0xffff) {
 745                 u16 buf;
 746
 747                 pci_read_config_word(pdev, offset, &buf);
 748                 value &= mask;
 749                 buf &= ~mask;
 750                 value |= buf;
 751         }
 752
 753         pci_write_config_word(pdev, offset, value);
 754 }
 755
 756 /* write all or some bits in a dword-register*/
 757 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 758                                     u32 value, u32 mask)
 759 {
 760         if (mask != 0xffff) {
 761                 u32 buf;
 762
 763                 pci_read_config_dword(pdev, offset, &buf);
 764                 value &= mask;
 765                 buf &= ~mask;
 766                 value |= buf;
 767         }
 768
 769         pci_write_config_dword(pdev, offset, value);
 770 }
 771
 772 #endif                          /* CONFIG_PCI */
 773
 774 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 775                                           unsigned nr_chans, int edac_index);
 776 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 777 extern void edac_mc_free(struct mem_ctl_info *mci);
 778 extern struct mem_ctl_info *edac_mc_find(int idx);
 779 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 780 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 781                                       unsigned long page);
 782
 783 /*
 784  * The no info errors are used when error overflows are reported.
 785  * There are a limited number of error logging registers that can
 786  * be exausted.  When all registers are exhausted and an additional
 787  * error occurs then an error overflow register records that an
 788  * error occured and the type of error, but doesn't have any
 789  * further information.  The ce/ue versions make for cleaner
 790  * reporting logic and function interface - reduces conditional
 791  * statement clutter and extra function arguments.
 792  */
 793 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 794                               unsigned long page_frame_number,
 795                               unsigned long offset_in_page,
 796                               unsigned long syndrome, int row, int channel,
 797                               const char *msg);
 798 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 799                                       const char *msg);
 800 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 801                               unsigned long page_frame_number,
 802                               unsigned long offset_in_page, int row,
 803                               const char *msg);
 804 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 805                                       const char *msg);
 806 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 807                                   unsigned int channel0, unsigned int channel1,
 808                                   char *msg);
 809 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 810                                   unsigned int channel, char *msg);
 811
 812 /*
 813  * edac_device APIs
 814  */
 815 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 816 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 817 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 818                                 int inst_nr, int block_nr, const char *msg);
 819 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 820                                 int inst_nr, int block_nr, const char *msg);
 821
 822 /*
 823  * edac_pci APIs
 824  */
 825 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 826                                 const char *edac_pci_name);
 827
 828 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 829
 830 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 831                                 unsigned long value);
 832
 833 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 834 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 835
 836 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 837                                 struct device *dev,
 838                                 const char *mod_name);
 839
 840 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 841 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 842 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 843
 844 /*
 845  * edac misc APIs
 846  */
 847 extern char *edac_op_state_to_string(int op_state);
 848
 849 #endif                          /* _EDAC_CORE_H_ */