2 * timb_dma.c timberdale FPGA DMA driver
3 * Copyright (c) 2010 Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * Timberdale FPGA DMA engine
23 #include <linux/dmaengine.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
32 #include <linux/timb_dma.h>
34 #include "dmaengine.h"
36 #define DRIVER_NAME "timb-dma"
38 /* Global DMA registers */
39 #define TIMBDMA_ACR 0x34
40 #define TIMBDMA_32BIT_ADDR 0x01
42 #define TIMBDMA_ISR 0x080000
43 #define TIMBDMA_IPR 0x080004
44 #define TIMBDMA_IER 0x080008
46 /* Channel specific registers */
47 /* RX instances base addresses are 0x00, 0x40, 0x80 ...
48 * TX instances base addresses are 0x18, 0x58, 0x98 ...
50 #define TIMBDMA_INSTANCE_OFFSET 0x40
51 #define TIMBDMA_INSTANCE_TX_OFFSET 0x18
53 /* RX registers, relative the instance base */
54 #define TIMBDMA_OFFS_RX_DHAR 0x00
55 #define TIMBDMA_OFFS_RX_DLAR 0x04
56 #define TIMBDMA_OFFS_RX_LR 0x0C
57 #define TIMBDMA_OFFS_RX_BLR 0x10
58 #define TIMBDMA_OFFS_RX_ER 0x14
59 #define TIMBDMA_RX_EN 0x01
60 /* bytes per Row, video specific register
61 * which is placed after the TX registers...
63 #define TIMBDMA_OFFS_RX_BPRR 0x30
65 /* TX registers, relative the instance base */
66 #define TIMBDMA_OFFS_TX_DHAR 0x00
67 #define TIMBDMA_OFFS_TX_DLAR 0x04
68 #define TIMBDMA_OFFS_TX_BLR 0x0C
69 #define TIMBDMA_OFFS_TX_LR 0x14
72 #define TIMB_DMA_DESC_SIZE 8
74 struct timb_dma_desc
{
75 struct list_head desc_node
;
76 struct dma_async_tx_descriptor txd
;
78 unsigned int desc_list_len
;
82 struct timb_dma_chan
{
84 void __iomem
*membase
;
85 spinlock_t lock
; /* Used to protect data structures,
86 especially the lists and descriptors,
87 from races between the tasklet and calls
90 struct list_head active_list
;
91 struct list_head queue
;
92 struct list_head free_list
;
93 unsigned int bytes_per_line
;
94 enum dma_transfer_direction direction
;
95 unsigned int descs
; /* Descriptors to allocate */
96 unsigned int desc_elems
; /* number of elems per descriptor */
100 struct dma_device dma
;
101 void __iomem
*membase
;
102 struct tasklet_struct tasklet
;
103 struct timb_dma_chan channels
[0];
106 static struct device
*chan2dev(struct dma_chan
*chan
)
108 return &chan
->dev
->device
;
110 static struct device
*chan2dmadev(struct dma_chan
*chan
)
112 return chan2dev(chan
)->parent
->parent
;
115 static struct timb_dma
*tdchantotd(struct timb_dma_chan
*td_chan
)
117 int id
= td_chan
->chan
.chan_id
;
118 return (struct timb_dma
*)((u8
*)td_chan
-
119 id
* sizeof(struct timb_dma_chan
) - sizeof(struct timb_dma
));
122 /* Must be called with the spinlock held */
123 static void __td_enable_chan_irq(struct timb_dma_chan
*td_chan
)
125 int id
= td_chan
->chan
.chan_id
;
126 struct timb_dma
*td
= tdchantotd(td_chan
);
129 /* enable interrupt for this channel */
130 ier
= ioread32(td
->membase
+ TIMBDMA_IER
);
132 dev_dbg(chan2dev(&td_chan
->chan
), "Enabling irq: %d, IER: 0x%x\n", id
,
134 iowrite32(ier
, td
->membase
+ TIMBDMA_IER
);
137 /* Should be called with the spinlock held */
138 static bool __td_dma_done_ack(struct timb_dma_chan
*td_chan
)
140 int id
= td_chan
->chan
.chan_id
;
141 struct timb_dma
*td
= (struct timb_dma
*)((u8
*)td_chan
-
142 id
* sizeof(struct timb_dma_chan
) - sizeof(struct timb_dma
));
146 dev_dbg(chan2dev(&td_chan
->chan
), "Checking irq: %d, td: %p\n", id
, td
);
148 isr
= ioread32(td
->membase
+ TIMBDMA_ISR
) & (1 << id
);
150 iowrite32(isr
, td
->membase
+ TIMBDMA_ISR
);
157 static void __td_unmap_desc(struct timb_dma_chan
*td_chan
, const u8
*dma_desc
,
163 addr
= (dma_desc
[7] << 24) | (dma_desc
[6] << 16) | (dma_desc
[5] << 8) |
166 len
= (dma_desc
[3] << 8) | dma_desc
[2];
169 dma_unmap_single(chan2dev(&td_chan
->chan
), addr
, len
,
172 dma_unmap_page(chan2dev(&td_chan
->chan
), addr
, len
,
176 static void __td_unmap_descs(struct timb_dma_desc
*td_desc
, bool single
)
178 struct timb_dma_chan
*td_chan
= container_of(td_desc
->txd
.chan
,
179 struct timb_dma_chan
, chan
);
182 for (descs
= td_desc
->desc_list
; ; descs
+= TIMB_DMA_DESC_SIZE
) {
183 __td_unmap_desc(td_chan
, descs
, single
);
189 static int td_fill_desc(struct timb_dma_chan
*td_chan
, u8
*dma_desc
,
190 struct scatterlist
*sg
, bool last
)
192 if (sg_dma_len(sg
) > USHRT_MAX
) {
193 dev_err(chan2dev(&td_chan
->chan
), "Too big sg element\n");
197 /* length must be word aligned */
198 if (sg_dma_len(sg
) % sizeof(u32
)) {
199 dev_err(chan2dev(&td_chan
->chan
), "Incorrect length: %d\n",
204 dev_dbg(chan2dev(&td_chan
->chan
), "desc: %p, addr: 0x%llx\n",
205 dma_desc
, (unsigned long long)sg_dma_address(sg
));
207 dma_desc
[7] = (sg_dma_address(sg
) >> 24) & 0xff;
208 dma_desc
[6] = (sg_dma_address(sg
) >> 16) & 0xff;
209 dma_desc
[5] = (sg_dma_address(sg
) >> 8) & 0xff;
210 dma_desc
[4] = (sg_dma_address(sg
) >> 0) & 0xff;
212 dma_desc
[3] = (sg_dma_len(sg
) >> 8) & 0xff;
213 dma_desc
[2] = (sg_dma_len(sg
) >> 0) & 0xff;
216 dma_desc
[0] = 0x21 | (last
? 0x02 : 0); /* tran, valid */
221 /* Must be called with the spinlock held */
222 static void __td_start_dma(struct timb_dma_chan
*td_chan
)
224 struct timb_dma_desc
*td_desc
;
226 if (td_chan
->ongoing
) {
227 dev_err(chan2dev(&td_chan
->chan
),
228 "Transfer already ongoing\n");
232 td_desc
= list_entry(td_chan
->active_list
.next
, struct timb_dma_desc
,
235 dev_dbg(chan2dev(&td_chan
->chan
),
236 "td_chan: %p, chan: %d, membase: %p\n",
237 td_chan
, td_chan
->chan
.chan_id
, td_chan
->membase
);
239 if (td_chan
->direction
== DMA_DEV_TO_MEM
) {
241 /* descriptor address */
242 iowrite32(0, td_chan
->membase
+ TIMBDMA_OFFS_RX_DHAR
);
243 iowrite32(td_desc
->txd
.phys
, td_chan
->membase
+
244 TIMBDMA_OFFS_RX_DLAR
);
246 iowrite32(td_chan
->bytes_per_line
, td_chan
->membase
+
247 TIMBDMA_OFFS_RX_BPRR
);
249 iowrite32(TIMBDMA_RX_EN
, td_chan
->membase
+ TIMBDMA_OFFS_RX_ER
);
252 iowrite32(0, td_chan
->membase
+ TIMBDMA_OFFS_TX_DHAR
);
253 iowrite32(td_desc
->txd
.phys
, td_chan
->membase
+
254 TIMBDMA_OFFS_TX_DLAR
);
257 td_chan
->ongoing
= true;
259 if (td_desc
->interrupt
)
260 __td_enable_chan_irq(td_chan
);
263 static void __td_finish(struct timb_dma_chan
*td_chan
)
265 dma_async_tx_callback callback
;
267 struct dma_async_tx_descriptor
*txd
;
268 struct timb_dma_desc
*td_desc
;
270 /* can happen if the descriptor is canceled */
271 if (list_empty(&td_chan
->active_list
))
274 td_desc
= list_entry(td_chan
->active_list
.next
, struct timb_dma_desc
,
278 dev_dbg(chan2dev(&td_chan
->chan
), "descriptor %u complete\n",
281 /* make sure to stop the transfer */
282 if (td_chan
->direction
== DMA_DEV_TO_MEM
)
283 iowrite32(0, td_chan
->membase
+ TIMBDMA_OFFS_RX_ER
);
284 /* Currently no support for stopping DMA transfers
286 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
288 dma_cookie_complete(txd
);
289 td_chan
->ongoing
= false;
291 callback
= txd
->callback
;
292 param
= txd
->callback_param
;
294 list_move(&td_desc
->desc_node
, &td_chan
->free_list
);
296 if (!(txd
->flags
& DMA_COMPL_SKIP_SRC_UNMAP
))
297 __td_unmap_descs(td_desc
,
298 txd
->flags
& DMA_COMPL_SRC_UNMAP_SINGLE
);
301 * The API requires that no submissions are done from a
302 * callback, so we don't need to drop the lock here
308 static u32
__td_ier_mask(struct timb_dma
*td
)
313 for (i
= 0; i
< td
->dma
.chancnt
; i
++) {
314 struct timb_dma_chan
*td_chan
= td
->channels
+ i
;
315 if (td_chan
->ongoing
) {
316 struct timb_dma_desc
*td_desc
=
317 list_entry(td_chan
->active_list
.next
,
318 struct timb_dma_desc
, desc_node
);
319 if (td_desc
->interrupt
)
327 static void __td_start_next(struct timb_dma_chan
*td_chan
)
329 struct timb_dma_desc
*td_desc
;
331 BUG_ON(list_empty(&td_chan
->queue
));
332 BUG_ON(td_chan
->ongoing
);
334 td_desc
= list_entry(td_chan
->queue
.next
, struct timb_dma_desc
,
337 dev_dbg(chan2dev(&td_chan
->chan
), "%s: started %u\n",
338 __func__
, td_desc
->txd
.cookie
);
340 list_move(&td_desc
->desc_node
, &td_chan
->active_list
);
341 __td_start_dma(td_chan
);
344 static dma_cookie_t
td_tx_submit(struct dma_async_tx_descriptor
*txd
)
346 struct timb_dma_desc
*td_desc
= container_of(txd
, struct timb_dma_desc
,
348 struct timb_dma_chan
*td_chan
= container_of(txd
->chan
,
349 struct timb_dma_chan
, chan
);
352 spin_lock_bh(&td_chan
->lock
);
353 cookie
= dma_cookie_assign(txd
);
355 if (list_empty(&td_chan
->active_list
)) {
356 dev_dbg(chan2dev(txd
->chan
), "%s: started %u\n", __func__
,
358 list_add_tail(&td_desc
->desc_node
, &td_chan
->active_list
);
359 __td_start_dma(td_chan
);
361 dev_dbg(chan2dev(txd
->chan
), "tx_submit: queued %u\n",
364 list_add_tail(&td_desc
->desc_node
, &td_chan
->queue
);
367 spin_unlock_bh(&td_chan
->lock
);
372 static struct timb_dma_desc
*td_alloc_init_desc(struct timb_dma_chan
*td_chan
)
374 struct dma_chan
*chan
= &td_chan
->chan
;
375 struct timb_dma_desc
*td_desc
;
378 td_desc
= kzalloc(sizeof(struct timb_dma_desc
), GFP_KERNEL
);
380 dev_err(chan2dev(chan
), "Failed to alloc descriptor\n");
384 td_desc
->desc_list_len
= td_chan
->desc_elems
* TIMB_DMA_DESC_SIZE
;
386 td_desc
->desc_list
= kzalloc(td_desc
->desc_list_len
, GFP_KERNEL
);
387 if (!td_desc
->desc_list
) {
388 dev_err(chan2dev(chan
), "Failed to alloc descriptor\n");
392 dma_async_tx_descriptor_init(&td_desc
->txd
, chan
);
393 td_desc
->txd
.tx_submit
= td_tx_submit
;
394 td_desc
->txd
.flags
= DMA_CTRL_ACK
;
396 td_desc
->txd
.phys
= dma_map_single(chan2dmadev(chan
),
397 td_desc
->desc_list
, td_desc
->desc_list_len
, DMA_TO_DEVICE
);
399 err
= dma_mapping_error(chan2dmadev(chan
), td_desc
->txd
.phys
);
401 dev_err(chan2dev(chan
), "DMA mapping error: %d\n", err
);
407 kfree(td_desc
->desc_list
);
414 static void td_free_desc(struct timb_dma_desc
*td_desc
)
416 dev_dbg(chan2dev(td_desc
->txd
.chan
), "Freeing desc: %p\n", td_desc
);
417 dma_unmap_single(chan2dmadev(td_desc
->txd
.chan
), td_desc
->txd
.phys
,
418 td_desc
->desc_list_len
, DMA_TO_DEVICE
);
420 kfree(td_desc
->desc_list
);
424 static void td_desc_put(struct timb_dma_chan
*td_chan
,
425 struct timb_dma_desc
*td_desc
)
427 dev_dbg(chan2dev(&td_chan
->chan
), "Putting desc: %p\n", td_desc
);
429 spin_lock_bh(&td_chan
->lock
);
430 list_add(&td_desc
->desc_node
, &td_chan
->free_list
);
431 spin_unlock_bh(&td_chan
->lock
);
434 static struct timb_dma_desc
*td_desc_get(struct timb_dma_chan
*td_chan
)
436 struct timb_dma_desc
*td_desc
, *_td_desc
;
437 struct timb_dma_desc
*ret
= NULL
;
439 spin_lock_bh(&td_chan
->lock
);
440 list_for_each_entry_safe(td_desc
, _td_desc
, &td_chan
->free_list
,
442 if (async_tx_test_ack(&td_desc
->txd
)) {
443 list_del(&td_desc
->desc_node
);
447 dev_dbg(chan2dev(&td_chan
->chan
), "desc %p not ACKed\n",
450 spin_unlock_bh(&td_chan
->lock
);
455 static int td_alloc_chan_resources(struct dma_chan
*chan
)
457 struct timb_dma_chan
*td_chan
=
458 container_of(chan
, struct timb_dma_chan
, chan
);
461 dev_dbg(chan2dev(chan
), "%s: entry\n", __func__
);
463 BUG_ON(!list_empty(&td_chan
->free_list
));
464 for (i
= 0; i
< td_chan
->descs
; i
++) {
465 struct timb_dma_desc
*td_desc
= td_alloc_init_desc(td_chan
);
470 dev_err(chan2dev(chan
),
471 "Couldnt allocate any descriptors\n");
476 td_desc_put(td_chan
, td_desc
);
479 spin_lock_bh(&td_chan
->lock
);
480 chan
->completed_cookie
= 1;
482 spin_unlock_bh(&td_chan
->lock
);
487 static void td_free_chan_resources(struct dma_chan
*chan
)
489 struct timb_dma_chan
*td_chan
=
490 container_of(chan
, struct timb_dma_chan
, chan
);
491 struct timb_dma_desc
*td_desc
, *_td_desc
;
494 dev_dbg(chan2dev(chan
), "%s: Entry\n", __func__
);
496 /* check that all descriptors are free */
497 BUG_ON(!list_empty(&td_chan
->active_list
));
498 BUG_ON(!list_empty(&td_chan
->queue
));
500 spin_lock_bh(&td_chan
->lock
);
501 list_splice_init(&td_chan
->free_list
, &list
);
502 spin_unlock_bh(&td_chan
->lock
);
504 list_for_each_entry_safe(td_desc
, _td_desc
, &list
, desc_node
) {
505 dev_dbg(chan2dev(chan
), "%s: Freeing desc: %p\n", __func__
,
507 td_free_desc(td_desc
);
511 static enum dma_status
td_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
512 struct dma_tx_state
*txstate
)
514 struct timb_dma_chan
*td_chan
=
515 container_of(chan
, struct timb_dma_chan
, chan
);
516 dma_cookie_t last_used
;
517 dma_cookie_t last_complete
;
520 dev_dbg(chan2dev(chan
), "%s: Entry\n", __func__
);
522 last_complete
= chan
->completed_cookie
;
523 last_used
= chan
->cookie
;
525 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
527 dma_set_tx_state(txstate
, last_complete
, last_used
, 0);
529 dev_dbg(chan2dev(chan
),
530 "%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
531 __func__
, ret
, last_complete
, last_used
);
536 static void td_issue_pending(struct dma_chan
*chan
)
538 struct timb_dma_chan
*td_chan
=
539 container_of(chan
, struct timb_dma_chan
, chan
);
541 dev_dbg(chan2dev(chan
), "%s: Entry\n", __func__
);
542 spin_lock_bh(&td_chan
->lock
);
544 if (!list_empty(&td_chan
->active_list
))
545 /* transfer ongoing */
546 if (__td_dma_done_ack(td_chan
))
547 __td_finish(td_chan
);
549 if (list_empty(&td_chan
->active_list
) && !list_empty(&td_chan
->queue
))
550 __td_start_next(td_chan
);
552 spin_unlock_bh(&td_chan
->lock
);
555 static struct dma_async_tx_descriptor
*td_prep_slave_sg(struct dma_chan
*chan
,
556 struct scatterlist
*sgl
, unsigned int sg_len
,
557 enum dma_transfer_direction direction
, unsigned long flags
)
559 struct timb_dma_chan
*td_chan
=
560 container_of(chan
, struct timb_dma_chan
, chan
);
561 struct timb_dma_desc
*td_desc
;
562 struct scatterlist
*sg
;
564 unsigned int desc_usage
= 0;
566 if (!sgl
|| !sg_len
) {
567 dev_err(chan2dev(chan
), "%s: No SG list\n", __func__
);
571 /* even channels are for RX, odd for TX */
572 if (td_chan
->direction
!= direction
) {
573 dev_err(chan2dev(chan
),
574 "Requesting channel in wrong direction\n");
578 td_desc
= td_desc_get(td_chan
);
580 dev_err(chan2dev(chan
), "Not enough descriptors available\n");
584 td_desc
->interrupt
= (flags
& DMA_PREP_INTERRUPT
) != 0;
586 for_each_sg(sgl
, sg
, sg_len
, i
) {
588 if (desc_usage
> td_desc
->desc_list_len
) {
589 dev_err(chan2dev(chan
), "No descriptor space\n");
593 err
= td_fill_desc(td_chan
, td_desc
->desc_list
+ desc_usage
, sg
,
596 dev_err(chan2dev(chan
), "Failed to update desc: %d\n",
598 td_desc_put(td_chan
, td_desc
);
601 desc_usage
+= TIMB_DMA_DESC_SIZE
;
604 dma_sync_single_for_device(chan2dmadev(chan
), td_desc
->txd
.phys
,
605 td_desc
->desc_list_len
, DMA_MEM_TO_DEV
);
607 return &td_desc
->txd
;
610 static int td_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
613 struct timb_dma_chan
*td_chan
=
614 container_of(chan
, struct timb_dma_chan
, chan
);
615 struct timb_dma_desc
*td_desc
, *_td_desc
;
617 dev_dbg(chan2dev(chan
), "%s: Entry\n", __func__
);
619 if (cmd
!= DMA_TERMINATE_ALL
)
622 /* first the easy part, put the queue into the free list */
623 spin_lock_bh(&td_chan
->lock
);
624 list_for_each_entry_safe(td_desc
, _td_desc
, &td_chan
->queue
,
626 list_move(&td_desc
->desc_node
, &td_chan
->free_list
);
628 /* now tear down the running */
629 __td_finish(td_chan
);
630 spin_unlock_bh(&td_chan
->lock
);
635 static void td_tasklet(unsigned long data
)
637 struct timb_dma
*td
= (struct timb_dma
*)data
;
643 isr
= ioread32(td
->membase
+ TIMBDMA_ISR
);
644 ipr
= isr
& __td_ier_mask(td
);
646 /* ack the interrupts */
647 iowrite32(ipr
, td
->membase
+ TIMBDMA_ISR
);
649 for (i
= 0; i
< td
->dma
.chancnt
; i
++)
650 if (ipr
& (1 << i
)) {
651 struct timb_dma_chan
*td_chan
= td
->channels
+ i
;
652 spin_lock(&td_chan
->lock
);
653 __td_finish(td_chan
);
654 if (!list_empty(&td_chan
->queue
))
655 __td_start_next(td_chan
);
656 spin_unlock(&td_chan
->lock
);
659 ier
= __td_ier_mask(td
);
660 iowrite32(ier
, td
->membase
+ TIMBDMA_IER
);
664 static irqreturn_t
td_irq(int irq
, void *devid
)
666 struct timb_dma
*td
= devid
;
667 u32 ipr
= ioread32(td
->membase
+ TIMBDMA_IPR
);
670 /* disable interrupts, will be re-enabled in tasklet */
671 iowrite32(0, td
->membase
+ TIMBDMA_IER
);
673 tasklet_schedule(&td
->tasklet
);
681 static int __devinit
td_probe(struct platform_device
*pdev
)
683 struct timb_dma_platform_data
*pdata
= pdev
->dev
.platform_data
;
685 struct resource
*iomem
;
691 dev_err(&pdev
->dev
, "No platform data\n");
695 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
699 irq
= platform_get_irq(pdev
, 0);
703 if (!request_mem_region(iomem
->start
, resource_size(iomem
),
707 td
= kzalloc(sizeof(struct timb_dma
) +
708 sizeof(struct timb_dma_chan
) * pdata
->nr_channels
, GFP_KERNEL
);
711 goto err_release_region
;
714 dev_dbg(&pdev
->dev
, "Allocated TD: %p\n", td
);
716 td
->membase
= ioremap(iomem
->start
, resource_size(iomem
));
718 dev_err(&pdev
->dev
, "Failed to remap I/O memory\n");
723 /* 32bit addressing */
724 iowrite32(TIMBDMA_32BIT_ADDR
, td
->membase
+ TIMBDMA_ACR
);
726 /* disable and clear any interrupts */
727 iowrite32(0x0, td
->membase
+ TIMBDMA_IER
);
728 iowrite32(0xFFFFFFFF, td
->membase
+ TIMBDMA_ISR
);
730 tasklet_init(&td
->tasklet
, td_tasklet
, (unsigned long)td
);
732 err
= request_irq(irq
, td_irq
, IRQF_SHARED
, DRIVER_NAME
, td
);
734 dev_err(&pdev
->dev
, "Failed to request IRQ\n");
735 goto err_tasklet_kill
;
738 td
->dma
.device_alloc_chan_resources
= td_alloc_chan_resources
;
739 td
->dma
.device_free_chan_resources
= td_free_chan_resources
;
740 td
->dma
.device_tx_status
= td_tx_status
;
741 td
->dma
.device_issue_pending
= td_issue_pending
;
743 dma_cap_set(DMA_SLAVE
, td
->dma
.cap_mask
);
744 dma_cap_set(DMA_PRIVATE
, td
->dma
.cap_mask
);
745 td
->dma
.device_prep_slave_sg
= td_prep_slave_sg
;
746 td
->dma
.device_control
= td_control
;
748 td
->dma
.dev
= &pdev
->dev
;
750 INIT_LIST_HEAD(&td
->dma
.channels
);
752 for (i
= 0; i
< pdata
->nr_channels
; i
++) {
753 struct timb_dma_chan
*td_chan
= &td
->channels
[i
];
754 struct timb_dma_platform_data_channel
*pchan
=
757 /* even channels are RX, odd are TX */
758 if ((i
% 2) == pchan
->rx
) {
759 dev_err(&pdev
->dev
, "Wrong channel configuration\n");
764 td_chan
->chan
.device
= &td
->dma
;
765 td_chan
->chan
.cookie
= 1;
766 spin_lock_init(&td_chan
->lock
);
767 INIT_LIST_HEAD(&td_chan
->active_list
);
768 INIT_LIST_HEAD(&td_chan
->queue
);
769 INIT_LIST_HEAD(&td_chan
->free_list
);
771 td_chan
->descs
= pchan
->descriptors
;
772 td_chan
->desc_elems
= pchan
->descriptor_elements
;
773 td_chan
->bytes_per_line
= pchan
->bytes_per_line
;
774 td_chan
->direction
= pchan
->rx
? DMA_DEV_TO_MEM
:
777 td_chan
->membase
= td
->membase
+
778 (i
/ 2) * TIMBDMA_INSTANCE_OFFSET
+
779 (pchan
->rx
? 0 : TIMBDMA_INSTANCE_TX_OFFSET
);
781 dev_dbg(&pdev
->dev
, "Chan: %d, membase: %p\n",
782 i
, td_chan
->membase
);
784 list_add_tail(&td_chan
->chan
.device_node
, &td
->dma
.channels
);
787 err
= dma_async_device_register(&td
->dma
);
789 dev_err(&pdev
->dev
, "Failed to register async device\n");
793 platform_set_drvdata(pdev
, td
);
795 dev_dbg(&pdev
->dev
, "Probe result: %d\n", err
);
801 tasklet_kill(&td
->tasklet
);
802 iounmap(td
->membase
);
806 release_mem_region(iomem
->start
, resource_size(iomem
));
812 static int __devexit
td_remove(struct platform_device
*pdev
)
814 struct timb_dma
*td
= platform_get_drvdata(pdev
);
815 struct resource
*iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
816 int irq
= platform_get_irq(pdev
, 0);
818 dma_async_device_unregister(&td
->dma
);
820 tasklet_kill(&td
->tasklet
);
821 iounmap(td
->membase
);
823 release_mem_region(iomem
->start
, resource_size(iomem
));
825 platform_set_drvdata(pdev
, NULL
);
827 dev_dbg(&pdev
->dev
, "Removed...\n");
831 static struct platform_driver td_driver
= {
834 .owner
= THIS_MODULE
,
837 .remove
= __exit_p(td_remove
),
840 module_platform_driver(td_driver
);
842 MODULE_LICENSE("GPL v2");
843 MODULE_DESCRIPTION("Timberdale DMA controller driver");
844 MODULE_AUTHOR("Pelagicore AB <info@pelagicore.com>");
845 MODULE_ALIAS("platform:"DRIVER_NAME
);