2 * Renesas SuperH DMA Engine support
4 * base is drivers/dma/flsdma.c
6 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
9 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * - DMA of SuperH does not have Hardware DMA chain mode.
17 * - MAX DMA size is 16MB.
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/dmaengine.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30 #include <linux/notifier.h>
31 #include <linux/kdebug.h>
32 #include <linux/spinlock.h>
33 #include <linux/rculist.h>
35 #include "../dmaengine.h"
38 #define SH_DMAE_DRV_NAME "sh-dma-engine"
40 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
41 #define LOG2_DEFAULT_XFER_SIZE 2
42 #define SH_DMA_SLAVE_NUMBER 256
43 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
46 * Used for write-side mutual exclusion for the global device list,
47 * read-side synchronization by way of RCU, and per-controller data.
49 static DEFINE_SPINLOCK(sh_dmae_lock
);
50 static LIST_HEAD(sh_dmae_devices
);
52 static void chclr_write(struct sh_dmae_chan
*sh_dc
, u32 data
)
54 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
56 __raw_writel(data
, shdev
->chan_reg
+
57 shdev
->pdata
->channel
[sh_dc
->shdma_chan
.id
].chclr_offset
);
60 static void sh_dmae_writel(struct sh_dmae_chan
*sh_dc
, u32 data
, u32 reg
)
62 __raw_writel(data
, sh_dc
->base
+ reg
/ sizeof(u32
));
65 static u32
sh_dmae_readl(struct sh_dmae_chan
*sh_dc
, u32 reg
)
67 return __raw_readl(sh_dc
->base
+ reg
/ sizeof(u32
));
70 static u16
dmaor_read(struct sh_dmae_device
*shdev
)
72 u32 __iomem
*addr
= shdev
->chan_reg
+ DMAOR
/ sizeof(u32
);
74 if (shdev
->pdata
->dmaor_is_32bit
)
75 return __raw_readl(addr
);
77 return __raw_readw(addr
);
80 static void dmaor_write(struct sh_dmae_device
*shdev
, u16 data
)
82 u32 __iomem
*addr
= shdev
->chan_reg
+ DMAOR
/ sizeof(u32
);
84 if (shdev
->pdata
->dmaor_is_32bit
)
85 __raw_writel(data
, addr
);
87 __raw_writew(data
, addr
);
90 static void chcr_write(struct sh_dmae_chan
*sh_dc
, u32 data
)
92 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
94 __raw_writel(data
, sh_dc
->base
+ shdev
->chcr_offset
/ sizeof(u32
));
97 static u32
chcr_read(struct sh_dmae_chan
*sh_dc
)
99 struct sh_dmae_device
*shdev
= to_sh_dev(sh_dc
);
101 return __raw_readl(sh_dc
->base
+ shdev
->chcr_offset
/ sizeof(u32
));
105 * Reset DMA controller
107 * SH7780 has two DMAOR register
109 static void sh_dmae_ctl_stop(struct sh_dmae_device
*shdev
)
111 unsigned short dmaor
;
114 spin_lock_irqsave(&sh_dmae_lock
, flags
);
116 dmaor
= dmaor_read(shdev
);
117 dmaor_write(shdev
, dmaor
& ~(DMAOR_NMIF
| DMAOR_AE
| DMAOR_DME
));
119 spin_unlock_irqrestore(&sh_dmae_lock
, flags
);
122 static int sh_dmae_rst(struct sh_dmae_device
*shdev
)
124 unsigned short dmaor
;
127 spin_lock_irqsave(&sh_dmae_lock
, flags
);
129 dmaor
= dmaor_read(shdev
) & ~(DMAOR_NMIF
| DMAOR_AE
| DMAOR_DME
);
131 if (shdev
->pdata
->chclr_present
) {
133 for (i
= 0; i
< shdev
->pdata
->channel_num
; i
++) {
134 struct sh_dmae_chan
*sh_chan
= shdev
->chan
[i
];
136 chclr_write(sh_chan
, 0);
140 dmaor_write(shdev
, dmaor
| shdev
->pdata
->dmaor_init
);
142 dmaor
= dmaor_read(shdev
);
144 spin_unlock_irqrestore(&sh_dmae_lock
, flags
);
146 if (dmaor
& (DMAOR_AE
| DMAOR_NMIF
)) {
147 dev_warn(shdev
->shdma_dev
.dma_dev
.dev
, "Can't initialize DMAOR.\n");
150 if (shdev
->pdata
->dmaor_init
& ~dmaor
)
151 dev_warn(shdev
->shdma_dev
.dma_dev
.dev
,
152 "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
153 dmaor
, shdev
->pdata
->dmaor_init
);
157 static bool dmae_is_busy(struct sh_dmae_chan
*sh_chan
)
159 u32 chcr
= chcr_read(sh_chan
);
161 if ((chcr
& (CHCR_DE
| CHCR_TE
)) == CHCR_DE
)
162 return true; /* working */
164 return false; /* waiting */
167 static unsigned int calc_xmit_shift(struct sh_dmae_chan
*sh_chan
, u32 chcr
)
169 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
170 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
171 int cnt
= ((chcr
& pdata
->ts_low_mask
) >> pdata
->ts_low_shift
) |
172 ((chcr
& pdata
->ts_high_mask
) >> pdata
->ts_high_shift
);
174 if (cnt
>= pdata
->ts_shift_num
)
177 return pdata
->ts_shift
[cnt
];
180 static u32
log2size_to_chcr(struct sh_dmae_chan
*sh_chan
, int l2size
)
182 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
183 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
186 for (i
= 0; i
< pdata
->ts_shift_num
; i
++)
187 if (pdata
->ts_shift
[i
] == l2size
)
190 if (i
== pdata
->ts_shift_num
)
193 return ((i
<< pdata
->ts_low_shift
) & pdata
->ts_low_mask
) |
194 ((i
<< pdata
->ts_high_shift
) & pdata
->ts_high_mask
);
197 static void dmae_set_reg(struct sh_dmae_chan
*sh_chan
, struct sh_dmae_regs
*hw
)
199 sh_dmae_writel(sh_chan
, hw
->sar
, SAR
);
200 sh_dmae_writel(sh_chan
, hw
->dar
, DAR
);
201 sh_dmae_writel(sh_chan
, hw
->tcr
>> sh_chan
->xmit_shift
, TCR
);
204 static void dmae_start(struct sh_dmae_chan
*sh_chan
)
206 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
207 u32 chcr
= chcr_read(sh_chan
);
209 if (shdev
->pdata
->needs_tend_set
)
210 sh_dmae_writel(sh_chan
, 0xFFFFFFFF, TEND
);
212 chcr
|= CHCR_DE
| shdev
->chcr_ie_bit
;
213 chcr_write(sh_chan
, chcr
& ~CHCR_TE
);
216 static void dmae_init(struct sh_dmae_chan
*sh_chan
)
219 * Default configuration for dual address memory-memory transfer.
220 * 0x400 represents auto-request.
222 u32 chcr
= DM_INC
| SM_INC
| 0x400 | log2size_to_chcr(sh_chan
,
223 LOG2_DEFAULT_XFER_SIZE
);
224 sh_chan
->xmit_shift
= calc_xmit_shift(sh_chan
, chcr
);
225 chcr_write(sh_chan
, chcr
);
228 static int dmae_set_chcr(struct sh_dmae_chan
*sh_chan
, u32 val
)
230 /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
231 if (dmae_is_busy(sh_chan
))
234 sh_chan
->xmit_shift
= calc_xmit_shift(sh_chan
, val
);
235 chcr_write(sh_chan
, val
);
240 static int dmae_set_dmars(struct sh_dmae_chan
*sh_chan
, u16 val
)
242 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
243 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
244 const struct sh_dmae_channel
*chan_pdata
= &pdata
->channel
[sh_chan
->shdma_chan
.id
];
245 u16 __iomem
*addr
= shdev
->dmars
;
246 unsigned int shift
= chan_pdata
->dmars_bit
;
248 if (dmae_is_busy(sh_chan
))
254 /* in the case of a missing DMARS resource use first memory window */
256 addr
= (u16 __iomem
*)shdev
->chan_reg
;
257 addr
+= chan_pdata
->dmars
/ sizeof(u16
);
259 __raw_writew((__raw_readw(addr
) & (0xff00 >> shift
)) | (val
<< shift
),
265 static void sh_dmae_start_xfer(struct shdma_chan
*schan
,
266 struct shdma_desc
*sdesc
)
268 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
270 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
271 struct sh_dmae_desc
, shdma_desc
);
272 dev_dbg(sh_chan
->shdma_chan
.dev
, "Queue #%d to %d: %u@%x -> %x\n",
273 sdesc
->async_tx
.cookie
, sh_chan
->shdma_chan
.id
,
274 sh_desc
->hw
.tcr
, sh_desc
->hw
.sar
, sh_desc
->hw
.dar
);
275 /* Get the ld start address from ld_queue */
276 dmae_set_reg(sh_chan
, &sh_desc
->hw
);
280 static bool sh_dmae_channel_busy(struct shdma_chan
*schan
)
282 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
284 return dmae_is_busy(sh_chan
);
287 static void sh_dmae_setup_xfer(struct shdma_chan
*schan
,
288 struct shdma_slave
*sslave
)
290 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
294 struct sh_dmae_slave
*slave
= container_of(sslave
,
295 struct sh_dmae_slave
, shdma_slave
);
296 const struct sh_dmae_slave_config
*cfg
=
299 dmae_set_dmars(sh_chan
, cfg
->mid_rid
);
300 dmae_set_chcr(sh_chan
, cfg
->chcr
);
306 static const struct sh_dmae_slave_config
*dmae_find_slave(
307 struct sh_dmae_chan
*sh_chan
, struct sh_dmae_slave
*slave
)
309 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
310 struct sh_dmae_pdata
*pdata
= shdev
->pdata
;
311 const struct sh_dmae_slave_config
*cfg
;
314 if (slave
->shdma_slave
.slave_id
>= SH_DMA_SLAVE_NUMBER
)
317 for (i
= 0, cfg
= pdata
->slave
; i
< pdata
->slave_num
; i
++, cfg
++)
318 if (cfg
->slave_id
== slave
->shdma_slave
.slave_id
)
324 static int sh_dmae_set_slave(struct shdma_chan
*schan
,
325 struct shdma_slave
*sslave
)
327 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
329 struct sh_dmae_slave
*slave
= container_of(sslave
, struct sh_dmae_slave
,
331 const struct sh_dmae_slave_config
*cfg
= dmae_find_slave(sh_chan
, slave
);
340 static void dmae_halt(struct sh_dmae_chan
*sh_chan
)
342 struct sh_dmae_device
*shdev
= to_sh_dev(sh_chan
);
343 u32 chcr
= chcr_read(sh_chan
);
345 chcr
&= ~(CHCR_DE
| CHCR_TE
| shdev
->chcr_ie_bit
);
346 chcr_write(sh_chan
, chcr
);
349 static int sh_dmae_desc_setup(struct shdma_chan
*schan
,
350 struct shdma_desc
*sdesc
,
351 dma_addr_t src
, dma_addr_t dst
, size_t *len
)
353 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
354 struct sh_dmae_desc
, shdma_desc
);
356 if (*len
> schan
->max_xfer_len
)
357 *len
= schan
->max_xfer_len
;
359 sh_desc
->hw
.sar
= src
;
360 sh_desc
->hw
.dar
= dst
;
361 sh_desc
->hw
.tcr
= *len
;
366 static void sh_dmae_halt(struct shdma_chan
*schan
)
368 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
373 static bool sh_dmae_chan_irq(struct shdma_chan
*schan
, int irq
)
375 struct sh_dmae_chan
*sh_chan
= container_of(schan
, struct sh_dmae_chan
,
378 if (!(chcr_read(sh_chan
) & CHCR_TE
))
387 /* Called from error IRQ or NMI */
388 static bool sh_dmae_reset(struct sh_dmae_device
*shdev
)
392 /* halt the dma controller */
393 sh_dmae_ctl_stop(shdev
);
395 /* We cannot detect, which channel caused the error, have to reset all */
396 ret
= shdma_reset(&shdev
->shdma_dev
);
403 static irqreturn_t
sh_dmae_err(int irq
, void *data
)
405 struct sh_dmae_device
*shdev
= data
;
407 if (!(dmaor_read(shdev
) & DMAOR_AE
))
410 sh_dmae_reset(shdev
);
414 static bool sh_dmae_desc_completed(struct shdma_chan
*schan
,
415 struct shdma_desc
*sdesc
)
417 struct sh_dmae_chan
*sh_chan
= container_of(schan
,
418 struct sh_dmae_chan
, shdma_chan
);
419 struct sh_dmae_desc
*sh_desc
= container_of(sdesc
,
420 struct sh_dmae_desc
, shdma_desc
);
421 u32 sar_buf
= sh_dmae_readl(sh_chan
, SAR
);
422 u32 dar_buf
= sh_dmae_readl(sh_chan
, DAR
);
424 return (sdesc
->direction
== DMA_DEV_TO_MEM
&&
425 (sh_desc
->hw
.dar
+ sh_desc
->hw
.tcr
) == dar_buf
) ||
426 (sdesc
->direction
!= DMA_DEV_TO_MEM
&&
427 (sh_desc
->hw
.sar
+ sh_desc
->hw
.tcr
) == sar_buf
);
430 static bool sh_dmae_nmi_notify(struct sh_dmae_device
*shdev
)
432 /* Fast path out if NMIF is not asserted for this controller */
433 if ((dmaor_read(shdev
) & DMAOR_NMIF
) == 0)
436 return sh_dmae_reset(shdev
);
439 static int sh_dmae_nmi_handler(struct notifier_block
*self
,
440 unsigned long cmd
, void *data
)
442 struct sh_dmae_device
*shdev
;
443 int ret
= NOTIFY_DONE
;
447 * Only concern ourselves with NMI events.
449 * Normally we would check the die chain value, but as this needs
450 * to be architecture independent, check for NMI context instead.
456 list_for_each_entry_rcu(shdev
, &sh_dmae_devices
, node
) {
458 * Only stop if one of the controllers has NMIF asserted,
459 * we do not want to interfere with regular address error
460 * handling or NMI events that don't concern the DMACs.
462 triggered
= sh_dmae_nmi_notify(shdev
);
463 if (triggered
== true)
471 static struct notifier_block sh_dmae_nmi_notifier __read_mostly
= {
472 .notifier_call
= sh_dmae_nmi_handler
,
474 /* Run before NMI debug handler and KGDB */
478 static int __devinit
sh_dmae_chan_probe(struct sh_dmae_device
*shdev
, int id
,
479 int irq
, unsigned long flags
)
481 const struct sh_dmae_channel
*chan_pdata
= &shdev
->pdata
->channel
[id
];
482 struct shdma_dev
*sdev
= &shdev
->shdma_dev
;
483 struct platform_device
*pdev
= to_platform_device(sdev
->dma_dev
.dev
);
484 struct sh_dmae_chan
*sh_chan
;
485 struct shdma_chan
*schan
;
488 sh_chan
= kzalloc(sizeof(struct sh_dmae_chan
), GFP_KERNEL
);
490 dev_err(sdev
->dma_dev
.dev
,
491 "No free memory for allocating dma channels!\n");
495 schan
= &sh_chan
->shdma_chan
;
496 schan
->max_xfer_len
= SH_DMA_TCR_MAX
+ 1;
498 shdma_chan_probe(sdev
, schan
, id
);
500 sh_chan
->base
= shdev
->chan_reg
+ chan_pdata
->offset
/ sizeof(u32
);
502 /* set up channel irq */
504 snprintf(sh_chan
->dev_id
, sizeof(sh_chan
->dev_id
),
505 "sh-dmae%d.%d", pdev
->id
, id
);
507 snprintf(sh_chan
->dev_id
, sizeof(sh_chan
->dev_id
),
510 err
= shdma_request_irq(schan
, irq
, flags
, sh_chan
->dev_id
);
512 dev_err(sdev
->dma_dev
.dev
,
513 "DMA channel %d request_irq error %d\n",
518 shdev
->chan
[id
] = sh_chan
;
522 /* remove from dmaengine device node */
523 shdma_chan_remove(schan
);
528 static void sh_dmae_chan_remove(struct sh_dmae_device
*shdev
)
530 struct dma_device
*dma_dev
= &shdev
->shdma_dev
.dma_dev
;
531 struct shdma_chan
*schan
;
534 shdma_for_each_chan(schan
, &shdev
->shdma_dev
, i
) {
535 struct sh_dmae_chan
*sh_chan
= container_of(schan
,
536 struct sh_dmae_chan
, shdma_chan
);
539 shdma_free_irq(&sh_chan
->shdma_chan
);
541 shdma_chan_remove(schan
);
544 dma_dev
->chancnt
= 0;
547 static void sh_dmae_shutdown(struct platform_device
*pdev
)
549 struct sh_dmae_device
*shdev
= platform_get_drvdata(pdev
);
550 sh_dmae_ctl_stop(shdev
);
553 static int sh_dmae_runtime_suspend(struct device
*dev
)
558 static int sh_dmae_runtime_resume(struct device
*dev
)
560 struct sh_dmae_device
*shdev
= dev_get_drvdata(dev
);
562 return sh_dmae_rst(shdev
);
566 static int sh_dmae_suspend(struct device
*dev
)
571 static int sh_dmae_resume(struct device
*dev
)
573 struct sh_dmae_device
*shdev
= dev_get_drvdata(dev
);
576 ret
= sh_dmae_rst(shdev
);
578 dev_err(dev
, "Failed to reset!\n");
580 for (i
= 0; i
< shdev
->pdata
->channel_num
; i
++) {
581 struct sh_dmae_chan
*sh_chan
= shdev
->chan
[i
];
582 struct sh_dmae_slave
*param
= sh_chan
->shdma_chan
.dma_chan
.private;
584 if (!sh_chan
->shdma_chan
.desc_num
)
588 const struct sh_dmae_slave_config
*cfg
= param
->config
;
589 dmae_set_dmars(sh_chan
, cfg
->mid_rid
);
590 dmae_set_chcr(sh_chan
, cfg
->chcr
);
599 #define sh_dmae_suspend NULL
600 #define sh_dmae_resume NULL
603 const struct dev_pm_ops sh_dmae_pm
= {
604 .suspend
= sh_dmae_suspend
,
605 .resume
= sh_dmae_resume
,
606 .runtime_suspend
= sh_dmae_runtime_suspend
,
607 .runtime_resume
= sh_dmae_runtime_resume
,
610 static dma_addr_t
sh_dmae_slave_addr(struct shdma_chan
*schan
)
612 struct sh_dmae_slave
*param
= schan
->dma_chan
.private;
615 * Implicit BUG_ON(!param)
616 * if (param != NULL), this is a successfully requested slave channel,
617 * therefore param->config != NULL too.
619 return param
->config
->addr
;
622 static struct shdma_desc
*sh_dmae_embedded_desc(void *buf
, int i
)
624 return &((struct sh_dmae_desc
*)buf
)[i
].shdma_desc
;
627 static const struct shdma_ops sh_dmae_shdma_ops
= {
628 .desc_completed
= sh_dmae_desc_completed
,
629 .halt_channel
= sh_dmae_halt
,
630 .channel_busy
= sh_dmae_channel_busy
,
631 .slave_addr
= sh_dmae_slave_addr
,
632 .desc_setup
= sh_dmae_desc_setup
,
633 .set_slave
= sh_dmae_set_slave
,
634 .setup_xfer
= sh_dmae_setup_xfer
,
635 .start_xfer
= sh_dmae_start_xfer
,
636 .embedded_desc
= sh_dmae_embedded_desc
,
637 .chan_irq
= sh_dmae_chan_irq
,
640 static int __devinit
sh_dmae_probe(struct platform_device
*pdev
)
642 struct sh_dmae_pdata
*pdata
= pdev
->dev
.platform_data
;
643 unsigned long irqflags
= IRQF_DISABLED
,
644 chan_flag
[SH_DMAE_MAX_CHANNELS
] = {};
645 int errirq
, chan_irq
[SH_DMAE_MAX_CHANNELS
];
646 int err
, i
, irq_cnt
= 0, irqres
= 0, irq_cap
= 0;
647 struct sh_dmae_device
*shdev
;
648 struct dma_device
*dma_dev
;
649 struct resource
*chan
, *dmars
, *errirq_res
, *chanirq_res
;
651 /* get platform data */
652 if (!pdata
|| !pdata
->channel_num
)
655 chan
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
656 /* DMARS area is optional */
657 dmars
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
660 * 1. there always must be at least one IRQ IO-resource. On SH4 it is
661 * the error IRQ, in which case it is the only IRQ in this resource:
662 * start == end. If it is the only IRQ resource, all channels also
664 * 2. DMA channel IRQ resources can be specified one per resource or in
665 * ranges (start != end)
666 * 3. iff all events (channels and, optionally, error) on this
667 * controller use the same IRQ, only one IRQ resource can be
668 * specified, otherwise there must be one IRQ per channel, even if
669 * some of them are equal
670 * 4. if all IRQs on this controller are equal or if some specific IRQs
671 * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
672 * requested with the IRQF_SHARED flag
674 errirq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
675 if (!chan
|| !errirq_res
)
678 if (!request_mem_region(chan
->start
, resource_size(chan
), pdev
->name
)) {
679 dev_err(&pdev
->dev
, "DMAC register region already claimed\n");
683 if (dmars
&& !request_mem_region(dmars
->start
, resource_size(dmars
), pdev
->name
)) {
684 dev_err(&pdev
->dev
, "DMAC DMARS region already claimed\n");
690 shdev
= kzalloc(sizeof(struct sh_dmae_device
), GFP_KERNEL
);
692 dev_err(&pdev
->dev
, "Not enough memory\n");
696 dma_dev
= &shdev
->shdma_dev
.dma_dev
;
698 shdev
->chan_reg
= ioremap(chan
->start
, resource_size(chan
));
699 if (!shdev
->chan_reg
)
702 shdev
->dmars
= ioremap(dmars
->start
, resource_size(dmars
));
707 if (!pdata
->slave_only
)
708 dma_cap_set(DMA_MEMCPY
, dma_dev
->cap_mask
);
709 if (pdata
->slave
&& pdata
->slave_num
)
710 dma_cap_set(DMA_SLAVE
, dma_dev
->cap_mask
);
712 /* Default transfer size of 32 bytes requires 32-byte alignment */
713 dma_dev
->copy_align
= LOG2_DEFAULT_XFER_SIZE
;
715 shdev
->shdma_dev
.ops
= &sh_dmae_shdma_ops
;
716 shdev
->shdma_dev
.desc_size
= sizeof(struct sh_dmae_desc
);
717 err
= shdma_init(&pdev
->dev
, &shdev
->shdma_dev
,
723 shdev
->pdata
= pdev
->dev
.platform_data
;
725 if (pdata
->chcr_offset
)
726 shdev
->chcr_offset
= pdata
->chcr_offset
;
728 shdev
->chcr_offset
= CHCR
;
730 if (pdata
->chcr_ie_bit
)
731 shdev
->chcr_ie_bit
= pdata
->chcr_ie_bit
;
733 shdev
->chcr_ie_bit
= CHCR_IE
;
735 platform_set_drvdata(pdev
, shdev
);
737 pm_runtime_enable(&pdev
->dev
);
738 err
= pm_runtime_get_sync(&pdev
->dev
);
740 dev_err(&pdev
->dev
, "%s(): GET = %d\n", __func__
, err
);
742 spin_lock_irq(&sh_dmae_lock
);
743 list_add_tail_rcu(&shdev
->node
, &sh_dmae_devices
);
744 spin_unlock_irq(&sh_dmae_lock
);
746 /* reset dma controller - only needed as a test */
747 err
= sh_dmae_rst(shdev
);
751 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
752 chanirq_res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 1);
755 chanirq_res
= errirq_res
;
759 if (chanirq_res
== errirq_res
||
760 (errirq_res
->flags
& IORESOURCE_BITS
) == IORESOURCE_IRQ_SHAREABLE
)
761 irqflags
= IRQF_SHARED
;
763 errirq
= errirq_res
->start
;
765 err
= request_irq(errirq
, sh_dmae_err
, irqflags
,
766 "DMAC Address Error", shdev
);
769 "DMA failed requesting irq #%d, error %d\n",
775 chanirq_res
= errirq_res
;
776 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
778 if (chanirq_res
->start
== chanirq_res
->end
&&
779 !platform_get_resource(pdev
, IORESOURCE_IRQ
, 1)) {
780 /* Special case - all multiplexed */
781 for (; irq_cnt
< pdata
->channel_num
; irq_cnt
++) {
782 if (irq_cnt
< SH_DMAE_MAX_CHANNELS
) {
783 chan_irq
[irq_cnt
] = chanirq_res
->start
;
784 chan_flag
[irq_cnt
] = IRQF_SHARED
;
792 for (i
= chanirq_res
->start
; i
<= chanirq_res
->end
; i
++) {
793 if (irq_cnt
>= SH_DMAE_MAX_CHANNELS
) {
798 if ((errirq_res
->flags
& IORESOURCE_BITS
) ==
799 IORESOURCE_IRQ_SHAREABLE
)
800 chan_flag
[irq_cnt
] = IRQF_SHARED
;
802 chan_flag
[irq_cnt
] = IRQF_DISABLED
;
804 "Found IRQ %d for channel %d\n",
806 chan_irq
[irq_cnt
++] = i
;
809 if (irq_cnt
>= SH_DMAE_MAX_CHANNELS
)
812 chanirq_res
= platform_get_resource(pdev
,
813 IORESOURCE_IRQ
, ++irqres
);
814 } while (irq_cnt
< pdata
->channel_num
&& chanirq_res
);
817 /* Create DMA Channel */
818 for (i
= 0; i
< irq_cnt
; i
++) {
819 err
= sh_dmae_chan_probe(shdev
, i
, chan_irq
[i
], chan_flag
[i
]);
825 dev_notice(&pdev
->dev
, "Attempting to register %d DMA "
826 "channels when a maximum of %d are supported.\n",
827 pdata
->channel_num
, SH_DMAE_MAX_CHANNELS
);
829 pm_runtime_put(&pdev
->dev
);
831 err
= dma_async_device_register(&shdev
->shdma_dev
.dma_dev
);
838 pm_runtime_get(&pdev
->dev
);
841 sh_dmae_chan_remove(shdev
);
843 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
844 free_irq(errirq
, shdev
);
848 spin_lock_irq(&sh_dmae_lock
);
849 list_del_rcu(&shdev
->node
);
850 spin_unlock_irq(&sh_dmae_lock
);
852 pm_runtime_put(&pdev
->dev
);
853 pm_runtime_disable(&pdev
->dev
);
855 platform_set_drvdata(pdev
, NULL
);
856 shdma_cleanup(&shdev
->shdma_dev
);
859 iounmap(shdev
->dmars
);
861 iounmap(shdev
->chan_reg
);
867 release_mem_region(dmars
->start
, resource_size(dmars
));
869 release_mem_region(chan
->start
, resource_size(chan
));
874 static int __devexit
sh_dmae_remove(struct platform_device
*pdev
)
876 struct sh_dmae_device
*shdev
= platform_get_drvdata(pdev
);
877 struct dma_device
*dma_dev
= &shdev
->shdma_dev
.dma_dev
;
878 struct resource
*res
;
879 int errirq
= platform_get_irq(pdev
, 0);
881 dma_async_device_unregister(dma_dev
);
884 free_irq(errirq
, shdev
);
886 spin_lock_irq(&sh_dmae_lock
);
887 list_del_rcu(&shdev
->node
);
888 spin_unlock_irq(&sh_dmae_lock
);
890 pm_runtime_disable(&pdev
->dev
);
892 sh_dmae_chan_remove(shdev
);
893 shdma_cleanup(&shdev
->shdma_dev
);
896 iounmap(shdev
->dmars
);
897 iounmap(shdev
->chan_reg
);
899 platform_set_drvdata(pdev
, NULL
);
904 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
906 release_mem_region(res
->start
, resource_size(res
));
907 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
909 release_mem_region(res
->start
, resource_size(res
));
914 static struct platform_driver sh_dmae_driver
= {
916 .owner
= THIS_MODULE
,
918 .name
= SH_DMAE_DRV_NAME
,
920 .remove
= __devexit_p(sh_dmae_remove
),
921 .shutdown
= sh_dmae_shutdown
,
924 static int __init
sh_dmae_init(void)
926 /* Wire up NMI handling */
927 int err
= register_die_notifier(&sh_dmae_nmi_notifier
);
931 return platform_driver_probe(&sh_dmae_driver
, sh_dmae_probe
);
933 module_init(sh_dmae_init
);
935 static void __exit
sh_dmae_exit(void)
937 platform_driver_unregister(&sh_dmae_driver
);
939 unregister_die_notifier(&sh_dmae_nmi_notifier
);
941 module_exit(sh_dmae_exit
);
943 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
944 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
945 MODULE_LICENSE("GPL");
946 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME
);