projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rtc: rtc-lp8788: use devm_rtc_device_register()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / mxs-dma.c
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Refer to drivers/dma/imx-sdma.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/mm.h>
14 #include <linux/interrupt.h>
15 #include <linux/clk.h>
16 #include <linux/wait.h>
17 #include <linux/sched.h>
18 #include <linux/semaphore.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/fsl/mxs-dma.h>
27 #include <linux/stmp_device.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30
31 #include <asm/irq.h>
32
33 #include "dmaengine.h"
34
35 /*
36 * NOTE: The term "PIO" throughout the mxs-dma implementation means
37 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
38 * dma can program the controller registers of peripheral devices.
39 */
40
41 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
42 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
43
44 #define HW_APBHX_CTRL0 0x000
45 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
46 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
47 #define BP_APBH_CTRL0_RESET_CHANNEL 16
48 #define HW_APBHX_CTRL1 0x010
49 #define HW_APBHX_CTRL2 0x020
50 #define HW_APBHX_CHANNEL_CTRL 0x030
51 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
52 /*
53 * The offset of NXTCMDAR register is different per both dma type and version,
54 * while stride for each channel is all the same 0x70.
55 */
56 #define HW_APBHX_CHn_NXTCMDAR(d, n) \
57 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
58 #define HW_APBHX_CHn_SEMA(d, n) \
59 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
60
61 /*
62 * ccw bits definitions
63 *
64 * COMMAND: 0..1 (2)
65 * CHAIN: 2 (1)
66 * IRQ: 3 (1)
67 * NAND_LOCK: 4 (1) - not implemented
68 * NAND_WAIT4READY: 5 (1) - not implemented
69 * DEC_SEM: 6 (1)
70 * WAIT4END: 7 (1)
71 * HALT_ON_TERMINATE: 8 (1)
72 * TERMINATE_FLUSH: 9 (1)
73 * RESERVED: 10..11 (2)
74 * PIO_NUM: 12..15 (4)
75 */
76 #define BP_CCW_COMMAND 0
77 #define BM_CCW_COMMAND (3 << 0)
78 #define CCW_CHAIN (1 << 2)
79 #define CCW_IRQ (1 << 3)
80 #define CCW_DEC_SEM (1 << 6)
81 #define CCW_WAIT4END (1 << 7)
82 #define CCW_HALT_ON_TERM (1 << 8)
83 #define CCW_TERM_FLUSH (1 << 9)
84 #define BP_CCW_PIO_NUM 12
85 #define BM_CCW_PIO_NUM (0xf << 12)
86
87 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
88
89 #define MXS_DMA_CMD_NO_XFER 0
90 #define MXS_DMA_CMD_WRITE 1
91 #define MXS_DMA_CMD_READ 2
92 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
93
94 struct mxs_dma_ccw {
95 u32 next;
96 u16 bits;
97 u16 xfer_bytes;
98 #define MAX_XFER_BYTES 0xff00
99 u32 bufaddr;
100 #define MXS_PIO_WORDS 16
101 u32 pio_words[MXS_PIO_WORDS];
102 };
103
104 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
105 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
106
107 struct mxs_dma_chan {
108 struct mxs_dma_engine *mxs_dma;
109 struct dma_chan chan;
110 struct dma_async_tx_descriptor desc;
111 struct tasklet_struct tasklet;
112 unsigned int chan_irq;
113 struct mxs_dma_ccw *ccw;
114 dma_addr_t ccw_phys;
115 int desc_count;
116 enum dma_status status;
117 unsigned int flags;
118 #define MXS_DMA_SG_LOOP (1 << 0)
119 };
120
121 #define MXS_DMA_CHANNELS 16
122 #define MXS_DMA_CHANNELS_MASK 0xffff
123
124 enum mxs_dma_devtype {
125 MXS_DMA_APBH,
126 MXS_DMA_APBX,
127 };
128
129 enum mxs_dma_id {
130 IMX23_DMA,
131 IMX28_DMA,
132 };
133
134 struct mxs_dma_engine {
135 enum mxs_dma_id dev_id;
136 enum mxs_dma_devtype type;
137 void __iomem *base;
138 struct clk *clk;
139 struct dma_device dma_device;
140 struct device_dma_parameters dma_parms;
141 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
142 };
143
144 struct mxs_dma_type {
145 enum mxs_dma_id id;
146 enum mxs_dma_devtype type;
147 };
148
149 static struct mxs_dma_type mxs_dma_types[] = {
150 {
151 .id = IMX23_DMA,
152 .type = MXS_DMA_APBH,
153 }, {
154 .id = IMX23_DMA,
155 .type = MXS_DMA_APBX,
156 }, {
157 .id = IMX28_DMA,
158 .type = MXS_DMA_APBH,
159 }, {
160 .id = IMX28_DMA,
161 .type = MXS_DMA_APBX,
162 }
163 };
164
165 static struct platform_device_id mxs_dma_ids[] = {
166 {
167 .name = "imx23-dma-apbh",
168 .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
169 }, {
170 .name = "imx23-dma-apbx",
171 .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
172 }, {
173 .name = "imx28-dma-apbh",
174 .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
175 }, {
176 .name = "imx28-dma-apbx",
177 .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
178 }, {
179 /* end of list */
180 }
181 };
182
183 static const struct of_device_id mxs_dma_dt_ids[] = {
184 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
185 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
186 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
187 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
188 { /* sentinel */ }
189 };
190 MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
191
192 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
193 {
194 return container_of(chan, struct mxs_dma_chan, chan);
195 }
196
197 int mxs_dma_is_apbh(struct dma_chan *chan)
198 {
199 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
200 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
201
202 return dma_is_apbh(mxs_dma);
203 }
204 EXPORT_SYMBOL_GPL(mxs_dma_is_apbh);
205
206 int mxs_dma_is_apbx(struct dma_chan *chan)
207 {
208 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
209 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
210
211 return !dma_is_apbh(mxs_dma);
212 }
213 EXPORT_SYMBOL_GPL(mxs_dma_is_apbx);
214
215 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
216 {
217 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
218 int chan_id = mxs_chan->chan.chan_id;
219
220 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
221 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
222 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
223 else
224 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
225 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
226 }
227
228 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
229 {
230 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
231 int chan_id = mxs_chan->chan.chan_id;
232
233 /* set cmd_addr up */
234 writel(mxs_chan->ccw_phys,
235 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
236
237 /* write 1 to SEMA to kick off the channel */
238 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
239 }
240
241 static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
242 {
243 mxs_chan->status = DMA_SUCCESS;
244 }
245
246 static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
247 {
248 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
249 int chan_id = mxs_chan->chan.chan_id;
250
251 /* freeze the channel */
252 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
253 writel(1 << chan_id,
254 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
255 else
256 writel(1 << chan_id,
257 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
258
259 mxs_chan->status = DMA_PAUSED;
260 }
261
262 static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
263 {
264 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
265 int chan_id = mxs_chan->chan.chan_id;
266
267 /* unfreeze the channel */
268 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
269 writel(1 << chan_id,
270 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
271 else
272 writel(1 << chan_id,
273 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
274
275 mxs_chan->status = DMA_IN_PROGRESS;
276 }
277
278 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
279 {
280 return dma_cookie_assign(tx);
281 }
282
283 static void mxs_dma_tasklet(unsigned long data)
284 {
285 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
286
287 if (mxs_chan->desc.callback)
288 mxs_chan->desc.callback(mxs_chan->desc.callback_param);
289 }
290
291 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
292 {
293 struct mxs_dma_engine *mxs_dma = dev_id;
294 u32 stat1, stat2;
295
296 /* completion status */
297 stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
298 stat1 &= MXS_DMA_CHANNELS_MASK;
299 writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
300
301 /* error status */
302 stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
303 writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
304
305 /*
306 * When both completion and error of termination bits set at the
307 * same time, we do not take it as an error. IOW, it only becomes
308 * an error we need to handle here in case of either it's (1) a bus
309 * error or (2) a termination error with no completion.
310 */
311 stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
312 (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
313
314 /* combine error and completion status for checking */
315 stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
316 while (stat1) {
317 int channel = fls(stat1) - 1;
318 struct mxs_dma_chan *mxs_chan =
319 &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
320
321 if (channel >= MXS_DMA_CHANNELS) {
322 dev_dbg(mxs_dma->dma_device.dev,
323 "%s: error in channel %d\n", __func__,
324 channel - MXS_DMA_CHANNELS);
325 mxs_chan->status = DMA_ERROR;
326 mxs_dma_reset_chan(mxs_chan);
327 } else {
328 if (mxs_chan->flags & MXS_DMA_SG_LOOP)
329 mxs_chan->status = DMA_IN_PROGRESS;
330 else
331 mxs_chan->status = DMA_SUCCESS;
332 }
333
334 stat1 &= ~(1 << channel);
335
336 if (mxs_chan->status == DMA_SUCCESS)
337 dma_cookie_complete(&mxs_chan->desc);
338
339 /* schedule tasklet on this channel */
340 tasklet_schedule(&mxs_chan->tasklet);
341 }
342
343 return IRQ_HANDLED;
344 }
345
346 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
347 {
348 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
349 struct mxs_dma_data *data = chan->private;
350 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
351 int ret;
352
353 if (!data)
354 return -EINVAL;
355
356 mxs_chan->chan_irq = data->chan_irq;
357
358 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
359 CCW_BLOCK_SIZE, &mxs_chan->ccw_phys,
360 GFP_KERNEL);
361 if (!mxs_chan->ccw) {
362 ret = -ENOMEM;
363 goto err_alloc;
364 }
365
366 memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE);
367
368 if (mxs_chan->chan_irq != NO_IRQ) {
369 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
370 0, "mxs-dma", mxs_dma);
371 if (ret)
372 goto err_irq;
373 }
374
375 ret = clk_prepare_enable(mxs_dma->clk);
376 if (ret)
377 goto err_clk;
378
379 mxs_dma_reset_chan(mxs_chan);
380
381 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
382 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
383
384 /* the descriptor is ready */
385 async_tx_ack(&mxs_chan->desc);
386
387 return 0;
388
389 err_clk:
390 free_irq(mxs_chan->chan_irq, mxs_dma);
391 err_irq:
392 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
393 mxs_chan->ccw, mxs_chan->ccw_phys);
394 err_alloc:
395 return ret;
396 }
397
398 static void mxs_dma_free_chan_resources(struct dma_chan *chan)
399 {
400 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
401 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
402
403 mxs_dma_disable_chan(mxs_chan);
404
405 free_irq(mxs_chan->chan_irq, mxs_dma);
406
407 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
408 mxs_chan->ccw, mxs_chan->ccw_phys);
409
410 clk_disable_unprepare(mxs_dma->clk);
411 }
412
413 /*
414 * How to use the flags for ->device_prep_slave_sg() :
415 * [1] If there is only one DMA command in the DMA chain, the code should be:
416 * ......
417 * ->device_prep_slave_sg(DMA_CTRL_ACK);
418 * ......
419 * [2] If there are two DMA commands in the DMA chain, the code should be
420 * ......
421 * ->device_prep_slave_sg(0);
422 * ......
423 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
424 * ......
425 * [3] If there are more than two DMA commands in the DMA chain, the code
426 * should be:
427 * ......
428 * ->device_prep_slave_sg(0); // First
429 * ......
430 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
431 * ......
432 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
433 * ......
434 */
435 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
436 struct dma_chan *chan, struct scatterlist *sgl,
437 unsigned int sg_len, enum dma_transfer_direction direction,
438 unsigned long flags, void *context)
439 {
440 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
441 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
442 struct mxs_dma_ccw *ccw;
443 struct scatterlist *sg;
444 u32 i, j;
445 u32 *pio;
446 bool append = flags & DMA_PREP_INTERRUPT;
447 int idx = append ? mxs_chan->desc_count : 0;
448
449 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
450 return NULL;
451
452 if (sg_len + (append ? idx : 0) > NUM_CCW) {
453 dev_err(mxs_dma->dma_device.dev,
454 "maximum number of sg exceeded: %d > %d\n",
455 sg_len, NUM_CCW);
456 goto err_out;
457 }
458
459 mxs_chan->status = DMA_IN_PROGRESS;
460 mxs_chan->flags = 0;
461
462 /*
463 * If the sg is prepared with append flag set, the sg
464 * will be appended to the last prepared sg.
465 */
466 if (append) {
467 BUG_ON(idx < 1);
468 ccw = &mxs_chan->ccw[idx - 1];
469 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
470 ccw->bits |= CCW_CHAIN;
471 ccw->bits &= ~CCW_IRQ;
472 ccw->bits &= ~CCW_DEC_SEM;
473 } else {
474 idx = 0;
475 }
476
477 if (direction == DMA_TRANS_NONE) {
478 ccw = &mxs_chan->ccw[idx++];
479 pio = (u32 *) sgl;
480
481 for (j = 0; j < sg_len;)
482 ccw->pio_words[j++] = *pio++;
483
484 ccw->bits = 0;
485 ccw->bits |= CCW_IRQ;
486 ccw->bits |= CCW_DEC_SEM;
487 if (flags & DMA_CTRL_ACK)
488 ccw->bits |= CCW_WAIT4END;
489 ccw->bits |= CCW_HALT_ON_TERM;
490 ccw->bits |= CCW_TERM_FLUSH;
491 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
492 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
493 } else {
494 for_each_sg(sgl, sg, sg_len, i) {
495 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
496 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
497 sg_dma_len(sg), MAX_XFER_BYTES);
498 goto err_out;
499 }
500
501 ccw = &mxs_chan->ccw[idx++];
502
503 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
504 ccw->bufaddr = sg->dma_address;
505 ccw->xfer_bytes = sg_dma_len(sg);
506
507 ccw->bits = 0;
508 ccw->bits |= CCW_CHAIN;
509 ccw->bits |= CCW_HALT_ON_TERM;
510 ccw->bits |= CCW_TERM_FLUSH;
511 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
512 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
513 COMMAND);
514
515 if (i + 1 == sg_len) {
516 ccw->bits &= ~CCW_CHAIN;
517 ccw->bits |= CCW_IRQ;
518 ccw->bits |= CCW_DEC_SEM;
519 if (flags & DMA_CTRL_ACK)
520 ccw->bits |= CCW_WAIT4END;
521 }
522 }
523 }
524 mxs_chan->desc_count = idx;
525
526 return &mxs_chan->desc;
527
528 err_out:
529 mxs_chan->status = DMA_ERROR;
530 return NULL;
531 }
532
533 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
534 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
535 size_t period_len, enum dma_transfer_direction direction,
536 unsigned long flags, void *context)
537 {
538 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
539 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
540 u32 num_periods = buf_len / period_len;
541 u32 i = 0, buf = 0;
542
543 if (mxs_chan->status == DMA_IN_PROGRESS)
544 return NULL;
545
546 mxs_chan->status = DMA_IN_PROGRESS;
547 mxs_chan->flags |= MXS_DMA_SG_LOOP;
548
549 if (num_periods > NUM_CCW) {
550 dev_err(mxs_dma->dma_device.dev,
551 "maximum number of sg exceeded: %d > %d\n",
552 num_periods, NUM_CCW);
553 goto err_out;
554 }
555
556 if (period_len > MAX_XFER_BYTES) {
557 dev_err(mxs_dma->dma_device.dev,
558 "maximum period size exceeded: %d > %d\n",
559 period_len, MAX_XFER_BYTES);
560 goto err_out;
561 }
562
563 while (buf < buf_len) {
564 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
565
566 if (i + 1 == num_periods)
567 ccw->next = mxs_chan->ccw_phys;
568 else
569 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
570
571 ccw->bufaddr = dma_addr;
572 ccw->xfer_bytes = period_len;
573
574 ccw->bits = 0;
575 ccw->bits |= CCW_CHAIN;
576 ccw->bits |= CCW_IRQ;
577 ccw->bits |= CCW_HALT_ON_TERM;
578 ccw->bits |= CCW_TERM_FLUSH;
579 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
580 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
581
582 dma_addr += period_len;
583 buf += period_len;
584
585 i++;
586 }
587 mxs_chan->desc_count = i;
588
589 return &mxs_chan->desc;
590
591 err_out:
592 mxs_chan->status = DMA_ERROR;
593 return NULL;
594 }
595
596 static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
597 unsigned long arg)
598 {
599 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
600 int ret = 0;
601
602 switch (cmd) {
603 case DMA_TERMINATE_ALL:
604 mxs_dma_reset_chan(mxs_chan);
605 mxs_dma_disable_chan(mxs_chan);
606 break;
607 case DMA_PAUSE:
608 mxs_dma_pause_chan(mxs_chan);
609 break;
610 case DMA_RESUME:
611 mxs_dma_resume_chan(mxs_chan);
612 break;
613 default:
614 ret = -ENOSYS;
615 }
616
617 return ret;
618 }
619
620 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
621 dma_cookie_t cookie, struct dma_tx_state *txstate)
622 {
623 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
624 dma_cookie_t last_used;
625
626 last_used = chan->cookie;
627 dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
628
629 return mxs_chan->status;
630 }
631
632 static void mxs_dma_issue_pending(struct dma_chan *chan)
633 {
634 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
635
636 mxs_dma_enable_chan(mxs_chan);
637 }
638
639 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
640 {
641 int ret;
642
643 ret = clk_prepare_enable(mxs_dma->clk);
644 if (ret)
645 return ret;
646
647 ret = stmp_reset_block(mxs_dma->base);
648 if (ret)
649 goto err_out;
650
651 /* enable apbh burst */
652 if (dma_is_apbh(mxs_dma)) {
653 writel(BM_APBH_CTRL0_APB_BURST_EN,
654 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
655 writel(BM_APBH_CTRL0_APB_BURST8_EN,
656 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
657 }
658
659 /* enable irq for all the channels */
660 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
661 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
662
663 err_out:
664 clk_disable_unprepare(mxs_dma->clk);
665 return ret;
666 }
667
668 static int __init mxs_dma_probe(struct platform_device *pdev)
669 {
670 const struct platform_device_id *id_entry;
671 const struct of_device_id *of_id;
672 const struct mxs_dma_type *dma_type;
673 struct mxs_dma_engine *mxs_dma;
674 struct resource *iores;
675 int ret, i;
676
677 mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
678 if (!mxs_dma)
679 return -ENOMEM;
680
681 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
682 if (of_id)
683 id_entry = of_id->data;
684 else
685 id_entry = platform_get_device_id(pdev);
686
687 dma_type = (struct mxs_dma_type *)id_entry->driver_data;
688 mxs_dma->type = dma_type->type;
689 mxs_dma->dev_id = dma_type->id;
690
691 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
692
693 if (!request_mem_region(iores->start, resource_size(iores),
694 pdev->name)) {
695 ret = -EBUSY;
696 goto err_request_region;
697 }
698
699 mxs_dma->base = ioremap(iores->start, resource_size(iores));
700 if (!mxs_dma->base) {
701 ret = -ENOMEM;
702 goto err_ioremap;
703 }
704
705 mxs_dma->clk = clk_get(&pdev->dev, NULL);
706 if (IS_ERR(mxs_dma->clk)) {
707 ret = PTR_ERR(mxs_dma->clk);
708 goto err_clk;
709 }
710
711 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
712 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
713
714 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
715
716 /* Initialize channel parameters */
717 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
718 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
719
720 mxs_chan->mxs_dma = mxs_dma;
721 mxs_chan->chan.device = &mxs_dma->dma_device;
722 dma_cookie_init(&mxs_chan->chan);
723
724 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
725 (unsigned long) mxs_chan);
726
727
728 /* Add the channel to mxs_chan list */
729 list_add_tail(&mxs_chan->chan.device_node,
730 &mxs_dma->dma_device.channels);
731 }
732
733 ret = mxs_dma_init(mxs_dma);
734 if (ret)
735 goto err_init;
736
737 mxs_dma->dma_device.dev = &pdev->dev;
738
739 /* mxs_dma gets 65535 bytes maximum sg size */
740 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
741 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
742
743 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
744 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
745 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
746 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
747 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
748 mxs_dma->dma_device.device_control = mxs_dma_control;
749 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
750
751 ret = dma_async_device_register(&mxs_dma->dma_device);
752 if (ret) {
753 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
754 goto err_init;
755 }
756
757 dev_info(mxs_dma->dma_device.dev, "initialized\n");
758
759 return 0;
760
761 err_init:
762 clk_put(mxs_dma->clk);
763 err_clk:
764 iounmap(mxs_dma->base);
765 err_ioremap:
766 release_mem_region(iores->start, resource_size(iores));
767 err_request_region:
768 kfree(mxs_dma);
769 return ret;
770 }
771
772 static struct platform_driver mxs_dma_driver = {
773 .driver = {
774 .name = "mxs-dma",
775 .of_match_table = mxs_dma_dt_ids,
776 },
777 .id_table = mxs_dma_ids,
778 };
779
780 static int __init mxs_dma_module_init(void)
781 {
782 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
783 }
784 subsys_initcall(mxs_dma_module_init);
kernel source for telekom puls (alcatel/mediatek)