2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/async_tx.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/memory.h>
28 #include <asm/plat-orion/mv_xor.h>
31 static void mv_xor_issue_pending(struct dma_chan
*chan
);
33 #define to_mv_xor_chan(chan) \
34 container_of(chan, struct mv_xor_chan, common)
36 #define to_mv_xor_device(dev) \
37 container_of(dev, struct mv_xor_device, common)
39 #define to_mv_xor_slot(tx) \
40 container_of(tx, struct mv_xor_desc_slot, async_tx)
42 static void mv_desc_init(struct mv_xor_desc_slot
*desc
, unsigned long flags
)
44 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
46 hw_desc
->status
= (1 << 31);
47 hw_desc
->phy_next_desc
= 0;
48 hw_desc
->desc_command
= (1 << 31);
51 static u32
mv_desc_get_dest_addr(struct mv_xor_desc_slot
*desc
)
53 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
54 return hw_desc
->phy_dest_addr
;
57 static u32
mv_desc_get_src_addr(struct mv_xor_desc_slot
*desc
,
60 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
61 return hw_desc
->phy_src_addr
[src_idx
];
65 static void mv_desc_set_byte_count(struct mv_xor_desc_slot
*desc
,
68 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
69 hw_desc
->byte_count
= byte_count
;
72 static void mv_desc_set_next_desc(struct mv_xor_desc_slot
*desc
,
75 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
76 BUG_ON(hw_desc
->phy_next_desc
);
77 hw_desc
->phy_next_desc
= next_desc_addr
;
80 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot
*desc
)
82 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
83 hw_desc
->phy_next_desc
= 0;
86 static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot
*desc
, u32 val
)
91 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot
*desc
,
94 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
95 hw_desc
->phy_dest_addr
= addr
;
98 static int mv_chan_memset_slot_count(size_t len
)
103 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
105 static void mv_desc_set_src_addr(struct mv_xor_desc_slot
*desc
,
106 int index
, dma_addr_t addr
)
108 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
109 hw_desc
->phy_src_addr
[index
] = addr
;
110 if (desc
->type
== DMA_XOR
)
111 hw_desc
->desc_command
|= (1 << index
);
114 static u32
mv_chan_get_current_desc(struct mv_xor_chan
*chan
)
116 return __raw_readl(XOR_CURR_DESC(chan
));
119 static void mv_chan_set_next_descriptor(struct mv_xor_chan
*chan
,
122 __raw_writel(next_desc_addr
, XOR_NEXT_DESC(chan
));
125 static void mv_chan_set_dest_pointer(struct mv_xor_chan
*chan
, u32 desc_addr
)
127 __raw_writel(desc_addr
, XOR_DEST_POINTER(chan
));
130 static void mv_chan_set_block_size(struct mv_xor_chan
*chan
, u32 block_size
)
132 __raw_writel(block_size
, XOR_BLOCK_SIZE(chan
));
135 static void mv_chan_set_value(struct mv_xor_chan
*chan
, u32 value
)
137 __raw_writel(value
, XOR_INIT_VALUE_LOW(chan
));
138 __raw_writel(value
, XOR_INIT_VALUE_HIGH(chan
));
141 static void mv_chan_unmask_interrupts(struct mv_xor_chan
*chan
)
143 u32 val
= __raw_readl(XOR_INTR_MASK(chan
));
144 val
|= XOR_INTR_MASK_VALUE
<< (chan
->idx
* 16);
145 __raw_writel(val
, XOR_INTR_MASK(chan
));
148 static u32
mv_chan_get_intr_cause(struct mv_xor_chan
*chan
)
150 u32 intr_cause
= __raw_readl(XOR_INTR_CAUSE(chan
));
151 intr_cause
= (intr_cause
>> (chan
->idx
* 16)) & 0xFFFF;
155 static int mv_is_err_intr(u32 intr_cause
)
157 if (intr_cause
& ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
163 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan
*chan
)
165 u32 val
= (1 << (1 + (chan
->idx
* 16)));
166 dev_dbg(chan
->device
->common
.dev
, "%s, val 0x%08x\n", __func__
, val
);
167 __raw_writel(val
, XOR_INTR_CAUSE(chan
));
170 static void mv_xor_device_clear_err_status(struct mv_xor_chan
*chan
)
172 u32 val
= 0xFFFF0000 >> (chan
->idx
* 16);
173 __raw_writel(val
, XOR_INTR_CAUSE(chan
));
176 static int mv_can_chain(struct mv_xor_desc_slot
*desc
)
178 struct mv_xor_desc_slot
*chain_old_tail
= list_entry(
179 desc
->chain_node
.prev
, struct mv_xor_desc_slot
, chain_node
);
181 if (chain_old_tail
->type
!= desc
->type
)
183 if (desc
->type
== DMA_MEMSET
)
189 static void mv_set_mode(struct mv_xor_chan
*chan
,
190 enum dma_transaction_type type
)
193 u32 config
= __raw_readl(XOR_CONFIG(chan
));
197 op_mode
= XOR_OPERATION_MODE_XOR
;
200 op_mode
= XOR_OPERATION_MODE_MEMCPY
;
203 op_mode
= XOR_OPERATION_MODE_MEMSET
;
206 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
207 "error: unsupported operation %d.\n",
215 __raw_writel(config
, XOR_CONFIG(chan
));
216 chan
->current_type
= type
;
219 static void mv_chan_activate(struct mv_xor_chan
*chan
)
223 dev_dbg(chan
->device
->common
.dev
, " activate chan.\n");
224 activation
= __raw_readl(XOR_ACTIVATION(chan
));
226 __raw_writel(activation
, XOR_ACTIVATION(chan
));
229 static char mv_chan_is_busy(struct mv_xor_chan
*chan
)
231 u32 state
= __raw_readl(XOR_ACTIVATION(chan
));
233 state
= (state
>> 4) & 0x3;
235 return (state
== 1) ? 1 : 0;
238 static int mv_chan_xor_slot_count(size_t len
, int src_cnt
)
244 * mv_xor_free_slots - flags descriptor slots for reuse
245 * @slot: Slot to free
246 * Caller must hold &mv_chan->lock while calling this function
248 static void mv_xor_free_slots(struct mv_xor_chan
*mv_chan
,
249 struct mv_xor_desc_slot
*slot
)
251 dev_dbg(mv_chan
->device
->common
.dev
, "%s %d slot %p\n",
252 __func__
, __LINE__
, slot
);
254 slot
->slots_per_op
= 0;
259 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
261 * Caller must hold &mv_chan->lock while calling this function
263 static void mv_xor_start_new_chain(struct mv_xor_chan
*mv_chan
,
264 struct mv_xor_desc_slot
*sw_desc
)
266 dev_dbg(mv_chan
->device
->common
.dev
, "%s %d: sw_desc %p\n",
267 __func__
, __LINE__
, sw_desc
);
268 if (sw_desc
->type
!= mv_chan
->current_type
)
269 mv_set_mode(mv_chan
, sw_desc
->type
);
271 if (sw_desc
->type
== DMA_MEMSET
) {
272 /* for memset requests we need to program the engine, no
275 struct mv_xor_desc
*hw_desc
= sw_desc
->hw_desc
;
276 mv_chan_set_dest_pointer(mv_chan
, hw_desc
->phy_dest_addr
);
277 mv_chan_set_block_size(mv_chan
, sw_desc
->unmap_len
);
278 mv_chan_set_value(mv_chan
, sw_desc
->value
);
280 /* set the hardware chain */
281 mv_chan_set_next_descriptor(mv_chan
, sw_desc
->async_tx
.phys
);
283 mv_chan
->pending
+= sw_desc
->slot_cnt
;
284 mv_xor_issue_pending(&mv_chan
->common
);
288 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot
*desc
,
289 struct mv_xor_chan
*mv_chan
, dma_cookie_t cookie
)
291 BUG_ON(desc
->async_tx
.cookie
< 0);
293 if (desc
->async_tx
.cookie
> 0) {
294 cookie
= desc
->async_tx
.cookie
;
296 /* call the callback (must not sleep or submit new
297 * operations to this channel)
299 if (desc
->async_tx
.callback
)
300 desc
->async_tx
.callback(
301 desc
->async_tx
.callback_param
);
303 /* unmap dma addresses
304 * (unmap_single vs unmap_page?)
306 if (desc
->group_head
&& desc
->unmap_len
) {
307 struct mv_xor_desc_slot
*unmap
= desc
->group_head
;
309 &mv_chan
->device
->pdev
->dev
;
310 u32 len
= unmap
->unmap_len
;
311 u32 src_cnt
= unmap
->unmap_src_cnt
;
312 dma_addr_t addr
= mv_desc_get_dest_addr(unmap
);
314 dma_unmap_page(dev
, addr
, len
, DMA_FROM_DEVICE
);
316 addr
= mv_desc_get_src_addr(unmap
, src_cnt
);
317 dma_unmap_page(dev
, addr
, len
, DMA_TO_DEVICE
);
319 desc
->group_head
= NULL
;
323 /* run dependent operations */
324 async_tx_run_dependencies(&desc
->async_tx
);
330 mv_xor_clean_completed_slots(struct mv_xor_chan
*mv_chan
)
332 struct mv_xor_desc_slot
*iter
, *_iter
;
334 dev_dbg(mv_chan
->device
->common
.dev
, "%s %d\n", __func__
, __LINE__
);
335 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
338 if (async_tx_test_ack(&iter
->async_tx
)) {
339 list_del(&iter
->completed_node
);
340 mv_xor_free_slots(mv_chan
, iter
);
347 mv_xor_clean_slot(struct mv_xor_desc_slot
*desc
,
348 struct mv_xor_chan
*mv_chan
)
350 dev_dbg(mv_chan
->device
->common
.dev
, "%s %d: desc %p flags %d\n",
351 __func__
, __LINE__
, desc
, desc
->async_tx
.flags
);
352 list_del(&desc
->chain_node
);
353 /* the client is allowed to attach dependent operations
356 if (!async_tx_test_ack(&desc
->async_tx
)) {
357 /* move this slot to the completed_slots */
358 list_add_tail(&desc
->completed_node
, &mv_chan
->completed_slots
);
362 mv_xor_free_slots(mv_chan
, desc
);
366 static void __mv_xor_slot_cleanup(struct mv_xor_chan
*mv_chan
)
368 struct mv_xor_desc_slot
*iter
, *_iter
;
369 dma_cookie_t cookie
= 0;
370 int busy
= mv_chan_is_busy(mv_chan
);
371 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
372 int seen_current
= 0;
374 dev_dbg(mv_chan
->device
->common
.dev
, "%s %d\n", __func__
, __LINE__
);
375 dev_dbg(mv_chan
->device
->common
.dev
, "current_desc %x\n", current_desc
);
376 mv_xor_clean_completed_slots(mv_chan
);
378 /* free completed slots from the chain starting with
379 * the oldest descriptor
382 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
385 prefetch(&_iter
->async_tx
);
387 /* do not advance past the current descriptor loaded into the
388 * hardware channel, subsequent descriptors are either in
389 * process or have not been submitted
394 /* stop the search if we reach the current descriptor and the
397 if (iter
->async_tx
.phys
== current_desc
) {
403 cookie
= mv_xor_run_tx_complete_actions(iter
, mv_chan
, cookie
);
405 if (mv_xor_clean_slot(iter
, mv_chan
))
409 if ((busy
== 0) && !list_empty(&mv_chan
->chain
)) {
410 struct mv_xor_desc_slot
*chain_head
;
411 chain_head
= list_entry(mv_chan
->chain
.next
,
412 struct mv_xor_desc_slot
,
415 mv_xor_start_new_chain(mv_chan
, chain_head
);
419 mv_chan
->completed_cookie
= cookie
;
423 mv_xor_slot_cleanup(struct mv_xor_chan
*mv_chan
)
425 spin_lock_bh(&mv_chan
->lock
);
426 __mv_xor_slot_cleanup(mv_chan
);
427 spin_unlock_bh(&mv_chan
->lock
);
430 static void mv_xor_tasklet(unsigned long data
)
432 struct mv_xor_chan
*chan
= (struct mv_xor_chan
*) data
;
433 __mv_xor_slot_cleanup(chan
);
436 static struct mv_xor_desc_slot
*
437 mv_xor_alloc_slots(struct mv_xor_chan
*mv_chan
, int num_slots
,
440 struct mv_xor_desc_slot
*iter
, *_iter
, *alloc_start
= NULL
;
442 int slots_found
, retry
= 0;
444 /* start search from the last allocated descrtiptor
445 * if a contiguous allocation can not be found start searching
446 * from the beginning of the list
451 iter
= mv_chan
->last_used
;
453 iter
= list_entry(&mv_chan
->all_slots
,
454 struct mv_xor_desc_slot
,
457 list_for_each_entry_safe_continue(
458 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
460 prefetch(&_iter
->async_tx
);
461 if (iter
->slots_per_op
) {
462 /* give up after finding the first busy slot
463 * on the second pass through the list
472 /* start the allocation if the slot is correctly aligned */
476 if (slots_found
== num_slots
) {
477 struct mv_xor_desc_slot
*alloc_tail
= NULL
;
478 struct mv_xor_desc_slot
*last_used
= NULL
;
483 /* pre-ack all but the last descriptor */
484 async_tx_ack(&iter
->async_tx
);
486 list_add_tail(&iter
->chain_node
, &chain
);
488 iter
->async_tx
.cookie
= 0;
489 iter
->slot_cnt
= num_slots
;
490 iter
->xor_check_result
= NULL
;
491 for (i
= 0; i
< slots_per_op
; i
++) {
492 iter
->slots_per_op
= slots_per_op
- i
;
494 iter
= list_entry(iter
->slot_node
.next
,
495 struct mv_xor_desc_slot
,
498 num_slots
-= slots_per_op
;
500 alloc_tail
->group_head
= alloc_start
;
501 alloc_tail
->async_tx
.cookie
= -EBUSY
;
502 list_splice(&chain
, &alloc_tail
->async_tx
.tx_list
);
503 mv_chan
->last_used
= last_used
;
504 mv_desc_clear_next_desc(alloc_start
);
505 mv_desc_clear_next_desc(alloc_tail
);
512 /* try to free some slots if the allocation fails */
513 tasklet_schedule(&mv_chan
->irq_tasklet
);
519 mv_desc_assign_cookie(struct mv_xor_chan
*mv_chan
,
520 struct mv_xor_desc_slot
*desc
)
522 dma_cookie_t cookie
= mv_chan
->common
.cookie
;
526 mv_chan
->common
.cookie
= desc
->async_tx
.cookie
= cookie
;
530 /************************ DMA engine API functions ****************************/
532 mv_xor_tx_submit(struct dma_async_tx_descriptor
*tx
)
534 struct mv_xor_desc_slot
*sw_desc
= to_mv_xor_slot(tx
);
535 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(tx
->chan
);
536 struct mv_xor_desc_slot
*grp_start
, *old_chain_tail
;
538 int new_hw_chain
= 1;
540 dev_dbg(mv_chan
->device
->common
.dev
,
541 "%s sw_desc %p: async_tx %p\n",
542 __func__
, sw_desc
, &sw_desc
->async_tx
);
544 grp_start
= sw_desc
->group_head
;
546 spin_lock_bh(&mv_chan
->lock
);
547 cookie
= mv_desc_assign_cookie(mv_chan
, sw_desc
);
549 if (list_empty(&mv_chan
->chain
))
550 list_splice_init(&sw_desc
->async_tx
.tx_list
, &mv_chan
->chain
);
554 old_chain_tail
= list_entry(mv_chan
->chain
.prev
,
555 struct mv_xor_desc_slot
,
557 list_splice_init(&grp_start
->async_tx
.tx_list
,
558 &old_chain_tail
->chain_node
);
560 if (!mv_can_chain(grp_start
))
563 dev_dbg(mv_chan
->device
->common
.dev
, "Append to last desc %x\n",
564 old_chain_tail
->async_tx
.phys
);
566 /* fix up the hardware chain */
567 mv_desc_set_next_desc(old_chain_tail
, grp_start
->async_tx
.phys
);
569 /* if the channel is not busy */
570 if (!mv_chan_is_busy(mv_chan
)) {
571 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
573 * and the curren desc is the end of the chain before
574 * the append, then we need to start the channel
576 if (current_desc
== old_chain_tail
->async_tx
.phys
)
582 mv_xor_start_new_chain(mv_chan
, grp_start
);
585 spin_unlock_bh(&mv_chan
->lock
);
590 /* returns the number of allocated descriptors */
591 static int mv_xor_alloc_chan_resources(struct dma_chan
*chan
,
592 struct dma_client
*client
)
596 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
597 struct mv_xor_desc_slot
*slot
= NULL
;
598 struct mv_xor_platform_data
*plat_data
=
599 mv_chan
->device
->pdev
->dev
.platform_data
;
600 int num_descs_in_pool
= plat_data
->pool_size
/MV_XOR_SLOT_SIZE
;
602 /* Allocate descriptor slots */
603 idx
= mv_chan
->slots_allocated
;
604 while (idx
< num_descs_in_pool
) {
605 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
607 printk(KERN_INFO
"MV XOR Channel only initialized"
608 " %d descriptor slots", idx
);
611 hw_desc
= (char *) mv_chan
->device
->dma_desc_pool_virt
;
612 slot
->hw_desc
= (void *) &hw_desc
[idx
* MV_XOR_SLOT_SIZE
];
614 dma_async_tx_descriptor_init(&slot
->async_tx
, chan
);
615 slot
->async_tx
.tx_submit
= mv_xor_tx_submit
;
616 INIT_LIST_HEAD(&slot
->chain_node
);
617 INIT_LIST_HEAD(&slot
->slot_node
);
618 INIT_LIST_HEAD(&slot
->async_tx
.tx_list
);
619 hw_desc
= (char *) mv_chan
->device
->dma_desc_pool
;
620 slot
->async_tx
.phys
=
621 (dma_addr_t
) &hw_desc
[idx
* MV_XOR_SLOT_SIZE
];
624 spin_lock_bh(&mv_chan
->lock
);
625 mv_chan
->slots_allocated
= idx
;
626 list_add_tail(&slot
->slot_node
, &mv_chan
->all_slots
);
627 spin_unlock_bh(&mv_chan
->lock
);
630 if (mv_chan
->slots_allocated
&& !mv_chan
->last_used
)
631 mv_chan
->last_used
= list_entry(mv_chan
->all_slots
.next
,
632 struct mv_xor_desc_slot
,
635 dev_dbg(mv_chan
->device
->common
.dev
,
636 "allocated %d descriptor slots last_used: %p\n",
637 mv_chan
->slots_allocated
, mv_chan
->last_used
);
639 return mv_chan
->slots_allocated
? : -ENOMEM
;
642 static struct dma_async_tx_descriptor
*
643 mv_xor_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
644 size_t len
, unsigned long flags
)
646 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
647 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
650 dev_dbg(mv_chan
->device
->common
.dev
,
651 "%s dest: %x src %x len: %u flags: %ld\n",
652 __func__
, dest
, src
, len
, flags
);
653 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
656 BUG_ON(unlikely(len
> MV_XOR_MAX_BYTE_COUNT
));
658 spin_lock_bh(&mv_chan
->lock
);
659 slot_cnt
= mv_chan_memcpy_slot_count(len
);
660 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
662 sw_desc
->type
= DMA_MEMCPY
;
663 sw_desc
->async_tx
.flags
= flags
;
664 grp_start
= sw_desc
->group_head
;
665 mv_desc_init(grp_start
, flags
);
666 mv_desc_set_byte_count(grp_start
, len
);
667 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
668 mv_desc_set_src_addr(grp_start
, 0, src
);
669 sw_desc
->unmap_src_cnt
= 1;
670 sw_desc
->unmap_len
= len
;
672 spin_unlock_bh(&mv_chan
->lock
);
674 dev_dbg(mv_chan
->device
->common
.dev
,
675 "%s sw_desc %p async_tx %p\n",
676 __func__
, sw_desc
, sw_desc
? &sw_desc
->async_tx
: 0);
678 return sw_desc
? &sw_desc
->async_tx
: NULL
;
681 static struct dma_async_tx_descriptor
*
682 mv_xor_prep_dma_memset(struct dma_chan
*chan
, dma_addr_t dest
, int value
,
683 size_t len
, unsigned long flags
)
685 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
686 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
689 dev_dbg(mv_chan
->device
->common
.dev
,
690 "%s dest: %x len: %u flags: %ld\n",
691 __func__
, dest
, len
, flags
);
692 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
695 BUG_ON(unlikely(len
> MV_XOR_MAX_BYTE_COUNT
));
697 spin_lock_bh(&mv_chan
->lock
);
698 slot_cnt
= mv_chan_memset_slot_count(len
);
699 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
701 sw_desc
->type
= DMA_MEMSET
;
702 sw_desc
->async_tx
.flags
= flags
;
703 grp_start
= sw_desc
->group_head
;
704 mv_desc_init(grp_start
, flags
);
705 mv_desc_set_byte_count(grp_start
, len
);
706 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
707 mv_desc_set_block_fill_val(grp_start
, value
);
708 sw_desc
->unmap_src_cnt
= 1;
709 sw_desc
->unmap_len
= len
;
711 spin_unlock_bh(&mv_chan
->lock
);
712 dev_dbg(mv_chan
->device
->common
.dev
,
713 "%s sw_desc %p async_tx %p \n",
714 __func__
, sw_desc
, &sw_desc
->async_tx
);
715 return sw_desc
? &sw_desc
->async_tx
: NULL
;
718 static struct dma_async_tx_descriptor
*
719 mv_xor_prep_dma_xor(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
720 unsigned int src_cnt
, size_t len
, unsigned long flags
)
722 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
723 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
726 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
729 BUG_ON(unlikely(len
> MV_XOR_MAX_BYTE_COUNT
));
731 dev_dbg(mv_chan
->device
->common
.dev
,
732 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
733 __func__
, src_cnt
, len
, dest
, flags
);
735 spin_lock_bh(&mv_chan
->lock
);
736 slot_cnt
= mv_chan_xor_slot_count(len
, src_cnt
);
737 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
739 sw_desc
->type
= DMA_XOR
;
740 sw_desc
->async_tx
.flags
= flags
;
741 grp_start
= sw_desc
->group_head
;
742 mv_desc_init(grp_start
, flags
);
743 /* the byte count field is the same as in memcpy desc*/
744 mv_desc_set_byte_count(grp_start
, len
);
745 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
746 sw_desc
->unmap_src_cnt
= src_cnt
;
747 sw_desc
->unmap_len
= len
;
749 mv_desc_set_src_addr(grp_start
, src_cnt
, src
[src_cnt
]);
751 spin_unlock_bh(&mv_chan
->lock
);
752 dev_dbg(mv_chan
->device
->common
.dev
,
753 "%s sw_desc %p async_tx %p \n",
754 __func__
, sw_desc
, &sw_desc
->async_tx
);
755 return sw_desc
? &sw_desc
->async_tx
: NULL
;
758 static void mv_xor_free_chan_resources(struct dma_chan
*chan
)
760 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
761 struct mv_xor_desc_slot
*iter
, *_iter
;
762 int in_use_descs
= 0;
764 mv_xor_slot_cleanup(mv_chan
);
766 spin_lock_bh(&mv_chan
->lock
);
767 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
770 list_del(&iter
->chain_node
);
772 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
775 list_del(&iter
->completed_node
);
777 list_for_each_entry_safe_reverse(
778 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
779 list_del(&iter
->slot_node
);
781 mv_chan
->slots_allocated
--;
783 mv_chan
->last_used
= NULL
;
785 dev_dbg(mv_chan
->device
->common
.dev
, "%s slots_allocated %d\n",
786 __func__
, mv_chan
->slots_allocated
);
787 spin_unlock_bh(&mv_chan
->lock
);
790 dev_err(mv_chan
->device
->common
.dev
,
791 "freeing %d in use descriptors!\n", in_use_descs
);
795 * mv_xor_is_complete - poll the status of an XOR transaction
796 * @chan: XOR channel handle
797 * @cookie: XOR transaction identifier
799 static enum dma_status
mv_xor_is_complete(struct dma_chan
*chan
,
804 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
805 dma_cookie_t last_used
;
806 dma_cookie_t last_complete
;
809 last_used
= chan
->cookie
;
810 last_complete
= mv_chan
->completed_cookie
;
811 mv_chan
->is_complete_cookie
= cookie
;
813 *done
= last_complete
;
817 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
818 if (ret
== DMA_SUCCESS
) {
819 mv_xor_clean_completed_slots(mv_chan
);
822 mv_xor_slot_cleanup(mv_chan
);
824 last_used
= chan
->cookie
;
825 last_complete
= mv_chan
->completed_cookie
;
828 *done
= last_complete
;
832 return dma_async_is_complete(cookie
, last_complete
, last_used
);
835 static void mv_dump_xor_regs(struct mv_xor_chan
*chan
)
839 val
= __raw_readl(XOR_CONFIG(chan
));
840 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
841 "config 0x%08x.\n", val
);
843 val
= __raw_readl(XOR_ACTIVATION(chan
));
844 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
845 "activation 0x%08x.\n", val
);
847 val
= __raw_readl(XOR_INTR_CAUSE(chan
));
848 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
849 "intr cause 0x%08x.\n", val
);
851 val
= __raw_readl(XOR_INTR_MASK(chan
));
852 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
853 "intr mask 0x%08x.\n", val
);
855 val
= __raw_readl(XOR_ERROR_CAUSE(chan
));
856 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
857 "error cause 0x%08x.\n", val
);
859 val
= __raw_readl(XOR_ERROR_ADDR(chan
));
860 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
861 "error addr 0x%08x.\n", val
);
864 static void mv_xor_err_interrupt_handler(struct mv_xor_chan
*chan
,
867 if (intr_cause
& (1 << 4)) {
868 dev_dbg(chan
->device
->common
.dev
,
869 "ignore this error\n");
873 dev_printk(KERN_ERR
, chan
->device
->common
.dev
,
874 "error on chan %d. intr cause 0x%08x.\n",
875 chan
->idx
, intr_cause
);
877 mv_dump_xor_regs(chan
);
881 static irqreturn_t
mv_xor_interrupt_handler(int irq
, void *data
)
883 struct mv_xor_chan
*chan
= data
;
884 u32 intr_cause
= mv_chan_get_intr_cause(chan
);
886 dev_dbg(chan
->device
->common
.dev
, "intr cause %x\n", intr_cause
);
888 if (mv_is_err_intr(intr_cause
))
889 mv_xor_err_interrupt_handler(chan
, intr_cause
);
891 tasklet_schedule(&chan
->irq_tasklet
);
893 mv_xor_device_clear_eoc_cause(chan
);
898 static void mv_xor_issue_pending(struct dma_chan
*chan
)
900 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
902 if (mv_chan
->pending
>= MV_XOR_THRESHOLD
) {
903 mv_chan
->pending
= 0;
904 mv_chan_activate(mv_chan
);
909 * Perform a transaction to verify the HW works.
911 #define MV_XOR_TEST_SIZE 2000
913 static int __devinit
mv_xor_memcpy_self_test(struct mv_xor_device
*device
)
917 dma_addr_t src_dma
, dest_dma
;
918 struct dma_chan
*dma_chan
;
920 struct dma_async_tx_descriptor
*tx
;
922 struct mv_xor_chan
*mv_chan
;
924 src
= kmalloc(sizeof(u8
) * MV_XOR_TEST_SIZE
, GFP_KERNEL
);
928 dest
= kzalloc(sizeof(u8
) * MV_XOR_TEST_SIZE
, GFP_KERNEL
);
934 /* Fill in src buffer */
935 for (i
= 0; i
< MV_XOR_TEST_SIZE
; i
++)
936 ((u8
*) src
)[i
] = (u8
)i
;
938 /* Start copy, using first DMA channel */
939 dma_chan
= container_of(device
->common
.channels
.next
,
942 if (mv_xor_alloc_chan_resources(dma_chan
, NULL
) < 1) {
947 dest_dma
= dma_map_single(dma_chan
->device
->dev
, dest
,
948 MV_XOR_TEST_SIZE
, DMA_FROM_DEVICE
);
950 src_dma
= dma_map_single(dma_chan
->device
->dev
, src
,
951 MV_XOR_TEST_SIZE
, DMA_TO_DEVICE
);
953 tx
= mv_xor_prep_dma_memcpy(dma_chan
, dest_dma
, src_dma
,
954 MV_XOR_TEST_SIZE
, 0);
955 cookie
= mv_xor_tx_submit(tx
);
956 mv_xor_issue_pending(dma_chan
);
960 if (mv_xor_is_complete(dma_chan
, cookie
, NULL
, NULL
) !=
962 dev_printk(KERN_ERR
, dma_chan
->device
->dev
,
963 "Self-test copy timed out, disabling\n");
968 mv_chan
= to_mv_xor_chan(dma_chan
);
969 dma_sync_single_for_cpu(&mv_chan
->device
->pdev
->dev
, dest_dma
,
970 MV_XOR_TEST_SIZE
, DMA_FROM_DEVICE
);
971 if (memcmp(src
, dest
, MV_XOR_TEST_SIZE
)) {
972 dev_printk(KERN_ERR
, dma_chan
->device
->dev
,
973 "Self-test copy failed compare, disabling\n");
979 mv_xor_free_chan_resources(dma_chan
);
986 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
988 mv_xor_xor_self_test(struct mv_xor_device
*device
)
992 struct page
*xor_srcs
[MV_XOR_NUM_SRC_TEST
];
993 dma_addr_t dma_srcs
[MV_XOR_NUM_SRC_TEST
];
995 struct dma_async_tx_descriptor
*tx
;
996 struct dma_chan
*dma_chan
;
1001 struct mv_xor_chan
*mv_chan
;
1003 for (src_idx
= 0; src_idx
< MV_XOR_NUM_SRC_TEST
; src_idx
++) {
1004 xor_srcs
[src_idx
] = alloc_page(GFP_KERNEL
);
1005 if (!xor_srcs
[src_idx
])
1007 __free_page(xor_srcs
[src_idx
]);
1012 dest
= alloc_page(GFP_KERNEL
);
1015 __free_page(xor_srcs
[src_idx
]);
1019 /* Fill in src buffers */
1020 for (src_idx
= 0; src_idx
< MV_XOR_NUM_SRC_TEST
; src_idx
++) {
1021 u8
*ptr
= page_address(xor_srcs
[src_idx
]);
1022 for (i
= 0; i
< PAGE_SIZE
; i
++)
1023 ptr
[i
] = (1 << src_idx
);
1026 for (src_idx
= 0; src_idx
< MV_XOR_NUM_SRC_TEST
; src_idx
++)
1027 cmp_byte
^= (u8
) (1 << src_idx
);
1029 cmp_word
= (cmp_byte
<< 24) | (cmp_byte
<< 16) |
1030 (cmp_byte
<< 8) | cmp_byte
;
1032 memset(page_address(dest
), 0, PAGE_SIZE
);
1034 dma_chan
= container_of(device
->common
.channels
.next
,
1037 if (mv_xor_alloc_chan_resources(dma_chan
, NULL
) < 1) {
1043 dest_dma
= dma_map_page(dma_chan
->device
->dev
, dest
, 0, PAGE_SIZE
,
1046 for (i
= 0; i
< MV_XOR_NUM_SRC_TEST
; i
++)
1047 dma_srcs
[i
] = dma_map_page(dma_chan
->device
->dev
, xor_srcs
[i
],
1048 0, PAGE_SIZE
, DMA_TO_DEVICE
);
1050 tx
= mv_xor_prep_dma_xor(dma_chan
, dest_dma
, dma_srcs
,
1051 MV_XOR_NUM_SRC_TEST
, PAGE_SIZE
, 0);
1053 cookie
= mv_xor_tx_submit(tx
);
1054 mv_xor_issue_pending(dma_chan
);
1058 if (mv_xor_is_complete(dma_chan
, cookie
, NULL
, NULL
) !=
1060 dev_printk(KERN_ERR
, dma_chan
->device
->dev
,
1061 "Self-test xor timed out, disabling\n");
1063 goto free_resources
;
1066 mv_chan
= to_mv_xor_chan(dma_chan
);
1067 dma_sync_single_for_cpu(&mv_chan
->device
->pdev
->dev
, dest_dma
,
1068 PAGE_SIZE
, DMA_FROM_DEVICE
);
1069 for (i
= 0; i
< (PAGE_SIZE
/ sizeof(u32
)); i
++) {
1070 u32
*ptr
= page_address(dest
);
1071 if (ptr
[i
] != cmp_word
) {
1072 dev_printk(KERN_ERR
, dma_chan
->device
->dev
,
1073 "Self-test xor failed compare, disabling."
1074 " index %d, data %x, expected %x\n", i
,
1077 goto free_resources
;
1082 mv_xor_free_chan_resources(dma_chan
);
1084 src_idx
= MV_XOR_NUM_SRC_TEST
;
1086 __free_page(xor_srcs
[src_idx
]);
1091 static int __devexit
mv_xor_remove(struct platform_device
*dev
)
1093 struct mv_xor_device
*device
= platform_get_drvdata(dev
);
1094 struct dma_chan
*chan
, *_chan
;
1095 struct mv_xor_chan
*mv_chan
;
1096 struct mv_xor_platform_data
*plat_data
= dev
->dev
.platform_data
;
1098 dma_async_device_unregister(&device
->common
);
1100 dma_free_coherent(&dev
->dev
, plat_data
->pool_size
,
1101 device
->dma_desc_pool_virt
, device
->dma_desc_pool
);
1103 list_for_each_entry_safe(chan
, _chan
, &device
->common
.channels
,
1105 mv_chan
= to_mv_xor_chan(chan
);
1106 list_del(&chan
->device_node
);
1112 static int __devinit
mv_xor_probe(struct platform_device
*pdev
)
1116 struct mv_xor_device
*adev
;
1117 struct mv_xor_chan
*mv_chan
;
1118 struct dma_device
*dma_dev
;
1119 struct mv_xor_platform_data
*plat_data
= pdev
->dev
.platform_data
;
1122 adev
= devm_kzalloc(&pdev
->dev
, sizeof(*adev
), GFP_KERNEL
);
1126 dma_dev
= &adev
->common
;
1128 /* allocate coherent memory for hardware descriptors
1129 * note: writecombine gives slightly better performance, but
1130 * requires that we explicitly flush the writes
1132 adev
->dma_desc_pool_virt
= dma_alloc_writecombine(&pdev
->dev
,
1133 plat_data
->pool_size
,
1134 &adev
->dma_desc_pool
,
1136 if (!adev
->dma_desc_pool_virt
)
1139 adev
->id
= plat_data
->hw_id
;
1141 /* discover transaction capabilites from the platform data */
1142 dma_dev
->cap_mask
= plat_data
->cap_mask
;
1144 platform_set_drvdata(pdev
, adev
);
1146 adev
->shared
= platform_get_drvdata(plat_data
->shared
);
1148 INIT_LIST_HEAD(&dma_dev
->channels
);
1150 /* set base routines */
1151 dma_dev
->device_alloc_chan_resources
= mv_xor_alloc_chan_resources
;
1152 dma_dev
->device_free_chan_resources
= mv_xor_free_chan_resources
;
1153 dma_dev
->device_is_tx_complete
= mv_xor_is_complete
;
1154 dma_dev
->device_issue_pending
= mv_xor_issue_pending
;
1155 dma_dev
->dev
= &pdev
->dev
;
1157 /* set prep routines based on capability */
1158 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
))
1159 dma_dev
->device_prep_dma_memcpy
= mv_xor_prep_dma_memcpy
;
1160 if (dma_has_cap(DMA_MEMSET
, dma_dev
->cap_mask
))
1161 dma_dev
->device_prep_dma_memset
= mv_xor_prep_dma_memset
;
1162 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1163 dma_dev
->max_xor
= 8; ;
1164 dma_dev
->device_prep_dma_xor
= mv_xor_prep_dma_xor
;
1167 mv_chan
= devm_kzalloc(&pdev
->dev
, sizeof(*mv_chan
), GFP_KERNEL
);
1172 mv_chan
->device
= adev
;
1173 mv_chan
->idx
= plat_data
->hw_id
;
1174 mv_chan
->mmr_base
= adev
->shared
->xor_base
;
1176 if (!mv_chan
->mmr_base
) {
1180 tasklet_init(&mv_chan
->irq_tasklet
, mv_xor_tasklet
, (unsigned long)
1183 /* clear errors before enabling interrupts */
1184 mv_xor_device_clear_err_status(mv_chan
);
1186 irq
= platform_get_irq(pdev
, 0);
1191 ret
= devm_request_irq(&pdev
->dev
, irq
,
1192 mv_xor_interrupt_handler
,
1193 0, dev_name(&pdev
->dev
), mv_chan
);
1197 mv_chan_unmask_interrupts(mv_chan
);
1199 mv_set_mode(mv_chan
, DMA_MEMCPY
);
1201 spin_lock_init(&mv_chan
->lock
);
1202 INIT_LIST_HEAD(&mv_chan
->chain
);
1203 INIT_LIST_HEAD(&mv_chan
->completed_slots
);
1204 INIT_LIST_HEAD(&mv_chan
->all_slots
);
1205 INIT_RCU_HEAD(&mv_chan
->common
.rcu
);
1206 mv_chan
->common
.device
= dma_dev
;
1208 list_add_tail(&mv_chan
->common
.device_node
, &dma_dev
->channels
);
1210 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
)) {
1211 ret
= mv_xor_memcpy_self_test(adev
);
1212 dev_dbg(&pdev
->dev
, "memcpy self test returned %d\n", ret
);
1217 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1218 ret
= mv_xor_xor_self_test(adev
);
1219 dev_dbg(&pdev
->dev
, "xor self test returned %d\n", ret
);
1224 dev_printk(KERN_INFO
, &pdev
->dev
, "Marvell XOR: "
1226 dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
) ? "xor " : "",
1227 dma_has_cap(DMA_MEMSET
, dma_dev
->cap_mask
) ? "fill " : "",
1228 dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
) ? "cpy " : "",
1229 dma_has_cap(DMA_INTERRUPT
, dma_dev
->cap_mask
) ? "intr " : "");
1231 dma_async_device_register(dma_dev
);
1235 dma_free_coherent(&adev
->pdev
->dev
, plat_data
->pool_size
,
1236 adev
->dma_desc_pool_virt
, adev
->dma_desc_pool
);
1242 mv_xor_conf_mbus_windows(struct mv_xor_shared_private
*msp
,
1243 struct mbus_dram_target_info
*dram
)
1245 void __iomem
*base
= msp
->xor_base
;
1249 for (i
= 0; i
< 8; i
++) {
1250 writel(0, base
+ WINDOW_BASE(i
));
1251 writel(0, base
+ WINDOW_SIZE(i
));
1253 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
1256 for (i
= 0; i
< dram
->num_cs
; i
++) {
1257 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
1259 writel((cs
->base
& 0xffff0000) |
1260 (cs
->mbus_attr
<< 8) |
1261 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
1262 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
1264 win_enable
|= (1 << i
);
1265 win_enable
|= 3 << (16 + (2 * i
));
1268 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(0));
1269 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(1));
1272 static struct platform_driver mv_xor_driver
= {
1273 .probe
= mv_xor_probe
,
1274 .remove
= mv_xor_remove
,
1276 .owner
= THIS_MODULE
,
1277 .name
= MV_XOR_NAME
,
1281 static int mv_xor_shared_probe(struct platform_device
*pdev
)
1283 struct mv_xor_platform_shared_data
*msd
= pdev
->dev
.platform_data
;
1284 struct mv_xor_shared_private
*msp
;
1285 struct resource
*res
;
1287 dev_printk(KERN_NOTICE
, &pdev
->dev
, "Marvell shared XOR driver\n");
1289 msp
= devm_kzalloc(&pdev
->dev
, sizeof(*msp
), GFP_KERNEL
);
1293 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1297 msp
->xor_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1298 res
->end
- res
->start
+ 1);
1302 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1306 msp
->xor_high_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1307 res
->end
- res
->start
+ 1);
1308 if (!msp
->xor_high_base
)
1311 platform_set_drvdata(pdev
, msp
);
1314 * (Re-)program MBUS remapping windows if we are asked to.
1316 if (msd
!= NULL
&& msd
->dram
!= NULL
)
1317 mv_xor_conf_mbus_windows(msp
, msd
->dram
);
1322 static int mv_xor_shared_remove(struct platform_device
*pdev
)
1327 static struct platform_driver mv_xor_shared_driver
= {
1328 .probe
= mv_xor_shared_probe
,
1329 .remove
= mv_xor_shared_remove
,
1331 .owner
= THIS_MODULE
,
1332 .name
= MV_XOR_SHARED_NAME
,
1337 static int __init
mv_xor_init(void)
1341 rc
= platform_driver_register(&mv_xor_shared_driver
);
1343 rc
= platform_driver_register(&mv_xor_driver
);
1345 platform_driver_unregister(&mv_xor_shared_driver
);
1349 module_init(mv_xor_init
);
1351 /* it's currently unsafe to unload this module */
1353 static void __exit
mv_xor_exit(void)
1355 platform_driver_unregister(&mv_xor_driver
);
1356 platform_driver_unregister(&mv_xor_shared_driver
);
1360 module_exit(mv_xor_exit
);
1363 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1364 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1365 MODULE_LICENSE("GPL");