2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
56 * Support routines for v3+ hardware
59 #include <linux/pci.h>
60 #include <linux/dmaengine.h>
61 #include <linux/dma-mapping.h>
62 #include "registers.h"
67 /* ioat hardware assumes at least two sources for raid operations */
68 #define src_cnt_to_sw(x) ((x) + 2)
69 #define src_cnt_to_hw(x) ((x) - 2)
71 /* provide a lookup table for setting the source address in the base or
72 * extended descriptor of an xor or pq descriptor
74 static const u8 xor_idx_to_desc __read_mostly
= 0xd0;
75 static const u8 xor_idx_to_field
[] __read_mostly
= { 1, 4, 5, 6, 7, 0, 1, 2 };
76 static const u8 pq_idx_to_desc __read_mostly
= 0xf8;
77 static const u8 pq_idx_to_field
[] __read_mostly
= { 1, 4, 5, 0, 1, 2, 4, 5 };
79 static dma_addr_t
xor_get_src(struct ioat_raw_descriptor
*descs
[2], int idx
)
81 struct ioat_raw_descriptor
*raw
= descs
[xor_idx_to_desc
>> idx
& 1];
83 return raw
->field
[xor_idx_to_field
[idx
]];
86 static void xor_set_src(struct ioat_raw_descriptor
*descs
[2],
87 dma_addr_t addr
, u32 offset
, int idx
)
89 struct ioat_raw_descriptor
*raw
= descs
[xor_idx_to_desc
>> idx
& 1];
91 raw
->field
[xor_idx_to_field
[idx
]] = addr
+ offset
;
94 static dma_addr_t
pq_get_src(struct ioat_raw_descriptor
*descs
[2], int idx
)
96 struct ioat_raw_descriptor
*raw
= descs
[pq_idx_to_desc
>> idx
& 1];
98 return raw
->field
[pq_idx_to_field
[idx
]];
101 static void pq_set_src(struct ioat_raw_descriptor
*descs
[2],
102 dma_addr_t addr
, u32 offset
, u8 coef
, int idx
)
104 struct ioat_pq_descriptor
*pq
= (struct ioat_pq_descriptor
*) descs
[0];
105 struct ioat_raw_descriptor
*raw
= descs
[pq_idx_to_desc
>> idx
& 1];
107 raw
->field
[pq_idx_to_field
[idx
]] = addr
+ offset
;
108 pq
->coef
[idx
] = coef
;
111 static void ioat3_dma_unmap(struct ioat2_dma_chan
*ioat
,
112 struct ioat_ring_ent
*desc
, int idx
)
114 struct ioat_chan_common
*chan
= &ioat
->base
;
115 struct pci_dev
*pdev
= chan
->device
->pdev
;
116 size_t len
= desc
->len
;
117 size_t offset
= len
- desc
->hw
->size
;
118 struct dma_async_tx_descriptor
*tx
= &desc
->txd
;
119 enum dma_ctrl_flags flags
= tx
->flags
;
121 switch (desc
->hw
->ctl_f
.op
) {
123 if (!desc
->hw
->ctl_f
.null
) /* skip 'interrupt' ops */
124 ioat_dma_unmap(chan
, flags
, len
, desc
->hw
);
127 struct ioat_fill_descriptor
*hw
= desc
->fill
;
129 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
))
130 ioat_unmap(pdev
, hw
->dst_addr
- offset
, len
,
131 PCI_DMA_FROMDEVICE
, flags
, 1);
134 case IOAT_OP_XOR_VAL
:
136 struct ioat_xor_descriptor
*xor = desc
->xor;
137 struct ioat_ring_ent
*ext
;
138 struct ioat_xor_ext_descriptor
*xor_ex
= NULL
;
139 int src_cnt
= src_cnt_to_sw(xor->ctl_f
.src_cnt
);
140 struct ioat_raw_descriptor
*descs
[2];
144 ext
= ioat2_get_ring_ent(ioat
, idx
+ 1);
145 xor_ex
= ext
->xor_ex
;
148 if (!(flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
149 descs
[0] = (struct ioat_raw_descriptor
*) xor;
150 descs
[1] = (struct ioat_raw_descriptor
*) xor_ex
;
151 for (i
= 0; i
< src_cnt
; i
++) {
152 dma_addr_t src
= xor_get_src(descs
, i
);
154 ioat_unmap(pdev
, src
- offset
, len
,
155 PCI_DMA_TODEVICE
, flags
, 0);
158 /* dest is a source in xor validate operations */
159 if (xor->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
160 ioat_unmap(pdev
, xor->dst_addr
- offset
, len
,
161 PCI_DMA_TODEVICE
, flags
, 1);
166 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
))
167 ioat_unmap(pdev
, xor->dst_addr
- offset
, len
,
168 PCI_DMA_FROMDEVICE
, flags
, 1);
173 struct ioat_pq_descriptor
*pq
= desc
->pq
;
174 struct ioat_ring_ent
*ext
;
175 struct ioat_pq_ext_descriptor
*pq_ex
= NULL
;
176 int src_cnt
= src_cnt_to_sw(pq
->ctl_f
.src_cnt
);
177 struct ioat_raw_descriptor
*descs
[2];
181 ext
= ioat2_get_ring_ent(ioat
, idx
+ 1);
185 /* in the 'continue' case don't unmap the dests as sources */
186 if (dmaf_p_disabled_continue(flags
))
188 else if (dmaf_continue(flags
))
191 if (!(flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
192 descs
[0] = (struct ioat_raw_descriptor
*) pq
;
193 descs
[1] = (struct ioat_raw_descriptor
*) pq_ex
;
194 for (i
= 0; i
< src_cnt
; i
++) {
195 dma_addr_t src
= pq_get_src(descs
, i
);
197 ioat_unmap(pdev
, src
- offset
, len
,
198 PCI_DMA_TODEVICE
, flags
, 0);
201 /* the dests are sources in pq validate operations */
202 if (pq
->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
203 if (!(flags
& DMA_PREP_PQ_DISABLE_P
))
204 ioat_unmap(pdev
, pq
->p_addr
- offset
,
205 len
, PCI_DMA_TODEVICE
, flags
, 0);
206 if (!(flags
& DMA_PREP_PQ_DISABLE_Q
))
207 ioat_unmap(pdev
, pq
->q_addr
- offset
,
208 len
, PCI_DMA_TODEVICE
, flags
, 0);
213 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
214 if (!(flags
& DMA_PREP_PQ_DISABLE_P
))
215 ioat_unmap(pdev
, pq
->p_addr
- offset
, len
,
216 PCI_DMA_BIDIRECTIONAL
, flags
, 1);
217 if (!(flags
& DMA_PREP_PQ_DISABLE_Q
))
218 ioat_unmap(pdev
, pq
->q_addr
- offset
, len
,
219 PCI_DMA_BIDIRECTIONAL
, flags
, 1);
224 dev_err(&pdev
->dev
, "%s: unknown op type: %#x\n",
225 __func__
, desc
->hw
->ctl_f
.op
);
229 static bool desc_has_ext(struct ioat_ring_ent
*desc
)
231 struct ioat_dma_descriptor
*hw
= desc
->hw
;
233 if (hw
->ctl_f
.op
== IOAT_OP_XOR
||
234 hw
->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
235 struct ioat_xor_descriptor
*xor = desc
->xor;
237 if (src_cnt_to_sw(xor->ctl_f
.src_cnt
) > 5)
239 } else if (hw
->ctl_f
.op
== IOAT_OP_PQ
||
240 hw
->ctl_f
.op
== IOAT_OP_PQ_VAL
) {
241 struct ioat_pq_descriptor
*pq
= desc
->pq
;
243 if (src_cnt_to_sw(pq
->ctl_f
.src_cnt
) > 3)
251 * __cleanup - reclaim used descriptors
252 * @ioat: channel (ring) to clean
254 * The difference from the dma_v2.c __cleanup() is that this routine
255 * handles extended descriptors and dma-unmapping raid operations.
257 static void __cleanup(struct ioat2_dma_chan
*ioat
, unsigned long phys_complete
)
259 struct ioat_chan_common
*chan
= &ioat
->base
;
260 struct ioat_ring_ent
*desc
;
261 bool seen_current
= false;
265 dev_dbg(to_dev(chan
), "%s: head: %#x tail: %#x issued: %#x\n",
266 __func__
, ioat
->head
, ioat
->tail
, ioat
->issued
);
268 active
= ioat2_ring_active(ioat
);
269 for (i
= 0; i
< active
&& !seen_current
; i
++) {
270 struct dma_async_tx_descriptor
*tx
;
272 prefetch(ioat2_get_ring_ent(ioat
, ioat
->tail
+ i
+ 1));
273 desc
= ioat2_get_ring_ent(ioat
, ioat
->tail
+ i
);
274 dump_desc_dbg(ioat
, desc
);
277 chan
->completed_cookie
= tx
->cookie
;
278 ioat3_dma_unmap(ioat
, desc
, ioat
->tail
+ i
);
281 tx
->callback(tx
->callback_param
);
286 if (tx
->phys
== phys_complete
)
289 /* skip extended descriptors */
290 if (desc_has_ext(desc
)) {
291 BUG_ON(i
+ 1 >= active
);
296 BUG_ON(!seen_current
); /* no active descs have written a completion? */
297 chan
->last_completion
= phys_complete
;
298 if (ioat
->head
== ioat
->tail
) {
299 dev_dbg(to_dev(chan
), "%s: cancel completion timeout\n",
301 clear_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
302 mod_timer(&chan
->timer
, jiffies
+ IDLE_TIMEOUT
);
306 static void ioat3_cleanup(struct ioat2_dma_chan
*ioat
)
308 struct ioat_chan_common
*chan
= &ioat
->base
;
309 unsigned long phys_complete
;
311 prefetch(chan
->completion
);
313 if (!spin_trylock_bh(&chan
->cleanup_lock
))
316 if (!ioat_cleanup_preamble(chan
, &phys_complete
)) {
317 spin_unlock_bh(&chan
->cleanup_lock
);
321 if (!spin_trylock_bh(&ioat
->ring_lock
)) {
322 spin_unlock_bh(&chan
->cleanup_lock
);
326 __cleanup(ioat
, phys_complete
);
328 spin_unlock_bh(&ioat
->ring_lock
);
329 spin_unlock_bh(&chan
->cleanup_lock
);
332 static void ioat3_cleanup_tasklet(unsigned long data
)
334 struct ioat2_dma_chan
*ioat
= (void *) data
;
337 writew(IOAT_CHANCTRL_RUN
, ioat
->base
.reg_base
+ IOAT_CHANCTRL_OFFSET
);
340 static void ioat3_restart_channel(struct ioat2_dma_chan
*ioat
)
342 struct ioat_chan_common
*chan
= &ioat
->base
;
343 unsigned long phys_complete
;
346 status
= ioat_chansts(chan
);
347 if (is_ioat_active(status
) || is_ioat_idle(status
))
349 while (is_ioat_active(status
) || is_ioat_idle(status
)) {
350 status
= ioat_chansts(chan
);
354 if (ioat_cleanup_preamble(chan
, &phys_complete
))
355 __cleanup(ioat
, phys_complete
);
357 __ioat2_restart_chan(ioat
);
360 static void ioat3_timer_event(unsigned long data
)
362 struct ioat2_dma_chan
*ioat
= (void *) data
;
363 struct ioat_chan_common
*chan
= &ioat
->base
;
365 spin_lock_bh(&chan
->cleanup_lock
);
366 if (test_bit(IOAT_COMPLETION_PENDING
, &chan
->state
)) {
367 unsigned long phys_complete
;
370 spin_lock_bh(&ioat
->ring_lock
);
371 status
= ioat_chansts(chan
);
373 /* when halted due to errors check for channel
374 * programming errors before advancing the completion state
376 if (is_ioat_halted(status
)) {
379 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
380 dev_err(to_dev(chan
), "%s: Channel halted (%x)\n",
382 BUG_ON(is_ioat_bug(chanerr
));
385 /* if we haven't made progress and we have already
386 * acknowledged a pending completion once, then be more
387 * forceful with a restart
389 if (ioat_cleanup_preamble(chan
, &phys_complete
))
390 __cleanup(ioat
, phys_complete
);
391 else if (test_bit(IOAT_COMPLETION_ACK
, &chan
->state
))
392 ioat3_restart_channel(ioat
);
394 set_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
395 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
397 spin_unlock_bh(&ioat
->ring_lock
);
401 /* if the ring is idle, empty, and oversized try to step
404 spin_lock_bh(&ioat
->ring_lock
);
405 active
= ioat2_ring_active(ioat
);
406 if (active
== 0 && ioat
->alloc_order
> ioat_get_alloc_order())
407 reshape_ring(ioat
, ioat
->alloc_order
-1);
408 spin_unlock_bh(&ioat
->ring_lock
);
410 /* keep shrinking until we get back to our minimum
413 if (ioat
->alloc_order
> ioat_get_alloc_order())
414 mod_timer(&chan
->timer
, jiffies
+ IDLE_TIMEOUT
);
416 spin_unlock_bh(&chan
->cleanup_lock
);
419 static enum dma_status
420 ioat3_is_complete(struct dma_chan
*c
, dma_cookie_t cookie
,
421 dma_cookie_t
*done
, dma_cookie_t
*used
)
423 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
425 if (ioat_is_complete(c
, cookie
, done
, used
) == DMA_SUCCESS
)
430 return ioat_is_complete(c
, cookie
, done
, used
);
433 static struct dma_async_tx_descriptor
*
434 ioat3_prep_memset_lock(struct dma_chan
*c
, dma_addr_t dest
, int value
,
435 size_t len
, unsigned long flags
)
437 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
438 struct ioat_ring_ent
*desc
;
439 size_t total_len
= len
;
440 struct ioat_fill_descriptor
*fill
;
442 u64 src_data
= (0x0101010101010101ULL
) * (value
& 0xff);
446 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
447 if (likely(num_descs
) &&
448 ioat2_alloc_and_lock(&idx
, ioat
, num_descs
) == 0)
454 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
456 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
459 fill
->size
= xfer_size
;
460 fill
->src_data
= src_data
;
461 fill
->dst_addr
= dest
;
463 fill
->ctl_f
.op
= IOAT_OP_FILL
;
467 dump_desc_dbg(ioat
, desc
);
468 } while (++i
< num_descs
);
470 desc
->txd
.flags
= flags
;
471 desc
->len
= total_len
;
472 fill
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
473 fill
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
474 fill
->ctl_f
.compl_write
= 1;
475 dump_desc_dbg(ioat
, desc
);
477 /* we leave the channel locked to ensure in order submission */
481 static struct dma_async_tx_descriptor
*
482 __ioat3_prep_xor_lock(struct dma_chan
*c
, enum sum_check_flags
*result
,
483 dma_addr_t dest
, dma_addr_t
*src
, unsigned int src_cnt
,
484 size_t len
, unsigned long flags
)
486 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
487 struct ioat_ring_ent
*compl_desc
;
488 struct ioat_ring_ent
*desc
;
489 struct ioat_ring_ent
*ext
;
490 size_t total_len
= len
;
491 struct ioat_xor_descriptor
*xor;
492 struct ioat_xor_ext_descriptor
*xor_ex
= NULL
;
493 struct ioat_dma_descriptor
*hw
;
499 u8 op
= result
? IOAT_OP_XOR_VAL
: IOAT_OP_XOR
;
503 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
504 /* we need 2x the number of descriptors to cover greater than 5
513 /* completion writes from the raid engine may pass completion
514 * writes from the legacy engine, so we need one extra null
515 * (legacy) descriptor to ensure all completion writes arrive in
518 if (likely(num_descs
) &&
519 ioat2_alloc_and_lock(&idx
, ioat
, num_descs
+1) == 0)
525 struct ioat_raw_descriptor
*descs
[2];
526 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
529 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
532 /* save a branch by unconditionally retrieving the
533 * extended descriptor xor_set_src() knows to not write
534 * to it in the single descriptor case
536 ext
= ioat2_get_ring_ent(ioat
, idx
+ i
+ 1);
537 xor_ex
= ext
->xor_ex
;
539 descs
[0] = (struct ioat_raw_descriptor
*) xor;
540 descs
[1] = (struct ioat_raw_descriptor
*) xor_ex
;
541 for (s
= 0; s
< src_cnt
; s
++)
542 xor_set_src(descs
, src
[s
], offset
, s
);
543 xor->size
= xfer_size
;
544 xor->dst_addr
= dest
+ offset
;
547 xor->ctl_f
.src_cnt
= src_cnt_to_hw(src_cnt
);
551 dump_desc_dbg(ioat
, desc
);
552 } while ((i
+= 1 + with_ext
) < num_descs
);
554 /* last xor descriptor carries the unmap parameters and fence bit */
555 desc
->txd
.flags
= flags
;
556 desc
->len
= total_len
;
558 desc
->result
= result
;
559 xor->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
561 /* completion descriptor carries interrupt bit */
562 compl_desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
563 compl_desc
->txd
.flags
= flags
& DMA_PREP_INTERRUPT
;
567 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
568 hw
->ctl_f
.compl_write
= 1;
569 hw
->size
= NULL_DESC_BUFFER_SIZE
;
570 dump_desc_dbg(ioat
, compl_desc
);
572 /* we leave the channel locked to ensure in order submission */
573 return &compl_desc
->txd
;
576 static struct dma_async_tx_descriptor
*
577 ioat3_prep_xor(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
578 unsigned int src_cnt
, size_t len
, unsigned long flags
)
580 return __ioat3_prep_xor_lock(chan
, NULL
, dest
, src
, src_cnt
, len
, flags
);
583 struct dma_async_tx_descriptor
*
584 ioat3_prep_xor_val(struct dma_chan
*chan
, dma_addr_t
*src
,
585 unsigned int src_cnt
, size_t len
,
586 enum sum_check_flags
*result
, unsigned long flags
)
588 /* the cleanup routine only sets bits on validate failure, it
589 * does not clear bits on validate success... so clear it here
593 return __ioat3_prep_xor_lock(chan
, result
, src
[0], &src
[1],
594 src_cnt
- 1, len
, flags
);
598 dump_pq_desc_dbg(struct ioat2_dma_chan
*ioat
, struct ioat_ring_ent
*desc
, struct ioat_ring_ent
*ext
)
600 struct device
*dev
= to_dev(&ioat
->base
);
601 struct ioat_pq_descriptor
*pq
= desc
->pq
;
602 struct ioat_pq_ext_descriptor
*pq_ex
= ext
? ext
->pq_ex
: NULL
;
603 struct ioat_raw_descriptor
*descs
[] = { (void *) pq
, (void *) pq_ex
};
604 int src_cnt
= src_cnt_to_sw(pq
->ctl_f
.src_cnt
);
607 dev_dbg(dev
, "desc[%d]: (%#llx->%#llx) flags: %#x"
608 " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
609 desc_id(desc
), (unsigned long long) desc
->txd
.phys
,
610 (unsigned long long) (pq_ex
? pq_ex
->next
: pq
->next
),
611 desc
->txd
.flags
, pq
->size
, pq
->ctl
, pq
->ctl_f
.op
, pq
->ctl_f
.int_en
,
612 pq
->ctl_f
.compl_write
,
613 pq
->ctl_f
.p_disable
? "" : "p", pq
->ctl_f
.q_disable
? "" : "q",
615 for (i
= 0; i
< src_cnt
; i
++)
616 dev_dbg(dev
, "\tsrc[%d]: %#llx coef: %#x\n", i
,
617 (unsigned long long) pq_get_src(descs
, i
), pq
->coef
[i
]);
618 dev_dbg(dev
, "\tP: %#llx\n", pq
->p_addr
);
619 dev_dbg(dev
, "\tQ: %#llx\n", pq
->q_addr
);
622 static struct dma_async_tx_descriptor
*
623 __ioat3_prep_pq_lock(struct dma_chan
*c
, enum sum_check_flags
*result
,
624 const dma_addr_t
*dst
, const dma_addr_t
*src
,
625 unsigned int src_cnt
, const unsigned char *scf
,
626 size_t len
, unsigned long flags
)
628 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
629 struct ioat_chan_common
*chan
= &ioat
->base
;
630 struct ioat_ring_ent
*compl_desc
;
631 struct ioat_ring_ent
*desc
;
632 struct ioat_ring_ent
*ext
;
633 size_t total_len
= len
;
634 struct ioat_pq_descriptor
*pq
;
635 struct ioat_pq_ext_descriptor
*pq_ex
= NULL
;
636 struct ioat_dma_descriptor
*hw
;
642 u8 op
= result
? IOAT_OP_PQ_VAL
: IOAT_OP_PQ
;
644 dev_dbg(to_dev(chan
), "%s\n", __func__
);
645 /* the engine requires at least two sources (we provide
646 * at least 1 implied source in the DMA_PREP_CONTINUE case)
648 BUG_ON(src_cnt
+ dmaf_continue(flags
) < 2);
650 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
651 /* we need 2x the number of descriptors to cover greater than 3
652 * sources (we need 1 extra source in the q-only continuation
653 * case and 3 extra sources in the p+q continuation case.
655 if (src_cnt
+ dmaf_p_disabled_continue(flags
) > 3 ||
656 (dmaf_continue(flags
) && !dmaf_p_disabled_continue(flags
))) {
662 /* completion writes from the raid engine may pass completion
663 * writes from the legacy engine, so we need one extra null
664 * (legacy) descriptor to ensure all completion writes arrive in
667 if (likely(num_descs
) &&
668 ioat2_alloc_and_lock(&idx
, ioat
, num_descs
+1) == 0)
674 struct ioat_raw_descriptor
*descs
[2];
675 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
677 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
680 /* save a branch by unconditionally retrieving the
681 * extended descriptor pq_set_src() knows to not write
682 * to it in the single descriptor case
684 ext
= ioat2_get_ring_ent(ioat
, idx
+ i
+ with_ext
);
687 descs
[0] = (struct ioat_raw_descriptor
*) pq
;
688 descs
[1] = (struct ioat_raw_descriptor
*) pq_ex
;
690 for (s
= 0; s
< src_cnt
; s
++)
691 pq_set_src(descs
, src
[s
], offset
, scf
[s
], s
);
693 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
694 if (dmaf_p_disabled_continue(flags
))
695 pq_set_src(descs
, dst
[1], offset
, 1, s
++);
696 else if (dmaf_continue(flags
)) {
697 pq_set_src(descs
, dst
[0], offset
, 0, s
++);
698 pq_set_src(descs
, dst
[1], offset
, 1, s
++);
699 pq_set_src(descs
, dst
[1], offset
, 0, s
++);
701 pq
->size
= xfer_size
;
702 pq
->p_addr
= dst
[0] + offset
;
703 pq
->q_addr
= dst
[1] + offset
;
706 pq
->ctl_f
.src_cnt
= src_cnt_to_hw(s
);
707 pq
->ctl_f
.p_disable
= !!(flags
& DMA_PREP_PQ_DISABLE_P
);
708 pq
->ctl_f
.q_disable
= !!(flags
& DMA_PREP_PQ_DISABLE_Q
);
712 } while ((i
+= 1 + with_ext
) < num_descs
);
714 /* last pq descriptor carries the unmap parameters and fence bit */
715 desc
->txd
.flags
= flags
;
716 desc
->len
= total_len
;
718 desc
->result
= result
;
719 pq
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
720 dump_pq_desc_dbg(ioat
, desc
, ext
);
722 /* completion descriptor carries interrupt bit */
723 compl_desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
724 compl_desc
->txd
.flags
= flags
& DMA_PREP_INTERRUPT
;
728 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
729 hw
->ctl_f
.compl_write
= 1;
730 hw
->size
= NULL_DESC_BUFFER_SIZE
;
731 dump_desc_dbg(ioat
, compl_desc
);
733 /* we leave the channel locked to ensure in order submission */
734 return &compl_desc
->txd
;
737 static struct dma_async_tx_descriptor
*
738 ioat3_prep_pq(struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
739 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
742 /* specify valid address for disabled result */
743 if (flags
& DMA_PREP_PQ_DISABLE_P
)
745 if (flags
& DMA_PREP_PQ_DISABLE_Q
)
748 /* handle the single source multiply case from the raid6
751 if ((flags
& DMA_PREP_PQ_DISABLE_P
) && src_cnt
== 1) {
752 dma_addr_t single_source
[2];
753 unsigned char single_source_coef
[2];
755 BUG_ON(flags
& DMA_PREP_PQ_DISABLE_Q
);
756 single_source
[0] = src
[0];
757 single_source
[1] = src
[0];
758 single_source_coef
[0] = scf
[0];
759 single_source_coef
[1] = 0;
761 return __ioat3_prep_pq_lock(chan
, NULL
, dst
, single_source
, 2,
762 single_source_coef
, len
, flags
);
764 return __ioat3_prep_pq_lock(chan
, NULL
, dst
, src
, src_cnt
, scf
,
768 struct dma_async_tx_descriptor
*
769 ioat3_prep_pq_val(struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
770 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
771 enum sum_check_flags
*pqres
, unsigned long flags
)
773 /* specify valid address for disabled result */
774 if (flags
& DMA_PREP_PQ_DISABLE_P
)
776 if (flags
& DMA_PREP_PQ_DISABLE_Q
)
779 /* the cleanup routine only sets bits on validate failure, it
780 * does not clear bits on validate success... so clear it here
784 return __ioat3_prep_pq_lock(chan
, pqres
, pq
, src
, src_cnt
, scf
, len
,
788 static struct dma_async_tx_descriptor
*
789 ioat3_prep_pqxor(struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
790 unsigned int src_cnt
, size_t len
, unsigned long flags
)
792 unsigned char scf
[src_cnt
];
795 memset(scf
, 0, src_cnt
);
797 flags
|= DMA_PREP_PQ_DISABLE_Q
;
798 pq
[1] = dst
; /* specify valid address for disabled result */
800 return __ioat3_prep_pq_lock(chan
, NULL
, pq
, src
, src_cnt
, scf
, len
,
804 struct dma_async_tx_descriptor
*
805 ioat3_prep_pqxor_val(struct dma_chan
*chan
, dma_addr_t
*src
,
806 unsigned int src_cnt
, size_t len
,
807 enum sum_check_flags
*result
, unsigned long flags
)
809 unsigned char scf
[src_cnt
];
812 /* the cleanup routine only sets bits on validate failure, it
813 * does not clear bits on validate success... so clear it here
817 memset(scf
, 0, src_cnt
);
819 flags
|= DMA_PREP_PQ_DISABLE_Q
;
820 pq
[1] = pq
[0]; /* specify valid address for disabled result */
822 return __ioat3_prep_pq_lock(chan
, result
, pq
, &src
[1], src_cnt
- 1, scf
,
826 static struct dma_async_tx_descriptor
*
827 ioat3_prep_interrupt_lock(struct dma_chan
*c
, unsigned long flags
)
829 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
830 struct ioat_ring_ent
*desc
;
831 struct ioat_dma_descriptor
*hw
;
834 if (ioat2_alloc_and_lock(&idx
, ioat
, 1) == 0)
835 desc
= ioat2_get_ring_ent(ioat
, idx
);
842 hw
->ctl_f
.int_en
= 1;
843 hw
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
844 hw
->ctl_f
.compl_write
= 1;
845 hw
->size
= NULL_DESC_BUFFER_SIZE
;
849 desc
->txd
.flags
= flags
;
852 dump_desc_dbg(ioat
, desc
);
854 /* we leave the channel locked to ensure in order submission */
858 static void __devinit
ioat3_dma_test_callback(void *dma_async_param
)
860 struct completion
*cmp
= dma_async_param
;
865 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
866 static int __devinit
ioat_xor_val_self_test(struct ioatdma_device
*device
)
870 struct page
*xor_srcs
[IOAT_NUM_SRC_TEST
];
871 struct page
*xor_val_srcs
[IOAT_NUM_SRC_TEST
+ 1];
872 dma_addr_t dma_srcs
[IOAT_NUM_SRC_TEST
+ 1];
873 dma_addr_t dma_addr
, dest_dma
;
874 struct dma_async_tx_descriptor
*tx
;
875 struct dma_chan
*dma_chan
;
881 struct completion cmp
;
883 struct device
*dev
= &device
->pdev
->dev
;
884 struct dma_device
*dma
= &device
->common
;
886 dev_dbg(dev
, "%s\n", __func__
);
888 if (!dma_has_cap(DMA_XOR
, dma
->cap_mask
))
891 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++) {
892 xor_srcs
[src_idx
] = alloc_page(GFP_KERNEL
);
893 if (!xor_srcs
[src_idx
]) {
895 __free_page(xor_srcs
[src_idx
]);
900 dest
= alloc_page(GFP_KERNEL
);
903 __free_page(xor_srcs
[src_idx
]);
907 /* Fill in src buffers */
908 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++) {
909 u8
*ptr
= page_address(xor_srcs
[src_idx
]);
910 for (i
= 0; i
< PAGE_SIZE
; i
++)
911 ptr
[i
] = (1 << src_idx
);
914 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++)
915 cmp_byte
^= (u8
) (1 << src_idx
);
917 cmp_word
= (cmp_byte
<< 24) | (cmp_byte
<< 16) |
918 (cmp_byte
<< 8) | cmp_byte
;
920 memset(page_address(dest
), 0, PAGE_SIZE
);
922 dma_chan
= container_of(dma
->channels
.next
, struct dma_chan
,
924 if (dma
->device_alloc_chan_resources(dma_chan
) < 1) {
930 dest_dma
= dma_map_page(dev
, dest
, 0, PAGE_SIZE
, DMA_FROM_DEVICE
);
931 for (i
= 0; i
< IOAT_NUM_SRC_TEST
; i
++)
932 dma_srcs
[i
] = dma_map_page(dev
, xor_srcs
[i
], 0, PAGE_SIZE
,
934 tx
= dma
->device_prep_dma_xor(dma_chan
, dest_dma
, dma_srcs
,
935 IOAT_NUM_SRC_TEST
, PAGE_SIZE
,
939 dev_err(dev
, "Self-test xor prep failed\n");
945 init_completion(&cmp
);
946 tx
->callback
= ioat3_dma_test_callback
;
947 tx
->callback_param
= &cmp
;
948 cookie
= tx
->tx_submit(tx
);
950 dev_err(dev
, "Self-test xor setup failed\n");
954 dma
->device_issue_pending(dma_chan
);
956 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
958 if (dma
->device_is_tx_complete(dma_chan
, cookie
, NULL
, NULL
) != DMA_SUCCESS
) {
959 dev_err(dev
, "Self-test xor timed out\n");
964 dma_sync_single_for_cpu(dev
, dest_dma
, PAGE_SIZE
, DMA_FROM_DEVICE
);
965 for (i
= 0; i
< (PAGE_SIZE
/ sizeof(u32
)); i
++) {
966 u32
*ptr
= page_address(dest
);
967 if (ptr
[i
] != cmp_word
) {
968 dev_err(dev
, "Self-test xor failed compare\n");
973 dma_sync_single_for_device(dev
, dest_dma
, PAGE_SIZE
, DMA_TO_DEVICE
);
975 /* skip validate if the capability is not present */
976 if (!dma_has_cap(DMA_XOR_VAL
, dma_chan
->device
->cap_mask
))
979 /* validate the sources with the destintation page */
980 for (i
= 0; i
< IOAT_NUM_SRC_TEST
; i
++)
981 xor_val_srcs
[i
] = xor_srcs
[i
];
982 xor_val_srcs
[i
] = dest
;
986 for (i
= 0; i
< IOAT_NUM_SRC_TEST
+ 1; i
++)
987 dma_srcs
[i
] = dma_map_page(dev
, xor_val_srcs
[i
], 0, PAGE_SIZE
,
989 tx
= dma
->device_prep_dma_xor_val(dma_chan
, dma_srcs
,
990 IOAT_NUM_SRC_TEST
+ 1, PAGE_SIZE
,
991 &xor_val_result
, DMA_PREP_INTERRUPT
);
993 dev_err(dev
, "Self-test zero prep failed\n");
999 init_completion(&cmp
);
1000 tx
->callback
= ioat3_dma_test_callback
;
1001 tx
->callback_param
= &cmp
;
1002 cookie
= tx
->tx_submit(tx
);
1004 dev_err(dev
, "Self-test zero setup failed\n");
1006 goto free_resources
;
1008 dma
->device_issue_pending(dma_chan
);
1010 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
1012 if (dma
->device_is_tx_complete(dma_chan
, cookie
, NULL
, NULL
) != DMA_SUCCESS
) {
1013 dev_err(dev
, "Self-test validate timed out\n");
1015 goto free_resources
;
1018 if (xor_val_result
!= 0) {
1019 dev_err(dev
, "Self-test validate failed compare\n");
1021 goto free_resources
;
1024 /* skip memset if the capability is not present */
1025 if (!dma_has_cap(DMA_MEMSET
, dma_chan
->device
->cap_mask
))
1026 goto free_resources
;
1029 dma_addr
= dma_map_page(dev
, dest
, 0,
1030 PAGE_SIZE
, DMA_FROM_DEVICE
);
1031 tx
= dma
->device_prep_dma_memset(dma_chan
, dma_addr
, 0, PAGE_SIZE
,
1032 DMA_PREP_INTERRUPT
);
1034 dev_err(dev
, "Self-test memset prep failed\n");
1036 goto free_resources
;
1040 init_completion(&cmp
);
1041 tx
->callback
= ioat3_dma_test_callback
;
1042 tx
->callback_param
= &cmp
;
1043 cookie
= tx
->tx_submit(tx
);
1045 dev_err(dev
, "Self-test memset setup failed\n");
1047 goto free_resources
;
1049 dma
->device_issue_pending(dma_chan
);
1051 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
1053 if (dma
->device_is_tx_complete(dma_chan
, cookie
, NULL
, NULL
) != DMA_SUCCESS
) {
1054 dev_err(dev
, "Self-test memset timed out\n");
1056 goto free_resources
;
1059 for (i
= 0; i
< PAGE_SIZE
/sizeof(u32
); i
++) {
1060 u32
*ptr
= page_address(dest
);
1062 dev_err(dev
, "Self-test memset failed compare\n");
1064 goto free_resources
;
1068 /* test for non-zero parity sum */
1070 for (i
= 0; i
< IOAT_NUM_SRC_TEST
+ 1; i
++)
1071 dma_srcs
[i
] = dma_map_page(dev
, xor_val_srcs
[i
], 0, PAGE_SIZE
,
1073 tx
= dma
->device_prep_dma_xor_val(dma_chan
, dma_srcs
,
1074 IOAT_NUM_SRC_TEST
+ 1, PAGE_SIZE
,
1075 &xor_val_result
, DMA_PREP_INTERRUPT
);
1077 dev_err(dev
, "Self-test 2nd zero prep failed\n");
1079 goto free_resources
;
1083 init_completion(&cmp
);
1084 tx
->callback
= ioat3_dma_test_callback
;
1085 tx
->callback_param
= &cmp
;
1086 cookie
= tx
->tx_submit(tx
);
1088 dev_err(dev
, "Self-test 2nd zero setup failed\n");
1090 goto free_resources
;
1092 dma
->device_issue_pending(dma_chan
);
1094 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
1096 if (dma
->device_is_tx_complete(dma_chan
, cookie
, NULL
, NULL
) != DMA_SUCCESS
) {
1097 dev_err(dev
, "Self-test 2nd validate timed out\n");
1099 goto free_resources
;
1102 if (xor_val_result
!= SUM_CHECK_P_RESULT
) {
1103 dev_err(dev
, "Self-test validate failed compare\n");
1105 goto free_resources
;
1109 dma
->device_free_chan_resources(dma_chan
);
1111 src_idx
= IOAT_NUM_SRC_TEST
;
1113 __free_page(xor_srcs
[src_idx
]);
1118 static int __devinit
ioat3_dma_self_test(struct ioatdma_device
*device
)
1120 int rc
= ioat_dma_self_test(device
);
1125 rc
= ioat_xor_val_self_test(device
);
1132 static int ioat3_reset_hw(struct ioat_chan_common
*chan
)
1134 /* throw away whatever the channel was doing and get it
1135 * initialized, with ioat3 specific workarounds
1137 struct ioatdma_device
*device
= chan
->device
;
1138 struct pci_dev
*pdev
= device
->pdev
;
1143 ioat2_quiesce(chan
, msecs_to_jiffies(100));
1145 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
1146 writel(chanerr
, chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
1148 /* -= IOAT ver.3 workarounds =- */
1149 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
1150 * that can cause stability issues for IOAT ver.3, and clear any
1153 pci_write_config_dword(pdev
, IOAT_PCI_CHANERRMASK_INT_OFFSET
, 0x3e07);
1154 err
= pci_read_config_dword(pdev
, IOAT_PCI_CHANERR_INT_OFFSET
, &chanerr
);
1156 dev_err(&pdev
->dev
, "channel error register unreachable\n");
1159 pci_write_config_dword(pdev
, IOAT_PCI_CHANERR_INT_OFFSET
, chanerr
);
1161 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1162 * (workaround for spurious config parity error after restart)
1164 pci_read_config_word(pdev
, IOAT_PCI_DEVICE_ID_OFFSET
, &dev_id
);
1165 if (dev_id
== PCI_DEVICE_ID_INTEL_IOAT_TBG0
)
1166 pci_write_config_dword(pdev
, IOAT_PCI_DMAUNCERRSTS_OFFSET
, 0x10);
1168 return ioat2_reset_sync(chan
, msecs_to_jiffies(200));
1171 int __devinit
ioat3_dma_probe(struct ioatdma_device
*device
, int dca
)
1173 struct pci_dev
*pdev
= device
->pdev
;
1174 int dca_en
= system_has_dca_enabled(pdev
);
1175 struct dma_device
*dma
;
1177 struct ioat_chan_common
*chan
;
1178 bool is_raid_device
= false;
1182 device
->enumerate_channels
= ioat2_enumerate_channels
;
1183 device
->reset_hw
= ioat3_reset_hw
;
1184 device
->self_test
= ioat3_dma_self_test
;
1185 dma
= &device
->common
;
1186 dma
->device_prep_dma_memcpy
= ioat2_dma_prep_memcpy_lock
;
1187 dma
->device_issue_pending
= ioat2_issue_pending
;
1188 dma
->device_alloc_chan_resources
= ioat2_alloc_chan_resources
;
1189 dma
->device_free_chan_resources
= ioat2_free_chan_resources
;
1191 dma_cap_set(DMA_INTERRUPT
, dma
->cap_mask
);
1192 dma
->device_prep_dma_interrupt
= ioat3_prep_interrupt_lock
;
1194 cap
= readl(device
->reg_base
+ IOAT_DMA_CAP_OFFSET
);
1196 /* dca is incompatible with raid operations */
1197 if (dca_en
&& (cap
& (IOAT_CAP_XOR
|IOAT_CAP_PQ
)))
1198 cap
&= ~(IOAT_CAP_XOR
|IOAT_CAP_PQ
);
1200 if (cap
& IOAT_CAP_XOR
) {
1201 is_raid_device
= true;
1205 dma_cap_set(DMA_XOR
, dma
->cap_mask
);
1206 dma
->device_prep_dma_xor
= ioat3_prep_xor
;
1208 dma_cap_set(DMA_XOR_VAL
, dma
->cap_mask
);
1209 dma
->device_prep_dma_xor_val
= ioat3_prep_xor_val
;
1211 if (cap
& IOAT_CAP_PQ
) {
1212 is_raid_device
= true;
1213 dma_set_maxpq(dma
, 8, 0);
1216 dma_cap_set(DMA_PQ
, dma
->cap_mask
);
1217 dma
->device_prep_dma_pq
= ioat3_prep_pq
;
1219 dma_cap_set(DMA_PQ_VAL
, dma
->cap_mask
);
1220 dma
->device_prep_dma_pq_val
= ioat3_prep_pq_val
;
1222 if (!(cap
& IOAT_CAP_XOR
)) {
1226 dma_cap_set(DMA_XOR
, dma
->cap_mask
);
1227 dma
->device_prep_dma_xor
= ioat3_prep_pqxor
;
1229 dma_cap_set(DMA_XOR_VAL
, dma
->cap_mask
);
1230 dma
->device_prep_dma_xor_val
= ioat3_prep_pqxor_val
;
1233 if (is_raid_device
&& (cap
& IOAT_CAP_FILL_BLOCK
)) {
1234 dma_cap_set(DMA_MEMSET
, dma
->cap_mask
);
1235 dma
->device_prep_dma_memset
= ioat3_prep_memset_lock
;
1239 if (is_raid_device
) {
1240 dma
->device_is_tx_complete
= ioat3_is_complete
;
1241 device
->cleanup_tasklet
= ioat3_cleanup_tasklet
;
1242 device
->timer_fn
= ioat3_timer_event
;
1244 dma
->device_is_tx_complete
= ioat2_is_complete
;
1245 device
->cleanup_tasklet
= ioat2_cleanup_tasklet
;
1246 device
->timer_fn
= ioat2_timer_event
;
1249 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
1250 dma_cap_clear(DMA_PQ_VAL
, dma
->cap_mask
);
1251 dma
->device_prep_dma_pq_val
= NULL
;
1254 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
1255 dma_cap_clear(DMA_XOR_VAL
, dma
->cap_mask
);
1256 dma
->device_prep_dma_xor_val
= NULL
;
1259 err
= ioat_probe(device
);
1262 ioat_set_tcp_copy_break(262144);
1264 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1265 chan
= to_chan_common(c
);
1266 writel(IOAT_DMA_DCA_ANY_CPU
,
1267 chan
->reg_base
+ IOAT_DCACTRL_OFFSET
);
1270 err
= ioat_register(device
);
1274 ioat_kobject_add(device
, &ioat2_ktype
);
1277 device
->dca
= ioat3_dca_init(pdev
, device
->reg_base
);