drivers/dma/ioat/dma.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef IOATDMA_H
  22 #define IOATDMA_H
  23
  24 #include <linux/dmaengine.h>
  25 #include "hw.h"
  26 #include "registers.h"
  27 #include <linux/init.h>
  28 #include <linux/dmapool.h>
  29 #include <linux/cache.h>
  30 #include <linux/pci_ids.h>
  31 #include <net/tcp.h>
  32
  33 #define IOAT_DMA_VERSION  "3.64"
  34
  35 #define IOAT_LOW_COMPLETION_MASK        0xffffffc0
  36 #define IOAT_DMA_DCA_ANY_CPU            ~0
  37
  38 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
  39 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
  40 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
  41 #define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
  42
  43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
  44
  45 /*
  46  * workaround for IOAT ver.3.0 null descriptor issue
  47  * (channel returns error when size is 0)
  48  */
  49 #define NULL_DESC_BUFFER_SIZE 1
  50
  51 /**
  52  * struct ioatdma_device - internal representation of a IOAT device
  53  * @pdev: PCI-Express device
  54  * @reg_base: MMIO register space base address
  55  * @dma_pool: for allocating DMA descriptors
  56  * @common: embedded struct dma_device
  57  * @version: version of ioatdma device
  58  * @msix_entries: irq handlers
  59  * @idx: per channel data
  60  * @dca: direct cache access context
  61  * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
  62  * @enumerate_channels: hw version specific channel enumeration
  63  */
  64
  65 struct ioatdma_device {
  66         struct pci_dev *pdev;
  67         void __iomem *reg_base;
  68         struct pci_pool *dma_pool;
  69         struct pci_pool *completion_pool;
  70         struct dma_device common;
  71         u8 version;
  72         struct msix_entry msix_entries[4];
  73         struct ioat_chan_common *idx[4];
  74         struct dca_provider *dca;
  75         void (*intr_quirk)(struct ioatdma_device *device);
  76         int (*enumerate_channels)(struct ioatdma_device *device);
  77 };
  78
  79 struct ioat_chan_common {
  80         struct dma_chan common;
  81         void __iomem *reg_base;
  82         unsigned long last_completion;
  83         spinlock_t cleanup_lock;
  84         dma_cookie_t completed_cookie;
  85         unsigned long state;
  86         #define IOAT_COMPLETION_PENDING 0
  87         #define IOAT_COMPLETION_ACK 1
  88         #define IOAT_RESET_PENDING 2
  89         struct timer_list timer;
  90         #define COMPLETION_TIMEOUT msecs_to_jiffies(100)
  91         #define IDLE_TIMEOUT msecs_to_jiffies(2000)
  92         #define RESET_DELAY msecs_to_jiffies(100)
  93         struct ioatdma_device *device;
  94         dma_addr_t completion_dma;
  95         u64 *completion;
  96         struct tasklet_struct cleanup_task;
  97 };
  98
  99
 100 /**
 101  * struct ioat_dma_chan - internal representation of a DMA channel
 102  */
 103 struct ioat_dma_chan {
 104         struct ioat_chan_common base;
 105
 106         size_t xfercap; /* XFERCAP register value expanded out */
 107
 108         spinlock_t desc_lock;
 109         struct list_head free_desc;
 110         struct list_head used_desc;
 111
 112         int pending;
 113         u16 desccount;
 114 };
 115
 116 static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
 117 {
 118         return container_of(c, struct ioat_chan_common, common);
 119 }
 120
 121 static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
 122 {
 123         struct ioat_chan_common *chan = to_chan_common(c);
 124
 125         return container_of(chan, struct ioat_dma_chan, base);
 126 }
 127
 128 /**
 129  * ioat_is_complete - poll the status of an ioat transaction
 130  * @c: channel handle
 131  * @cookie: transaction identifier
 132  * @done: if set, updated with last completed transaction
 133  * @used: if set, updated with last used transaction
 134  */
 135 static inline enum dma_status
 136 ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
 137                  dma_cookie_t *done, dma_cookie_t *used)
 138 {
 139         struct ioat_chan_common *chan = to_chan_common(c);
 140         dma_cookie_t last_used;
 141         dma_cookie_t last_complete;
 142
 143         last_used = c->cookie;
 144         last_complete = chan->completed_cookie;
 145
 146         if (done)
 147                 *done = last_complete;
 148         if (used)
 149                 *used = last_used;
 150
 151         return dma_async_is_complete(cookie, last_complete, last_used);
 152 }
 153
 154 /* wrapper around hardware descriptor format + additional software fields */
 155
 156 /**
 157  * struct ioat_desc_sw - wrapper around hardware descriptor
 158  * @hw: hardware DMA descriptor
 159  * @node: this descriptor will either be on the free list,
 160  *     or attached to a transaction list (tx_list)
 161  * @txd: the generic software descriptor for all engines
 162  * @id: identifier for debug
 163  */
 164 struct ioat_desc_sw {
 165         struct ioat_dma_descriptor *hw;
 166         struct list_head node;
 167         size_t len;
 168         struct list_head tx_list;
 169         struct dma_async_tx_descriptor txd;
 170         #ifdef DEBUG
 171         int id;
 172         #endif
 173 };
 174
 175 #ifdef DEBUG
 176 #define set_desc_id(desc, i) ((desc)->id = (i))
 177 #define desc_id(desc) ((desc)->id)
 178 #else
 179 #define set_desc_id(desc, i)
 180 #define desc_id(desc) (0)
 181 #endif
 182
 183 static inline void
 184 __dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
 185                 struct dma_async_tx_descriptor *tx, int id)
 186 {
 187         struct device *dev = to_dev(chan);
 188
 189         dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
 190                 " ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
 191                 (unsigned long long) tx->phys,
 192                 (unsigned long long) hw->next, tx->cookie, tx->flags,
 193                 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
 194 }
 195
 196 #define dump_desc_dbg(c, d) \
 197         ({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
 198
 199 static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
 200 {
 201         #ifdef CONFIG_NET_DMA
 202         sysctl_tcp_dma_copybreak = copybreak;
 203         #endif
 204 }
 205
 206 static inline struct ioat_chan_common *
 207 ioat_chan_by_index(struct ioatdma_device *device, int index)
 208 {
 209         return device->idx[index];
 210 }
 211
 212 static inline u64 ioat_chansts(struct ioat_chan_common *chan)
 213 {
 214         u8 ver = chan->device->version;
 215         u64 status;
 216         u32 status_lo;
 217
 218         /* We need to read the low address first as this causes the
 219          * chipset to latch the upper bits for the subsequent read
 220          */
 221         status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
 222         status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
 223         status <<= 32;
 224         status |= status_lo;
 225
 226         return status;
 227 }
 228
 229 static inline void ioat_start(struct ioat_chan_common *chan)
 230 {
 231         u8 ver = chan->device->version;
 232
 233         writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 234 }
 235
 236 static inline u64 ioat_chansts_to_addr(u64 status)
 237 {
 238         return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 239 }
 240
 241 static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
 242 {
 243         return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 244 }
 245
 246 static inline void ioat_suspend(struct ioat_chan_common *chan)
 247 {
 248         u8 ver = chan->device->version;
 249
 250         writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
 251 }
 252
 253 static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
 254 {
 255         struct ioat_chan_common *chan = &ioat->base;
 256
 257         writel(addr & 0x00000000FFFFFFFF,
 258                chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 259         writel(addr >> 32,
 260                chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
 261 }
 262
 263 static inline bool is_ioat_active(unsigned long status)
 264 {
 265         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
 266 }
 267
 268 static inline bool is_ioat_idle(unsigned long status)
 269 {
 270         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
 271 }
 272
 273 static inline bool is_ioat_halted(unsigned long status)
 274 {
 275         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
 276 }
 277
 278 static inline bool is_ioat_suspended(unsigned long status)
 279 {
 280         return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
 281 }
 282
 283 /* channel was fatally programmed */
 284 static inline bool is_ioat_bug(unsigned long err)
 285 {
 286         return !!(err & (IOAT_CHANERR_SRC_ADDR_ERR|IOAT_CHANERR_DEST_ADDR_ERR|
 287                          IOAT_CHANERR_NEXT_ADDR_ERR|IOAT_CHANERR_CONTROL_ERR|
 288                          IOAT_CHANERR_LENGTH_ERR));
 289 }
 290
 291 int __devinit ioat_probe(struct ioatdma_device *device);
 292 int __devinit ioat_register(struct ioatdma_device *device);
 293 int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca);
 294 void __devexit ioat_dma_remove(struct ioatdma_device *device);
 295 struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev,
 296                                               void __iomem *iobase);
 297 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
 298 void ioat_init_channel(struct ioatdma_device *device,
 299                        struct ioat_chan_common *chan, int idx,
 300                        void (*timer_fn)(unsigned long),
 301                        void (*tasklet)(unsigned long),
 302                        unsigned long ioat);
 303 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 304                     size_t len, struct ioat_dma_descriptor *hw);
 305 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 306                            unsigned long *phys_complete);
 307 #endif /* IOATDMA_H */