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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / imx-dma.c
1 /*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
9 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/mm.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/module.h>
30
31 #include <asm/irq.h>
32 #include <linux/platform_data/dma-imx.h>
33
34 #include "dmaengine.h"
35 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
36 #define IMX_DMA_CHANNELS 16
37
38 #define IMX_DMA_2D_SLOTS 2
39 #define IMX_DMA_2D_SLOT_A 0
40 #define IMX_DMA_2D_SLOT_B 1
41
42 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
43 #define IMX_DMA_MEMSIZE_32 (0 << 4)
44 #define IMX_DMA_MEMSIZE_8 (1 << 4)
45 #define IMX_DMA_MEMSIZE_16 (2 << 4)
46 #define IMX_DMA_TYPE_LINEAR (0 << 10)
47 #define IMX_DMA_TYPE_2D (1 << 10)
48 #define IMX_DMA_TYPE_FIFO (2 << 10)
49
50 #define IMX_DMA_ERR_BURST (1 << 0)
51 #define IMX_DMA_ERR_REQUEST (1 << 1)
52 #define IMX_DMA_ERR_TRANSFER (1 << 2)
53 #define IMX_DMA_ERR_BUFFER (1 << 3)
54 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
55
56 #define DMA_DCR 0x00 /* Control Register */
57 #define DMA_DISR 0x04 /* Interrupt status Register */
58 #define DMA_DIMR 0x08 /* Interrupt mask Register */
59 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
60 #define DMA_DRTOSR 0x10 /* Request timeout Register */
61 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
62 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
63 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
64 #define DMA_WSRA 0x40 /* W-Size Register A */
65 #define DMA_XSRA 0x44 /* X-Size Register A */
66 #define DMA_YSRA 0x48 /* Y-Size Register A */
67 #define DMA_WSRB 0x4c /* W-Size Register B */
68 #define DMA_XSRB 0x50 /* X-Size Register B */
69 #define DMA_YSRB 0x54 /* Y-Size Register B */
70 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
71 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
72 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
73 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
74 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
75 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
76 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
77 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
78 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
79
80 #define DCR_DRST (1<<1)
81 #define DCR_DEN (1<<0)
82 #define DBTOCR_EN (1<<15)
83 #define DBTOCR_CNT(x) ((x) & 0x7fff)
84 #define CNTR_CNT(x) ((x) & 0xffffff)
85 #define CCR_ACRPT (1<<14)
86 #define CCR_DMOD_LINEAR (0x0 << 12)
87 #define CCR_DMOD_2D (0x1 << 12)
88 #define CCR_DMOD_FIFO (0x2 << 12)
89 #define CCR_DMOD_EOBFIFO (0x3 << 12)
90 #define CCR_SMOD_LINEAR (0x0 << 10)
91 #define CCR_SMOD_2D (0x1 << 10)
92 #define CCR_SMOD_FIFO (0x2 << 10)
93 #define CCR_SMOD_EOBFIFO (0x3 << 10)
94 #define CCR_MDIR_DEC (1<<9)
95 #define CCR_MSEL_B (1<<8)
96 #define CCR_DSIZ_32 (0x0 << 6)
97 #define CCR_DSIZ_8 (0x1 << 6)
98 #define CCR_DSIZ_16 (0x2 << 6)
99 #define CCR_SSIZ_32 (0x0 << 4)
100 #define CCR_SSIZ_8 (0x1 << 4)
101 #define CCR_SSIZ_16 (0x2 << 4)
102 #define CCR_REN (1<<3)
103 #define CCR_RPT (1<<2)
104 #define CCR_FRC (1<<1)
105 #define CCR_CEN (1<<0)
106 #define RTOR_EN (1<<15)
107 #define RTOR_CLK (1<<14)
108 #define RTOR_PSC (1<<13)
109
110 enum imxdma_prep_type {
111 IMXDMA_DESC_MEMCPY,
112 IMXDMA_DESC_INTERLEAVED,
113 IMXDMA_DESC_SLAVE_SG,
114 IMXDMA_DESC_CYCLIC,
115 };
116
117 struct imx_dma_2d_config {
118 u16 xsr;
119 u16 ysr;
120 u16 wsr;
121 int count;
122 };
123
124 struct imxdma_desc {
125 struct list_head node;
126 struct dma_async_tx_descriptor desc;
127 enum dma_status status;
128 dma_addr_t src;
129 dma_addr_t dest;
130 size_t len;
131 enum dma_transfer_direction direction;
132 enum imxdma_prep_type type;
133 /* For memcpy and interleaved */
134 unsigned int config_port;
135 unsigned int config_mem;
136 /* For interleaved transfers */
137 unsigned int x;
138 unsigned int y;
139 unsigned int w;
140 /* For slave sg and cyclic */
141 struct scatterlist *sg;
142 unsigned int sgcount;
143 };
144
145 struct imxdma_channel {
146 int hw_chaining;
147 struct timer_list watchdog;
148 struct imxdma_engine *imxdma;
149 unsigned int channel;
150
151 struct tasklet_struct dma_tasklet;
152 struct list_head ld_free;
153 struct list_head ld_queue;
154 struct list_head ld_active;
155 int descs_allocated;
156 enum dma_slave_buswidth word_size;
157 dma_addr_t per_address;
158 u32 watermark_level;
159 struct dma_chan chan;
160 struct dma_async_tx_descriptor desc;
161 enum dma_status status;
162 int dma_request;
163 struct scatterlist *sg_list;
164 u32 ccr_from_device;
165 u32 ccr_to_device;
166 bool enabled_2d;
167 int slot_2d;
168 };
169
170 enum imx_dma_type {
171 IMX1_DMA,
172 IMX21_DMA,
173 IMX27_DMA,
174 };
175
176 struct imxdma_engine {
177 struct device *dev;
178 struct device_dma_parameters dma_parms;
179 struct dma_device dma_device;
180 void __iomem *base;
181 struct clk *dma_ahb;
182 struct clk *dma_ipg;
183 spinlock_t lock;
184 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
185 struct imxdma_channel channel[IMX_DMA_CHANNELS];
186 enum imx_dma_type devtype;
187 };
188
189 static struct platform_device_id imx_dma_devtype[] = {
190 {
191 .name = "imx1-dma",
192 .driver_data = IMX1_DMA,
193 }, {
194 .name = "imx21-dma",
195 .driver_data = IMX21_DMA,
196 }, {
197 .name = "imx27-dma",
198 .driver_data = IMX27_DMA,
199 }, {
200 /* sentinel */
201 }
202 };
203 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
204
205 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
206 {
207 return imxdma->devtype == IMX1_DMA;
208 }
209
210 static inline int is_imx21_dma(struct imxdma_engine *imxdma)
211 {
212 return imxdma->devtype == IMX21_DMA;
213 }
214
215 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
216 {
217 return imxdma->devtype == IMX27_DMA;
218 }
219
220 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
221 {
222 return container_of(chan, struct imxdma_channel, chan);
223 }
224
225 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
226 {
227 struct imxdma_desc *desc;
228
229 if (!list_empty(&imxdmac->ld_active)) {
230 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
231 node);
232 if (desc->type == IMXDMA_DESC_CYCLIC)
233 return true;
234 }
235 return false;
236 }
237
238
239
240 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
241 unsigned offset)
242 {
243 __raw_writel(val, imxdma->base + offset);
244 }
245
246 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
247 {
248 return __raw_readl(imxdma->base + offset);
249 }
250
251 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
252 {
253 struct imxdma_engine *imxdma = imxdmac->imxdma;
254
255 if (is_imx27_dma(imxdma))
256 return imxdmac->hw_chaining;
257 else
258 return 0;
259 }
260
261 /*
262 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
263 */
264 static inline int imxdma_sg_next(struct imxdma_desc *d)
265 {
266 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
267 struct imxdma_engine *imxdma = imxdmac->imxdma;
268 struct scatterlist *sg = d->sg;
269 unsigned long now;
270
271 now = min(d->len, sg_dma_len(sg));
272 if (d->len != IMX_DMA_LENGTH_LOOP)
273 d->len -= now;
274
275 if (d->direction == DMA_DEV_TO_MEM)
276 imx_dmav1_writel(imxdma, sg->dma_address,
277 DMA_DAR(imxdmac->channel));
278 else
279 imx_dmav1_writel(imxdma, sg->dma_address,
280 DMA_SAR(imxdmac->channel));
281
282 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
283
284 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
285 "size 0x%08x\n", __func__, imxdmac->channel,
286 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
287 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
288 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
289
290 return now;
291 }
292
293 static void imxdma_enable_hw(struct imxdma_desc *d)
294 {
295 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
296 struct imxdma_engine *imxdma = imxdmac->imxdma;
297 int channel = imxdmac->channel;
298 unsigned long flags;
299
300 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
301
302 local_irq_save(flags);
303
304 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
305 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
306 ~(1 << channel), DMA_DIMR);
307 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
308 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
309
310 if (!is_imx1_dma(imxdma) &&
311 d->sg && imxdma_hw_chain(imxdmac)) {
312 d->sg = sg_next(d->sg);
313 if (d->sg) {
314 u32 tmp;
315 imxdma_sg_next(d);
316 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
317 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
318 DMA_CCR(channel));
319 }
320 }
321
322 local_irq_restore(flags);
323 }
324
325 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
326 {
327 struct imxdma_engine *imxdma = imxdmac->imxdma;
328 int channel = imxdmac->channel;
329 unsigned long flags;
330
331 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
332
333 if (imxdma_hw_chain(imxdmac))
334 del_timer(&imxdmac->watchdog);
335
336 local_irq_save(flags);
337 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
338 (1 << channel), DMA_DIMR);
339 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
340 ~CCR_CEN, DMA_CCR(channel));
341 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
342 local_irq_restore(flags);
343 }
344
345 static void imxdma_watchdog(unsigned long data)
346 {
347 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
348 struct imxdma_engine *imxdma = imxdmac->imxdma;
349 int channel = imxdmac->channel;
350
351 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
352
353 /* Tasklet watchdog error handler */
354 tasklet_schedule(&imxdmac->dma_tasklet);
355 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
356 imxdmac->channel);
357 }
358
359 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
360 {
361 struct imxdma_engine *imxdma = dev_id;
362 unsigned int err_mask;
363 int i, disr;
364 int errcode;
365
366 disr = imx_dmav1_readl(imxdma, DMA_DISR);
367
368 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
369 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
370 imx_dmav1_readl(imxdma, DMA_DSESR) |
371 imx_dmav1_readl(imxdma, DMA_DBOSR);
372
373 if (!err_mask)
374 return IRQ_HANDLED;
375
376 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
377
378 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
379 if (!(err_mask & (1 << i)))
380 continue;
381 errcode = 0;
382
383 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
384 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
385 errcode |= IMX_DMA_ERR_BURST;
386 }
387 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
388 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
389 errcode |= IMX_DMA_ERR_REQUEST;
390 }
391 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
392 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
393 errcode |= IMX_DMA_ERR_TRANSFER;
394 }
395 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
396 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
397 errcode |= IMX_DMA_ERR_BUFFER;
398 }
399 /* Tasklet error handler */
400 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
401
402 printk(KERN_WARNING
403 "DMA timeout on channel %d -%s%s%s%s\n", i,
404 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
405 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
406 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
407 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
408 }
409 return IRQ_HANDLED;
410 }
411
412 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
413 {
414 struct imxdma_engine *imxdma = imxdmac->imxdma;
415 int chno = imxdmac->channel;
416 struct imxdma_desc *desc;
417 unsigned long flags;
418
419 spin_lock_irqsave(&imxdma->lock, flags);
420 if (list_empty(&imxdmac->ld_active)) {
421 spin_unlock_irqrestore(&imxdma->lock, flags);
422 goto out;
423 }
424
425 desc = list_first_entry(&imxdmac->ld_active,
426 struct imxdma_desc,
427 node);
428 spin_unlock_irqrestore(&imxdma->lock, flags);
429
430 if (desc->sg) {
431 u32 tmp;
432 desc->sg = sg_next(desc->sg);
433
434 if (desc->sg) {
435 imxdma_sg_next(desc);
436
437 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
438
439 if (imxdma_hw_chain(imxdmac)) {
440 /* FIXME: The timeout should probably be
441 * configurable
442 */
443 mod_timer(&imxdmac->watchdog,
444 jiffies + msecs_to_jiffies(500));
445
446 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
447 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
448 } else {
449 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
450 DMA_CCR(chno));
451 tmp |= CCR_CEN;
452 }
453
454 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
455
456 if (imxdma_chan_is_doing_cyclic(imxdmac))
457 /* Tasklet progression */
458 tasklet_schedule(&imxdmac->dma_tasklet);
459
460 return;
461 }
462
463 if (imxdma_hw_chain(imxdmac)) {
464 del_timer(&imxdmac->watchdog);
465 return;
466 }
467 }
468
469 out:
470 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
471 /* Tasklet irq */
472 tasklet_schedule(&imxdmac->dma_tasklet);
473 }
474
475 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
476 {
477 struct imxdma_engine *imxdma = dev_id;
478 int i, disr;
479
480 if (!is_imx1_dma(imxdma))
481 imxdma_err_handler(irq, dev_id);
482
483 disr = imx_dmav1_readl(imxdma, DMA_DISR);
484
485 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
486
487 imx_dmav1_writel(imxdma, disr, DMA_DISR);
488 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
489 if (disr & (1 << i))
490 dma_irq_handle_channel(&imxdma->channel[i]);
491 }
492
493 return IRQ_HANDLED;
494 }
495
496 static int imxdma_xfer_desc(struct imxdma_desc *d)
497 {
498 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
499 struct imxdma_engine *imxdma = imxdmac->imxdma;
500 int slot = -1;
501 int i;
502
503 /* Configure and enable */
504 switch (d->type) {
505 case IMXDMA_DESC_INTERLEAVED:
506 /* Try to get a free 2D slot */
507 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
508 if ((imxdma->slots_2d[i].count > 0) &&
509 ((imxdma->slots_2d[i].xsr != d->x) ||
510 (imxdma->slots_2d[i].ysr != d->y) ||
511 (imxdma->slots_2d[i].wsr != d->w)))
512 continue;
513 slot = i;
514 break;
515 }
516 if (slot < 0)
517 return -EBUSY;
518
519 imxdma->slots_2d[slot].xsr = d->x;
520 imxdma->slots_2d[slot].ysr = d->y;
521 imxdma->slots_2d[slot].wsr = d->w;
522 imxdma->slots_2d[slot].count++;
523
524 imxdmac->slot_2d = slot;
525 imxdmac->enabled_2d = true;
526
527 if (slot == IMX_DMA_2D_SLOT_A) {
528 d->config_mem &= ~CCR_MSEL_B;
529 d->config_port &= ~CCR_MSEL_B;
530 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
531 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
532 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
533 } else {
534 d->config_mem |= CCR_MSEL_B;
535 d->config_port |= CCR_MSEL_B;
536 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
537 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
538 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
539 }
540 /*
541 * We fall-through here intentionally, since a 2D transfer is
542 * similar to MEMCPY just adding the 2D slot configuration.
543 */
544 case IMXDMA_DESC_MEMCPY:
545 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
546 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
547 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
548 DMA_CCR(imxdmac->channel));
549
550 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
551
552 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
553 "dma_length=%d\n", __func__, imxdmac->channel,
554 d->dest, d->src, d->len);
555
556 break;
557 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
558 case IMXDMA_DESC_CYCLIC:
559 case IMXDMA_DESC_SLAVE_SG:
560 if (d->direction == DMA_DEV_TO_MEM) {
561 imx_dmav1_writel(imxdma, imxdmac->per_address,
562 DMA_SAR(imxdmac->channel));
563 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
564 DMA_CCR(imxdmac->channel));
565
566 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
567 "total length=%d dev_addr=0x%08x (dev2mem)\n",
568 __func__, imxdmac->channel, d->sg, d->sgcount,
569 d->len, imxdmac->per_address);
570 } else if (d->direction == DMA_MEM_TO_DEV) {
571 imx_dmav1_writel(imxdma, imxdmac->per_address,
572 DMA_DAR(imxdmac->channel));
573 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
574 DMA_CCR(imxdmac->channel));
575
576 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
577 "total length=%d dev_addr=0x%08x (mem2dev)\n",
578 __func__, imxdmac->channel, d->sg, d->sgcount,
579 d->len, imxdmac->per_address);
580 } else {
581 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
582 __func__, imxdmac->channel);
583 return -EINVAL;
584 }
585
586 imxdma_sg_next(d);
587
588 break;
589 default:
590 return -EINVAL;
591 }
592 imxdma_enable_hw(d);
593 return 0;
594 }
595
596 static void imxdma_tasklet(unsigned long data)
597 {
598 struct imxdma_channel *imxdmac = (void *)data;
599 struct imxdma_engine *imxdma = imxdmac->imxdma;
600 struct imxdma_desc *desc;
601 unsigned long flags;
602
603 spin_lock_irqsave(&imxdma->lock, flags);
604
605 if (list_empty(&imxdmac->ld_active)) {
606 /* Someone might have called terminate all */
607 spin_unlock_irqrestore(&imxdma->lock, flags);
608 return;
609 }
610 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
611
612 /* If we are dealing with a cyclic descriptor, keep it on ld_active
613 * and dont mark the descriptor as complete.
614 * Only in non-cyclic cases it would be marked as complete
615 */
616 if (imxdma_chan_is_doing_cyclic(imxdmac))
617 goto out;
618 else
619 dma_cookie_complete(&desc->desc);
620
621 /* Free 2D slot if it was an interleaved transfer */
622 if (imxdmac->enabled_2d) {
623 imxdma->slots_2d[imxdmac->slot_2d].count--;
624 imxdmac->enabled_2d = false;
625 }
626
627 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
628
629 if (!list_empty(&imxdmac->ld_queue)) {
630 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
631 node);
632 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
633 if (imxdma_xfer_desc(desc) < 0)
634 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
635 __func__, imxdmac->channel);
636 }
637 out:
638 spin_unlock_irqrestore(&imxdma->lock, flags);
639
640 if (desc->desc.callback)
641 desc->desc.callback(desc->desc.callback_param);
642
643 }
644
645 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
646 unsigned long arg)
647 {
648 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
649 struct dma_slave_config *dmaengine_cfg = (void *)arg;
650 struct imxdma_engine *imxdma = imxdmac->imxdma;
651 unsigned long flags;
652 unsigned int mode = 0;
653
654 switch (cmd) {
655 case DMA_TERMINATE_ALL:
656 imxdma_disable_hw(imxdmac);
657
658 spin_lock_irqsave(&imxdma->lock, flags);
659 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
660 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
661 spin_unlock_irqrestore(&imxdma->lock, flags);
662 return 0;
663 case DMA_SLAVE_CONFIG:
664 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
665 imxdmac->per_address = dmaengine_cfg->src_addr;
666 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
667 imxdmac->word_size = dmaengine_cfg->src_addr_width;
668 } else {
669 imxdmac->per_address = dmaengine_cfg->dst_addr;
670 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
671 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
672 }
673
674 switch (imxdmac->word_size) {
675 case DMA_SLAVE_BUSWIDTH_1_BYTE:
676 mode = IMX_DMA_MEMSIZE_8;
677 break;
678 case DMA_SLAVE_BUSWIDTH_2_BYTES:
679 mode = IMX_DMA_MEMSIZE_16;
680 break;
681 default:
682 case DMA_SLAVE_BUSWIDTH_4_BYTES:
683 mode = IMX_DMA_MEMSIZE_32;
684 break;
685 }
686
687 imxdmac->hw_chaining = 0;
688
689 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
690 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
691 CCR_REN;
692 imxdmac->ccr_to_device =
693 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
694 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
695 imx_dmav1_writel(imxdma, imxdmac->dma_request,
696 DMA_RSSR(imxdmac->channel));
697
698 /* Set burst length */
699 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
700 imxdmac->word_size, DMA_BLR(imxdmac->channel));
701
702 return 0;
703 default:
704 return -ENOSYS;
705 }
706
707 return -EINVAL;
708 }
709
710 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
711 dma_cookie_t cookie,
712 struct dma_tx_state *txstate)
713 {
714 return dma_cookie_status(chan, cookie, txstate);
715 }
716
717 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
718 {
719 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
720 struct imxdma_engine *imxdma = imxdmac->imxdma;
721 dma_cookie_t cookie;
722 unsigned long flags;
723
724 spin_lock_irqsave(&imxdma->lock, flags);
725 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
726 cookie = dma_cookie_assign(tx);
727 spin_unlock_irqrestore(&imxdma->lock, flags);
728
729 return cookie;
730 }
731
732 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
733 {
734 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
735 struct imx_dma_data *data = chan->private;
736
737 if (data != NULL)
738 imxdmac->dma_request = data->dma_request;
739
740 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
741 struct imxdma_desc *desc;
742
743 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
744 if (!desc)
745 break;
746 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
747 dma_async_tx_descriptor_init(&desc->desc, chan);
748 desc->desc.tx_submit = imxdma_tx_submit;
749 /* txd.flags will be overwritten in prep funcs */
750 desc->desc.flags = DMA_CTRL_ACK;
751 desc->status = DMA_SUCCESS;
752
753 list_add_tail(&desc->node, &imxdmac->ld_free);
754 imxdmac->descs_allocated++;
755 }
756
757 if (!imxdmac->descs_allocated)
758 return -ENOMEM;
759
760 return imxdmac->descs_allocated;
761 }
762
763 static void imxdma_free_chan_resources(struct dma_chan *chan)
764 {
765 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
766 struct imxdma_engine *imxdma = imxdmac->imxdma;
767 struct imxdma_desc *desc, *_desc;
768 unsigned long flags;
769
770 spin_lock_irqsave(&imxdma->lock, flags);
771
772 imxdma_disable_hw(imxdmac);
773 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
774 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
775
776 spin_unlock_irqrestore(&imxdma->lock, flags);
777
778 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
779 kfree(desc);
780 imxdmac->descs_allocated--;
781 }
782 INIT_LIST_HEAD(&imxdmac->ld_free);
783
784 if (imxdmac->sg_list) {
785 kfree(imxdmac->sg_list);
786 imxdmac->sg_list = NULL;
787 }
788 }
789
790 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
791 struct dma_chan *chan, struct scatterlist *sgl,
792 unsigned int sg_len, enum dma_transfer_direction direction,
793 unsigned long flags, void *context)
794 {
795 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
796 struct scatterlist *sg;
797 int i, dma_length = 0;
798 struct imxdma_desc *desc;
799
800 if (list_empty(&imxdmac->ld_free) ||
801 imxdma_chan_is_doing_cyclic(imxdmac))
802 return NULL;
803
804 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
805
806 for_each_sg(sgl, sg, sg_len, i) {
807 dma_length += sg_dma_len(sg);
808 }
809
810 switch (imxdmac->word_size) {
811 case DMA_SLAVE_BUSWIDTH_4_BYTES:
812 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
813 return NULL;
814 break;
815 case DMA_SLAVE_BUSWIDTH_2_BYTES:
816 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
817 return NULL;
818 break;
819 case DMA_SLAVE_BUSWIDTH_1_BYTE:
820 break;
821 default:
822 return NULL;
823 }
824
825 desc->type = IMXDMA_DESC_SLAVE_SG;
826 desc->sg = sgl;
827 desc->sgcount = sg_len;
828 desc->len = dma_length;
829 desc->direction = direction;
830 if (direction == DMA_DEV_TO_MEM) {
831 desc->src = imxdmac->per_address;
832 } else {
833 desc->dest = imxdmac->per_address;
834 }
835 desc->desc.callback = NULL;
836 desc->desc.callback_param = NULL;
837
838 return &desc->desc;
839 }
840
841 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
842 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
843 size_t period_len, enum dma_transfer_direction direction,
844 unsigned long flags, void *context)
845 {
846 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
847 struct imxdma_engine *imxdma = imxdmac->imxdma;
848 struct imxdma_desc *desc;
849 int i;
850 unsigned int periods = buf_len / period_len;
851
852 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
853 __func__, imxdmac->channel, buf_len, period_len);
854
855 if (list_empty(&imxdmac->ld_free) ||
856 imxdma_chan_is_doing_cyclic(imxdmac))
857 return NULL;
858
859 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
860
861 kfree(imxdmac->sg_list);
862
863 imxdmac->sg_list = kcalloc(periods + 1,
864 sizeof(struct scatterlist), GFP_ATOMIC);
865 if (!imxdmac->sg_list)
866 return NULL;
867
868 sg_init_table(imxdmac->sg_list, periods);
869
870 for (i = 0; i < periods; i++) {
871 imxdmac->sg_list[i].page_link = 0;
872 imxdmac->sg_list[i].offset = 0;
873 imxdmac->sg_list[i].dma_address = dma_addr;
874 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
875 dma_addr += period_len;
876 }
877
878 /* close the loop */
879 imxdmac->sg_list[periods].offset = 0;
880 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
881 imxdmac->sg_list[periods].page_link =
882 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
883
884 desc->type = IMXDMA_DESC_CYCLIC;
885 desc->sg = imxdmac->sg_list;
886 desc->sgcount = periods;
887 desc->len = IMX_DMA_LENGTH_LOOP;
888 desc->direction = direction;
889 if (direction == DMA_DEV_TO_MEM) {
890 desc->src = imxdmac->per_address;
891 } else {
892 desc->dest = imxdmac->per_address;
893 }
894 desc->desc.callback = NULL;
895 desc->desc.callback_param = NULL;
896
897 return &desc->desc;
898 }
899
900 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
901 struct dma_chan *chan, dma_addr_t dest,
902 dma_addr_t src, size_t len, unsigned long flags)
903 {
904 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
905 struct imxdma_engine *imxdma = imxdmac->imxdma;
906 struct imxdma_desc *desc;
907
908 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
909 __func__, imxdmac->channel, src, dest, len);
910
911 if (list_empty(&imxdmac->ld_free) ||
912 imxdma_chan_is_doing_cyclic(imxdmac))
913 return NULL;
914
915 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
916
917 desc->type = IMXDMA_DESC_MEMCPY;
918 desc->src = src;
919 desc->dest = dest;
920 desc->len = len;
921 desc->direction = DMA_MEM_TO_MEM;
922 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
923 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
924 desc->desc.callback = NULL;
925 desc->desc.callback_param = NULL;
926
927 return &desc->desc;
928 }
929
930 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
931 struct dma_chan *chan, struct dma_interleaved_template *xt,
932 unsigned long flags)
933 {
934 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
935 struct imxdma_engine *imxdma = imxdmac->imxdma;
936 struct imxdma_desc *desc;
937
938 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
939 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
940 imxdmac->channel, xt->src_start, xt->dst_start,
941 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
942 xt->numf, xt->frame_size);
943
944 if (list_empty(&imxdmac->ld_free) ||
945 imxdma_chan_is_doing_cyclic(imxdmac))
946 return NULL;
947
948 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
949 return NULL;
950
951 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
952
953 desc->type = IMXDMA_DESC_INTERLEAVED;
954 desc->src = xt->src_start;
955 desc->dest = xt->dst_start;
956 desc->x = xt->sgl[0].size;
957 desc->y = xt->numf;
958 desc->w = xt->sgl[0].icg + desc->x;
959 desc->len = desc->x * desc->y;
960 desc->direction = DMA_MEM_TO_MEM;
961 desc->config_port = IMX_DMA_MEMSIZE_32;
962 desc->config_mem = IMX_DMA_MEMSIZE_32;
963 if (xt->src_sgl)
964 desc->config_mem |= IMX_DMA_TYPE_2D;
965 if (xt->dst_sgl)
966 desc->config_port |= IMX_DMA_TYPE_2D;
967 desc->desc.callback = NULL;
968 desc->desc.callback_param = NULL;
969
970 return &desc->desc;
971 }
972
973 static void imxdma_issue_pending(struct dma_chan *chan)
974 {
975 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
976 struct imxdma_engine *imxdma = imxdmac->imxdma;
977 struct imxdma_desc *desc;
978 unsigned long flags;
979
980 spin_lock_irqsave(&imxdma->lock, flags);
981 if (list_empty(&imxdmac->ld_active) &&
982 !list_empty(&imxdmac->ld_queue)) {
983 desc = list_first_entry(&imxdmac->ld_queue,
984 struct imxdma_desc, node);
985
986 if (imxdma_xfer_desc(desc) < 0) {
987 dev_warn(imxdma->dev,
988 "%s: channel: %d couldn't issue DMA xfer\n",
989 __func__, imxdmac->channel);
990 } else {
991 list_move_tail(imxdmac->ld_queue.next,
992 &imxdmac->ld_active);
993 }
994 }
995 spin_unlock_irqrestore(&imxdma->lock, flags);
996 }
997
998 static int __init imxdma_probe(struct platform_device *pdev)
999 {
1000 struct imxdma_engine *imxdma;
1001 struct resource *res;
1002 int ret, i;
1003 int irq, irq_err;
1004
1005 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1006 if (!imxdma)
1007 return -ENOMEM;
1008
1009 imxdma->devtype = pdev->id_entry->driver_data;
1010
1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1012 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1013 if (IS_ERR(imxdma->base))
1014 return PTR_ERR(imxdma->base);
1015
1016 irq = platform_get_irq(pdev, 0);
1017 if (irq < 0)
1018 return irq;
1019
1020 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1021 if (IS_ERR(imxdma->dma_ipg))
1022 return PTR_ERR(imxdma->dma_ipg);
1023
1024 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1025 if (IS_ERR(imxdma->dma_ahb))
1026 return PTR_ERR(imxdma->dma_ahb);
1027
1028 clk_prepare_enable(imxdma->dma_ipg);
1029 clk_prepare_enable(imxdma->dma_ahb);
1030
1031 /* reset DMA module */
1032 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1033
1034 if (is_imx1_dma(imxdma)) {
1035 ret = devm_request_irq(&pdev->dev, irq,
1036 dma_irq_handler, 0, "DMA", imxdma);
1037 if (ret) {
1038 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1039 goto err;
1040 }
1041
1042 irq_err = platform_get_irq(pdev, 1);
1043 if (irq_err < 0) {
1044 ret = irq_err;
1045 goto err;
1046 }
1047
1048 ret = devm_request_irq(&pdev->dev, irq_err,
1049 imxdma_err_handler, 0, "DMA", imxdma);
1050 if (ret) {
1051 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1052 goto err;
1053 }
1054 }
1055
1056 /* enable DMA module */
1057 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1058
1059 /* clear all interrupts */
1060 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1061
1062 /* disable interrupts */
1063 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1064
1065 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1066
1067 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1068 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1069 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1070 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1071
1072 /* Initialize 2D global parameters */
1073 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1074 imxdma->slots_2d[i].count = 0;
1075
1076 spin_lock_init(&imxdma->lock);
1077
1078 /* Initialize channel parameters */
1079 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1080 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1081
1082 if (!is_imx1_dma(imxdma)) {
1083 ret = devm_request_irq(&pdev->dev, irq + i,
1084 dma_irq_handler, 0, "DMA", imxdma);
1085 if (ret) {
1086 dev_warn(imxdma->dev, "Can't register IRQ %d "
1087 "for DMA channel %d\n",
1088 irq + i, i);
1089 goto err;
1090 }
1091 init_timer(&imxdmac->watchdog);
1092 imxdmac->watchdog.function = &imxdma_watchdog;
1093 imxdmac->watchdog.data = (unsigned long)imxdmac;
1094 }
1095
1096 imxdmac->imxdma = imxdma;
1097
1098 INIT_LIST_HEAD(&imxdmac->ld_queue);
1099 INIT_LIST_HEAD(&imxdmac->ld_free);
1100 INIT_LIST_HEAD(&imxdmac->ld_active);
1101
1102 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1103 (unsigned long)imxdmac);
1104 imxdmac->chan.device = &imxdma->dma_device;
1105 dma_cookie_init(&imxdmac->chan);
1106 imxdmac->channel = i;
1107
1108 /* Add the channel to the DMAC list */
1109 list_add_tail(&imxdmac->chan.device_node,
1110 &imxdma->dma_device.channels);
1111 }
1112
1113 imxdma->dev = &pdev->dev;
1114 imxdma->dma_device.dev = &pdev->dev;
1115
1116 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1117 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1118 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1119 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1120 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1121 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1122 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1123 imxdma->dma_device.device_control = imxdma_control;
1124 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1125
1126 platform_set_drvdata(pdev, imxdma);
1127
1128 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1129 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1130 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1131
1132 ret = dma_async_device_register(&imxdma->dma_device);
1133 if (ret) {
1134 dev_err(&pdev->dev, "unable to register\n");
1135 goto err;
1136 }
1137
1138 return 0;
1139
1140 err:
1141 clk_disable_unprepare(imxdma->dma_ipg);
1142 clk_disable_unprepare(imxdma->dma_ahb);
1143 return ret;
1144 }
1145
1146 static int imxdma_remove(struct platform_device *pdev)
1147 {
1148 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1149
1150 dma_async_device_unregister(&imxdma->dma_device);
1151
1152 clk_disable_unprepare(imxdma->dma_ipg);
1153 clk_disable_unprepare(imxdma->dma_ahb);
1154
1155 return 0;
1156 }
1157
1158 static struct platform_driver imxdma_driver = {
1159 .driver = {
1160 .name = "imx-dma",
1161 },
1162 .id_table = imx_dma_devtype,
1163 .remove = imxdma_remove,
1164 };
1165
1166 static int __init imxdma_module_init(void)
1167 {
1168 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1169 }
1170 subsys_initcall(imxdma_module_init);
1171
1172 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1173 MODULE_DESCRIPTION("i.MX dma driver");
1174 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)