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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / imx-dma.c
1 /*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
9 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/mm.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/module.h>
30
31 #include <asm/irq.h>
32 #include <linux/platform_data/dma-imx.h>
33
34 #include "dmaengine.h"
35 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
36 #define IMX_DMA_CHANNELS 16
37
38 #define IMX_DMA_2D_SLOTS 2
39 #define IMX_DMA_2D_SLOT_A 0
40 #define IMX_DMA_2D_SLOT_B 1
41
42 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
43 #define IMX_DMA_MEMSIZE_32 (0 << 4)
44 #define IMX_DMA_MEMSIZE_8 (1 << 4)
45 #define IMX_DMA_MEMSIZE_16 (2 << 4)
46 #define IMX_DMA_TYPE_LINEAR (0 << 10)
47 #define IMX_DMA_TYPE_2D (1 << 10)
48 #define IMX_DMA_TYPE_FIFO (2 << 10)
49
50 #define IMX_DMA_ERR_BURST (1 << 0)
51 #define IMX_DMA_ERR_REQUEST (1 << 1)
52 #define IMX_DMA_ERR_TRANSFER (1 << 2)
53 #define IMX_DMA_ERR_BUFFER (1 << 3)
54 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
55
56 #define DMA_DCR 0x00 /* Control Register */
57 #define DMA_DISR 0x04 /* Interrupt status Register */
58 #define DMA_DIMR 0x08 /* Interrupt mask Register */
59 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
60 #define DMA_DRTOSR 0x10 /* Request timeout Register */
61 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
62 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
63 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
64 #define DMA_WSRA 0x40 /* W-Size Register A */
65 #define DMA_XSRA 0x44 /* X-Size Register A */
66 #define DMA_YSRA 0x48 /* Y-Size Register A */
67 #define DMA_WSRB 0x4c /* W-Size Register B */
68 #define DMA_XSRB 0x50 /* X-Size Register B */
69 #define DMA_YSRB 0x54 /* Y-Size Register B */
70 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
71 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
72 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
73 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
74 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
75 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
76 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
77 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
78 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
79
80 #define DCR_DRST (1<<1)
81 #define DCR_DEN (1<<0)
82 #define DBTOCR_EN (1<<15)
83 #define DBTOCR_CNT(x) ((x) & 0x7fff)
84 #define CNTR_CNT(x) ((x) & 0xffffff)
85 #define CCR_ACRPT (1<<14)
86 #define CCR_DMOD_LINEAR (0x0 << 12)
87 #define CCR_DMOD_2D (0x1 << 12)
88 #define CCR_DMOD_FIFO (0x2 << 12)
89 #define CCR_DMOD_EOBFIFO (0x3 << 12)
90 #define CCR_SMOD_LINEAR (0x0 << 10)
91 #define CCR_SMOD_2D (0x1 << 10)
92 #define CCR_SMOD_FIFO (0x2 << 10)
93 #define CCR_SMOD_EOBFIFO (0x3 << 10)
94 #define CCR_MDIR_DEC (1<<9)
95 #define CCR_MSEL_B (1<<8)
96 #define CCR_DSIZ_32 (0x0 << 6)
97 #define CCR_DSIZ_8 (0x1 << 6)
98 #define CCR_DSIZ_16 (0x2 << 6)
99 #define CCR_SSIZ_32 (0x0 << 4)
100 #define CCR_SSIZ_8 (0x1 << 4)
101 #define CCR_SSIZ_16 (0x2 << 4)
102 #define CCR_REN (1<<3)
103 #define CCR_RPT (1<<2)
104 #define CCR_FRC (1<<1)
105 #define CCR_CEN (1<<0)
106 #define RTOR_EN (1<<15)
107 #define RTOR_CLK (1<<14)
108 #define RTOR_PSC (1<<13)
109
110 enum imxdma_prep_type {
111 IMXDMA_DESC_MEMCPY,
112 IMXDMA_DESC_INTERLEAVED,
113 IMXDMA_DESC_SLAVE_SG,
114 IMXDMA_DESC_CYCLIC,
115 };
116
117 struct imx_dma_2d_config {
118 u16 xsr;
119 u16 ysr;
120 u16 wsr;
121 int count;
122 };
123
124 struct imxdma_desc {
125 struct list_head node;
126 struct dma_async_tx_descriptor desc;
127 enum dma_status status;
128 dma_addr_t src;
129 dma_addr_t dest;
130 size_t len;
131 enum dma_transfer_direction direction;
132 enum imxdma_prep_type type;
133 /* For memcpy and interleaved */
134 unsigned int config_port;
135 unsigned int config_mem;
136 /* For interleaved transfers */
137 unsigned int x;
138 unsigned int y;
139 unsigned int w;
140 /* For slave sg and cyclic */
141 struct scatterlist *sg;
142 unsigned int sgcount;
143 };
144
145 struct imxdma_channel {
146 int hw_chaining;
147 struct timer_list watchdog;
148 struct imxdma_engine *imxdma;
149 unsigned int channel;
150
151 struct tasklet_struct dma_tasklet;
152 struct list_head ld_free;
153 struct list_head ld_queue;
154 struct list_head ld_active;
155 int descs_allocated;
156 enum dma_slave_buswidth word_size;
157 dma_addr_t per_address;
158 u32 watermark_level;
159 struct dma_chan chan;
160 struct dma_async_tx_descriptor desc;
161 enum dma_status status;
162 int dma_request;
163 struct scatterlist *sg_list;
164 u32 ccr_from_device;
165 u32 ccr_to_device;
166 bool enabled_2d;
167 int slot_2d;
168 };
169
170 enum imx_dma_type {
171 IMX1_DMA,
172 IMX21_DMA,
173 IMX27_DMA,
174 };
175
176 struct imxdma_engine {
177 struct device *dev;
178 struct device_dma_parameters dma_parms;
179 struct dma_device dma_device;
180 void __iomem *base;
181 struct clk *dma_ahb;
182 struct clk *dma_ipg;
183 spinlock_t lock;
184 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
185 struct imxdma_channel channel[IMX_DMA_CHANNELS];
186 enum imx_dma_type devtype;
187 };
188
189 static struct platform_device_id imx_dma_devtype[] = {
190 {
191 .name = "imx1-dma",
192 .driver_data = IMX1_DMA,
193 }, {
194 .name = "imx21-dma",
195 .driver_data = IMX21_DMA,
196 }, {
197 .name = "imx27-dma",
198 .driver_data = IMX27_DMA,
199 }, {
200 /* sentinel */
201 }
202 };
203 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
204
205 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
206 {
207 return imxdma->devtype == IMX1_DMA;
208 }
209
210 static inline int is_imx21_dma(struct imxdma_engine *imxdma)
211 {
212 return imxdma->devtype == IMX21_DMA;
213 }
214
215 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
216 {
217 return imxdma->devtype == IMX27_DMA;
218 }
219
220 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
221 {
222 return container_of(chan, struct imxdma_channel, chan);
223 }
224
225 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
226 {
227 struct imxdma_desc *desc;
228
229 if (!list_empty(&imxdmac->ld_active)) {
230 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
231 node);
232 if (desc->type == IMXDMA_DESC_CYCLIC)
233 return true;
234 }
235 return false;
236 }
237
238
239
240 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
241 unsigned offset)
242 {
243 __raw_writel(val, imxdma->base + offset);
244 }
245
246 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
247 {
248 return __raw_readl(imxdma->base + offset);
249 }
250
251 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
252 {
253 struct imxdma_engine *imxdma = imxdmac->imxdma;
254
255 if (is_imx27_dma(imxdma))
256 return imxdmac->hw_chaining;
257 else
258 return 0;
259 }
260
261 /*
262 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
263 */
264 static inline int imxdma_sg_next(struct imxdma_desc *d)
265 {
266 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
267 struct imxdma_engine *imxdma = imxdmac->imxdma;
268 struct scatterlist *sg = d->sg;
269 unsigned long now;
270
271 now = min(d->len, sg_dma_len(sg));
272 if (d->len != IMX_DMA_LENGTH_LOOP)
273 d->len -= now;
274
275 if (d->direction == DMA_DEV_TO_MEM)
276 imx_dmav1_writel(imxdma, sg->dma_address,
277 DMA_DAR(imxdmac->channel));
278 else
279 imx_dmav1_writel(imxdma, sg->dma_address,
280 DMA_SAR(imxdmac->channel));
281
282 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
283
284 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
285 "size 0x%08x\n", __func__, imxdmac->channel,
286 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
287 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
288 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
289
290 return now;
291 }
292
293 static void imxdma_enable_hw(struct imxdma_desc *d)
294 {
295 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
296 struct imxdma_engine *imxdma = imxdmac->imxdma;
297 int channel = imxdmac->channel;
298 unsigned long flags;
299
300 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
301
302 local_irq_save(flags);
303
304 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
305 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
306 ~(1 << channel), DMA_DIMR);
307 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
308 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
309
310 if (!is_imx1_dma(imxdma) &&
311 d->sg && imxdma_hw_chain(imxdmac)) {
312 d->sg = sg_next(d->sg);
313 if (d->sg) {
314 u32 tmp;
315 imxdma_sg_next(d);
316 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
317 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
318 DMA_CCR(channel));
319 }
320 }
321
322 local_irq_restore(flags);
323 }
324
325 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
326 {
327 struct imxdma_engine *imxdma = imxdmac->imxdma;
328 int channel = imxdmac->channel;
329 unsigned long flags;
330
331 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
332
333 if (imxdma_hw_chain(imxdmac))
334 del_timer(&imxdmac->watchdog);
335
336 local_irq_save(flags);
337 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
338 (1 << channel), DMA_DIMR);
339 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
340 ~CCR_CEN, DMA_CCR(channel));
341 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
342 local_irq_restore(flags);
343 }
344
345 static void imxdma_watchdog(unsigned long data)
346 {
347 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
348 struct imxdma_engine *imxdma = imxdmac->imxdma;
349 int channel = imxdmac->channel;
350
351 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
352
353 /* Tasklet watchdog error handler */
354 tasklet_schedule(&imxdmac->dma_tasklet);
355 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
356 imxdmac->channel);
357 }
358
359 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
360 {
361 struct imxdma_engine *imxdma = dev_id;
362 unsigned int err_mask;
363 int i, disr;
364 int errcode;
365
366 disr = imx_dmav1_readl(imxdma, DMA_DISR);
367
368 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
369 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
370 imx_dmav1_readl(imxdma, DMA_DSESR) |
371 imx_dmav1_readl(imxdma, DMA_DBOSR);
372
373 if (!err_mask)
374 return IRQ_HANDLED;
375
376 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
377
378 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
379 if (!(err_mask & (1 << i)))
380 continue;
381 errcode = 0;
382
383 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
384 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
385 errcode |= IMX_DMA_ERR_BURST;
386 }
387 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
388 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
389 errcode |= IMX_DMA_ERR_REQUEST;
390 }
391 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
392 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
393 errcode |= IMX_DMA_ERR_TRANSFER;
394 }
395 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
396 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
397 errcode |= IMX_DMA_ERR_BUFFER;
398 }
399 /* Tasklet error handler */
400 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
401
402 printk(KERN_WARNING
403 "DMA timeout on channel %d -%s%s%s%s\n", i,
404 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
405 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
406 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
407 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
408 }
409 return IRQ_HANDLED;
410 }
411
412 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
413 {
414 struct imxdma_engine *imxdma = imxdmac->imxdma;
415 int chno = imxdmac->channel;
416 struct imxdma_desc *desc;
417
418 spin_lock(&imxdma->lock);
419 if (list_empty(&imxdmac->ld_active)) {
420 spin_unlock(&imxdma->lock);
421 goto out;
422 }
423
424 desc = list_first_entry(&imxdmac->ld_active,
425 struct imxdma_desc,
426 node);
427 spin_unlock(&imxdma->lock);
428
429 if (desc->sg) {
430 u32 tmp;
431 desc->sg = sg_next(desc->sg);
432
433 if (desc->sg) {
434 imxdma_sg_next(desc);
435
436 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
437
438 if (imxdma_hw_chain(imxdmac)) {
439 /* FIXME: The timeout should probably be
440 * configurable
441 */
442 mod_timer(&imxdmac->watchdog,
443 jiffies + msecs_to_jiffies(500));
444
445 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
446 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
447 } else {
448 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
449 DMA_CCR(chno));
450 tmp |= CCR_CEN;
451 }
452
453 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
454
455 if (imxdma_chan_is_doing_cyclic(imxdmac))
456 /* Tasklet progression */
457 tasklet_schedule(&imxdmac->dma_tasklet);
458
459 return;
460 }
461
462 if (imxdma_hw_chain(imxdmac)) {
463 del_timer(&imxdmac->watchdog);
464 return;
465 }
466 }
467
468 out:
469 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
470 /* Tasklet irq */
471 tasklet_schedule(&imxdmac->dma_tasklet);
472 }
473
474 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
475 {
476 struct imxdma_engine *imxdma = dev_id;
477 int i, disr;
478
479 if (!is_imx1_dma(imxdma))
480 imxdma_err_handler(irq, dev_id);
481
482 disr = imx_dmav1_readl(imxdma, DMA_DISR);
483
484 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
485
486 imx_dmav1_writel(imxdma, disr, DMA_DISR);
487 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
488 if (disr & (1 << i))
489 dma_irq_handle_channel(&imxdma->channel[i]);
490 }
491
492 return IRQ_HANDLED;
493 }
494
495 static int imxdma_xfer_desc(struct imxdma_desc *d)
496 {
497 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
498 struct imxdma_engine *imxdma = imxdmac->imxdma;
499 unsigned long flags;
500 int slot = -1;
501 int i;
502
503 /* Configure and enable */
504 switch (d->type) {
505 case IMXDMA_DESC_INTERLEAVED:
506 /* Try to get a free 2D slot */
507 spin_lock_irqsave(&imxdma->lock, flags);
508 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
509 if ((imxdma->slots_2d[i].count > 0) &&
510 ((imxdma->slots_2d[i].xsr != d->x) ||
511 (imxdma->slots_2d[i].ysr != d->y) ||
512 (imxdma->slots_2d[i].wsr != d->w)))
513 continue;
514 slot = i;
515 break;
516 }
517 if (slot < 0) {
518 spin_unlock_irqrestore(&imxdma->lock, flags);
519 return -EBUSY;
520 }
521
522 imxdma->slots_2d[slot].xsr = d->x;
523 imxdma->slots_2d[slot].ysr = d->y;
524 imxdma->slots_2d[slot].wsr = d->w;
525 imxdma->slots_2d[slot].count++;
526
527 imxdmac->slot_2d = slot;
528 imxdmac->enabled_2d = true;
529 spin_unlock_irqrestore(&imxdma->lock, flags);
530
531 if (slot == IMX_DMA_2D_SLOT_A) {
532 d->config_mem &= ~CCR_MSEL_B;
533 d->config_port &= ~CCR_MSEL_B;
534 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
535 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
536 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
537 } else {
538 d->config_mem |= CCR_MSEL_B;
539 d->config_port |= CCR_MSEL_B;
540 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
541 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
542 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
543 }
544 /*
545 * We fall-through here intentionally, since a 2D transfer is
546 * similar to MEMCPY just adding the 2D slot configuration.
547 */
548 case IMXDMA_DESC_MEMCPY:
549 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
550 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
551 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
552 DMA_CCR(imxdmac->channel));
553
554 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
555
556 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
557 "dma_length=%d\n", __func__, imxdmac->channel,
558 d->dest, d->src, d->len);
559
560 break;
561 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
562 case IMXDMA_DESC_CYCLIC:
563 case IMXDMA_DESC_SLAVE_SG:
564 if (d->direction == DMA_DEV_TO_MEM) {
565 imx_dmav1_writel(imxdma, imxdmac->per_address,
566 DMA_SAR(imxdmac->channel));
567 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
568 DMA_CCR(imxdmac->channel));
569
570 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
571 "total length=%d dev_addr=0x%08x (dev2mem)\n",
572 __func__, imxdmac->channel, d->sg, d->sgcount,
573 d->len, imxdmac->per_address);
574 } else if (d->direction == DMA_MEM_TO_DEV) {
575 imx_dmav1_writel(imxdma, imxdmac->per_address,
576 DMA_DAR(imxdmac->channel));
577 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
578 DMA_CCR(imxdmac->channel));
579
580 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
581 "total length=%d dev_addr=0x%08x (mem2dev)\n",
582 __func__, imxdmac->channel, d->sg, d->sgcount,
583 d->len, imxdmac->per_address);
584 } else {
585 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
586 __func__, imxdmac->channel);
587 return -EINVAL;
588 }
589
590 imxdma_sg_next(d);
591
592 break;
593 default:
594 return -EINVAL;
595 }
596 imxdma_enable_hw(d);
597 return 0;
598 }
599
600 static void imxdma_tasklet(unsigned long data)
601 {
602 struct imxdma_channel *imxdmac = (void *)data;
603 struct imxdma_engine *imxdma = imxdmac->imxdma;
604 struct imxdma_desc *desc;
605
606 spin_lock(&imxdma->lock);
607
608 if (list_empty(&imxdmac->ld_active)) {
609 /* Someone might have called terminate all */
610 goto out;
611 }
612 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
613
614 if (desc->desc.callback)
615 desc->desc.callback(desc->desc.callback_param);
616
617 /* If we are dealing with a cyclic descriptor, keep it on ld_active
618 * and dont mark the descriptor as complete.
619 * Only in non-cyclic cases it would be marked as complete
620 */
621 if (imxdma_chan_is_doing_cyclic(imxdmac))
622 goto out;
623 else
624 dma_cookie_complete(&desc->desc);
625
626 /* Free 2D slot if it was an interleaved transfer */
627 if (imxdmac->enabled_2d) {
628 imxdma->slots_2d[imxdmac->slot_2d].count--;
629 imxdmac->enabled_2d = false;
630 }
631
632 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
633
634 if (!list_empty(&imxdmac->ld_queue)) {
635 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
636 node);
637 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
638 if (imxdma_xfer_desc(desc) < 0)
639 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
640 __func__, imxdmac->channel);
641 }
642 out:
643 spin_unlock(&imxdma->lock);
644 }
645
646 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
647 unsigned long arg)
648 {
649 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
650 struct dma_slave_config *dmaengine_cfg = (void *)arg;
651 struct imxdma_engine *imxdma = imxdmac->imxdma;
652 unsigned long flags;
653 unsigned int mode = 0;
654
655 switch (cmd) {
656 case DMA_TERMINATE_ALL:
657 imxdma_disable_hw(imxdmac);
658
659 spin_lock_irqsave(&imxdma->lock, flags);
660 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
661 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
662 spin_unlock_irqrestore(&imxdma->lock, flags);
663 return 0;
664 case DMA_SLAVE_CONFIG:
665 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
666 imxdmac->per_address = dmaengine_cfg->src_addr;
667 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
668 imxdmac->word_size = dmaengine_cfg->src_addr_width;
669 } else {
670 imxdmac->per_address = dmaengine_cfg->dst_addr;
671 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
672 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
673 }
674
675 switch (imxdmac->word_size) {
676 case DMA_SLAVE_BUSWIDTH_1_BYTE:
677 mode = IMX_DMA_MEMSIZE_8;
678 break;
679 case DMA_SLAVE_BUSWIDTH_2_BYTES:
680 mode = IMX_DMA_MEMSIZE_16;
681 break;
682 default:
683 case DMA_SLAVE_BUSWIDTH_4_BYTES:
684 mode = IMX_DMA_MEMSIZE_32;
685 break;
686 }
687
688 imxdmac->hw_chaining = 0;
689
690 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
691 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
692 CCR_REN;
693 imxdmac->ccr_to_device =
694 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
695 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
696 imx_dmav1_writel(imxdma, imxdmac->dma_request,
697 DMA_RSSR(imxdmac->channel));
698
699 /* Set burst length */
700 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
701 imxdmac->word_size, DMA_BLR(imxdmac->channel));
702
703 return 0;
704 default:
705 return -ENOSYS;
706 }
707
708 return -EINVAL;
709 }
710
711 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
712 dma_cookie_t cookie,
713 struct dma_tx_state *txstate)
714 {
715 return dma_cookie_status(chan, cookie, txstate);
716 }
717
718 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
719 {
720 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
721 struct imxdma_engine *imxdma = imxdmac->imxdma;
722 dma_cookie_t cookie;
723 unsigned long flags;
724
725 spin_lock_irqsave(&imxdma->lock, flags);
726 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
727 cookie = dma_cookie_assign(tx);
728 spin_unlock_irqrestore(&imxdma->lock, flags);
729
730 return cookie;
731 }
732
733 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
734 {
735 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
736 struct imx_dma_data *data = chan->private;
737
738 if (data != NULL)
739 imxdmac->dma_request = data->dma_request;
740
741 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
742 struct imxdma_desc *desc;
743
744 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
745 if (!desc)
746 break;
747 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
748 dma_async_tx_descriptor_init(&desc->desc, chan);
749 desc->desc.tx_submit = imxdma_tx_submit;
750 /* txd.flags will be overwritten in prep funcs */
751 desc->desc.flags = DMA_CTRL_ACK;
752 desc->status = DMA_SUCCESS;
753
754 list_add_tail(&desc->node, &imxdmac->ld_free);
755 imxdmac->descs_allocated++;
756 }
757
758 if (!imxdmac->descs_allocated)
759 return -ENOMEM;
760
761 return imxdmac->descs_allocated;
762 }
763
764 static void imxdma_free_chan_resources(struct dma_chan *chan)
765 {
766 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
767 struct imxdma_engine *imxdma = imxdmac->imxdma;
768 struct imxdma_desc *desc, *_desc;
769 unsigned long flags;
770
771 spin_lock_irqsave(&imxdma->lock, flags);
772
773 imxdma_disable_hw(imxdmac);
774 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
775 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
776
777 spin_unlock_irqrestore(&imxdma->lock, flags);
778
779 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
780 kfree(desc);
781 imxdmac->descs_allocated--;
782 }
783 INIT_LIST_HEAD(&imxdmac->ld_free);
784
785 if (imxdmac->sg_list) {
786 kfree(imxdmac->sg_list);
787 imxdmac->sg_list = NULL;
788 }
789 }
790
791 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
792 struct dma_chan *chan, struct scatterlist *sgl,
793 unsigned int sg_len, enum dma_transfer_direction direction,
794 unsigned long flags, void *context)
795 {
796 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
797 struct scatterlist *sg;
798 int i, dma_length = 0;
799 struct imxdma_desc *desc;
800
801 if (list_empty(&imxdmac->ld_free) ||
802 imxdma_chan_is_doing_cyclic(imxdmac))
803 return NULL;
804
805 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
806
807 for_each_sg(sgl, sg, sg_len, i) {
808 dma_length += sg_dma_len(sg);
809 }
810
811 switch (imxdmac->word_size) {
812 case DMA_SLAVE_BUSWIDTH_4_BYTES:
813 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
814 return NULL;
815 break;
816 case DMA_SLAVE_BUSWIDTH_2_BYTES:
817 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
818 return NULL;
819 break;
820 case DMA_SLAVE_BUSWIDTH_1_BYTE:
821 break;
822 default:
823 return NULL;
824 }
825
826 desc->type = IMXDMA_DESC_SLAVE_SG;
827 desc->sg = sgl;
828 desc->sgcount = sg_len;
829 desc->len = dma_length;
830 desc->direction = direction;
831 if (direction == DMA_DEV_TO_MEM) {
832 desc->src = imxdmac->per_address;
833 } else {
834 desc->dest = imxdmac->per_address;
835 }
836 desc->desc.callback = NULL;
837 desc->desc.callback_param = NULL;
838
839 return &desc->desc;
840 }
841
842 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
843 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
844 size_t period_len, enum dma_transfer_direction direction,
845 unsigned long flags, void *context)
846 {
847 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
848 struct imxdma_engine *imxdma = imxdmac->imxdma;
849 struct imxdma_desc *desc;
850 int i;
851 unsigned int periods = buf_len / period_len;
852
853 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
854 __func__, imxdmac->channel, buf_len, period_len);
855
856 if (list_empty(&imxdmac->ld_free) ||
857 imxdma_chan_is_doing_cyclic(imxdmac))
858 return NULL;
859
860 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
861
862 kfree(imxdmac->sg_list);
863
864 imxdmac->sg_list = kcalloc(periods + 1,
865 sizeof(struct scatterlist), GFP_KERNEL);
866 if (!imxdmac->sg_list)
867 return NULL;
868
869 sg_init_table(imxdmac->sg_list, periods);
870
871 for (i = 0; i < periods; i++) {
872 imxdmac->sg_list[i].page_link = 0;
873 imxdmac->sg_list[i].offset = 0;
874 imxdmac->sg_list[i].dma_address = dma_addr;
875 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
876 dma_addr += period_len;
877 }
878
879 /* close the loop */
880 imxdmac->sg_list[periods].offset = 0;
881 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
882 imxdmac->sg_list[periods].page_link =
883 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
884
885 desc->type = IMXDMA_DESC_CYCLIC;
886 desc->sg = imxdmac->sg_list;
887 desc->sgcount = periods;
888 desc->len = IMX_DMA_LENGTH_LOOP;
889 desc->direction = direction;
890 if (direction == DMA_DEV_TO_MEM) {
891 desc->src = imxdmac->per_address;
892 } else {
893 desc->dest = imxdmac->per_address;
894 }
895 desc->desc.callback = NULL;
896 desc->desc.callback_param = NULL;
897
898 return &desc->desc;
899 }
900
901 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
902 struct dma_chan *chan, dma_addr_t dest,
903 dma_addr_t src, size_t len, unsigned long flags)
904 {
905 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
906 struct imxdma_engine *imxdma = imxdmac->imxdma;
907 struct imxdma_desc *desc;
908
909 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
910 __func__, imxdmac->channel, src, dest, len);
911
912 if (list_empty(&imxdmac->ld_free) ||
913 imxdma_chan_is_doing_cyclic(imxdmac))
914 return NULL;
915
916 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
917
918 desc->type = IMXDMA_DESC_MEMCPY;
919 desc->src = src;
920 desc->dest = dest;
921 desc->len = len;
922 desc->direction = DMA_MEM_TO_MEM;
923 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
924 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
925 desc->desc.callback = NULL;
926 desc->desc.callback_param = NULL;
927
928 return &desc->desc;
929 }
930
931 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
932 struct dma_chan *chan, struct dma_interleaved_template *xt,
933 unsigned long flags)
934 {
935 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
936 struct imxdma_engine *imxdma = imxdmac->imxdma;
937 struct imxdma_desc *desc;
938
939 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
940 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
941 imxdmac->channel, xt->src_start, xt->dst_start,
942 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
943 xt->numf, xt->frame_size);
944
945 if (list_empty(&imxdmac->ld_free) ||
946 imxdma_chan_is_doing_cyclic(imxdmac))
947 return NULL;
948
949 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
950 return NULL;
951
952 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
953
954 desc->type = IMXDMA_DESC_INTERLEAVED;
955 desc->src = xt->src_start;
956 desc->dest = xt->dst_start;
957 desc->x = xt->sgl[0].size;
958 desc->y = xt->numf;
959 desc->w = xt->sgl[0].icg + desc->x;
960 desc->len = desc->x * desc->y;
961 desc->direction = DMA_MEM_TO_MEM;
962 desc->config_port = IMX_DMA_MEMSIZE_32;
963 desc->config_mem = IMX_DMA_MEMSIZE_32;
964 if (xt->src_sgl)
965 desc->config_mem |= IMX_DMA_TYPE_2D;
966 if (xt->dst_sgl)
967 desc->config_port |= IMX_DMA_TYPE_2D;
968 desc->desc.callback = NULL;
969 desc->desc.callback_param = NULL;
970
971 return &desc->desc;
972 }
973
974 static void imxdma_issue_pending(struct dma_chan *chan)
975 {
976 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
977 struct imxdma_engine *imxdma = imxdmac->imxdma;
978 struct imxdma_desc *desc;
979 unsigned long flags;
980
981 spin_lock_irqsave(&imxdma->lock, flags);
982 if (list_empty(&imxdmac->ld_active) &&
983 !list_empty(&imxdmac->ld_queue)) {
984 desc = list_first_entry(&imxdmac->ld_queue,
985 struct imxdma_desc, node);
986
987 if (imxdma_xfer_desc(desc) < 0) {
988 dev_warn(imxdma->dev,
989 "%s: channel: %d couldn't issue DMA xfer\n",
990 __func__, imxdmac->channel);
991 } else {
992 list_move_tail(imxdmac->ld_queue.next,
993 &imxdmac->ld_active);
994 }
995 }
996 spin_unlock_irqrestore(&imxdma->lock, flags);
997 }
998
999 static int __init imxdma_probe(struct platform_device *pdev)
1000 {
1001 struct imxdma_engine *imxdma;
1002 struct resource *res;
1003 int ret, i;
1004 int irq, irq_err;
1005
1006 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1007 if (!imxdma)
1008 return -ENOMEM;
1009
1010 imxdma->devtype = pdev->id_entry->driver_data;
1011
1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1013 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1014 if (IS_ERR(imxdma->base))
1015 return PTR_ERR(imxdma->base);
1016
1017 irq = platform_get_irq(pdev, 0);
1018 if (irq < 0)
1019 return irq;
1020
1021 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1022 if (IS_ERR(imxdma->dma_ipg))
1023 return PTR_ERR(imxdma->dma_ipg);
1024
1025 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1026 if (IS_ERR(imxdma->dma_ahb))
1027 return PTR_ERR(imxdma->dma_ahb);
1028
1029 clk_prepare_enable(imxdma->dma_ipg);
1030 clk_prepare_enable(imxdma->dma_ahb);
1031
1032 /* reset DMA module */
1033 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1034
1035 if (is_imx1_dma(imxdma)) {
1036 ret = devm_request_irq(&pdev->dev, irq,
1037 dma_irq_handler, 0, "DMA", imxdma);
1038 if (ret) {
1039 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1040 goto err;
1041 }
1042
1043 irq_err = platform_get_irq(pdev, 1);
1044 if (irq_err < 0) {
1045 ret = irq_err;
1046 goto err;
1047 }
1048
1049 ret = devm_request_irq(&pdev->dev, irq_err,
1050 imxdma_err_handler, 0, "DMA", imxdma);
1051 if (ret) {
1052 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1053 goto err;
1054 }
1055 }
1056
1057 /* enable DMA module */
1058 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1059
1060 /* clear all interrupts */
1061 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1062
1063 /* disable interrupts */
1064 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1065
1066 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1067
1068 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1069 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1070 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1071 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1072
1073 /* Initialize 2D global parameters */
1074 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1075 imxdma->slots_2d[i].count = 0;
1076
1077 spin_lock_init(&imxdma->lock);
1078
1079 /* Initialize channel parameters */
1080 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1081 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1082
1083 if (!is_imx1_dma(imxdma)) {
1084 ret = devm_request_irq(&pdev->dev, irq + i,
1085 dma_irq_handler, 0, "DMA", imxdma);
1086 if (ret) {
1087 dev_warn(imxdma->dev, "Can't register IRQ %d "
1088 "for DMA channel %d\n",
1089 irq + i, i);
1090 goto err;
1091 }
1092 init_timer(&imxdmac->watchdog);
1093 imxdmac->watchdog.function = &imxdma_watchdog;
1094 imxdmac->watchdog.data = (unsigned long)imxdmac;
1095 }
1096
1097 imxdmac->imxdma = imxdma;
1098
1099 INIT_LIST_HEAD(&imxdmac->ld_queue);
1100 INIT_LIST_HEAD(&imxdmac->ld_free);
1101 INIT_LIST_HEAD(&imxdmac->ld_active);
1102
1103 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1104 (unsigned long)imxdmac);
1105 imxdmac->chan.device = &imxdma->dma_device;
1106 dma_cookie_init(&imxdmac->chan);
1107 imxdmac->channel = i;
1108
1109 /* Add the channel to the DMAC list */
1110 list_add_tail(&imxdmac->chan.device_node,
1111 &imxdma->dma_device.channels);
1112 }
1113
1114 imxdma->dev = &pdev->dev;
1115 imxdma->dma_device.dev = &pdev->dev;
1116
1117 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1118 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1119 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1120 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1121 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1122 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1123 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1124 imxdma->dma_device.device_control = imxdma_control;
1125 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1126
1127 platform_set_drvdata(pdev, imxdma);
1128
1129 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1130 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1131 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1132
1133 ret = dma_async_device_register(&imxdma->dma_device);
1134 if (ret) {
1135 dev_err(&pdev->dev, "unable to register\n");
1136 goto err;
1137 }
1138
1139 return 0;
1140
1141 err:
1142 clk_disable_unprepare(imxdma->dma_ipg);
1143 clk_disable_unprepare(imxdma->dma_ahb);
1144 return ret;
1145 }
1146
1147 static int imxdma_remove(struct platform_device *pdev)
1148 {
1149 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1150
1151 dma_async_device_unregister(&imxdma->dma_device);
1152
1153 clk_disable_unprepare(imxdma->dma_ipg);
1154 clk_disable_unprepare(imxdma->dma_ahb);
1155
1156 return 0;
1157 }
1158
1159 static struct platform_driver imxdma_driver = {
1160 .driver = {
1161 .name = "imx-dma",
1162 },
1163 .id_table = imx_dma_devtype,
1164 .remove = imxdma_remove,
1165 };
1166
1167 static int __init imxdma_module_init(void)
1168 {
1169 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1170 }
1171 subsys_initcall(imxdma_module_init);
1172
1173 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1174 MODULE_DESCRIPTION("i.MX dma driver");
1175 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)