2 * drivers/dma/imx-dma.c
4 * This file contains a driver for the Freescale i.MX DMA engine
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/module.h>
33 #include <mach/hardware.h>
35 #include "dmaengine.h"
36 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
37 #define IMX_DMA_CHANNELS 16
39 #define DMA_MODE_READ 0
40 #define DMA_MODE_WRITE 1
41 #define DMA_MODE_MASK 1
43 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
44 #define IMX_DMA_MEMSIZE_32 (0 << 4)
45 #define IMX_DMA_MEMSIZE_8 (1 << 4)
46 #define IMX_DMA_MEMSIZE_16 (2 << 4)
47 #define IMX_DMA_TYPE_LINEAR (0 << 10)
48 #define IMX_DMA_TYPE_2D (1 << 10)
49 #define IMX_DMA_TYPE_FIFO (2 << 10)
51 #define IMX_DMA_ERR_BURST (1 << 0)
52 #define IMX_DMA_ERR_REQUEST (1 << 1)
53 #define IMX_DMA_ERR_TRANSFER (1 << 2)
54 #define IMX_DMA_ERR_BUFFER (1 << 3)
55 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
57 #define DMA_DCR 0x00 /* Control Register */
58 #define DMA_DISR 0x04 /* Interrupt status Register */
59 #define DMA_DIMR 0x08 /* Interrupt mask Register */
60 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
61 #define DMA_DRTOSR 0x10 /* Request timeout Register */
62 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
63 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
64 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
65 #define DMA_WSRA 0x40 /* W-Size Register A */
66 #define DMA_XSRA 0x44 /* X-Size Register A */
67 #define DMA_YSRA 0x48 /* Y-Size Register A */
68 #define DMA_WSRB 0x4c /* W-Size Register B */
69 #define DMA_XSRB 0x50 /* X-Size Register B */
70 #define DMA_YSRB 0x54 /* Y-Size Register B */
71 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
72 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
73 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
74 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
75 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
76 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
77 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
78 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
79 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
81 #define DCR_DRST (1<<1)
82 #define DCR_DEN (1<<0)
83 #define DBTOCR_EN (1<<15)
84 #define DBTOCR_CNT(x) ((x) & 0x7fff)
85 #define CNTR_CNT(x) ((x) & 0xffffff)
86 #define CCR_ACRPT (1<<14)
87 #define CCR_DMOD_LINEAR (0x0 << 12)
88 #define CCR_DMOD_2D (0x1 << 12)
89 #define CCR_DMOD_FIFO (0x2 << 12)
90 #define CCR_DMOD_EOBFIFO (0x3 << 12)
91 #define CCR_SMOD_LINEAR (0x0 << 10)
92 #define CCR_SMOD_2D (0x1 << 10)
93 #define CCR_SMOD_FIFO (0x2 << 10)
94 #define CCR_SMOD_EOBFIFO (0x3 << 10)
95 #define CCR_MDIR_DEC (1<<9)
96 #define CCR_MSEL_B (1<<8)
97 #define CCR_DSIZ_32 (0x0 << 6)
98 #define CCR_DSIZ_8 (0x1 << 6)
99 #define CCR_DSIZ_16 (0x2 << 6)
100 #define CCR_SSIZ_32 (0x0 << 4)
101 #define CCR_SSIZ_8 (0x1 << 4)
102 #define CCR_SSIZ_16 (0x2 << 4)
103 #define CCR_REN (1<<3)
104 #define CCR_RPT (1<<2)
105 #define CCR_FRC (1<<1)
106 #define CCR_CEN (1<<0)
107 #define RTOR_EN (1<<15)
108 #define RTOR_CLK (1<<14)
109 #define RTOR_PSC (1<<13)
111 enum imxdma_prep_type
{
113 IMXDMA_DESC_INTERLEAVED
,
114 IMXDMA_DESC_SLAVE_SG
,
119 * struct imxdma_channel_internal - i.MX specific DMA extension
120 * @name: name specified by DMA client
121 * @irq_handler: client callback for end of transfer
122 * @err_handler: client callback for error condition
123 * @data: clients context data for callbacks
124 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
125 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
126 * @resbytes: total residual number of bytes to transfer
127 * (it can be lower or same as sum of SG mapped chunk sizes)
128 * @sgcount: number of chunks to be read/written
130 * Structure is used for IMX DMA processing. It would be probably good
131 * @struct dma_struct in the future for external interfacing and use
132 * @struct imxdma_channel_internal only as extension to it.
135 struct imxdma_channel_internal
{
137 unsigned int dma_mode
;
138 struct scatterlist
*sg
;
139 unsigned int resbytes
;
146 struct timer_list watchdog
;
152 struct list_head node
;
153 struct dma_async_tx_descriptor desc
;
154 enum dma_status status
;
158 unsigned int dmamode
;
159 enum imxdma_prep_type type
;
160 /* For memcpy and interleaved */
161 unsigned int config_port
;
162 unsigned int config_mem
;
163 /* For interleaved transfers */
167 /* For slave sg and cyclic */
168 struct scatterlist
*sg
;
169 unsigned int sgcount
;
172 struct imxdma_channel
{
173 struct imxdma_channel_internal internal
;
174 struct imxdma_engine
*imxdma
;
175 unsigned int channel
;
177 struct tasklet_struct dma_tasklet
;
178 struct list_head ld_free
;
179 struct list_head ld_queue
;
180 struct list_head ld_active
;
182 enum dma_slave_buswidth word_size
;
183 dma_addr_t per_address
;
185 struct dma_chan chan
;
187 struct dma_async_tx_descriptor desc
;
188 enum dma_status status
;
190 struct scatterlist
*sg_list
;
193 struct imxdma_engine
{
195 struct device_dma_parameters dma_parms
;
196 struct dma_device dma_device
;
197 struct imxdma_channel channel
[IMX_DMA_CHANNELS
];
200 static struct imxdma_channel
*to_imxdma_chan(struct dma_chan
*chan
)
202 return container_of(chan
, struct imxdma_channel
, chan
);
205 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel
*imxdmac
)
207 struct imxdma_desc
*desc
;
209 if (!list_empty(&imxdmac
->ld_active
)) {
210 desc
= list_first_entry(&imxdmac
->ld_active
, struct imxdma_desc
,
212 if (desc
->type
== IMXDMA_DESC_CYCLIC
)
218 /* TODO: put this inside any struct */
219 static void __iomem
*imx_dmav1_baseaddr
;
220 static struct clk
*dma_clk
;
222 static void imx_dmav1_writel(unsigned val
, unsigned offset
)
224 __raw_writel(val
, imx_dmav1_baseaddr
+ offset
);
227 static unsigned imx_dmav1_readl(unsigned offset
)
229 return __raw_readl(imx_dmav1_baseaddr
+ offset
);
232 static int imxdma_hw_chain(struct imxdma_channel_internal
*imxdma
)
235 return imxdma
->hw_chaining
;
241 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
243 static inline int imxdma_sg_next(struct imxdma_channel
*imxdmac
, struct scatterlist
*sg
)
245 struct imxdma_channel_internal
*imxdma
= &imxdmac
->internal
;
248 now
= min(imxdma
->resbytes
, sg
->length
);
249 if (imxdma
->resbytes
!= IMX_DMA_LENGTH_LOOP
)
250 imxdma
->resbytes
-= now
;
252 if ((imxdma
->dma_mode
& DMA_MODE_MASK
) == DMA_MODE_READ
)
253 imx_dmav1_writel(sg
->dma_address
, DMA_DAR(imxdmac
->channel
));
255 imx_dmav1_writel(sg
->dma_address
, DMA_SAR(imxdmac
->channel
));
257 imx_dmav1_writel(now
, DMA_CNTR(imxdmac
->channel
));
259 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
260 "size 0x%08x\n", imxdmac
->channel
,
261 imx_dmav1_readl(DMA_DAR(imxdmac
->channel
)),
262 imx_dmav1_readl(DMA_SAR(imxdmac
->channel
)),
263 imx_dmav1_readl(DMA_CNTR(imxdmac
->channel
)));
269 imxdma_setup_single_hw(struct imxdma_channel
*imxdmac
, dma_addr_t dma_address
,
270 unsigned int dma_length
, unsigned int dev_addr
,
271 unsigned int dmamode
)
273 int channel
= imxdmac
->channel
;
275 imxdmac
->internal
.sg
= NULL
;
276 imxdmac
->internal
.dma_mode
= dmamode
;
279 printk(KERN_ERR
"imxdma%d: imx_dma_setup_single null address\n",
285 printk(KERN_ERR
"imxdma%d: imx_dma_setup_single zero length\n",
290 if ((dmamode
& DMA_MODE_MASK
) == DMA_MODE_READ
) {
291 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
292 "dev_addr=0x%08x for read\n",
293 channel
, __func__
, (unsigned int)dma_address
,
294 dma_length
, dev_addr
);
296 imx_dmav1_writel(dev_addr
, DMA_SAR(channel
));
297 imx_dmav1_writel(dma_address
, DMA_DAR(channel
));
298 imx_dmav1_writel(imxdmac
->internal
.ccr_from_device
, DMA_CCR(channel
));
299 } else if ((dmamode
& DMA_MODE_MASK
) == DMA_MODE_WRITE
) {
300 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
301 "dev_addr=0x%08x for write\n",
302 channel
, __func__
, (unsigned int)dma_address
,
303 dma_length
, dev_addr
);
305 imx_dmav1_writel(dma_address
, DMA_SAR(channel
));
306 imx_dmav1_writel(dev_addr
, DMA_DAR(channel
));
307 imx_dmav1_writel(imxdmac
->internal
.ccr_to_device
,
310 printk(KERN_ERR
"imxdma%d: imx_dma_setup_single bad dmamode\n",
315 imx_dmav1_writel(dma_length
, DMA_CNTR(channel
));
320 static void imxdma_enable_hw(struct imxdma_channel
*imxdmac
)
322 int channel
= imxdmac
->channel
;
325 pr_debug("imxdma%d: imx_dma_enable\n", channel
);
327 if (imxdmac
->internal
.in_use
)
330 local_irq_save(flags
);
332 imx_dmav1_writel(1 << channel
, DMA_DISR
);
333 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR
) & ~(1 << channel
), DMA_DIMR
);
334 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel
)) | CCR_CEN
|
335 CCR_ACRPT
, DMA_CCR(channel
));
337 if ((cpu_is_mx21() || cpu_is_mx27()) &&
338 imxdmac
->internal
.sg
&& imxdma_hw_chain(&imxdmac
->internal
)) {
339 imxdmac
->internal
.sg
= sg_next(imxdmac
->internal
.sg
);
340 if (imxdmac
->internal
.sg
) {
342 imxdma_sg_next(imxdmac
, imxdmac
->internal
.sg
);
343 tmp
= imx_dmav1_readl(DMA_CCR(channel
));
344 imx_dmav1_writel(tmp
| CCR_RPT
| CCR_ACRPT
,
348 imxdmac
->internal
.in_use
= 1;
350 local_irq_restore(flags
);
353 static void imxdma_disable_hw(struct imxdma_channel
*imxdmac
)
355 int channel
= imxdmac
->channel
;
358 pr_debug("imxdma%d: imx_dma_disable\n", channel
);
360 if (imxdma_hw_chain(&imxdmac
->internal
))
361 del_timer(&imxdmac
->internal
.watchdog
);
363 local_irq_save(flags
);
364 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR
) | (1 << channel
), DMA_DIMR
);
365 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel
)) & ~CCR_CEN
,
367 imx_dmav1_writel(1 << channel
, DMA_DISR
);
368 imxdmac
->internal
.in_use
= 0;
369 local_irq_restore(flags
);
373 imxdma_config_channel_hw(struct imxdma_channel
*imxdmac
, unsigned int config_port
,
374 unsigned int config_mem
, unsigned int dmareq
, int hw_chaining
)
376 int channel
= imxdmac
->channel
;
379 imxdmac
->internal
.hw_chaining
= 0;
382 imxdmac
->internal
.hw_chaining
= 1;
383 if (!imxdma_hw_chain(&imxdmac
->internal
))
390 imxdmac
->internal
.ccr_from_device
= config_port
| (config_mem
<< 2) | dreq
;
391 imxdmac
->internal
.ccr_to_device
= config_mem
| (config_port
<< 2) | dreq
;
393 imx_dmav1_writel(dmareq
, DMA_RSSR(channel
));
399 imxdma_setup_sg_hw(struct imxdma_channel
*imxdmac
,
400 struct scatterlist
*sg
, unsigned int sgcount
,
401 unsigned int dma_length
, unsigned int dev_addr
,
402 unsigned int dmamode
)
404 int channel
= imxdmac
->channel
;
406 if (imxdmac
->internal
.in_use
)
409 imxdmac
->internal
.sg
= sg
;
410 imxdmac
->internal
.dma_mode
= dmamode
;
411 imxdmac
->internal
.resbytes
= dma_length
;
413 if (!sg
|| !sgcount
) {
414 printk(KERN_ERR
"imxdma%d: imx_dma_setup_sg empty sg list\n",
420 printk(KERN_ERR
"imxdma%d: imx_dma_setup_sg zero length\n",
425 if ((dmamode
& DMA_MODE_MASK
) == DMA_MODE_READ
) {
426 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
427 "dev_addr=0x%08x for read\n",
428 channel
, __func__
, sg
, sgcount
, dma_length
, dev_addr
);
430 imx_dmav1_writel(dev_addr
, DMA_SAR(channel
));
431 imx_dmav1_writel(imxdmac
->internal
.ccr_from_device
, DMA_CCR(channel
));
432 } else if ((dmamode
& DMA_MODE_MASK
) == DMA_MODE_WRITE
) {
433 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
434 "dev_addr=0x%08x for write\n",
435 channel
, __func__
, sg
, sgcount
, dma_length
, dev_addr
);
437 imx_dmav1_writel(dev_addr
, DMA_DAR(channel
));
438 imx_dmav1_writel(imxdmac
->internal
.ccr_to_device
, DMA_CCR(channel
));
440 printk(KERN_ERR
"imxdma%d: imx_dma_setup_sg bad dmamode\n",
445 imxdma_sg_next(imxdmac
, sg
);
450 static void imxdma_watchdog(unsigned long data
)
452 struct imxdma_channel
*imxdmac
= (struct imxdma_channel
*)data
;
453 int channel
= imxdmac
->channel
;
455 imx_dmav1_writel(0, DMA_CCR(channel
));
456 imxdmac
->internal
.in_use
= 0;
457 imxdmac
->internal
.sg
= NULL
;
459 /* Tasklet watchdog error handler */
460 tasklet_schedule(&imxdmac
->dma_tasklet
);
461 pr_debug("imxdma%d: watchdog timeout!\n", imxdmac
->channel
);
464 static irqreturn_t
imxdma_err_handler(int irq
, void *dev_id
)
466 struct imxdma_engine
*imxdma
= dev_id
;
467 struct imxdma_channel_internal
*internal
;
468 unsigned int err_mask
;
472 disr
= imx_dmav1_readl(DMA_DISR
);
474 err_mask
= imx_dmav1_readl(DMA_DBTOSR
) |
475 imx_dmav1_readl(DMA_DRTOSR
) |
476 imx_dmav1_readl(DMA_DSESR
) |
477 imx_dmav1_readl(DMA_DBOSR
);
482 imx_dmav1_writel(disr
& err_mask
, DMA_DISR
);
484 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
485 if (!(err_mask
& (1 << i
)))
487 internal
= &imxdma
->channel
[i
].internal
;
490 if (imx_dmav1_readl(DMA_DBTOSR
) & (1 << i
)) {
491 imx_dmav1_writel(1 << i
, DMA_DBTOSR
);
492 errcode
|= IMX_DMA_ERR_BURST
;
494 if (imx_dmav1_readl(DMA_DRTOSR
) & (1 << i
)) {
495 imx_dmav1_writel(1 << i
, DMA_DRTOSR
);
496 errcode
|= IMX_DMA_ERR_REQUEST
;
498 if (imx_dmav1_readl(DMA_DSESR
) & (1 << i
)) {
499 imx_dmav1_writel(1 << i
, DMA_DSESR
);
500 errcode
|= IMX_DMA_ERR_TRANSFER
;
502 if (imx_dmav1_readl(DMA_DBOSR
) & (1 << i
)) {
503 imx_dmav1_writel(1 << i
, DMA_DBOSR
);
504 errcode
|= IMX_DMA_ERR_BUFFER
;
506 /* Tasklet error handler */
507 tasklet_schedule(&imxdma
->channel
[i
].dma_tasklet
);
510 "DMA timeout on channel %d -%s%s%s%s\n", i
,
511 errcode
& IMX_DMA_ERR_BURST
? " burst" : "",
512 errcode
& IMX_DMA_ERR_REQUEST
? " request" : "",
513 errcode
& IMX_DMA_ERR_TRANSFER
? " transfer" : "",
514 errcode
& IMX_DMA_ERR_BUFFER
? " buffer" : "");
519 static void dma_irq_handle_channel(struct imxdma_channel
*imxdmac
)
521 struct imxdma_channel_internal
*imxdma
= &imxdmac
->internal
;
522 int chno
= imxdmac
->channel
;
526 imxdma
->sg
= sg_next(imxdma
->sg
);
529 imxdma_sg_next(imxdmac
, imxdma
->sg
);
531 tmp
= imx_dmav1_readl(DMA_CCR(chno
));
533 if (imxdma_hw_chain(imxdma
)) {
534 /* FIXME: The timeout should probably be
537 mod_timer(&imxdma
->watchdog
,
538 jiffies
+ msecs_to_jiffies(500));
540 tmp
|= CCR_CEN
| CCR_RPT
| CCR_ACRPT
;
541 imx_dmav1_writel(tmp
, DMA_CCR(chno
));
543 imx_dmav1_writel(tmp
& ~CCR_CEN
, DMA_CCR(chno
));
547 imx_dmav1_writel(tmp
, DMA_CCR(chno
));
549 if (imxdma_chan_is_doing_cyclic(imxdmac
))
550 /* Tasklet progression */
551 tasklet_schedule(&imxdmac
->dma_tasklet
);
556 if (imxdma_hw_chain(imxdma
)) {
557 del_timer(&imxdma
->watchdog
);
562 imx_dmav1_writel(0, DMA_CCR(chno
));
565 tasklet_schedule(&imxdmac
->dma_tasklet
);
568 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
570 struct imxdma_engine
*imxdma
= dev_id
;
571 struct imxdma_channel_internal
*internal
;
574 if (cpu_is_mx21() || cpu_is_mx27())
575 imxdma_err_handler(irq
, dev_id
);
577 disr
= imx_dmav1_readl(DMA_DISR
);
579 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
582 imx_dmav1_writel(disr
, DMA_DISR
);
583 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
584 if (disr
& (1 << i
)) {
585 internal
= &imxdma
->channel
[i
].internal
;
586 dma_irq_handle_channel(&imxdma
->channel
[i
]);
593 static int imxdma_xfer_desc(struct imxdma_desc
*d
)
595 struct imxdma_channel
*imxdmac
= to_imxdma_chan(d
->desc
.chan
);
598 /* Configure and enable */
600 case IMXDMA_DESC_MEMCPY
:
601 ret
= imxdma_config_channel_hw(imxdmac
,
602 d
->config_port
, d
->config_mem
, 0, 0);
605 ret
= imxdma_setup_single_hw(imxdmac
, d
->src
,
606 d
->len
, d
->dest
, d
->dmamode
);
611 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
612 case IMXDMA_DESC_CYCLIC
:
613 case IMXDMA_DESC_SLAVE_SG
:
614 if (d
->dmamode
== DMA_MODE_READ
)
615 ret
= imxdma_setup_sg_hw(imxdmac
, d
->sg
,
616 d
->sgcount
, d
->len
, d
->src
, d
->dmamode
);
618 ret
= imxdma_setup_sg_hw(imxdmac
, d
->sg
,
619 d
->sgcount
, d
->len
, d
->dest
, d
->dmamode
);
626 imxdma_enable_hw(imxdmac
);
630 static void imxdma_tasklet(unsigned long data
)
632 struct imxdma_channel
*imxdmac
= (void *)data
;
633 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
634 struct imxdma_desc
*desc
;
636 spin_lock(&imxdmac
->lock
);
638 if (list_empty(&imxdmac
->ld_active
)) {
639 /* Someone might have called terminate all */
642 desc
= list_first_entry(&imxdmac
->ld_active
, struct imxdma_desc
, node
);
644 if (desc
->desc
.callback
)
645 desc
->desc
.callback(desc
->desc
.callback_param
);
647 dma_cookie_complete(&desc
->desc
);
649 /* If we are dealing with a cyclic descriptor keep it on ld_active */
650 if (imxdma_chan_is_doing_cyclic(imxdmac
))
653 list_move_tail(imxdmac
->ld_active
.next
, &imxdmac
->ld_free
);
655 if (!list_empty(&imxdmac
->ld_queue
)) {
656 desc
= list_first_entry(&imxdmac
->ld_queue
, struct imxdma_desc
,
658 list_move_tail(imxdmac
->ld_queue
.next
, &imxdmac
->ld_active
);
659 if (imxdma_xfer_desc(desc
) < 0)
660 dev_warn(imxdma
->dev
, "%s: channel: %d couldn't xfer desc\n",
661 __func__
, imxdmac
->channel
);
664 spin_unlock(&imxdmac
->lock
);
667 static int imxdma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
670 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
671 struct dma_slave_config
*dmaengine_cfg
= (void *)arg
;
674 unsigned int mode
= 0;
677 case DMA_TERMINATE_ALL
:
678 imxdma_disable_hw(imxdmac
);
680 spin_lock_irqsave(&imxdmac
->lock
, flags
);
681 list_splice_tail_init(&imxdmac
->ld_active
, &imxdmac
->ld_free
);
682 list_splice_tail_init(&imxdmac
->ld_queue
, &imxdmac
->ld_free
);
683 spin_unlock_irqrestore(&imxdmac
->lock
, flags
);
685 case DMA_SLAVE_CONFIG
:
686 if (dmaengine_cfg
->direction
== DMA_DEV_TO_MEM
) {
687 imxdmac
->per_address
= dmaengine_cfg
->src_addr
;
688 imxdmac
->watermark_level
= dmaengine_cfg
->src_maxburst
;
689 imxdmac
->word_size
= dmaengine_cfg
->src_addr_width
;
691 imxdmac
->per_address
= dmaengine_cfg
->dst_addr
;
692 imxdmac
->watermark_level
= dmaengine_cfg
->dst_maxburst
;
693 imxdmac
->word_size
= dmaengine_cfg
->dst_addr_width
;
696 switch (imxdmac
->word_size
) {
697 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
698 mode
= IMX_DMA_MEMSIZE_8
;
700 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
701 mode
= IMX_DMA_MEMSIZE_16
;
704 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
705 mode
= IMX_DMA_MEMSIZE_32
;
708 ret
= imxdma_config_channel_hw(imxdmac
,
709 mode
| IMX_DMA_TYPE_FIFO
,
710 IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
,
711 imxdmac
->dma_request
, 1);
715 /* Set burst length */
716 imx_dmav1_writel(imxdmac
->watermark_level
* imxdmac
->word_size
,
717 DMA_BLR(imxdmac
->channel
));
727 static enum dma_status
imxdma_tx_status(struct dma_chan
*chan
,
729 struct dma_tx_state
*txstate
)
731 return dma_cookie_status(chan
, cookie
, txstate
);
734 static dma_cookie_t
imxdma_tx_submit(struct dma_async_tx_descriptor
*tx
)
736 struct imxdma_channel
*imxdmac
= to_imxdma_chan(tx
->chan
);
740 spin_lock_irqsave(&imxdmac
->lock
, flags
);
741 cookie
= dma_cookie_assign(tx
);
742 spin_unlock_irqrestore(&imxdmac
->lock
, flags
);
747 static int imxdma_alloc_chan_resources(struct dma_chan
*chan
)
749 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
750 struct imx_dma_data
*data
= chan
->private;
753 imxdmac
->dma_request
= data
->dma_request
;
755 while (imxdmac
->descs_allocated
< IMXDMA_MAX_CHAN_DESCRIPTORS
) {
756 struct imxdma_desc
*desc
;
758 desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
761 __memzero(&desc
->desc
, sizeof(struct dma_async_tx_descriptor
));
762 dma_async_tx_descriptor_init(&desc
->desc
, chan
);
763 desc
->desc
.tx_submit
= imxdma_tx_submit
;
764 /* txd.flags will be overwritten in prep funcs */
765 desc
->desc
.flags
= DMA_CTRL_ACK
;
766 desc
->status
= DMA_SUCCESS
;
768 list_add_tail(&desc
->node
, &imxdmac
->ld_free
);
769 imxdmac
->descs_allocated
++;
772 if (!imxdmac
->descs_allocated
)
775 return imxdmac
->descs_allocated
;
778 static void imxdma_free_chan_resources(struct dma_chan
*chan
)
780 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
781 struct imxdma_desc
*desc
, *_desc
;
784 spin_lock_irqsave(&imxdmac
->lock
, flags
);
786 imxdma_disable_hw(imxdmac
);
787 list_splice_tail_init(&imxdmac
->ld_active
, &imxdmac
->ld_free
);
788 list_splice_tail_init(&imxdmac
->ld_queue
, &imxdmac
->ld_free
);
790 spin_unlock_irqrestore(&imxdmac
->lock
, flags
);
792 list_for_each_entry_safe(desc
, _desc
, &imxdmac
->ld_free
, node
) {
794 imxdmac
->descs_allocated
--;
796 INIT_LIST_HEAD(&imxdmac
->ld_free
);
798 if (imxdmac
->sg_list
) {
799 kfree(imxdmac
->sg_list
);
800 imxdmac
->sg_list
= NULL
;
804 static struct dma_async_tx_descriptor
*imxdma_prep_slave_sg(
805 struct dma_chan
*chan
, struct scatterlist
*sgl
,
806 unsigned int sg_len
, enum dma_transfer_direction direction
,
807 unsigned long flags
, void *context
)
809 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
810 struct scatterlist
*sg
;
811 int i
, dma_length
= 0;
812 struct imxdma_desc
*desc
;
814 if (list_empty(&imxdmac
->ld_free
) ||
815 imxdma_chan_is_doing_cyclic(imxdmac
))
818 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
820 for_each_sg(sgl
, sg
, sg_len
, i
) {
821 dma_length
+= sg
->length
;
824 switch (imxdmac
->word_size
) {
825 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
826 if (sgl
->length
& 3 || sgl
->dma_address
& 3)
829 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
830 if (sgl
->length
& 1 || sgl
->dma_address
& 1)
833 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
839 desc
->type
= IMXDMA_DESC_SLAVE_SG
;
841 desc
->sgcount
= sg_len
;
842 desc
->len
= dma_length
;
843 if (direction
== DMA_DEV_TO_MEM
) {
844 desc
->dmamode
= DMA_MODE_READ
;
845 desc
->src
= imxdmac
->per_address
;
847 desc
->dmamode
= DMA_MODE_WRITE
;
848 desc
->dest
= imxdmac
->per_address
;
850 desc
->desc
.callback
= NULL
;
851 desc
->desc
.callback_param
= NULL
;
856 static struct dma_async_tx_descriptor
*imxdma_prep_dma_cyclic(
857 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
858 size_t period_len
, enum dma_transfer_direction direction
,
861 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
862 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
863 struct imxdma_desc
*desc
;
865 unsigned int periods
= buf_len
/ period_len
;
867 dev_dbg(imxdma
->dev
, "%s channel: %d buf_len=%d period_len=%d\n",
868 __func__
, imxdmac
->channel
, buf_len
, period_len
);
870 if (list_empty(&imxdmac
->ld_free
) ||
871 imxdma_chan_is_doing_cyclic(imxdmac
))
874 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
876 if (imxdmac
->sg_list
)
877 kfree(imxdmac
->sg_list
);
879 imxdmac
->sg_list
= kcalloc(periods
+ 1,
880 sizeof(struct scatterlist
), GFP_KERNEL
);
881 if (!imxdmac
->sg_list
)
884 sg_init_table(imxdmac
->sg_list
, periods
);
886 for (i
= 0; i
< periods
; i
++) {
887 imxdmac
->sg_list
[i
].page_link
= 0;
888 imxdmac
->sg_list
[i
].offset
= 0;
889 imxdmac
->sg_list
[i
].dma_address
= dma_addr
;
890 imxdmac
->sg_list
[i
].length
= period_len
;
891 dma_addr
+= period_len
;
895 imxdmac
->sg_list
[periods
].offset
= 0;
896 imxdmac
->sg_list
[periods
].length
= 0;
897 imxdmac
->sg_list
[periods
].page_link
=
898 ((unsigned long)imxdmac
->sg_list
| 0x01) & ~0x02;
900 desc
->type
= IMXDMA_DESC_CYCLIC
;
901 desc
->sg
= imxdmac
->sg_list
;
902 desc
->sgcount
= periods
;
903 desc
->len
= IMX_DMA_LENGTH_LOOP
;
904 if (direction
== DMA_DEV_TO_MEM
) {
905 desc
->dmamode
= DMA_MODE_READ
;
906 desc
->src
= imxdmac
->per_address
;
908 desc
->dmamode
= DMA_MODE_WRITE
;
909 desc
->dest
= imxdmac
->per_address
;
911 desc
->desc
.callback
= NULL
;
912 desc
->desc
.callback_param
= NULL
;
917 static struct dma_async_tx_descriptor
*imxdma_prep_dma_memcpy(
918 struct dma_chan
*chan
, dma_addr_t dest
,
919 dma_addr_t src
, size_t len
, unsigned long flags
)
921 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
922 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
923 struct imxdma_desc
*desc
;
925 dev_dbg(imxdma
->dev
, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
926 __func__
, imxdmac
->channel
, src
, dest
, len
);
928 if (list_empty(&imxdmac
->ld_free
) ||
929 imxdma_chan_is_doing_cyclic(imxdmac
))
932 desc
= list_first_entry(&imxdmac
->ld_free
, struct imxdma_desc
, node
);
934 desc
->type
= IMXDMA_DESC_MEMCPY
;
938 desc
->dmamode
= DMA_MODE_WRITE
;
939 desc
->config_port
= IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
;
940 desc
->config_mem
= IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
;
941 desc
->desc
.callback
= NULL
;
942 desc
->desc
.callback_param
= NULL
;
947 static void imxdma_issue_pending(struct dma_chan
*chan
)
949 struct imxdma_channel
*imxdmac
= to_imxdma_chan(chan
);
950 struct imxdma_engine
*imxdma
= imxdmac
->imxdma
;
951 struct imxdma_desc
*desc
;
954 spin_lock_irqsave(&imxdmac
->lock
, flags
);
955 if (list_empty(&imxdmac
->ld_active
) &&
956 !list_empty(&imxdmac
->ld_queue
)) {
957 desc
= list_first_entry(&imxdmac
->ld_queue
,
958 struct imxdma_desc
, node
);
960 if (imxdma_xfer_desc(desc
) < 0) {
961 dev_warn(imxdma
->dev
,
962 "%s: channel: %d couldn't issue DMA xfer\n",
963 __func__
, imxdmac
->channel
);
965 list_move_tail(imxdmac
->ld_queue
.next
,
966 &imxdmac
->ld_active
);
969 spin_unlock_irqrestore(&imxdmac
->lock
, flags
);
972 static int __init
imxdma_probe(struct platform_device
*pdev
)
974 struct imxdma_engine
*imxdma
;
978 imx_dmav1_baseaddr
= MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR
);
979 else if (cpu_is_mx21())
980 imx_dmav1_baseaddr
= MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR
);
981 else if (cpu_is_mx27())
982 imx_dmav1_baseaddr
= MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR
);
986 dma_clk
= clk_get(NULL
, "dma");
988 return PTR_ERR(dma_clk
);
991 /* reset DMA module */
992 imx_dmav1_writel(DCR_DRST
, DMA_DCR
);
995 ret
= request_irq(MX1_DMA_INT
, dma_irq_handler
, 0, "DMA", imxdma
);
997 pr_crit("Can't register IRQ for DMA\n");
1001 ret
= request_irq(MX1_DMA_ERR
, imxdma_err_handler
, 0, "DMA", imxdma
);
1003 pr_crit("Can't register ERRIRQ for DMA\n");
1004 free_irq(MX1_DMA_INT
, NULL
);
1009 /* enable DMA module */
1010 imx_dmav1_writel(DCR_DEN
, DMA_DCR
);
1012 /* clear all interrupts */
1013 imx_dmav1_writel((1 << IMX_DMA_CHANNELS
) - 1, DMA_DISR
);
1015 /* disable interrupts */
1016 imx_dmav1_writel((1 << IMX_DMA_CHANNELS
) - 1, DMA_DIMR
);
1018 imxdma
= kzalloc(sizeof(*imxdma
), GFP_KERNEL
);
1022 INIT_LIST_HEAD(&imxdma
->dma_device
.channels
);
1024 dma_cap_set(DMA_SLAVE
, imxdma
->dma_device
.cap_mask
);
1025 dma_cap_set(DMA_CYCLIC
, imxdma
->dma_device
.cap_mask
);
1026 dma_cap_set(DMA_MEMCPY
, imxdma
->dma_device
.cap_mask
);
1028 /* Initialize channel parameters */
1029 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++) {
1030 struct imxdma_channel
*imxdmac
= &imxdma
->channel
[i
];
1031 memset(&imxdmac
->internal
, 0, sizeof(imxdmac
->internal
));
1032 if (cpu_is_mx21() || cpu_is_mx27()) {
1033 ret
= request_irq(MX2x_INT_DMACH0
+ i
,
1034 dma_irq_handler
, 0, "DMA", imxdma
);
1036 pr_crit("Can't register IRQ %d for DMA channel %d\n",
1037 MX2x_INT_DMACH0
+ i
, i
);
1040 init_timer(&imxdmac
->internal
.watchdog
);
1041 imxdmac
->internal
.watchdog
.function
= &imxdma_watchdog
;
1042 imxdmac
->internal
.watchdog
.data
= (unsigned long)imxdmac
;
1045 imxdmac
->imxdma
= imxdma
;
1046 spin_lock_init(&imxdmac
->lock
);
1048 INIT_LIST_HEAD(&imxdmac
->ld_queue
);
1049 INIT_LIST_HEAD(&imxdmac
->ld_free
);
1050 INIT_LIST_HEAD(&imxdmac
->ld_active
);
1052 tasklet_init(&imxdmac
->dma_tasklet
, imxdma_tasklet
,
1053 (unsigned long)imxdmac
);
1054 imxdmac
->chan
.device
= &imxdma
->dma_device
;
1055 dma_cookie_init(&imxdmac
->chan
);
1056 imxdmac
->channel
= i
;
1058 /* Add the channel to the DMAC list */
1059 list_add_tail(&imxdmac
->chan
.device_node
,
1060 &imxdma
->dma_device
.channels
);
1063 imxdma
->dev
= &pdev
->dev
;
1064 imxdma
->dma_device
.dev
= &pdev
->dev
;
1066 imxdma
->dma_device
.device_alloc_chan_resources
= imxdma_alloc_chan_resources
;
1067 imxdma
->dma_device
.device_free_chan_resources
= imxdma_free_chan_resources
;
1068 imxdma
->dma_device
.device_tx_status
= imxdma_tx_status
;
1069 imxdma
->dma_device
.device_prep_slave_sg
= imxdma_prep_slave_sg
;
1070 imxdma
->dma_device
.device_prep_dma_cyclic
= imxdma_prep_dma_cyclic
;
1071 imxdma
->dma_device
.device_prep_dma_memcpy
= imxdma_prep_dma_memcpy
;
1072 imxdma
->dma_device
.device_control
= imxdma_control
;
1073 imxdma
->dma_device
.device_issue_pending
= imxdma_issue_pending
;
1075 platform_set_drvdata(pdev
, imxdma
);
1077 imxdma
->dma_device
.copy_align
= 2; /* 2^2 = 4 bytes alignment */
1078 imxdma
->dma_device
.dev
->dma_parms
= &imxdma
->dma_parms
;
1079 dma_set_max_seg_size(imxdma
->dma_device
.dev
, 0xffffff);
1081 ret
= dma_async_device_register(&imxdma
->dma_device
);
1083 dev_err(&pdev
->dev
, "unable to register\n");
1091 if (cpu_is_mx21() || cpu_is_mx27()) {
1093 free_irq(MX2x_INT_DMACH0
+ i
, NULL
);
1094 } else if cpu_is_mx1() {
1095 free_irq(MX1_DMA_INT
, NULL
);
1096 free_irq(MX1_DMA_ERR
, NULL
);
1103 static int __exit
imxdma_remove(struct platform_device
*pdev
)
1105 struct imxdma_engine
*imxdma
= platform_get_drvdata(pdev
);
1108 dma_async_device_unregister(&imxdma
->dma_device
);
1110 if (cpu_is_mx21() || cpu_is_mx27()) {
1111 for (i
= 0; i
< IMX_DMA_CHANNELS
; i
++)
1112 free_irq(MX2x_INT_DMACH0
+ i
, NULL
);
1113 } else if cpu_is_mx1() {
1114 free_irq(MX1_DMA_INT
, NULL
);
1115 free_irq(MX1_DMA_ERR
, NULL
);
1123 static struct platform_driver imxdma_driver
= {
1127 .remove
= __exit_p(imxdma_remove
),
1130 static int __init
imxdma_module_init(void)
1132 return platform_driver_probe(&imxdma_driver
, imxdma_probe
);
1134 subsys_initcall(imxdma_module_init
);
1136 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1137 MODULE_DESCRIPTION("i.MX dma driver");
1138 MODULE_LICENSE("GPL");