b6442f09d0fe2639db62f305be26ef26f567e9c8
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / dmaengine.c
1 /*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21
22 /*
23 * This code implements the DMA subsystem. It provides a HW-neutral interface
24 * for other kernel code to use asynchronous memory copy capabilities,
25 * if present, and allows different HW DMA drivers to register as providing
26 * this capability.
27 *
28 * Due to the fact we are accelerating what is already a relatively fast
29 * operation, the code goes to great lengths to avoid additional overhead,
30 * such as locking.
31 *
32 * LOCKING:
33 *
34 * The subsystem keeps a global list of dma_device structs it is protected by a
35 * mutex, dma_list_mutex.
36 *
37 * A subsystem can get access to a channel by calling dmaengine_get() followed
38 * by dma_find_channel(), or if it has need for an exclusive channel it can call
39 * dma_request_channel(). Once a channel is allocated a reference is taken
40 * against its corresponding driver to disable removal.
41 *
42 * Each device has a channels list, which runs unlocked but is never modified
43 * once the device is registered, it's just setup by the driver.
44 *
45 * See Documentation/dmaengine.txt for more details
46 */
47
48 #include <linux/init.h>
49 #include <linux/module.h>
50 #include <linux/mm.h>
51 #include <linux/device.h>
52 #include <linux/dmaengine.h>
53 #include <linux/hardirq.h>
54 #include <linux/spinlock.h>
55 #include <linux/percpu.h>
56 #include <linux/rcupdate.h>
57 #include <linux/mutex.h>
58 #include <linux/jiffies.h>
59 #include <linux/rculist.h>
60 #include <linux/idr.h>
61
62 static DEFINE_MUTEX(dma_list_mutex);
63 static LIST_HEAD(dma_device_list);
64 static long dmaengine_ref_count;
65 static struct idr dma_idr;
66
67 /* --- sysfs implementation --- */
68
69 /**
70 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
71 * @dev - device node
72 *
73 * Must be called under dma_list_mutex
74 */
75 static struct dma_chan *dev_to_dma_chan(struct device *dev)
76 {
77 struct dma_chan_dev *chan_dev;
78
79 chan_dev = container_of(dev, typeof(*chan_dev), device);
80 return chan_dev->chan;
81 }
82
83 static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
84 {
85 struct dma_chan *chan;
86 unsigned long count = 0;
87 int i;
88 int err;
89
90 mutex_lock(&dma_list_mutex);
91 chan = dev_to_dma_chan(dev);
92 if (chan) {
93 for_each_possible_cpu(i)
94 count += per_cpu_ptr(chan->local, i)->memcpy_count;
95 err = sprintf(buf, "%lu\n", count);
96 } else
97 err = -ENODEV;
98 mutex_unlock(&dma_list_mutex);
99
100 return err;
101 }
102
103 static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
104 char *buf)
105 {
106 struct dma_chan *chan;
107 unsigned long count = 0;
108 int i;
109 int err;
110
111 mutex_lock(&dma_list_mutex);
112 chan = dev_to_dma_chan(dev);
113 if (chan) {
114 for_each_possible_cpu(i)
115 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
116 err = sprintf(buf, "%lu\n", count);
117 } else
118 err = -ENODEV;
119 mutex_unlock(&dma_list_mutex);
120
121 return err;
122 }
123
124 static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
125 {
126 struct dma_chan *chan;
127 int err;
128
129 mutex_lock(&dma_list_mutex);
130 chan = dev_to_dma_chan(dev);
131 if (chan)
132 err = sprintf(buf, "%d\n", chan->client_count);
133 else
134 err = -ENODEV;
135 mutex_unlock(&dma_list_mutex);
136
137 return err;
138 }
139
140 static struct device_attribute dma_attrs[] = {
141 __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
142 __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
143 __ATTR(in_use, S_IRUGO, show_in_use, NULL),
144 __ATTR_NULL
145 };
146
147 static void chan_dev_release(struct device *dev)
148 {
149 struct dma_chan_dev *chan_dev;
150
151 chan_dev = container_of(dev, typeof(*chan_dev), device);
152 if (atomic_dec_and_test(chan_dev->idr_ref)) {
153 mutex_lock(&dma_list_mutex);
154 idr_remove(&dma_idr, chan_dev->dev_id);
155 mutex_unlock(&dma_list_mutex);
156 kfree(chan_dev->idr_ref);
157 }
158 kfree(chan_dev);
159 }
160
161 static struct class dma_devclass = {
162 .name = "dma",
163 .dev_attrs = dma_attrs,
164 .dev_release = chan_dev_release,
165 };
166
167 /* --- client and device registration --- */
168
169 #define dma_device_satisfies_mask(device, mask) \
170 __dma_device_satisfies_mask((device), &(mask))
171 static int
172 __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
173 {
174 dma_cap_mask_t has;
175
176 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
177 DMA_TX_TYPE_END);
178 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
179 }
180
181 static struct module *dma_chan_to_owner(struct dma_chan *chan)
182 {
183 return chan->device->dev->driver->owner;
184 }
185
186 /**
187 * balance_ref_count - catch up the channel reference count
188 * @chan - channel to balance ->client_count versus dmaengine_ref_count
189 *
190 * balance_ref_count must be called under dma_list_mutex
191 */
192 static void balance_ref_count(struct dma_chan *chan)
193 {
194 struct module *owner = dma_chan_to_owner(chan);
195
196 while (chan->client_count < dmaengine_ref_count) {
197 __module_get(owner);
198 chan->client_count++;
199 }
200 }
201
202 /**
203 * dma_chan_get - try to grab a dma channel's parent driver module
204 * @chan - channel to grab
205 *
206 * Must be called under dma_list_mutex
207 */
208 static int dma_chan_get(struct dma_chan *chan)
209 {
210 int err = -ENODEV;
211 struct module *owner = dma_chan_to_owner(chan);
212
213 if (chan->client_count) {
214 __module_get(owner);
215 err = 0;
216 } else if (try_module_get(owner))
217 err = 0;
218
219 if (err == 0)
220 chan->client_count++;
221
222 /* allocate upon first client reference */
223 if (chan->client_count == 1 && err == 0) {
224 int desc_cnt = chan->device->device_alloc_chan_resources(chan);
225
226 if (desc_cnt < 0) {
227 err = desc_cnt;
228 chan->client_count = 0;
229 module_put(owner);
230 } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
231 balance_ref_count(chan);
232 }
233
234 return err;
235 }
236
237 /**
238 * dma_chan_put - drop a reference to a dma channel's parent driver module
239 * @chan - channel to release
240 *
241 * Must be called under dma_list_mutex
242 */
243 static void dma_chan_put(struct dma_chan *chan)
244 {
245 if (!chan->client_count)
246 return; /* this channel failed alloc_chan_resources */
247 chan->client_count--;
248 module_put(dma_chan_to_owner(chan));
249 if (chan->client_count == 0)
250 chan->device->device_free_chan_resources(chan);
251 }
252
253 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
254 {
255 enum dma_status status;
256 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
257
258 dma_async_issue_pending(chan);
259 do {
260 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
261 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
262 printk(KERN_ERR "dma_sync_wait_timeout!\n");
263 return DMA_ERROR;
264 }
265 } while (status == DMA_IN_PROGRESS);
266
267 return status;
268 }
269 EXPORT_SYMBOL(dma_sync_wait);
270
271 /**
272 * dma_cap_mask_all - enable iteration over all operation types
273 */
274 static dma_cap_mask_t dma_cap_mask_all;
275
276 /**
277 * dma_chan_tbl_ent - tracks channel allocations per core/operation
278 * @chan - associated channel for this entry
279 */
280 struct dma_chan_tbl_ent {
281 struct dma_chan *chan;
282 };
283
284 /**
285 * channel_table - percpu lookup table for memory-to-memory offload providers
286 */
287 static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END];
288
289 static int __init dma_channel_table_init(void)
290 {
291 enum dma_transaction_type cap;
292 int err = 0;
293
294 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
295
296 /* 'interrupt', 'private', and 'slave' are channel capabilities,
297 * but are not associated with an operation so they do not need
298 * an entry in the channel_table
299 */
300 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
301 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
302 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
303
304 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
305 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
306 if (!channel_table[cap]) {
307 err = -ENOMEM;
308 break;
309 }
310 }
311
312 if (err) {
313 pr_err("dmaengine: initialization failure\n");
314 for_each_dma_cap_mask(cap, dma_cap_mask_all)
315 if (channel_table[cap])
316 free_percpu(channel_table[cap]);
317 }
318
319 return err;
320 }
321 arch_initcall(dma_channel_table_init);
322
323 /**
324 * dma_find_channel - find a channel to carry out the operation
325 * @tx_type: transaction type
326 */
327 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
328 {
329 struct dma_chan *chan;
330 int cpu;
331
332 cpu = get_cpu();
333 chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan;
334 put_cpu();
335
336 return chan;
337 }
338 EXPORT_SYMBOL(dma_find_channel);
339
340 /**
341 * dma_issue_pending_all - flush all pending operations across all channels
342 */
343 void dma_issue_pending_all(void)
344 {
345 struct dma_device *device;
346 struct dma_chan *chan;
347
348 rcu_read_lock();
349 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
350 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
351 continue;
352 list_for_each_entry(chan, &device->channels, device_node)
353 if (chan->client_count)
354 device->device_issue_pending(chan);
355 }
356 rcu_read_unlock();
357 }
358 EXPORT_SYMBOL(dma_issue_pending_all);
359
360 /**
361 * nth_chan - returns the nth channel of the given capability
362 * @cap: capability to match
363 * @n: nth channel desired
364 *
365 * Defaults to returning the channel with the desired capability and the
366 * lowest reference count when 'n' cannot be satisfied. Must be called
367 * under dma_list_mutex.
368 */
369 static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
370 {
371 struct dma_device *device;
372 struct dma_chan *chan;
373 struct dma_chan *ret = NULL;
374 struct dma_chan *min = NULL;
375
376 list_for_each_entry(device, &dma_device_list, global_node) {
377 if (!dma_has_cap(cap, device->cap_mask) ||
378 dma_has_cap(DMA_PRIVATE, device->cap_mask))
379 continue;
380 list_for_each_entry(chan, &device->channels, device_node) {
381 if (!chan->client_count)
382 continue;
383 if (!min)
384 min = chan;
385 else if (chan->table_count < min->table_count)
386 min = chan;
387
388 if (n-- == 0) {
389 ret = chan;
390 break; /* done */
391 }
392 }
393 if (ret)
394 break; /* done */
395 }
396
397 if (!ret)
398 ret = min;
399
400 if (ret)
401 ret->table_count++;
402
403 return ret;
404 }
405
406 /**
407 * dma_channel_rebalance - redistribute the available channels
408 *
409 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
410 * operation type) in the SMP case, and operation isolation (avoid
411 * multi-tasking channels) in the non-SMP case. Must be called under
412 * dma_list_mutex.
413 */
414 static void dma_channel_rebalance(void)
415 {
416 struct dma_chan *chan;
417 struct dma_device *device;
418 int cpu;
419 int cap;
420 int n;
421
422 /* undo the last distribution */
423 for_each_dma_cap_mask(cap, dma_cap_mask_all)
424 for_each_possible_cpu(cpu)
425 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
426
427 list_for_each_entry(device, &dma_device_list, global_node) {
428 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
429 continue;
430 list_for_each_entry(chan, &device->channels, device_node)
431 chan->table_count = 0;
432 }
433
434 /* don't populate the channel_table if no clients are available */
435 if (!dmaengine_ref_count)
436 return;
437
438 /* redistribute available channels */
439 n = 0;
440 for_each_dma_cap_mask(cap, dma_cap_mask_all)
441 for_each_online_cpu(cpu) {
442 if (num_possible_cpus() > 1)
443 chan = nth_chan(cap, n++);
444 else
445 chan = nth_chan(cap, -1);
446
447 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
448 }
449 }
450
451 static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
452 dma_filter_fn fn, void *fn_param)
453 {
454 struct dma_chan *chan;
455
456 if (!__dma_device_satisfies_mask(dev, mask)) {
457 pr_debug("%s: wrong capabilities\n", __func__);
458 return NULL;
459 }
460 /* devices with multiple channels need special handling as we need to
461 * ensure that all channels are either private or public.
462 */
463 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
464 list_for_each_entry(chan, &dev->channels, device_node) {
465 /* some channels are already publicly allocated */
466 if (chan->client_count)
467 return NULL;
468 }
469
470 list_for_each_entry(chan, &dev->channels, device_node) {
471 if (chan->client_count) {
472 pr_debug("%s: %s busy\n",
473 __func__, dma_chan_name(chan));
474 continue;
475 }
476 if (fn && !fn(chan, fn_param)) {
477 pr_debug("%s: %s filter said false\n",
478 __func__, dma_chan_name(chan));
479 continue;
480 }
481 return chan;
482 }
483
484 return NULL;
485 }
486
487 /**
488 * dma_request_channel - try to allocate an exclusive channel
489 * @mask: capabilities that the channel must satisfy
490 * @fn: optional callback to disposition available channels
491 * @fn_param: opaque parameter to pass to dma_filter_fn
492 */
493 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
494 {
495 struct dma_device *device, *_d;
496 struct dma_chan *chan = NULL;
497 int err;
498
499 /* Find a channel */
500 mutex_lock(&dma_list_mutex);
501 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
502 chan = private_candidate(mask, device, fn, fn_param);
503 if (chan) {
504 /* Found a suitable channel, try to grab, prep, and
505 * return it. We first set DMA_PRIVATE to disable
506 * balance_ref_count as this channel will not be
507 * published in the general-purpose allocator
508 */
509 dma_cap_set(DMA_PRIVATE, device->cap_mask);
510 device->privatecnt++;
511 err = dma_chan_get(chan);
512
513 if (err == -ENODEV) {
514 pr_debug("%s: %s module removed\n", __func__,
515 dma_chan_name(chan));
516 list_del_rcu(&device->global_node);
517 } else if (err)
518 pr_err("dmaengine: failed to get %s: (%d)\n",
519 dma_chan_name(chan), err);
520 else
521 break;
522 if (--device->privatecnt == 0)
523 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
524 chan->private = NULL;
525 chan = NULL;
526 }
527 }
528 mutex_unlock(&dma_list_mutex);
529
530 pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
531 chan ? dma_chan_name(chan) : NULL);
532
533 return chan;
534 }
535 EXPORT_SYMBOL_GPL(__dma_request_channel);
536
537 void dma_release_channel(struct dma_chan *chan)
538 {
539 mutex_lock(&dma_list_mutex);
540 WARN_ONCE(chan->client_count != 1,
541 "chan reference count %d != 1\n", chan->client_count);
542 dma_chan_put(chan);
543 /* drop PRIVATE cap enabled by __dma_request_channel() */
544 if (--chan->device->privatecnt == 0)
545 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
546 chan->private = NULL;
547 mutex_unlock(&dma_list_mutex);
548 }
549 EXPORT_SYMBOL_GPL(dma_release_channel);
550
551 /**
552 * dmaengine_get - register interest in dma_channels
553 */
554 void dmaengine_get(void)
555 {
556 struct dma_device *device, *_d;
557 struct dma_chan *chan;
558 int err;
559
560 mutex_lock(&dma_list_mutex);
561 dmaengine_ref_count++;
562
563 /* try to grab channels */
564 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
565 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
566 continue;
567 list_for_each_entry(chan, &device->channels, device_node) {
568 err = dma_chan_get(chan);
569 if (err == -ENODEV) {
570 /* module removed before we could use it */
571 list_del_rcu(&device->global_node);
572 break;
573 } else if (err)
574 pr_err("dmaengine: failed to get %s: (%d)\n",
575 dma_chan_name(chan), err);
576 }
577 }
578
579 /* if this is the first reference and there were channels
580 * waiting we need to rebalance to get those channels
581 * incorporated into the channel table
582 */
583 if (dmaengine_ref_count == 1)
584 dma_channel_rebalance();
585 mutex_unlock(&dma_list_mutex);
586 }
587 EXPORT_SYMBOL(dmaengine_get);
588
589 /**
590 * dmaengine_put - let dma drivers be removed when ref_count == 0
591 */
592 void dmaengine_put(void)
593 {
594 struct dma_device *device;
595 struct dma_chan *chan;
596
597 mutex_lock(&dma_list_mutex);
598 dmaengine_ref_count--;
599 BUG_ON(dmaengine_ref_count < 0);
600 /* drop channel references */
601 list_for_each_entry(device, &dma_device_list, global_node) {
602 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
603 continue;
604 list_for_each_entry(chan, &device->channels, device_node)
605 dma_chan_put(chan);
606 }
607 mutex_unlock(&dma_list_mutex);
608 }
609 EXPORT_SYMBOL(dmaengine_put);
610
611 static bool device_has_all_tx_types(struct dma_device *device)
612 {
613 /* A device that satisfies this test has channels that will never cause
614 * an async_tx channel switch event as all possible operation types can
615 * be handled.
616 */
617 #ifdef CONFIG_ASYNC_TX_DMA
618 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
619 return false;
620 #endif
621
622 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
623 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
624 return false;
625 #endif
626
627 #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
628 if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
629 return false;
630 #endif
631
632 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
633 if (!dma_has_cap(DMA_XOR, device->cap_mask))
634 return false;
635 if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
636 return false;
637 #endif
638
639 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
640 if (!dma_has_cap(DMA_PQ, device->cap_mask))
641 return false;
642 if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
643 return false;
644 #endif
645
646 return true;
647 }
648
649 static int get_dma_id(struct dma_device *device)
650 {
651 int rc;
652
653 idr_retry:
654 if (!idr_pre_get(&dma_idr, GFP_KERNEL))
655 return -ENOMEM;
656 mutex_lock(&dma_list_mutex);
657 rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
658 mutex_unlock(&dma_list_mutex);
659 if (rc == -EAGAIN)
660 goto idr_retry;
661 else if (rc != 0)
662 return rc;
663
664 return 0;
665 }
666
667 /**
668 * dma_async_device_register - registers DMA devices found
669 * @device: &dma_device
670 */
671 int dma_async_device_register(struct dma_device *device)
672 {
673 int chancnt = 0, rc;
674 struct dma_chan* chan;
675 atomic_t *idr_ref;
676
677 if (!device)
678 return -ENODEV;
679
680 /* validate device routines */
681 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
682 !device->device_prep_dma_memcpy);
683 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
684 !device->device_prep_dma_xor);
685 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
686 !device->device_prep_dma_xor_val);
687 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
688 !device->device_prep_dma_pq);
689 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
690 !device->device_prep_dma_pq_val);
691 BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
692 !device->device_prep_dma_memset);
693 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
694 !device->device_prep_dma_interrupt);
695 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
696 !device->device_prep_slave_sg);
697 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
698 !device->device_terminate_all);
699
700 BUG_ON(!device->device_alloc_chan_resources);
701 BUG_ON(!device->device_free_chan_resources);
702 BUG_ON(!device->device_is_tx_complete);
703 BUG_ON(!device->device_issue_pending);
704 BUG_ON(!device->dev);
705
706 /* note: this only matters in the
707 * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case
708 */
709 if (device_has_all_tx_types(device))
710 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
711
712 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
713 if (!idr_ref)
714 return -ENOMEM;
715 rc = get_dma_id(device);
716 if (rc != 0) {
717 kfree(idr_ref);
718 return rc;
719 }
720
721 atomic_set(idr_ref, 0);
722
723 /* represent channels in sysfs. Probably want devs too */
724 list_for_each_entry(chan, &device->channels, device_node) {
725 rc = -ENOMEM;
726 chan->local = alloc_percpu(typeof(*chan->local));
727 if (chan->local == NULL)
728 goto err_out;
729 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
730 if (chan->dev == NULL) {
731 free_percpu(chan->local);
732 chan->local = NULL;
733 goto err_out;
734 }
735
736 chan->chan_id = chancnt++;
737 chan->dev->device.class = &dma_devclass;
738 chan->dev->device.parent = device->dev;
739 chan->dev->chan = chan;
740 chan->dev->idr_ref = idr_ref;
741 chan->dev->dev_id = device->dev_id;
742 atomic_inc(idr_ref);
743 dev_set_name(&chan->dev->device, "dma%dchan%d",
744 device->dev_id, chan->chan_id);
745
746 rc = device_register(&chan->dev->device);
747 if (rc) {
748 free_percpu(chan->local);
749 chan->local = NULL;
750 kfree(chan->dev);
751 atomic_dec(idr_ref);
752 goto err_out;
753 }
754 chan->client_count = 0;
755 }
756 device->chancnt = chancnt;
757
758 mutex_lock(&dma_list_mutex);
759 /* take references on public channels */
760 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
761 list_for_each_entry(chan, &device->channels, device_node) {
762 /* if clients are already waiting for channels we need
763 * to take references on their behalf
764 */
765 if (dma_chan_get(chan) == -ENODEV) {
766 /* note we can only get here for the first
767 * channel as the remaining channels are
768 * guaranteed to get a reference
769 */
770 rc = -ENODEV;
771 mutex_unlock(&dma_list_mutex);
772 goto err_out;
773 }
774 }
775 list_add_tail_rcu(&device->global_node, &dma_device_list);
776 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
777 device->privatecnt++; /* Always private */
778 dma_channel_rebalance();
779 mutex_unlock(&dma_list_mutex);
780
781 return 0;
782
783 err_out:
784 /* if we never registered a channel just release the idr */
785 if (atomic_read(idr_ref) == 0) {
786 mutex_lock(&dma_list_mutex);
787 idr_remove(&dma_idr, device->dev_id);
788 mutex_unlock(&dma_list_mutex);
789 kfree(idr_ref);
790 return rc;
791 }
792
793 list_for_each_entry(chan, &device->channels, device_node) {
794 if (chan->local == NULL)
795 continue;
796 mutex_lock(&dma_list_mutex);
797 chan->dev->chan = NULL;
798 mutex_unlock(&dma_list_mutex);
799 device_unregister(&chan->dev->device);
800 free_percpu(chan->local);
801 }
802 return rc;
803 }
804 EXPORT_SYMBOL(dma_async_device_register);
805
806 /**
807 * dma_async_device_unregister - unregister a DMA device
808 * @device: &dma_device
809 *
810 * This routine is called by dma driver exit routines, dmaengine holds module
811 * references to prevent it being called while channels are in use.
812 */
813 void dma_async_device_unregister(struct dma_device *device)
814 {
815 struct dma_chan *chan;
816
817 mutex_lock(&dma_list_mutex);
818 list_del_rcu(&device->global_node);
819 dma_channel_rebalance();
820 mutex_unlock(&dma_list_mutex);
821
822 list_for_each_entry(chan, &device->channels, device_node) {
823 WARN_ONCE(chan->client_count,
824 "%s called while %d clients hold a reference\n",
825 __func__, chan->client_count);
826 mutex_lock(&dma_list_mutex);
827 chan->dev->chan = NULL;
828 mutex_unlock(&dma_list_mutex);
829 device_unregister(&chan->dev->device);
830 }
831 }
832 EXPORT_SYMBOL(dma_async_device_unregister);
833
834 /**
835 * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
836 * @chan: DMA channel to offload copy to
837 * @dest: destination address (virtual)
838 * @src: source address (virtual)
839 * @len: length
840 *
841 * Both @dest and @src must be mappable to a bus address according to the
842 * DMA mapping API rules for streaming mappings.
843 * Both @dest and @src must stay memory resident (kernel memory or locked
844 * user space pages).
845 */
846 dma_cookie_t
847 dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
848 void *src, size_t len)
849 {
850 struct dma_device *dev = chan->device;
851 struct dma_async_tx_descriptor *tx;
852 dma_addr_t dma_dest, dma_src;
853 dma_cookie_t cookie;
854 int cpu;
855 unsigned long flags;
856
857 dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
858 dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
859 flags = DMA_CTRL_ACK |
860 DMA_COMPL_SRC_UNMAP_SINGLE |
861 DMA_COMPL_DEST_UNMAP_SINGLE;
862 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
863
864 if (!tx) {
865 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
866 dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
867 return -ENOMEM;
868 }
869
870 tx->callback = NULL;
871 cookie = tx->tx_submit(tx);
872
873 cpu = get_cpu();
874 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
875 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
876 put_cpu();
877
878 return cookie;
879 }
880 EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
881
882 /**
883 * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
884 * @chan: DMA channel to offload copy to
885 * @page: destination page
886 * @offset: offset in page to copy to
887 * @kdata: source address (virtual)
888 * @len: length
889 *
890 * Both @page/@offset and @kdata must be mappable to a bus address according
891 * to the DMA mapping API rules for streaming mappings.
892 * Both @page/@offset and @kdata must stay memory resident (kernel memory or
893 * locked user space pages)
894 */
895 dma_cookie_t
896 dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
897 unsigned int offset, void *kdata, size_t len)
898 {
899 struct dma_device *dev = chan->device;
900 struct dma_async_tx_descriptor *tx;
901 dma_addr_t dma_dest, dma_src;
902 dma_cookie_t cookie;
903 int cpu;
904 unsigned long flags;
905
906 dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
907 dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
908 flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
909 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
910
911 if (!tx) {
912 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
913 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
914 return -ENOMEM;
915 }
916
917 tx->callback = NULL;
918 cookie = tx->tx_submit(tx);
919
920 cpu = get_cpu();
921 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
922 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
923 put_cpu();
924
925 return cookie;
926 }
927 EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
928
929 /**
930 * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
931 * @chan: DMA channel to offload copy to
932 * @dest_pg: destination page
933 * @dest_off: offset in page to copy to
934 * @src_pg: source page
935 * @src_off: offset in page to copy from
936 * @len: length
937 *
938 * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
939 * address according to the DMA mapping API rules for streaming mappings.
940 * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
941 * (kernel memory or locked user space pages).
942 */
943 dma_cookie_t
944 dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
945 unsigned int dest_off, struct page *src_pg, unsigned int src_off,
946 size_t len)
947 {
948 struct dma_device *dev = chan->device;
949 struct dma_async_tx_descriptor *tx;
950 dma_addr_t dma_dest, dma_src;
951 dma_cookie_t cookie;
952 int cpu;
953 unsigned long flags;
954
955 dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
956 dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
957 DMA_FROM_DEVICE);
958 flags = DMA_CTRL_ACK;
959 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
960
961 if (!tx) {
962 dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
963 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
964 return -ENOMEM;
965 }
966
967 tx->callback = NULL;
968 cookie = tx->tx_submit(tx);
969
970 cpu = get_cpu();
971 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
972 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
973 put_cpu();
974
975 return cookie;
976 }
977 EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
978
979 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
980 struct dma_chan *chan)
981 {
982 tx->chan = chan;
983 spin_lock_init(&tx->lock);
984 }
985 EXPORT_SYMBOL(dma_async_tx_descriptor_init);
986
987 /* dma_wait_for_async_tx - spin wait for a transaction to complete
988 * @tx: in-flight transaction to wait on
989 */
990 enum dma_status
991 dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
992 {
993 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
994
995 if (!tx)
996 return DMA_SUCCESS;
997
998 while (tx->cookie == -EBUSY) {
999 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
1000 pr_err("%s timeout waiting for descriptor submission\n",
1001 __func__);
1002 return DMA_ERROR;
1003 }
1004 cpu_relax();
1005 }
1006 return dma_sync_wait(tx->chan, tx->cookie);
1007 }
1008 EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1009
1010 /* dma_run_dependencies - helper routine for dma drivers to process
1011 * (start) dependent operations on their target channel
1012 * @tx: transaction with dependencies
1013 */
1014 void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1015 {
1016 struct dma_async_tx_descriptor *dep = tx->next;
1017 struct dma_async_tx_descriptor *dep_next;
1018 struct dma_chan *chan;
1019
1020 if (!dep)
1021 return;
1022
1023 /* we'll submit tx->next now, so clear the link */
1024 tx->next = NULL;
1025 chan = dep->chan;
1026
1027 /* keep submitting up until a channel switch is detected
1028 * in that case we will be called again as a result of
1029 * processing the interrupt from async_tx_channel_switch
1030 */
1031 for (; dep; dep = dep_next) {
1032 spin_lock_bh(&dep->lock);
1033 dep->parent = NULL;
1034 dep_next = dep->next;
1035 if (dep_next && dep_next->chan == chan)
1036 dep->next = NULL; /* ->next will be submitted */
1037 else
1038 dep_next = NULL; /* submit current dep and terminate */
1039 spin_unlock_bh(&dep->lock);
1040
1041 dep->tx_submit(dep);
1042 }
1043
1044 chan->device->device_issue_pending(chan);
1045 }
1046 EXPORT_SYMBOL_GPL(dma_run_dependencies);
1047
1048 static int __init dma_bus_init(void)
1049 {
1050 idr_init(&dma_idr);
1051 mutex_init(&dma_list_mutex);
1052 return class_register(&dma_devclass);
1053 }
1054 arch_initcall(dma_bus_init);
1055
1056