2 # DMA engine configuration
6 bool "DMA Engine support"
9 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
12 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
16 config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
23 config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
36 config ASYNC_TX_DISABLE_CHANNEL_SWITCH
40 tristate "Intel I/OAT DMA support"
44 select ASYNC_TX_DISABLE_CHANNEL_SWITCH
45 select ASYNC_TX_DISABLE_PQ_VAL_DMA
46 select ASYNC_TX_DISABLE_XOR_VAL_DMA
48 Enable support for the Intel(R) I/OAT DMA engine present
49 in recent Intel Xeon chipsets.
51 Say Y here if you have such a chipset.
56 tristate "Intel IOP ADMA support"
57 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
60 Enable support for the Intel(R) IOP Series RAID engines.
63 tristate "Synopsys DesignWare AHB DMA support"
66 default y if CPU_AT32AP7000
68 Support the Synopsys DesignWare AHB DMA controller. This
69 can be integrated in chips such as the Atmel AT32ap7000.
72 tristate "Atmel AHB DMA support"
73 depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
76 Support the Atmel AHB DMA controller. This can be integrated in
77 chips such as the Atmel AT91SAM9RL.
80 tristate "Freescale Elo and Elo Plus DMA support"
84 Enable support for the Freescale Elo and Elo Plus DMA controllers.
85 The Elo is the DMA controller on some 82xx and 83xx parts, and the
86 Elo Plus is the DMA controller on 85xx and 86xx parts.
89 bool "Marvell XOR engine support"
93 Enable support for the Marvell XOR engine.
96 bool "MX3x Image Processing Unit support"
101 If you plan to use the Image Processing unit in the i.MX3x, say
102 Y here. If unsure, select Y.
105 int "Number of dynamically mapped interrupts for IPU"
110 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
111 To avoid bloating the irq_desc[] array we allocate a sufficient
112 number of IRQ slots and map them dynamically to specific sources.
115 tristate "Toshiba TXx9 SoC DMA support"
116 depends on MACH_TX49XX || MACH_TX39XX
119 Support the TXx9 SoC internal DMA controller. This can be
120 integrated in chips such as the Toshiba TX4927/38/39.
123 tristate "Renesas SuperH DMAC support"
124 depends on SUPERH && SH_DMA
125 depends on !SH_DMA_API
128 Enable support for the Renesas SuperH DMA controllers.
131 bool "ST-Ericsson COH901318 DMA support"
135 Enable support for ST-Ericsson COH 901 318 DMA.
137 config AMCC_PPC440SPE_ADMA
138 tristate "AMCC PPC440SPe ADMA support"
139 depends on 440SPe || 440SP
141 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
143 Enable support for the AMCC PPC440SPe RAID engines.
145 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
151 comment "DMA Clients"
152 depends on DMA_ENGINE
155 bool "Network: TCP receive copy offload"
156 depends on DMA_ENGINE && NET
157 default (INTEL_IOATDMA || FSL_DMA)
159 This enables the use of DMA engines in the network stack to
160 offload receive copy-to-user operations, freeing CPU cycles.
162 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
166 bool "Async_tx: Offload support for the async_tx api"
167 depends on DMA_ENGINE
169 This allows the async_tx api to take advantage of offload engines for
170 memcpy, memset, xor, and raid6 p+q operations. If your platform has
171 a dma engine that can perform raid operations and you have enabled
177 tristate "DMA Test client"
178 depends on DMA_ENGINE
180 Simple DMA test client. Say N unless you're debugging a