Merge tag 'for-linus-v3.10-rc3' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / nx / nx-sha512.c
1 /**
2 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
3 *
4 * Copyright (C) 2011-2012 International Business Machines Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 only.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Author: Kent Yoder <yoder1@us.ibm.com>
20 */
21
22 #include <crypto/internal/hash.h>
23 #include <crypto/sha.h>
24 #include <linux/module.h>
25 #include <asm/vio.h>
26
27 #include "nx_csbcpb.h"
28 #include "nx.h"
29
30
31 static int nx_sha512_init(struct shash_desc *desc)
32 {
33 struct sha512_state *sctx = shash_desc_ctx(desc);
34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
35 struct nx_sg *out_sg;
36
37 nx_ctx_init(nx_ctx, HCOP_FC_SHA);
38
39 memset(sctx, 0, sizeof *sctx);
40
41 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
42
43 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
44 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
45 SHA512_DIGEST_SIZE, nx_ctx->ap->sglen);
46 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
47
48 return 0;
49 }
50
51 static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
52 unsigned int len)
53 {
54 struct sha512_state *sctx = shash_desc_ctx(desc);
55 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
56 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
57 struct nx_sg *in_sg;
58 u64 to_process, leftover, spbc_bits;
59 int rc = 0;
60
61 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
62 /* we've hit the nx chip previously and we're updating again,
63 * so copy over the partial digest */
64 memcpy(csbcpb->cpb.sha512.input_partial_digest,
65 csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
66 }
67
68 /* 2 cases for total data len:
69 * 1: <= SHA512_BLOCK_SIZE: copy into state, return 0
70 * 2: > SHA512_BLOCK_SIZE: process X blocks, copy in leftover
71 */
72 if ((u64)len + sctx->count[0] < SHA512_BLOCK_SIZE) {
73 memcpy(sctx->buf + sctx->count[0], data, len);
74 sctx->count[0] += len;
75 goto out;
76 }
77
78 /* to_process: the SHA512_BLOCK_SIZE data chunk to process in this
79 * update */
80 to_process = (sctx->count[0] + len) & ~(SHA512_BLOCK_SIZE - 1);
81 leftover = (sctx->count[0] + len) & (SHA512_BLOCK_SIZE - 1);
82
83 if (sctx->count[0]) {
84 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)sctx->buf,
85 sctx->count[0], nx_ctx->ap->sglen);
86 in_sg = nx_build_sg_list(in_sg, (u8 *)data,
87 to_process - sctx->count[0],
88 nx_ctx->ap->sglen);
89 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
90 sizeof(struct nx_sg);
91 } else {
92 in_sg = nx_build_sg_list(nx_ctx->in_sg, (u8 *)data,
93 to_process, nx_ctx->ap->sglen);
94 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
95 sizeof(struct nx_sg);
96 }
97
98 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
99
100 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
101 rc = -EINVAL;
102 goto out;
103 }
104
105 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
106 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
107 if (rc)
108 goto out;
109
110 atomic_inc(&(nx_ctx->stats->sha512_ops));
111
112 /* copy the leftover back into the state struct */
113 if (leftover)
114 memcpy(sctx->buf, data + len - leftover, leftover);
115 sctx->count[0] = leftover;
116
117 spbc_bits = csbcpb->cpb.sha512.spbc * 8;
118 csbcpb->cpb.sha512.message_bit_length_lo += spbc_bits;
119 if (csbcpb->cpb.sha512.message_bit_length_lo < spbc_bits)
120 csbcpb->cpb.sha512.message_bit_length_hi++;
121
122 /* everything after the first update is continuation */
123 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
124 out:
125 return rc;
126 }
127
128 static int nx_sha512_final(struct shash_desc *desc, u8 *out)
129 {
130 struct sha512_state *sctx = shash_desc_ctx(desc);
131 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
132 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
133 struct nx_sg *in_sg, *out_sg;
134 u64 count0;
135 int rc;
136
137 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
138 /* we've hit the nx chip previously, now we're finalizing,
139 * so copy over the partial digest */
140 memcpy(csbcpb->cpb.sha512.input_partial_digest,
141 csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
142 }
143
144 /* final is represented by continuing the operation and indicating that
145 * this is not an intermediate operation */
146 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
147
148 count0 = sctx->count[0] * 8;
149
150 csbcpb->cpb.sha512.message_bit_length_lo += count0;
151 if (csbcpb->cpb.sha512.message_bit_length_lo < count0)
152 csbcpb->cpb.sha512.message_bit_length_hi++;
153
154 in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, sctx->count[0],
155 nx_ctx->ap->sglen);
156 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, SHA512_DIGEST_SIZE,
157 nx_ctx->ap->sglen);
158 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
159 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
160
161 if (!nx_ctx->op.outlen) {
162 rc = -EINVAL;
163 goto out;
164 }
165
166 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
167 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
168 if (rc)
169 goto out;
170
171 atomic_inc(&(nx_ctx->stats->sha512_ops));
172 atomic64_add(csbcpb->cpb.sha512.message_bit_length_lo / 8,
173 &(nx_ctx->stats->sha512_bytes));
174
175 memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
176 out:
177 return rc;
178 }
179
180 static int nx_sha512_export(struct shash_desc *desc, void *out)
181 {
182 struct sha512_state *sctx = shash_desc_ctx(desc);
183 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
184 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
185 struct sha512_state *octx = out;
186
187 /* move message_bit_length (128 bits) into count and convert its value
188 * to bytes */
189 octx->count[0] = csbcpb->cpb.sha512.message_bit_length_lo >> 3 |
190 ((csbcpb->cpb.sha512.message_bit_length_hi & 7) << 61);
191 octx->count[1] = csbcpb->cpb.sha512.message_bit_length_hi >> 3;
192
193 octx->count[0] += sctx->count[0];
194 if (octx->count[0] < sctx->count[0])
195 octx->count[1]++;
196
197 memcpy(octx->buf, sctx->buf, sizeof(octx->buf));
198
199 /* if no data has been processed yet, we need to export SHA512's
200 * initial data, in case this context gets imported into a software
201 * context */
202 if (csbcpb->cpb.sha512.message_bit_length_hi ||
203 csbcpb->cpb.sha512.message_bit_length_lo)
204 memcpy(octx->state, csbcpb->cpb.sha512.message_digest,
205 SHA512_DIGEST_SIZE);
206 else {
207 octx->state[0] = SHA512_H0;
208 octx->state[1] = SHA512_H1;
209 octx->state[2] = SHA512_H2;
210 octx->state[3] = SHA512_H3;
211 octx->state[4] = SHA512_H4;
212 octx->state[5] = SHA512_H5;
213 octx->state[6] = SHA512_H6;
214 octx->state[7] = SHA512_H7;
215 }
216
217 return 0;
218 }
219
220 static int nx_sha512_import(struct shash_desc *desc, const void *in)
221 {
222 struct sha512_state *sctx = shash_desc_ctx(desc);
223 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
224 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
225 const struct sha512_state *ictx = in;
226
227 memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf));
228 sctx->count[0] = ictx->count[0] & 0x3f;
229 csbcpb->cpb.sha512.message_bit_length_lo = (ictx->count[0] & ~0x3f)
230 << 3;
231 csbcpb->cpb.sha512.message_bit_length_hi = ictx->count[1] << 3 |
232 ictx->count[0] >> 61;
233
234 if (csbcpb->cpb.sha512.message_bit_length_hi ||
235 csbcpb->cpb.sha512.message_bit_length_lo) {
236 memcpy(csbcpb->cpb.sha512.message_digest, ictx->state,
237 SHA512_DIGEST_SIZE);
238
239 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
240 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
241 }
242
243 return 0;
244 }
245
246 struct shash_alg nx_shash_sha512_alg = {
247 .digestsize = SHA512_DIGEST_SIZE,
248 .init = nx_sha512_init,
249 .update = nx_sha512_update,
250 .final = nx_sha512_final,
251 .export = nx_sha512_export,
252 .import = nx_sha512_import,
253 .descsize = sizeof(struct sha512_state),
254 .statesize = sizeof(struct sha512_state),
255 .base = {
256 .cra_name = "sha512",
257 .cra_driver_name = "sha512-nx",
258 .cra_priority = 300,
259 .cra_flags = CRYPTO_ALG_TYPE_SHASH,
260 .cra_blocksize = SHA512_BLOCK_SIZE,
261 .cra_module = THIS_MODULE,
262 .cra_ctxsize = sizeof(struct nx_crypto_ctx),
263 .cra_init = nx_crypto_ctx_sha_init,
264 .cra_exit = nx_crypto_ctx_exit,
265 }
266 };