3 bool "Hardware crypto devices"
6 Say Y here to get to see options for hardware crypto devices and
7 processors. This option alone does not add any kernel code.
9 If you say N, all options in this submenu will be skipped and disabled.
13 config CRYPTO_DEV_PADLOCK
14 tristate "Support for VIA PadLock ACE"
15 depends on X86 && !UML
17 Some VIA processors come with an integrated crypto engine
18 (so called VIA PadLock ACE, Advanced Cryptography Engine)
19 that provides instructions for very fast cryptographic
20 operations with supported algorithms.
22 The instructions are used only when the CPU supports them.
23 Otherwise software encryption is used.
25 config CRYPTO_DEV_PADLOCK_AES
26 tristate "PadLock driver for AES algorithm"
27 depends on CRYPTO_DEV_PADLOCK
28 select CRYPTO_BLKCIPHER
31 Use VIA PadLock for AES algorithm.
33 Available in VIA C3 and newer CPUs.
35 If unsure say M. The compiled module will be
38 config CRYPTO_DEV_PADLOCK_SHA
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"
40 depends on CRYPTO_DEV_PADLOCK
45 Use VIA PadLock for SHA1/SHA256 algorithms.
47 Available in VIA C7 and newer processors.
49 If unsure say M. The compiled module will be
52 config CRYPTO_DEV_GEODE
53 tristate "Support for the Geode LX AES engine"
54 depends on X86_32 && PCI
56 select CRYPTO_BLKCIPHER
58 Say 'Y' here to use the AMD Geode LX processor on-board AES
59 engine for the CryptoAPI AES algorithm.
61 To compile this driver as a module, choose M here: the module
62 will be called geode-aes.
65 tristate "Support for PCI-attached cryptographic adapters"
69 Select this option if you want to use a PCI-attached cryptographic
71 + PCI Cryptographic Accelerator (PCICA)
72 + PCI Cryptographic Coprocessor (PCICC)
73 + PCI-X Cryptographic Coprocessor (PCIXCC)
74 + Crypto Express2 Coprocessor (CEX2C)
75 + Crypto Express2 Accelerator (CEX2A)
76 + Crypto Express3 Coprocessor (CEX3C)
77 + Crypto Express3 Accelerator (CEX3A)
79 config CRYPTO_SHA1_S390
80 tristate "SHA1 digest algorithm"
84 This is the s390 hardware accelerated implementation of the
85 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
87 It is available as of z990.
89 config CRYPTO_SHA256_S390
90 tristate "SHA256 digest algorithm"
94 This is the s390 hardware accelerated implementation of the
95 SHA256 secure hash standard (DFIPS 180-2).
97 It is available as of z9.
99 config CRYPTO_SHA512_S390
100 tristate "SHA384 and SHA512 digest algorithm"
104 This is the s390 hardware accelerated implementation of the
105 SHA512 secure hash standard.
107 It is available as of z10.
109 config CRYPTO_DES_S390
110 tristate "DES and Triple DES cipher algorithms"
113 select CRYPTO_BLKCIPHER
115 This is the s390 hardware accelerated implementation of the
116 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
118 As of z990 the ECB and CBC mode are hardware accelerated.
119 As of z196 the CTR mode is hardware accelerated.
121 config CRYPTO_AES_S390
122 tristate "AES cipher algorithms"
125 select CRYPTO_BLKCIPHER
127 This is the s390 hardware accelerated implementation of the
128 AES cipher algorithms (FIPS-197).
130 As of z9 the ECB and CBC modes are hardware accelerated
132 As of z10 the ECB and CBC modes are hardware accelerated
133 for all AES key sizes.
134 As of z196 the CTR mode is hardware accelerated for all AES
135 key sizes and XTS mode is hardware accelerated for 256 and
139 tristate "Pseudo random number generator device driver"
143 Select this option if you want to use the s390 pseudo random number
144 generator. The PRNG is part of the cryptographic processor functions
145 and uses triple-DES to generate secure random numbers like the
146 ANSI X9.17 standard. User-space programs access the
147 pseudo-random-number device through the char device /dev/prandom.
149 It is available as of z9.
151 config CRYPTO_GHASH_S390
152 tristate "GHASH digest algorithm"
156 This is the s390 hardware accelerated implementation of the
157 GHASH message digest algorithm for GCM (Galois/Counter Mode).
159 It is available as of z196.
161 config CRYPTO_DEV_MV_CESA
162 tristate "Marvell's Cryptographic Engine"
163 depends on PLAT_ORION
166 select CRYPTO_BLKCIPHER2
168 This driver allows you to utilize the Cryptographic Engines and
169 Security Accelerator (CESA) which can be found on the Marvell Orion
170 and Kirkwood SoCs, such as QNAP's TS-209.
172 Currently the driver supports AES in ECB and CBC mode without DMA.
174 config CRYPTO_DEV_NIAGARA2
175 tristate "Niagara2 Stream Processing Unit driver"
180 Each core of a Niagara2 processor contains a Stream
181 Processing Unit, which itself contains several cryptographic
182 sub-units. One set provides the Modular Arithmetic Unit,
183 used for SSL offload. The other set provides the Cipher
184 Group, which can perform encryption, decryption, hashing,
185 checksumming, and raw copies.
187 config CRYPTO_DEV_HIFN_795X
188 tristate "Driver HIFN 795x crypto accelerator chips"
191 select CRYPTO_BLKCIPHER
192 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
194 depends on !ARCH_DMA_ADDR_T_64BIT
196 This option allows you to have support for HIFN 795x crypto adapters.
198 config CRYPTO_DEV_HIFN_795X_RNG
199 bool "HIFN 795x random number generator"
200 depends on CRYPTO_DEV_HIFN_795X
202 Select this option if you want to enable the random number generator
203 on the HIFN 795x crypto adapters.
205 source drivers/crypto/caam/Kconfig
207 config CRYPTO_DEV_TALITOS
208 tristate "Talitos Freescale Security Engine (SEC)"
210 select CRYPTO_AUTHENC
214 Say 'Y' here to use the Freescale Security Engine (SEC)
215 to offload cryptographic algorithm computation.
217 The Freescale SEC is present on PowerQUICC 'E' processors, such
218 as the MPC8349E and MPC8548E.
220 To compile this driver as a module, choose M here: the module
221 will be called talitos.
223 config CRYPTO_DEV_IXP4XX
224 tristate "Driver for IXP4xx crypto hardware acceleration"
225 depends on ARCH_IXP4XX
228 select CRYPTO_AUTHENC
229 select CRYPTO_BLKCIPHER
231 Driver for the IXP4xx NPE crypto engine.
233 config CRYPTO_DEV_PPC4XX
234 tristate "Driver AMCC PPC4xx crypto accelerator"
235 depends on PPC && 4xx
238 select CRYPTO_BLKCIPHER
240 This option allows you to have support for AMCC crypto acceleration.
242 config CRYPTO_DEV_OMAP_SHAM
243 tristate "Support for OMAP SHA1/MD5 hw accelerator"
244 depends on ARCH_OMAP2 || ARCH_OMAP3
248 OMAP processors have SHA1/MD5 hw accelerator. Select this if you
249 want to use the OMAP module for SHA1/MD5 algorithms.
251 config CRYPTO_DEV_OMAP_AES
252 tristate "Support for OMAP AES hw engine"
253 depends on ARCH_OMAP2 || ARCH_OMAP3
256 OMAP processors have AES module accelerator. Select this if you
257 want to use the OMAP module for AES algorithms.
259 config CRYPTO_DEV_PICOXCELL
260 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
261 depends on ARCH_PICOXCELL && HAVE_CLK
263 select CRYPTO_AUTHENC
270 This option enables support for the hardware offload engines in the
271 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
272 and for 3gpp Layer 2 ciphering support.
274 Saying m here will build a module named pipcoxcell_crypto.
276 config CRYPTO_DEV_S5P
277 tristate "Support for Samsung S5PV210 crypto accelerator"
278 depends on ARCH_S5PV210
281 select CRYPTO_BLKCIPHER
283 This option allows you to have support for S5P crypto acceleration.
284 Select this to offload Samsung S5PV210 or S5PC110 from AES
285 algorithms execution.
287 config CRYPTO_DEV_TEGRA_AES
288 tristate "Support for TEGRA AES hw engine"
289 depends on ARCH_TEGRA
292 TEGRA processors have AES module accelerator. Select this if you
293 want to use the TEGRA module for AES algorithms.
295 To compile this driver as a module, choose M here: the module
296 will be called tegra-aes.