2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC)
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
47 #include <acpi/processor.h>
48 #include <acpi/cppc_acpi.h>
52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53 #define fp_toint(X) ((X) >> FRAC_BITS)
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60 static inline int32_t mul_fp(int32_t x
, int32_t y
)
62 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
65 static inline int32_t div_fp(s64 x
, s64 y
)
67 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
70 static inline int ceiling_fp(int32_t x
)
75 mask
= (1 << FRAC_BITS
) - 1;
81 static inline int32_t percent_fp(int percent
)
83 return div_fp(percent
, 100);
86 static inline u64
mul_ext_fp(u64 x
, u64 y
)
88 return (x
* y
) >> EXT_FRAC_BITS
;
91 static inline u64
div_ext_fp(u64 x
, u64 y
)
93 return div64_u64(x
<< EXT_FRAC_BITS
, y
);
96 static inline int32_t percent_ext_fp(int percent
)
98 return div_ext_fp(percent
, 100);
102 * struct sample - Store performance sample
103 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
104 * performance during last sample period
105 * @busy_scaled: Scaled busy value which is used to calculate next
106 * P state. This can be different than core_avg_perf
107 * to account for cpu idle period
108 * @aperf: Difference of actual performance frequency clock count
109 * read from APERF MSR between last and current sample
110 * @mperf: Difference of maximum performance frequency clock count
111 * read from MPERF MSR between last and current sample
112 * @tsc: Difference of time stamp counter between last and
114 * @time: Current time from scheduler
116 * This structure is used in the cpudata structure to store performance sample
117 * data for choosing next P State.
120 int32_t core_avg_perf
;
129 * struct pstate_data - Store P state data
130 * @current_pstate: Current requested P state
131 * @min_pstate: Min P state possible for this platform
132 * @max_pstate: Max P state possible for this platform
133 * @max_pstate_physical:This is physical Max P state for a processor
134 * This can be higher than the max_pstate which can
135 * be limited by platform thermal design power limits
136 * @scaling: Scaling factor to convert frequency to cpufreq
138 * @turbo_pstate: Max Turbo P state possible for this platform
139 * @max_freq: @max_pstate frequency in cpufreq units
140 * @turbo_freq: @turbo_pstate frequency in cpufreq units
142 * Stores the per cpu model P state limits and current P state.
148 int max_pstate_physical
;
151 unsigned int max_freq
;
152 unsigned int turbo_freq
;
156 * struct vid_data - Stores voltage information data
157 * @min: VID data for this platform corresponding to
159 * @max: VID data corresponding to the highest P State.
160 * @turbo: VID data for turbo P state
161 * @ratio: Ratio of (vid max - vid min) /
162 * (max P state - Min P State)
164 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165 * This data is used in Atom platforms, where in addition to target P state,
166 * the voltage data needs to be specified to select next P State.
176 * struct _pid - Stores PID data
177 * @setpoint: Target set point for busyness or performance
178 * @integral: Storage for accumulated error values
179 * @p_gain: PID proportional gain
180 * @i_gain: PID integral gain
181 * @d_gain: PID derivative gain
182 * @deadband: PID deadband
183 * @last_err: Last error storage for integral part of PID calculation
185 * Stores PID coefficients and last error for PID controller.
198 * struct global_params - Global parameters, mostly tunable via sysfs.
199 * @no_turbo: Whether or not to use turbo P-states.
200 * @turbo_disabled: Whethet or not turbo P-states are available at all,
201 * based on the MSR_IA32_MISC_ENABLE value and whether or
202 * not the maximum reported turbo P-state is different from
203 * the maximum reported non-turbo one.
204 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
206 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
209 struct global_params
{
217 * struct cpudata - Per CPU instance data storage
218 * @cpu: CPU number for this instance data
219 * @policy: CPUFreq policy value
220 * @update_util: CPUFreq utility callback information
221 * @update_util_set: CPUFreq utility callback is set
222 * @iowait_boost: iowait-related boost fraction
223 * @last_update: Time of the last update.
224 * @pstate: Stores P state limits for this CPU
225 * @vid: Stores VID limits for this CPU
226 * @pid: Stores PID parameters for this CPU
227 * @last_sample_time: Last Sample time
228 * @prev_aperf: Last APERF value read from APERF MSR
229 * @prev_mperf: Last MPERF value read from MPERF MSR
230 * @prev_tsc: Last timestamp counter (TSC) value
231 * @prev_cummulative_iowait: IO Wait time difference from last and
233 * @sample: Storage for storing last Sample data
234 * @min_perf: Minimum capacity limit as a fraction of the maximum
235 * turbo P-state capacity.
236 * @max_perf: Maximum capacity limit as a fraction of the maximum
237 * turbo P-state capacity.
238 * @acpi_perf_data: Stores ACPI perf information read from _PSS
239 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
240 * @epp_powersave: Last saved HWP energy performance preference
241 * (EPP) or energy performance bias (EPB),
242 * when policy switched to performance
243 * @epp_policy: Last saved policy used to set EPP/EPB
244 * @epp_default: Power on default HWP energy performance
246 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
249 * This structure stores per CPU instance data for all CPUs.
255 struct update_util_data update_util
;
256 bool update_util_set
;
258 struct pstate_data pstate
;
263 u64 last_sample_time
;
267 u64 prev_cummulative_iowait
;
268 struct sample sample
;
272 struct acpi_processor_performance acpi_perf_data
;
273 bool valid_pss_table
;
275 unsigned int iowait_boost
;
282 static struct cpudata
**all_cpu_data
;
285 * struct pstate_adjust_policy - Stores static PID configuration data
286 * @sample_rate_ms: PID calculation sample rate in ms
287 * @sample_rate_ns: Sample rate calculation in ns
288 * @deadband: PID deadband
289 * @setpoint: PID Setpoint
290 * @p_gain_pct: PID proportional gain
291 * @i_gain_pct: PID integral gain
292 * @d_gain_pct: PID derivative gain
294 * Stores per CPU model static PID configuration data.
296 struct pstate_adjust_policy
{
307 * struct pstate_funcs - Per CPU model specific callbacks
308 * @get_max: Callback to get maximum non turbo effective P state
309 * @get_max_physical: Callback to get maximum non turbo physical P state
310 * @get_min: Callback to get minimum P state
311 * @get_turbo: Callback to get turbo P state
312 * @get_scaling: Callback to get frequency scaling factor
313 * @get_val: Callback to convert P state to actual MSR write value
314 * @get_vid: Callback to get VID data for Atom platforms
315 * @update_util: Active mode utilization update callback.
317 * Core and Atom CPU models have different way to get P State limits. This
318 * structure is used to store those callbacks.
320 struct pstate_funcs
{
321 int (*get_max
)(void);
322 int (*get_max_physical
)(void);
323 int (*get_min
)(void);
324 int (*get_turbo
)(void);
325 int (*get_scaling
)(void);
326 u64 (*get_val
)(struct cpudata
*, int pstate
);
327 void (*get_vid
)(struct cpudata
*);
328 void (*update_util
)(struct update_util_data
*data
, u64 time
,
332 static struct pstate_funcs pstate_funcs __read_mostly
;
333 static struct pstate_adjust_policy pid_params __read_mostly
= {
334 .sample_rate_ms
= 10,
335 .sample_rate_ns
= 10 * NSEC_PER_MSEC
,
343 static int hwp_active __read_mostly
;
344 static bool per_cpu_limits __read_mostly
;
346 static struct cpufreq_driver
*intel_pstate_driver __read_mostly
;
349 static bool acpi_ppc
;
352 static struct global_params global
;
354 static DEFINE_MUTEX(intel_pstate_driver_lock
);
355 static DEFINE_MUTEX(intel_pstate_limits_lock
);
359 static bool intel_pstate_get_ppc_enable_status(void)
361 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
362 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
368 #ifdef CONFIG_ACPI_CPPC_LIB
370 /* The work item is needed to avoid CPU hotplug locking issues */
371 static void intel_pstste_sched_itmt_work_fn(struct work_struct
*work
)
373 sched_set_itmt_support();
376 static DECLARE_WORK(sched_itmt_work
, intel_pstste_sched_itmt_work_fn
);
378 static void intel_pstate_set_itmt_prio(int cpu
)
380 struct cppc_perf_caps cppc_perf
;
381 static u32 max_highest_perf
= 0, min_highest_perf
= U32_MAX
;
384 ret
= cppc_get_perf_caps(cpu
, &cppc_perf
);
389 * The priorities can be set regardless of whether or not
390 * sched_set_itmt_support(true) has been called and it is valid to
391 * update them at any time after it has been called.
393 sched_set_itmt_core_prio(cppc_perf
.highest_perf
, cpu
);
395 if (max_highest_perf
<= min_highest_perf
) {
396 if (cppc_perf
.highest_perf
> max_highest_perf
)
397 max_highest_perf
= cppc_perf
.highest_perf
;
399 if (cppc_perf
.highest_perf
< min_highest_perf
)
400 min_highest_perf
= cppc_perf
.highest_perf
;
402 if (max_highest_perf
> min_highest_perf
) {
404 * This code can be run during CPU online under the
405 * CPU hotplug locks, so sched_set_itmt_support()
406 * cannot be called from here. Queue up a work item
409 schedule_work(&sched_itmt_work
);
414 static void intel_pstate_set_itmt_prio(int cpu
)
419 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
426 intel_pstate_set_itmt_prio(policy
->cpu
);
430 if (!intel_pstate_get_ppc_enable_status())
433 cpu
= all_cpu_data
[policy
->cpu
];
435 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
441 * Check if the control value in _PSS is for PERF_CTL MSR, which should
442 * guarantee that the states returned by it map to the states in our
445 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
446 ACPI_ADR_SPACE_FIXED_HARDWARE
)
450 * If there is only one entry _PSS, simply ignore _PSS and continue as
451 * usual without taking _PSS into account
453 if (cpu
->acpi_perf_data
.state_count
< 2)
456 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
457 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
458 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
459 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
460 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
461 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
462 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
466 * The _PSS table doesn't contain whole turbo frequency range.
467 * This just contains +1 MHZ above the max non turbo frequency,
468 * with control value corresponding to max turbo ratio. But
469 * when cpufreq set policy is called, it will call with this
470 * max frequency, which will cause a reduced performance as
471 * this driver uses real max turbo frequency as the max
472 * frequency. So correct this frequency in _PSS table to
473 * correct max turbo frequency based on the turbo state.
474 * Also need to convert to MHz as _PSS freq is in MHz.
476 if (!global
.turbo_disabled
)
477 cpu
->acpi_perf_data
.states
[0].core_frequency
=
478 policy
->cpuinfo
.max_freq
/ 1000;
479 cpu
->valid_pss_table
= true;
480 pr_debug("_PPC limits will be enforced\n");
485 cpu
->valid_pss_table
= false;
486 acpi_processor_unregister_performance(policy
->cpu
);
489 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
493 cpu
= all_cpu_data
[policy
->cpu
];
494 if (!cpu
->valid_pss_table
)
497 acpi_processor_unregister_performance(policy
->cpu
);
500 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
504 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
509 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
512 int32_t pterm
, dterm
, fp_error
;
513 int32_t integral_limit
;
515 fp_error
= pid
->setpoint
- busy
;
517 if (abs(fp_error
) <= pid
->deadband
)
520 pterm
= mul_fp(pid
->p_gain
, fp_error
);
522 pid
->integral
+= fp_error
;
525 * We limit the integral here so that it will never
526 * get higher than 30. This prevents it from becoming
527 * too large an input over long periods of time and allows
528 * it to get factored out sooner.
530 * The value of 30 was chosen through experimentation.
532 integral_limit
= int_tofp(30);
533 if (pid
->integral
> integral_limit
)
534 pid
->integral
= integral_limit
;
535 if (pid
->integral
< -integral_limit
)
536 pid
->integral
= -integral_limit
;
538 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
539 pid
->last_err
= fp_error
;
541 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
542 result
= result
+ (1 << (FRAC_BITS
-1));
543 return (signed int)fp_toint(result
);
546 static inline void intel_pstate_pid_reset(struct cpudata
*cpu
)
548 struct _pid
*pid
= &cpu
->pid
;
550 pid
->p_gain
= percent_fp(pid_params
.p_gain_pct
);
551 pid
->d_gain
= percent_fp(pid_params
.d_gain_pct
);
552 pid
->i_gain
= percent_fp(pid_params
.i_gain_pct
);
553 pid
->setpoint
= int_tofp(pid_params
.setpoint
);
554 pid
->last_err
= pid
->setpoint
- int_tofp(100);
555 pid
->deadband
= int_tofp(pid_params
.deadband
);
559 static inline void update_turbo_state(void)
564 cpu
= all_cpu_data
[0];
565 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
566 global
.turbo_disabled
=
567 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
568 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
571 static int min_perf_pct_min(void)
573 struct cpudata
*cpu
= all_cpu_data
[0];
575 return DIV_ROUND_UP(cpu
->pstate
.min_pstate
* 100,
576 cpu
->pstate
.turbo_pstate
);
579 static s16
intel_pstate_get_epb(struct cpudata
*cpu_data
)
584 if (!static_cpu_has(X86_FEATURE_EPB
))
587 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
591 return (s16
)(epb
& 0x0f);
594 static s16
intel_pstate_get_epp(struct cpudata
*cpu_data
, u64 hwp_req_data
)
598 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
600 * When hwp_req_data is 0, means that caller didn't read
601 * MSR_HWP_REQUEST, so need to read and get EPP.
604 epp
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
,
609 epp
= (hwp_req_data
>> 24) & 0xff;
611 /* When there is no EPP present, HWP uses EPB settings */
612 epp
= intel_pstate_get_epb(cpu_data
);
618 static int intel_pstate_set_epb(int cpu
, s16 pref
)
623 if (!static_cpu_has(X86_FEATURE_EPB
))
626 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &epb
);
630 epb
= (epb
& ~0x0f) | pref
;
631 wrmsrl_on_cpu(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, epb
);
637 * EPP/EPB display strings corresponding to EPP index in the
638 * energy_perf_strings[]
640 *-------------------------------------
643 * 2 balance_performance
647 static const char * const energy_perf_strings
[] = {
650 "balance_performance",
656 static int intel_pstate_get_energy_pref_index(struct cpudata
*cpu_data
)
661 epp
= intel_pstate_get_epp(cpu_data
, 0);
665 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
668 * 0x00-0x3F : Performance
669 * 0x40-0x7F : Balance performance
670 * 0x80-0xBF : Balance power
672 * The EPP is a 8 bit value, but our ranges restrict the
673 * value which can be set. Here only using top two bits
676 index
= (epp
>> 6) + 1;
677 } else if (static_cpu_has(X86_FEATURE_EPB
)) {
680 * 0x00-0x03 : Performance
681 * 0x04-0x07 : Balance performance
682 * 0x08-0x0B : Balance power
684 * The EPB is a 4 bit value, but our ranges restrict the
685 * value which can be set. Here only using top two bits
688 index
= (epp
>> 2) + 1;
694 static int intel_pstate_set_energy_pref_index(struct cpudata
*cpu_data
,
701 epp
= cpu_data
->epp_default
;
703 mutex_lock(&intel_pstate_limits_lock
);
705 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
708 ret
= rdmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, &value
);
712 value
&= ~GENMASK_ULL(31, 24);
715 * If epp is not default, convert from index into
716 * energy_perf_strings to epp value, by shifting 6
717 * bits left to use only top two bits in epp.
718 * The resultant epp need to shifted by 24 bits to
719 * epp position in MSR_HWP_REQUEST.
722 epp
= (pref_index
- 1) << 6;
724 value
|= (u64
)epp
<< 24;
725 ret
= wrmsrl_on_cpu(cpu_data
->cpu
, MSR_HWP_REQUEST
, value
);
728 epp
= (pref_index
- 1) << 2;
729 ret
= intel_pstate_set_epb(cpu_data
->cpu
, epp
);
732 mutex_unlock(&intel_pstate_limits_lock
);
737 static ssize_t
show_energy_performance_available_preferences(
738 struct cpufreq_policy
*policy
, char *buf
)
743 while (energy_perf_strings
[i
] != NULL
)
744 ret
+= sprintf(&buf
[ret
], "%s ", energy_perf_strings
[i
++]);
746 ret
+= sprintf(&buf
[ret
], "\n");
751 cpufreq_freq_attr_ro(energy_performance_available_preferences
);
753 static ssize_t
store_energy_performance_preference(
754 struct cpufreq_policy
*policy
, const char *buf
, size_t count
)
756 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
757 char str_preference
[21];
760 ret
= sscanf(buf
, "%20s", str_preference
);
764 while (energy_perf_strings
[i
] != NULL
) {
765 if (!strcmp(str_preference
, energy_perf_strings
[i
])) {
766 intel_pstate_set_energy_pref_index(cpu_data
, i
);
775 static ssize_t
show_energy_performance_preference(
776 struct cpufreq_policy
*policy
, char *buf
)
778 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
781 preference
= intel_pstate_get_energy_pref_index(cpu_data
);
785 return sprintf(buf
, "%s\n", energy_perf_strings
[preference
]);
788 cpufreq_freq_attr_rw(energy_performance_preference
);
790 static struct freq_attr
*hwp_cpufreq_attrs
[] = {
791 &energy_performance_preference
,
792 &energy_performance_available_preferences
,
796 static void intel_pstate_hwp_set(unsigned int cpu
)
798 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
799 int min
, hw_min
, max
, hw_max
;
803 rdmsrl_on_cpu(cpu
, MSR_HWP_CAPABILITIES
, &cap
);
804 hw_min
= HWP_LOWEST_PERF(cap
);
806 hw_max
= HWP_GUARANTEED_PERF(cap
);
808 hw_max
= HWP_HIGHEST_PERF(cap
);
810 max
= fp_ext_toint(hw_max
* cpu_data
->max_perf
);
811 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
814 min
= fp_ext_toint(hw_max
* cpu_data
->min_perf
);
816 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
818 value
&= ~HWP_MIN_PERF(~0L);
819 value
|= HWP_MIN_PERF(min
);
821 value
&= ~HWP_MAX_PERF(~0L);
822 value
|= HWP_MAX_PERF(max
);
824 if (cpu_data
->epp_policy
== cpu_data
->policy
)
827 cpu_data
->epp_policy
= cpu_data
->policy
;
829 if (cpu_data
->epp_saved
>= 0) {
830 epp
= cpu_data
->epp_saved
;
831 cpu_data
->epp_saved
= -EINVAL
;
835 if (cpu_data
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
836 epp
= intel_pstate_get_epp(cpu_data
, value
);
837 cpu_data
->epp_powersave
= epp
;
838 /* If EPP read was failed, then don't try to write */
844 /* skip setting EPP, when saved value is invalid */
845 if (cpu_data
->epp_powersave
< 0)
849 * No need to restore EPP when it is not zero. This
851 * - Policy is not changed
852 * - user has manually changed
853 * - Error reading EPB
855 epp
= intel_pstate_get_epp(cpu_data
, value
);
859 epp
= cpu_data
->epp_powersave
;
862 if (static_cpu_has(X86_FEATURE_HWP_EPP
)) {
863 value
&= ~GENMASK_ULL(31, 24);
864 value
|= (u64
)epp
<< 24;
866 intel_pstate_set_epb(cpu
, epp
);
869 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
872 static int intel_pstate_hwp_save_state(struct cpufreq_policy
*policy
)
874 struct cpudata
*cpu_data
= all_cpu_data
[policy
->cpu
];
879 cpu_data
->epp_saved
= intel_pstate_get_epp(cpu_data
, 0);
884 static int intel_pstate_resume(struct cpufreq_policy
*policy
)
889 mutex_lock(&intel_pstate_limits_lock
);
891 all_cpu_data
[policy
->cpu
]->epp_policy
= 0;
892 intel_pstate_hwp_set(policy
->cpu
);
894 mutex_unlock(&intel_pstate_limits_lock
);
899 static void intel_pstate_update_policies(void)
903 for_each_possible_cpu(cpu
)
904 cpufreq_update_policy(cpu
);
907 /************************** debugfs begin ************************/
908 static int pid_param_set(void *data
, u64 val
)
913 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
914 for_each_possible_cpu(cpu
)
915 if (all_cpu_data
[cpu
])
916 intel_pstate_pid_reset(all_cpu_data
[cpu
]);
921 static int pid_param_get(void *data
, u64
*val
)
926 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
928 static struct dentry
*debugfs_parent
;
933 struct dentry
*dentry
;
936 static struct pid_param pid_files
[] = {
937 {"sample_rate_ms", &pid_params
.sample_rate_ms
, },
938 {"d_gain_pct", &pid_params
.d_gain_pct
, },
939 {"i_gain_pct", &pid_params
.i_gain_pct
, },
940 {"deadband", &pid_params
.deadband
, },
941 {"setpoint", &pid_params
.setpoint
, },
942 {"p_gain_pct", &pid_params
.p_gain_pct
, },
946 static void intel_pstate_debug_expose_params(void)
950 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
951 if (IS_ERR_OR_NULL(debugfs_parent
))
954 for (i
= 0; pid_files
[i
].name
; i
++) {
955 struct dentry
*dentry
;
957 dentry
= debugfs_create_file(pid_files
[i
].name
, 0660,
958 debugfs_parent
, pid_files
[i
].value
,
961 pid_files
[i
].dentry
= dentry
;
965 static void intel_pstate_debug_hide_params(void)
969 if (IS_ERR_OR_NULL(debugfs_parent
))
972 for (i
= 0; pid_files
[i
].name
; i
++) {
973 debugfs_remove(pid_files
[i
].dentry
);
974 pid_files
[i
].dentry
= NULL
;
977 debugfs_remove(debugfs_parent
);
978 debugfs_parent
= NULL
;
981 /************************** debugfs end ************************/
983 /************************** sysfs begin ************************/
984 #define show_one(file_name, object) \
985 static ssize_t show_##file_name \
986 (struct kobject *kobj, struct attribute *attr, char *buf) \
988 return sprintf(buf, "%u\n", global.object); \
991 static ssize_t
intel_pstate_show_status(char *buf
);
992 static int intel_pstate_update_status(const char *buf
, size_t size
);
994 static ssize_t
show_status(struct kobject
*kobj
,
995 struct attribute
*attr
, char *buf
)
999 mutex_lock(&intel_pstate_driver_lock
);
1000 ret
= intel_pstate_show_status(buf
);
1001 mutex_unlock(&intel_pstate_driver_lock
);
1006 static ssize_t
store_status(struct kobject
*a
, struct attribute
*b
,
1007 const char *buf
, size_t count
)
1009 char *p
= memchr(buf
, '\n', count
);
1012 mutex_lock(&intel_pstate_driver_lock
);
1013 ret
= intel_pstate_update_status(buf
, p
? p
- buf
: count
);
1014 mutex_unlock(&intel_pstate_driver_lock
);
1016 return ret
< 0 ? ret
: count
;
1019 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
1020 struct attribute
*attr
, char *buf
)
1022 struct cpudata
*cpu
;
1023 int total
, no_turbo
, turbo_pct
;
1026 mutex_lock(&intel_pstate_driver_lock
);
1028 if (!intel_pstate_driver
) {
1029 mutex_unlock(&intel_pstate_driver_lock
);
1033 cpu
= all_cpu_data
[0];
1035 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1036 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
1037 turbo_fp
= div_fp(no_turbo
, total
);
1038 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
1040 mutex_unlock(&intel_pstate_driver_lock
);
1042 return sprintf(buf
, "%u\n", turbo_pct
);
1045 static ssize_t
show_num_pstates(struct kobject
*kobj
,
1046 struct attribute
*attr
, char *buf
)
1048 struct cpudata
*cpu
;
1051 mutex_lock(&intel_pstate_driver_lock
);
1053 if (!intel_pstate_driver
) {
1054 mutex_unlock(&intel_pstate_driver_lock
);
1058 cpu
= all_cpu_data
[0];
1059 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
1061 mutex_unlock(&intel_pstate_driver_lock
);
1063 return sprintf(buf
, "%u\n", total
);
1066 static ssize_t
show_no_turbo(struct kobject
*kobj
,
1067 struct attribute
*attr
, char *buf
)
1071 mutex_lock(&intel_pstate_driver_lock
);
1073 if (!intel_pstate_driver
) {
1074 mutex_unlock(&intel_pstate_driver_lock
);
1078 update_turbo_state();
1079 if (global
.turbo_disabled
)
1080 ret
= sprintf(buf
, "%u\n", global
.turbo_disabled
);
1082 ret
= sprintf(buf
, "%u\n", global
.no_turbo
);
1084 mutex_unlock(&intel_pstate_driver_lock
);
1089 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
1090 const char *buf
, size_t count
)
1095 ret
= sscanf(buf
, "%u", &input
);
1099 mutex_lock(&intel_pstate_driver_lock
);
1101 if (!intel_pstate_driver
) {
1102 mutex_unlock(&intel_pstate_driver_lock
);
1106 mutex_lock(&intel_pstate_limits_lock
);
1108 update_turbo_state();
1109 if (global
.turbo_disabled
) {
1110 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1111 mutex_unlock(&intel_pstate_limits_lock
);
1112 mutex_unlock(&intel_pstate_driver_lock
);
1116 global
.no_turbo
= clamp_t(int, input
, 0, 1);
1118 if (global
.no_turbo
) {
1119 struct cpudata
*cpu
= all_cpu_data
[0];
1120 int pct
= cpu
->pstate
.max_pstate
* 100 / cpu
->pstate
.turbo_pstate
;
1122 /* Squash the global minimum into the permitted range. */
1123 if (global
.min_perf_pct
> pct
)
1124 global
.min_perf_pct
= pct
;
1127 mutex_unlock(&intel_pstate_limits_lock
);
1129 intel_pstate_update_policies();
1131 mutex_unlock(&intel_pstate_driver_lock
);
1136 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
1137 const char *buf
, size_t count
)
1142 ret
= sscanf(buf
, "%u", &input
);
1146 mutex_lock(&intel_pstate_driver_lock
);
1148 if (!intel_pstate_driver
) {
1149 mutex_unlock(&intel_pstate_driver_lock
);
1153 mutex_lock(&intel_pstate_limits_lock
);
1155 global
.max_perf_pct
= clamp_t(int, input
, global
.min_perf_pct
, 100);
1157 mutex_unlock(&intel_pstate_limits_lock
);
1159 intel_pstate_update_policies();
1161 mutex_unlock(&intel_pstate_driver_lock
);
1166 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
1167 const char *buf
, size_t count
)
1172 ret
= sscanf(buf
, "%u", &input
);
1176 mutex_lock(&intel_pstate_driver_lock
);
1178 if (!intel_pstate_driver
) {
1179 mutex_unlock(&intel_pstate_driver_lock
);
1183 mutex_lock(&intel_pstate_limits_lock
);
1185 global
.min_perf_pct
= clamp_t(int, input
,
1186 min_perf_pct_min(), global
.max_perf_pct
);
1188 mutex_unlock(&intel_pstate_limits_lock
);
1190 intel_pstate_update_policies();
1192 mutex_unlock(&intel_pstate_driver_lock
);
1197 show_one(max_perf_pct
, max_perf_pct
);
1198 show_one(min_perf_pct
, min_perf_pct
);
1200 define_one_global_rw(status
);
1201 define_one_global_rw(no_turbo
);
1202 define_one_global_rw(max_perf_pct
);
1203 define_one_global_rw(min_perf_pct
);
1204 define_one_global_ro(turbo_pct
);
1205 define_one_global_ro(num_pstates
);
1207 static struct attribute
*intel_pstate_attributes
[] = {
1215 static struct attribute_group intel_pstate_attr_group
= {
1216 .attrs
= intel_pstate_attributes
,
1219 static void __init
intel_pstate_sysfs_expose_params(void)
1221 struct kobject
*intel_pstate_kobject
;
1224 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
1225 &cpu_subsys
.dev_root
->kobj
);
1226 if (WARN_ON(!intel_pstate_kobject
))
1229 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
1234 * If per cpu limits are enforced there are no global limits, so
1235 * return without creating max/min_perf_pct attributes
1240 rc
= sysfs_create_file(intel_pstate_kobject
, &max_perf_pct
.attr
);
1243 rc
= sysfs_create_file(intel_pstate_kobject
, &min_perf_pct
.attr
);
1247 /************************** sysfs end ************************/
1249 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
1251 /* First disable HWP notification interrupt as we don't process them */
1252 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY
))
1253 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
1255 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
1256 cpudata
->epp_policy
= 0;
1257 if (cpudata
->epp_default
== -EINVAL
)
1258 cpudata
->epp_default
= intel_pstate_get_epp(cpudata
, 0);
1261 #define MSR_IA32_POWER_CTL_BIT_EE 19
1263 /* Disable energy efficiency optimization */
1264 static void intel_pstate_disable_ee(int cpu
)
1269 ret
= rdmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, &power_ctl
);
1273 if (!(power_ctl
& BIT(MSR_IA32_POWER_CTL_BIT_EE
))) {
1274 pr_info("Disabling energy efficiency optimization\n");
1275 power_ctl
|= BIT(MSR_IA32_POWER_CTL_BIT_EE
);
1276 wrmsrl_on_cpu(cpu
, MSR_IA32_POWER_CTL
, power_ctl
);
1280 static int atom_get_min_pstate(void)
1284 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1285 return (value
>> 8) & 0x7F;
1288 static int atom_get_max_pstate(void)
1292 rdmsrl(MSR_ATOM_CORE_RATIOS
, value
);
1293 return (value
>> 16) & 0x7F;
1296 static int atom_get_turbo_pstate(void)
1300 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS
, value
);
1301 return value
& 0x7F;
1304 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
1310 val
= (u64
)pstate
<< 8;
1311 if (global
.no_turbo
&& !global
.turbo_disabled
)
1312 val
|= (u64
)1 << 32;
1314 vid_fp
= cpudata
->vid
.min
+ mul_fp(
1315 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
1316 cpudata
->vid
.ratio
);
1318 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
1319 vid
= ceiling_fp(vid_fp
);
1321 if (pstate
> cpudata
->pstate
.max_pstate
)
1322 vid
= cpudata
->vid
.turbo
;
1327 static int silvermont_get_scaling(void)
1331 /* Defined in Table 35-6 from SDM (Sept 2015) */
1332 static int silvermont_freq_table
[] = {
1333 83300, 100000, 133300, 116700, 80000};
1335 rdmsrl(MSR_FSB_FREQ
, value
);
1339 return silvermont_freq_table
[i
];
1342 static int airmont_get_scaling(void)
1346 /* Defined in Table 35-10 from SDM (Sept 2015) */
1347 static int airmont_freq_table
[] = {
1348 83300, 100000, 133300, 116700, 80000,
1349 93300, 90000, 88900, 87500};
1351 rdmsrl(MSR_FSB_FREQ
, value
);
1355 return airmont_freq_table
[i
];
1358 static void atom_get_vid(struct cpudata
*cpudata
)
1362 rdmsrl(MSR_ATOM_CORE_VIDS
, value
);
1363 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
1364 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
1365 cpudata
->vid
.ratio
= div_fp(
1366 cpudata
->vid
.max
- cpudata
->vid
.min
,
1367 int_tofp(cpudata
->pstate
.max_pstate
-
1368 cpudata
->pstate
.min_pstate
));
1370 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS
, value
);
1371 cpudata
->vid
.turbo
= value
& 0x7f;
1374 static int core_get_min_pstate(void)
1378 rdmsrl(MSR_PLATFORM_INFO
, value
);
1379 return (value
>> 40) & 0xFF;
1382 static int core_get_max_pstate_physical(void)
1386 rdmsrl(MSR_PLATFORM_INFO
, value
);
1387 return (value
>> 8) & 0xFF;
1390 static int core_get_tdp_ratio(u64 plat_info
)
1392 /* Check how many TDP levels present */
1393 if (plat_info
& 0x600000000) {
1399 /* Get the TDP level (0, 1, 2) to get ratios */
1400 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
1404 /* TDP MSR are continuous starting at 0x648 */
1405 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ (tdp_ctrl
& 0x03);
1406 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
1410 /* For level 1 and 2, bits[23:16] contain the ratio */
1411 if (tdp_ctrl
& 0x03)
1414 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
1415 pr_debug("tdp_ratio %x\n", (int)tdp_ratio
);
1417 return (int)tdp_ratio
;
1423 static int core_get_max_pstate(void)
1431 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
1432 max_pstate
= (plat_info
>> 8) & 0xFF;
1434 tdp_ratio
= core_get_tdp_ratio(plat_info
);
1439 /* Turbo activation ratio is not used on HWP platforms */
1443 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
1447 /* Do some sanity checking for safety */
1448 tar_levels
= tar
& 0xff;
1449 if (tdp_ratio
- 1 == tar_levels
) {
1450 max_pstate
= tar_levels
;
1451 pr_debug("max_pstate=TAC %x\n", max_pstate
);
1458 static int core_get_turbo_pstate(void)
1463 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1464 nont
= core_get_max_pstate();
1465 ret
= (value
) & 255;
1471 static inline int core_get_scaling(void)
1476 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
1480 val
= (u64
)pstate
<< 8;
1481 if (global
.no_turbo
&& !global
.turbo_disabled
)
1482 val
|= (u64
)1 << 32;
1487 static int knl_get_turbo_pstate(void)
1492 rdmsrl(MSR_TURBO_RATIO_LIMIT
, value
);
1493 nont
= core_get_max_pstate();
1494 ret
= (((value
) >> 8) & 0xFF);
1500 static int intel_pstate_get_base_pstate(struct cpudata
*cpu
)
1502 return global
.no_turbo
|| global
.turbo_disabled
?
1503 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1506 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
1508 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1509 cpu
->pstate
.current_pstate
= pstate
;
1511 * Generally, there is no guarantee that this code will always run on
1512 * the CPU being updated, so force the register update to run on the
1515 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1516 pstate_funcs
.get_val(cpu
, pstate
));
1519 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1521 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
1524 static void intel_pstate_max_within_limits(struct cpudata
*cpu
)
1528 update_turbo_state();
1529 pstate
= intel_pstate_get_base_pstate(cpu
);
1530 pstate
= max(cpu
->pstate
.min_pstate
,
1531 fp_ext_toint(pstate
* cpu
->max_perf
));
1532 intel_pstate_set_pstate(cpu
, pstate
);
1535 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1537 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1538 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1539 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1540 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1541 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1542 cpu
->pstate
.max_freq
= cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
;
1543 cpu
->pstate
.turbo_freq
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1545 if (pstate_funcs
.get_vid
)
1546 pstate_funcs
.get_vid(cpu
);
1548 intel_pstate_set_min_pstate(cpu
);
1551 static inline void intel_pstate_calc_avg_perf(struct cpudata
*cpu
)
1553 struct sample
*sample
= &cpu
->sample
;
1555 sample
->core_avg_perf
= div_ext_fp(sample
->aperf
, sample
->mperf
);
1558 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1561 unsigned long flags
;
1564 local_irq_save(flags
);
1565 rdmsrl(MSR_IA32_APERF
, aperf
);
1566 rdmsrl(MSR_IA32_MPERF
, mperf
);
1568 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1569 local_irq_restore(flags
);
1572 local_irq_restore(flags
);
1574 cpu
->last_sample_time
= cpu
->sample
.time
;
1575 cpu
->sample
.time
= time
;
1576 cpu
->sample
.aperf
= aperf
;
1577 cpu
->sample
.mperf
= mperf
;
1578 cpu
->sample
.tsc
= tsc
;
1579 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1580 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1581 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1583 cpu
->prev_aperf
= aperf
;
1584 cpu
->prev_mperf
= mperf
;
1585 cpu
->prev_tsc
= tsc
;
1587 * First time this function is invoked in a given cycle, all of the
1588 * previous sample data fields are equal to zero or stale and they must
1589 * be populated with meaningful numbers for things to work, so assume
1590 * that sample.time will always be reset before setting the utilization
1591 * update hook and make the caller skip the sample then.
1593 if (cpu
->last_sample_time
) {
1594 intel_pstate_calc_avg_perf(cpu
);
1600 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1602 return mul_ext_fp(cpu
->sample
.core_avg_perf
,
1603 cpu
->pstate
.max_pstate_physical
* cpu
->pstate
.scaling
);
1606 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1608 return mul_ext_fp(cpu
->pstate
.max_pstate_physical
,
1609 cpu
->sample
.core_avg_perf
);
1612 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1614 struct sample
*sample
= &cpu
->sample
;
1615 int32_t busy_frac
, boost
;
1616 int target
, avg_pstate
;
1618 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
1619 return cpu
->pstate
.turbo_pstate
;
1621 busy_frac
= div_fp(sample
->mperf
, sample
->tsc
);
1623 boost
= cpu
->iowait_boost
;
1624 cpu
->iowait_boost
>>= 1;
1626 if (busy_frac
< boost
)
1629 sample
->busy_scaled
= busy_frac
* 100;
1631 target
= global
.no_turbo
|| global
.turbo_disabled
?
1632 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
1633 target
+= target
>> 2;
1634 target
= mul_fp(target
, busy_frac
);
1635 if (target
< cpu
->pstate
.min_pstate
)
1636 target
= cpu
->pstate
.min_pstate
;
1639 * If the average P-state during the previous cycle was higher than the
1640 * current target, add 50% of the difference to the target to reduce
1641 * possible performance oscillations and offset possible performance
1642 * loss related to moving the workload from one CPU to another within
1645 avg_pstate
= get_avg_pstate(cpu
);
1646 if (avg_pstate
> target
)
1647 target
+= (avg_pstate
- target
) >> 1;
1652 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1654 int32_t perf_scaled
, max_pstate
, current_pstate
, sample_ratio
;
1657 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
)
1658 return cpu
->pstate
.turbo_pstate
;
1661 * perf_scaled is the ratio of the average P-state during the last
1662 * sampling period to the P-state requested last time (in percent).
1664 * That measures the system's response to the previous P-state
1667 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1668 current_pstate
= cpu
->pstate
.current_pstate
;
1669 perf_scaled
= mul_ext_fp(cpu
->sample
.core_avg_perf
,
1670 div_fp(100 * max_pstate
, current_pstate
));
1673 * Since our utilization update callback will not run unless we are
1674 * in C0, check if the actual elapsed time is significantly greater (3x)
1675 * than our sample interval. If it is, then we were idle for a long
1676 * enough period of time to adjust our performance metric.
1678 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1679 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1680 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1681 perf_scaled
= mul_fp(perf_scaled
, sample_ratio
);
1683 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1684 if (sample_ratio
< int_tofp(1))
1688 cpu
->sample
.busy_scaled
= perf_scaled
;
1689 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, perf_scaled
);
1692 static int intel_pstate_prepare_request(struct cpudata
*cpu
, int pstate
)
1694 int max_pstate
= intel_pstate_get_base_pstate(cpu
);
1697 min_pstate
= max(cpu
->pstate
.min_pstate
,
1698 fp_ext_toint(max_pstate
* cpu
->min_perf
));
1699 max_pstate
= max(min_pstate
, fp_ext_toint(max_pstate
* cpu
->max_perf
));
1700 return clamp_t(int, pstate
, min_pstate
, max_pstate
);
1703 static void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1705 if (pstate
== cpu
->pstate
.current_pstate
)
1708 cpu
->pstate
.current_pstate
= pstate
;
1709 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1712 static void intel_pstate_adjust_pstate(struct cpudata
*cpu
, int target_pstate
)
1714 int from
= cpu
->pstate
.current_pstate
;
1715 struct sample
*sample
;
1717 update_turbo_state();
1719 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
1720 trace_cpu_frequency(target_pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1721 intel_pstate_update_pstate(cpu
, target_pstate
);
1723 sample
= &cpu
->sample
;
1724 trace_pstate_sample(mul_ext_fp(100, sample
->core_avg_perf
),
1725 fp_toint(sample
->busy_scaled
),
1727 cpu
->pstate
.current_pstate
,
1731 get_avg_frequency(cpu
),
1732 fp_toint(cpu
->iowait_boost
* 100));
1735 static void intel_pstate_update_util_hwp(struct update_util_data
*data
,
1736 u64 time
, unsigned int flags
)
1738 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1739 u64 delta_ns
= time
- cpu
->sample
.time
;
1741 if ((s64
)delta_ns
>= INTEL_PSTATE_HWP_SAMPLING_INTERVAL
)
1742 intel_pstate_sample(cpu
, time
);
1745 static void intel_pstate_update_util_pid(struct update_util_data
*data
,
1746 u64 time
, unsigned int flags
)
1748 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1749 u64 delta_ns
= time
- cpu
->sample
.time
;
1751 if ((s64
)delta_ns
< pid_params
.sample_rate_ns
)
1754 if (intel_pstate_sample(cpu
, time
)) {
1757 target_pstate
= get_target_pstate_use_performance(cpu
);
1758 intel_pstate_adjust_pstate(cpu
, target_pstate
);
1762 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1765 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1768 if (flags
& SCHED_CPUFREQ_IOWAIT
) {
1769 cpu
->iowait_boost
= int_tofp(1);
1770 } else if (cpu
->iowait_boost
) {
1771 /* Clear iowait_boost if the CPU may have been idle. */
1772 delta_ns
= time
- cpu
->last_update
;
1773 if (delta_ns
> TICK_NSEC
)
1774 cpu
->iowait_boost
= 0;
1776 cpu
->last_update
= time
;
1777 delta_ns
= time
- cpu
->sample
.time
;
1778 if ((s64
)delta_ns
< INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL
)
1781 if (intel_pstate_sample(cpu
, time
)) {
1784 target_pstate
= get_target_pstate_use_cpu_load(cpu
);
1785 intel_pstate_adjust_pstate(cpu
, target_pstate
);
1789 static struct pstate_funcs core_funcs
= {
1790 .get_max
= core_get_max_pstate
,
1791 .get_max_physical
= core_get_max_pstate_physical
,
1792 .get_min
= core_get_min_pstate
,
1793 .get_turbo
= core_get_turbo_pstate
,
1794 .get_scaling
= core_get_scaling
,
1795 .get_val
= core_get_val
,
1796 .update_util
= intel_pstate_update_util_pid
,
1799 static const struct pstate_funcs silvermont_funcs
= {
1800 .get_max
= atom_get_max_pstate
,
1801 .get_max_physical
= atom_get_max_pstate
,
1802 .get_min
= atom_get_min_pstate
,
1803 .get_turbo
= atom_get_turbo_pstate
,
1804 .get_val
= atom_get_val
,
1805 .get_scaling
= silvermont_get_scaling
,
1806 .get_vid
= atom_get_vid
,
1807 .update_util
= intel_pstate_update_util
,
1810 static const struct pstate_funcs airmont_funcs
= {
1811 .get_max
= atom_get_max_pstate
,
1812 .get_max_physical
= atom_get_max_pstate
,
1813 .get_min
= atom_get_min_pstate
,
1814 .get_turbo
= atom_get_turbo_pstate
,
1815 .get_val
= atom_get_val
,
1816 .get_scaling
= airmont_get_scaling
,
1817 .get_vid
= atom_get_vid
,
1818 .update_util
= intel_pstate_update_util
,
1821 static const struct pstate_funcs knl_funcs
= {
1822 .get_max
= core_get_max_pstate
,
1823 .get_max_physical
= core_get_max_pstate_physical
,
1824 .get_min
= core_get_min_pstate
,
1825 .get_turbo
= knl_get_turbo_pstate
,
1826 .get_scaling
= core_get_scaling
,
1827 .get_val
= core_get_val
,
1828 .update_util
= intel_pstate_update_util_pid
,
1831 static const struct pstate_funcs bxt_funcs
= {
1832 .get_max
= core_get_max_pstate
,
1833 .get_max_physical
= core_get_max_pstate_physical
,
1834 .get_min
= core_get_min_pstate
,
1835 .get_turbo
= core_get_turbo_pstate
,
1836 .get_scaling
= core_get_scaling
,
1837 .get_val
= core_get_val
,
1838 .update_util
= intel_pstate_update_util
,
1841 #define ICPU(model, policy) \
1842 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1843 (unsigned long)&policy }
1845 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1846 ICPU(INTEL_FAM6_SANDYBRIDGE
, core_funcs
),
1847 ICPU(INTEL_FAM6_SANDYBRIDGE_X
, core_funcs
),
1848 ICPU(INTEL_FAM6_ATOM_SILVERMONT1
, silvermont_funcs
),
1849 ICPU(INTEL_FAM6_IVYBRIDGE
, core_funcs
),
1850 ICPU(INTEL_FAM6_HASWELL_CORE
, core_funcs
),
1851 ICPU(INTEL_FAM6_BROADWELL_CORE
, core_funcs
),
1852 ICPU(INTEL_FAM6_IVYBRIDGE_X
, core_funcs
),
1853 ICPU(INTEL_FAM6_HASWELL_X
, core_funcs
),
1854 ICPU(INTEL_FAM6_HASWELL_ULT
, core_funcs
),
1855 ICPU(INTEL_FAM6_HASWELL_GT3E
, core_funcs
),
1856 ICPU(INTEL_FAM6_BROADWELL_GT3E
, core_funcs
),
1857 ICPU(INTEL_FAM6_ATOM_AIRMONT
, airmont_funcs
),
1858 ICPU(INTEL_FAM6_SKYLAKE_MOBILE
, core_funcs
),
1859 ICPU(INTEL_FAM6_BROADWELL_X
, core_funcs
),
1860 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP
, core_funcs
),
1861 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_funcs
),
1862 ICPU(INTEL_FAM6_XEON_PHI_KNL
, knl_funcs
),
1863 ICPU(INTEL_FAM6_XEON_PHI_KNM
, knl_funcs
),
1864 ICPU(INTEL_FAM6_ATOM_GOLDMONT
, bxt_funcs
),
1865 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE
, bxt_funcs
),
1868 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1870 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] __initconst
= {
1871 ICPU(INTEL_FAM6_BROADWELL_XEON_D
, core_funcs
),
1872 ICPU(INTEL_FAM6_BROADWELL_X
, core_funcs
),
1873 ICPU(INTEL_FAM6_SKYLAKE_X
, core_funcs
),
1877 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids
[] = {
1878 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP
, core_funcs
),
1882 static bool pid_in_use(void);
1884 static int intel_pstate_init_cpu(unsigned int cpunum
)
1886 struct cpudata
*cpu
;
1888 cpu
= all_cpu_data
[cpunum
];
1891 cpu
= kzalloc(sizeof(*cpu
), GFP_KERNEL
);
1895 all_cpu_data
[cpunum
] = cpu
;
1897 cpu
->epp_default
= -EINVAL
;
1898 cpu
->epp_powersave
= -EINVAL
;
1899 cpu
->epp_saved
= -EINVAL
;
1902 cpu
= all_cpu_data
[cpunum
];
1907 const struct x86_cpu_id
*id
;
1909 id
= x86_match_cpu(intel_pstate_cpu_ee_disable_ids
);
1911 intel_pstate_disable_ee(cpunum
);
1913 intel_pstate_hwp_enable(cpu
);
1914 } else if (pid_in_use()) {
1915 intel_pstate_pid_reset(cpu
);
1918 intel_pstate_get_cpu_pstates(cpu
);
1920 pr_debug("controlling: cpu %d\n", cpunum
);
1925 static unsigned int intel_pstate_get(unsigned int cpu_num
)
1927 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1929 return cpu
? get_avg_frequency(cpu
) : 0;
1932 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
1934 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1936 if (cpu
->update_util_set
)
1939 /* Prevent intel_pstate_update_util() from using stale data. */
1940 cpu
->sample
.time
= 0;
1941 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
1942 pstate_funcs
.update_util
);
1943 cpu
->update_util_set
= true;
1946 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
1948 struct cpudata
*cpu_data
= all_cpu_data
[cpu
];
1950 if (!cpu_data
->update_util_set
)
1953 cpufreq_remove_update_util_hook(cpu
);
1954 cpu_data
->update_util_set
= false;
1955 synchronize_sched();
1958 static int intel_pstate_get_max_freq(struct cpudata
*cpu
)
1960 return global
.turbo_disabled
|| global
.no_turbo
?
1961 cpu
->pstate
.max_freq
: cpu
->pstate
.turbo_freq
;
1964 static void intel_pstate_update_perf_limits(struct cpufreq_policy
*policy
,
1965 struct cpudata
*cpu
)
1967 int max_freq
= intel_pstate_get_max_freq(cpu
);
1968 int32_t max_policy_perf
, min_policy_perf
;
1970 max_policy_perf
= div_ext_fp(policy
->max
, max_freq
);
1971 max_policy_perf
= clamp_t(int32_t, max_policy_perf
, 0, int_ext_tofp(1));
1972 if (policy
->max
== policy
->min
) {
1973 min_policy_perf
= max_policy_perf
;
1975 min_policy_perf
= div_ext_fp(policy
->min
, max_freq
);
1976 min_policy_perf
= clamp_t(int32_t, min_policy_perf
,
1977 0, max_policy_perf
);
1980 /* Normalize user input to [min_perf, max_perf] */
1981 if (per_cpu_limits
) {
1982 cpu
->min_perf
= min_policy_perf
;
1983 cpu
->max_perf
= max_policy_perf
;
1985 int32_t global_min
, global_max
;
1987 /* Global limits are in percent of the maximum turbo P-state. */
1988 global_max
= percent_ext_fp(global
.max_perf_pct
);
1989 global_min
= percent_ext_fp(global
.min_perf_pct
);
1990 if (max_freq
!= cpu
->pstate
.turbo_freq
) {
1991 int32_t turbo_factor
;
1993 turbo_factor
= div_ext_fp(cpu
->pstate
.turbo_pstate
,
1994 cpu
->pstate
.max_pstate
);
1995 global_min
= mul_ext_fp(global_min
, turbo_factor
);
1996 global_max
= mul_ext_fp(global_max
, turbo_factor
);
1998 global_min
= clamp_t(int32_t, global_min
, 0, global_max
);
2000 cpu
->min_perf
= max(min_policy_perf
, global_min
);
2001 cpu
->min_perf
= min(cpu
->min_perf
, max_policy_perf
);
2002 cpu
->max_perf
= min(max_policy_perf
, global_max
);
2003 cpu
->max_perf
= max(min_policy_perf
, cpu
->max_perf
);
2005 /* Make sure min_perf <= max_perf */
2006 cpu
->min_perf
= min(cpu
->min_perf
, cpu
->max_perf
);
2009 cpu
->max_perf
= round_up(cpu
->max_perf
, EXT_FRAC_BITS
);
2010 cpu
->min_perf
= round_up(cpu
->min_perf
, EXT_FRAC_BITS
);
2012 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy
->cpu
,
2013 fp_ext_toint(cpu
->max_perf
* 100),
2014 fp_ext_toint(cpu
->min_perf
* 100));
2017 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
2019 struct cpudata
*cpu
;
2021 if (!policy
->cpuinfo
.max_freq
)
2024 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2025 policy
->cpuinfo
.max_freq
, policy
->max
);
2027 cpu
= all_cpu_data
[policy
->cpu
];
2028 cpu
->policy
= policy
->policy
;
2030 mutex_lock(&intel_pstate_limits_lock
);
2032 intel_pstate_update_perf_limits(policy
, cpu
);
2034 if (cpu
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
2036 * NOHZ_FULL CPUs need this as the governor callback may not
2037 * be invoked on them.
2039 intel_pstate_clear_update_util_hook(policy
->cpu
);
2040 intel_pstate_max_within_limits(cpu
);
2043 intel_pstate_set_update_util_hook(policy
->cpu
);
2046 intel_pstate_hwp_set(policy
->cpu
);
2048 mutex_unlock(&intel_pstate_limits_lock
);
2053 static void intel_pstate_adjust_policy_max(struct cpufreq_policy
*policy
,
2054 struct cpudata
*cpu
)
2056 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
&&
2057 policy
->max
< policy
->cpuinfo
.max_freq
&&
2058 policy
->max
> cpu
->pstate
.max_freq
) {
2059 pr_debug("policy->max > max non turbo frequency\n");
2060 policy
->max
= policy
->cpuinfo
.max_freq
;
2064 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
2066 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2068 update_turbo_state();
2069 cpufreq_verify_within_limits(policy
, policy
->cpuinfo
.min_freq
,
2070 intel_pstate_get_max_freq(cpu
));
2072 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
2073 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
2076 intel_pstate_adjust_policy_max(policy
, cpu
);
2081 static void intel_cpufreq_stop_cpu(struct cpufreq_policy
*policy
)
2083 intel_pstate_set_min_pstate(all_cpu_data
[policy
->cpu
]);
2086 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
2088 pr_debug("CPU %d exiting\n", policy
->cpu
);
2090 intel_pstate_clear_update_util_hook(policy
->cpu
);
2092 intel_pstate_hwp_save_state(policy
);
2094 intel_cpufreq_stop_cpu(policy
);
2097 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
2099 intel_pstate_exit_perf_limits(policy
);
2101 policy
->fast_switch_possible
= false;
2106 static int __intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2108 struct cpudata
*cpu
;
2111 rc
= intel_pstate_init_cpu(policy
->cpu
);
2115 cpu
= all_cpu_data
[policy
->cpu
];
2117 cpu
->max_perf
= int_ext_tofp(1);
2120 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2121 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
2123 /* cpuinfo and default policy values */
2124 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
2125 update_turbo_state();
2126 policy
->cpuinfo
.max_freq
= global
.turbo_disabled
?
2127 cpu
->pstate
.max_pstate
: cpu
->pstate
.turbo_pstate
;
2128 policy
->cpuinfo
.max_freq
*= cpu
->pstate
.scaling
;
2130 intel_pstate_init_acpi_perf_limits(policy
);
2131 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
2133 policy
->fast_switch_possible
= true;
2138 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
2140 int ret
= __intel_pstate_cpu_init(policy
);
2145 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
2146 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
))
2147 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
2149 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
2154 static struct cpufreq_driver intel_pstate
= {
2155 .flags
= CPUFREQ_CONST_LOOPS
,
2156 .verify
= intel_pstate_verify_policy
,
2157 .setpolicy
= intel_pstate_set_policy
,
2158 .suspend
= intel_pstate_hwp_save_state
,
2159 .resume
= intel_pstate_resume
,
2160 .get
= intel_pstate_get
,
2161 .init
= intel_pstate_cpu_init
,
2162 .exit
= intel_pstate_cpu_exit
,
2163 .stop_cpu
= intel_pstate_stop_cpu
,
2164 .name
= "intel_pstate",
2167 static int intel_cpufreq_verify_policy(struct cpufreq_policy
*policy
)
2169 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2171 update_turbo_state();
2172 cpufreq_verify_within_limits(policy
, policy
->cpuinfo
.min_freq
,
2173 intel_pstate_get_max_freq(cpu
));
2175 intel_pstate_adjust_policy_max(policy
, cpu
);
2177 intel_pstate_update_perf_limits(policy
, cpu
);
2182 static int intel_cpufreq_target(struct cpufreq_policy
*policy
,
2183 unsigned int target_freq
,
2184 unsigned int relation
)
2186 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2187 struct cpufreq_freqs freqs
;
2190 update_turbo_state();
2192 freqs
.old
= policy
->cur
;
2193 freqs
.new = target_freq
;
2195 cpufreq_freq_transition_begin(policy
, &freqs
);
2197 case CPUFREQ_RELATION_L
:
2198 target_pstate
= DIV_ROUND_UP(freqs
.new, cpu
->pstate
.scaling
);
2200 case CPUFREQ_RELATION_H
:
2201 target_pstate
= freqs
.new / cpu
->pstate
.scaling
;
2204 target_pstate
= DIV_ROUND_CLOSEST(freqs
.new, cpu
->pstate
.scaling
);
2207 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2208 if (target_pstate
!= cpu
->pstate
.current_pstate
) {
2209 cpu
->pstate
.current_pstate
= target_pstate
;
2210 wrmsrl_on_cpu(policy
->cpu
, MSR_IA32_PERF_CTL
,
2211 pstate_funcs
.get_val(cpu
, target_pstate
));
2213 freqs
.new = target_pstate
* cpu
->pstate
.scaling
;
2214 cpufreq_freq_transition_end(policy
, &freqs
, false);
2219 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy
*policy
,
2220 unsigned int target_freq
)
2222 struct cpudata
*cpu
= all_cpu_data
[policy
->cpu
];
2225 update_turbo_state();
2227 target_pstate
= DIV_ROUND_UP(target_freq
, cpu
->pstate
.scaling
);
2228 target_pstate
= intel_pstate_prepare_request(cpu
, target_pstate
);
2229 intel_pstate_update_pstate(cpu
, target_pstate
);
2230 return target_pstate
* cpu
->pstate
.scaling
;
2233 static int intel_cpufreq_cpu_init(struct cpufreq_policy
*policy
)
2235 int ret
= __intel_pstate_cpu_init(policy
);
2240 policy
->cpuinfo
.transition_latency
= INTEL_CPUFREQ_TRANSITION_LATENCY
;
2241 policy
->transition_delay_us
= INTEL_CPUFREQ_TRANSITION_DELAY
;
2242 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2243 policy
->cur
= policy
->cpuinfo
.min_freq
;
2248 static struct cpufreq_driver intel_cpufreq
= {
2249 .flags
= CPUFREQ_CONST_LOOPS
,
2250 .verify
= intel_cpufreq_verify_policy
,
2251 .target
= intel_cpufreq_target
,
2252 .fast_switch
= intel_cpufreq_fast_switch
,
2253 .init
= intel_cpufreq_cpu_init
,
2254 .exit
= intel_pstate_cpu_exit
,
2255 .stop_cpu
= intel_cpufreq_stop_cpu
,
2256 .name
= "intel_cpufreq",
2259 static struct cpufreq_driver
*default_driver
= &intel_pstate
;
2261 static bool pid_in_use(void)
2263 return intel_pstate_driver
== &intel_pstate
&&
2264 pstate_funcs
.update_util
== intel_pstate_update_util_pid
;
2267 static void intel_pstate_driver_cleanup(void)
2272 for_each_online_cpu(cpu
) {
2273 if (all_cpu_data
[cpu
]) {
2274 if (intel_pstate_driver
== &intel_pstate
)
2275 intel_pstate_clear_update_util_hook(cpu
);
2277 kfree(all_cpu_data
[cpu
]);
2278 all_cpu_data
[cpu
] = NULL
;
2282 intel_pstate_driver
= NULL
;
2285 static int intel_pstate_register_driver(struct cpufreq_driver
*driver
)
2289 memset(&global
, 0, sizeof(global
));
2290 global
.max_perf_pct
= 100;
2292 intel_pstate_driver
= driver
;
2293 ret
= cpufreq_register_driver(intel_pstate_driver
);
2295 intel_pstate_driver_cleanup();
2299 global
.min_perf_pct
= min_perf_pct_min();
2302 intel_pstate_debug_expose_params();
2307 static int intel_pstate_unregister_driver(void)
2313 intel_pstate_debug_hide_params();
2315 cpufreq_unregister_driver(intel_pstate_driver
);
2316 intel_pstate_driver_cleanup();
2321 static ssize_t
intel_pstate_show_status(char *buf
)
2323 if (!intel_pstate_driver
)
2324 return sprintf(buf
, "off\n");
2326 return sprintf(buf
, "%s\n", intel_pstate_driver
== &intel_pstate
?
2327 "active" : "passive");
2330 static int intel_pstate_update_status(const char *buf
, size_t size
)
2334 if (size
== 3 && !strncmp(buf
, "off", size
))
2335 return intel_pstate_driver
?
2336 intel_pstate_unregister_driver() : -EINVAL
;
2338 if (size
== 6 && !strncmp(buf
, "active", size
)) {
2339 if (intel_pstate_driver
) {
2340 if (intel_pstate_driver
== &intel_pstate
)
2343 ret
= intel_pstate_unregister_driver();
2348 return intel_pstate_register_driver(&intel_pstate
);
2351 if (size
== 7 && !strncmp(buf
, "passive", size
)) {
2352 if (intel_pstate_driver
) {
2353 if (intel_pstate_driver
== &intel_cpufreq
)
2356 ret
= intel_pstate_unregister_driver();
2361 return intel_pstate_register_driver(&intel_cpufreq
);
2367 static int no_load __initdata
;
2368 static int no_hwp __initdata
;
2369 static int hwp_only __initdata
;
2370 static unsigned int force_load __initdata
;
2372 static int __init
intel_pstate_msrs_not_valid(void)
2374 if (!pstate_funcs
.get_max() ||
2375 !pstate_funcs
.get_min() ||
2376 !pstate_funcs
.get_turbo())
2383 static void intel_pstate_use_acpi_profile(void)
2385 switch (acpi_gbl_FADT
.preferred_profile
) {
2388 case PM_APPLIANCE_PC
:
2390 case PM_WORKSTATION
:
2391 pstate_funcs
.update_util
= intel_pstate_update_util
;
2395 static void intel_pstate_use_acpi_profile(void)
2400 static void __init
copy_cpu_funcs(struct pstate_funcs
*funcs
)
2402 pstate_funcs
.get_max
= funcs
->get_max
;
2403 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
2404 pstate_funcs
.get_min
= funcs
->get_min
;
2405 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
2406 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
2407 pstate_funcs
.get_val
= funcs
->get_val
;
2408 pstate_funcs
.get_vid
= funcs
->get_vid
;
2409 pstate_funcs
.update_util
= funcs
->update_util
;
2411 intel_pstate_use_acpi_profile();
2416 static bool __init
intel_pstate_no_acpi_pss(void)
2420 for_each_possible_cpu(i
) {
2422 union acpi_object
*pss
;
2423 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
2424 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2429 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
2430 if (ACPI_FAILURE(status
))
2433 pss
= buffer
.pointer
;
2434 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
2445 static bool __init
intel_pstate_has_acpi_ppc(void)
2449 for_each_possible_cpu(i
) {
2450 struct acpi_processor
*pr
= per_cpu(processors
, i
);
2454 if (acpi_has_method(pr
->handle
, "_PPC"))
2465 struct hw_vendor_info
{
2467 char oem_id
[ACPI_OEM_ID_SIZE
];
2468 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
2472 /* Hardware vendor-specific info that has its own power management modes */
2473 static struct hw_vendor_info vendor_info
[] __initdata
= {
2474 {1, "HP ", "ProLiant", PSS
},
2475 {1, "ORACLE", "X4-2 ", PPC
},
2476 {1, "ORACLE", "X4-2L ", PPC
},
2477 {1, "ORACLE", "X4-2B ", PPC
},
2478 {1, "ORACLE", "X3-2 ", PPC
},
2479 {1, "ORACLE", "X3-2L ", PPC
},
2480 {1, "ORACLE", "X3-2B ", PPC
},
2481 {1, "ORACLE", "X4470M2 ", PPC
},
2482 {1, "ORACLE", "X4270M3 ", PPC
},
2483 {1, "ORACLE", "X4270M2 ", PPC
},
2484 {1, "ORACLE", "X4170M2 ", PPC
},
2485 {1, "ORACLE", "X4170 M3", PPC
},
2486 {1, "ORACLE", "X4275 M3", PPC
},
2487 {1, "ORACLE", "X6-2 ", PPC
},
2488 {1, "ORACLE", "Sudbury ", PPC
},
2492 static bool __init
intel_pstate_platform_pwr_mgmt_exists(void)
2494 struct acpi_table_header hdr
;
2495 struct hw_vendor_info
*v_info
;
2496 const struct x86_cpu_id
*id
;
2499 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
2501 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
2502 if ( misc_pwr
& (1 << 8))
2506 if (acpi_disabled
||
2507 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
2510 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
2511 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
2512 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
2513 ACPI_OEM_TABLE_ID_SIZE
))
2514 switch (v_info
->oem_pwr_table
) {
2516 return intel_pstate_no_acpi_pss();
2518 return intel_pstate_has_acpi_ppc() &&
2526 static void intel_pstate_request_control_from_smm(void)
2529 * It may be unsafe to request P-states control from SMM if _PPC support
2530 * has not been enabled.
2533 acpi_processor_pstate_control();
2535 #else /* CONFIG_ACPI not enabled */
2536 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2537 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2538 static inline void intel_pstate_request_control_from_smm(void) {}
2539 #endif /* CONFIG_ACPI */
2541 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
2542 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
2546 static int __init
intel_pstate_init(void)
2553 if (x86_match_cpu(hwp_support_ids
)) {
2554 copy_cpu_funcs(&core_funcs
);
2556 pstate_funcs
.update_util
= intel_pstate_update_util
;
2559 intel_pstate
.attr
= hwp_cpufreq_attrs
;
2560 pstate_funcs
.update_util
= intel_pstate_update_util_hwp
;
2561 goto hwp_cpu_matched
;
2564 const struct x86_cpu_id
*id
;
2566 id
= x86_match_cpu(intel_pstate_cpu_ids
);
2570 copy_cpu_funcs((struct pstate_funcs
*)id
->driver_data
);
2573 if (intel_pstate_msrs_not_valid())
2578 * The Intel pstate driver will be ignored if the platform
2579 * firmware has its own power management modes.
2581 if (intel_pstate_platform_pwr_mgmt_exists())
2584 if (!hwp_active
&& hwp_only
)
2587 pr_info("Intel P-state driver initializing\n");
2589 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
2593 intel_pstate_request_control_from_smm();
2595 intel_pstate_sysfs_expose_params();
2597 mutex_lock(&intel_pstate_driver_lock
);
2598 rc
= intel_pstate_register_driver(default_driver
);
2599 mutex_unlock(&intel_pstate_driver_lock
);
2604 pr_info("HWP enabled\n");
2608 device_initcall(intel_pstate_init
);
2610 static int __init
intel_pstate_setup(char *str
)
2615 if (!strcmp(str
, "disable")) {
2617 } else if (!strcmp(str
, "passive")) {
2618 pr_info("Passive mode enabled\n");
2619 default_driver
= &intel_cpufreq
;
2622 if (!strcmp(str
, "no_hwp")) {
2623 pr_info("HWP disabled\n");
2626 if (!strcmp(str
, "force"))
2628 if (!strcmp(str
, "hwp_only"))
2630 if (!strcmp(str
, "per_cpu_perf_limits"))
2631 per_cpu_limits
= true;
2634 if (!strcmp(str
, "support_acpi_ppc"))
2640 early_param("intel_pstate", intel_pstate_setup
);
2642 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2643 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2644 MODULE_LICENSE("GPL");