drivers/cpufreq/exynos4x12-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4X12 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include <mach/regs-clock.h>
  21 #include <mach/cpufreq.h>
  22
  23 static struct clk *cpu_clk;
  24 static struct clk *moutcore;
  25 static struct clk *mout_mpll;
  26 static struct clk *mout_apll;
  27
  28 static unsigned int exynos4x12_volt_table[] = {
  29         1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
  30         1000000,  987500,  975000,  950000,  925000,  900000,  900000
  31 };
  32
  33 static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
  34         {L0, CPUFREQ_ENTRY_INVALID},
  35         {L1, 1400 * 1000},
  36         {L2, 1300 * 1000},
  37         {L3, 1200 * 1000},
  38         {L4, 1100 * 1000},
  39         {L5, 1000 * 1000},
  40         {L6,  900 * 1000},
  41         {L7,  800 * 1000},
  42         {L8,  700 * 1000},
  43         {L9,  600 * 1000},
  44         {L10, 500 * 1000},
  45         {L11, 400 * 1000},
  46         {L12, 300 * 1000},
  47         {L13, 200 * 1000},
  48         {0, CPUFREQ_TABLE_END},
  49 };
  50
  51 static struct apll_freq *apll_freq_4x12;
  52
  53 static struct apll_freq apll_freq_4212[] = {
  54         /*
  55          * values:
  56          * freq
  57          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  58          * clock divider for COPY, HPM, RESERVED
  59          * PLL M, P, S
  60          */
  61         APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
  62         APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
  63         APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
  64         APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
  65         APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
  66         APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
  67         APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
  68         APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
  69         APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
  70         APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
  71         APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
  72         APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
  73         APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
  74         APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
  75 };
  76
  77 static struct apll_freq apll_freq_4412[] = {
  78         /*
  79          * values:
  80          * freq
  81          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
  82          * clock divider for COPY, HPM, CORES
  83          * PLL M, P, S
  84          */
  85         APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
  86         APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
  87         APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
  88         APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
  89         APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
  90         APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
  91         APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
  92         APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
  93         APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
  94         APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
  95         APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
  96         APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
  97         APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
  98         APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
  99 };
 100
 101 static void exynos4x12_set_clkdiv(unsigned int div_index)
 102 {
 103         unsigned int tmp;
 104         unsigned int stat_cpu1;
 105
 106         /* Change Divider - CPU0 */
 107
 108         tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 109
 110         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 111
 112         while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
 113                 cpu_relax();
 114
 115         /* Change Divider - CPU1 */
 116         tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 117
 118         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 119         if (soc_is_exynos4212())
 120                 stat_cpu1 = 0x11;
 121         else
 122                 stat_cpu1 = 0x111;
 123
 124         while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
 125                 cpu_relax();
 126 }
 127
 128 static void exynos4x12_set_apll(unsigned int index)
 129 {
 130         unsigned int tmp, pdiv;
 131
 132         /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 133         clk_set_parent(moutcore, mout_mpll);
 134
 135         do {
 136                 cpu_relax();
 137                 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 138                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 139                 tmp &= 0x7;
 140         } while (tmp != 0x2);
 141
 142         /* 2. Set APLL Lock time */
 143         pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
 144
 145         __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
 146
 147         /* 3. Change PLL PMS values */
 148         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 149         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 150         tmp |= apll_freq_4x12[index].mps;
 151         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 152
 153         /* 4. wait_lock_time */
 154         do {
 155                 cpu_relax();
 156                 tmp = __raw_readl(EXYNOS4_APLL_CON0);
 157         } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
 158
 159         /* 5. MUX_CORE_SEL = APLL */
 160         clk_set_parent(moutcore, mout_apll);
 161
 162         do {
 163                 cpu_relax();
 164                 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 165                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 166         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 167 }
 168
 169 static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
 170 {
 171         unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
 172         unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
 173
 174         return (old_pm == new_pm) ? 0 : 1;
 175 }
 176
 177 static void exynos4x12_set_frequency(unsigned int old_index,
 178                                   unsigned int new_index)
 179 {
 180         unsigned int tmp;
 181
 182         if (old_index > new_index) {
 183                 if (!exynos4x12_pms_change(old_index, new_index)) {
 184                         /* 1. Change the system clock divider values */
 185                         exynos4x12_set_clkdiv(new_index);
 186                         /* 2. Change just s value in apll m,p,s value */
 187                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 188                         tmp &= ~(0x7 << 0);
 189                         tmp |= apll_freq_4x12[new_index].mps & 0x7;
 190                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 191
 192                 } else {
 193                         /* Clock Configuration Procedure */
 194                         /* 1. Change the system clock divider values */
 195                         exynos4x12_set_clkdiv(new_index);
 196                         /* 2. Change the apll m,p,s value */
 197                         exynos4x12_set_apll(new_index);
 198                 }
 199         } else if (old_index < new_index) {
 200                 if (!exynos4x12_pms_change(old_index, new_index)) {
 201                         /* 1. Change just s value in apll m,p,s value */
 202                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 203                         tmp &= ~(0x7 << 0);
 204                         tmp |= apll_freq_4x12[new_index].mps & 0x7;
 205                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 206                         /* 2. Change the system clock divider values */
 207                         exynos4x12_set_clkdiv(new_index);
 208                 } else {
 209                         /* Clock Configuration Procedure */
 210                         /* 1. Change the apll m,p,s value */
 211                         exynos4x12_set_apll(new_index);
 212                         /* 2. Change the system clock divider values */
 213                         exynos4x12_set_clkdiv(new_index);
 214                 }
 215         }
 216 }
 217
 218 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 219 {
 220         unsigned long rate;
 221
 222         cpu_clk = clk_get(NULL, "armclk");
 223         if (IS_ERR(cpu_clk))
 224                 return PTR_ERR(cpu_clk);
 225
 226         moutcore = clk_get(NULL, "moutcore");
 227         if (IS_ERR(moutcore))
 228                 goto err_moutcore;
 229
 230         mout_mpll = clk_get(NULL, "mout_mpll");
 231         if (IS_ERR(mout_mpll))
 232                 goto err_mout_mpll;
 233
 234         rate = clk_get_rate(mout_mpll) / 1000;
 235
 236         mout_apll = clk_get(NULL, "mout_apll");
 237         if (IS_ERR(mout_apll))
 238                 goto err_mout_apll;
 239
 240         if (soc_is_exynos4212())
 241                 apll_freq_4x12 = apll_freq_4212;
 242         else
 243                 apll_freq_4x12 = apll_freq_4412;
 244
 245         info->mpll_freq_khz = rate;
 246         /* 800Mhz */
 247         info->pll_safe_idx = L7;
 248         info->cpu_clk = cpu_clk;
 249         info->volt_table = exynos4x12_volt_table;
 250         info->freq_table = exynos4x12_freq_table;
 251         info->set_freq = exynos4x12_set_frequency;
 252         info->need_apll_change = exynos4x12_pms_change;
 253
 254         return 0;
 255
 256 err_mout_apll:
 257         clk_put(mout_mpll);
 258 err_mout_mpll:
 259         clk_put(moutcore);
 260 err_moutcore:
 261         clk_put(cpu_clk);
 262
 263         pr_debug("%s: failed initialization\n", __func__);
 264         return -EINVAL;
 265 }
 266 EXPORT_SYMBOL(exynos4x12_cpufreq_init);