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[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / clk / hisilicon / clk-hi3620.c
1 /*
2 * Hisilicon Hi3620 clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/clk-provider.h>
28 #include <linux/clkdev.h>
29 #include <linux/io.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_device.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35
36 #include <dt-bindings/clock/hi3620-clock.h>
37
38 #include "clk.h"
39
40 /* clock parent list */
41 static const char *const timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
42 static const char *const timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
43 static const char *const timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
44 static const char *const timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
45 static const char *const timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
46 static const char *const timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
47 static const char *const timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
48 static const char *const timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
49 static const char *const timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
50 static const char *const timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
51 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
52 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
53 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
54 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
55 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
56 static const char *const spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
57 static const char *const spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
58 static const char *const spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
59 /* share axi parent */
60 static const char *const saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
61 static const char *const pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
62 static const char *const pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
63 static const char *const sd_mux_p[] __initconst = { "armpll2", "armpll3", };
64 static const char *const mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
65 static const char *const mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
66 static const char *const g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
67 static const char *const venc_mux_p[] __initconst = { "armpll2", "armpll3", };
68 static const char *const vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
69 static const char *const vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
70 static const char *const edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
71 static const char *const ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
72 "armpll3", "armpll5", };
73 static const char *const edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
74 static const char *const ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
75 "armpll3", "armpll5", };
76 static const char *const rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
77 static const char *const mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
78 static const char *const mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
79
80
81 /* fixed rate clocks */
82 static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
83 { HI3620_OSC32K, "osc32k", NULL, CLK_IS_ROOT, 32768, },
84 { HI3620_OSC26M, "osc26m", NULL, CLK_IS_ROOT, 26000000, },
85 { HI3620_PCLK, "pclk", NULL, CLK_IS_ROOT, 26000000, },
86 { HI3620_PLL_ARM0, "armpll0", NULL, CLK_IS_ROOT, 1600000000, },
87 { HI3620_PLL_ARM1, "armpll1", NULL, CLK_IS_ROOT, 1600000000, },
88 { HI3620_PLL_PERI, "armpll2", NULL, CLK_IS_ROOT, 1440000000, },
89 { HI3620_PLL_USB, "armpll3", NULL, CLK_IS_ROOT, 1440000000, },
90 { HI3620_PLL_HDMI, "armpll4", NULL, CLK_IS_ROOT, 1188000000, },
91 { HI3620_PLL_GPU, "armpll5", NULL, CLK_IS_ROOT, 1300000000, },
92 };
93
94 /* fixed factor clocks */
95 static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
96 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
97 { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, },
98 { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, },
99 };
100
101 static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
102 { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
103 { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
104 { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
105 { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0, 21, 2, 0, },
106 { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18, 0, 2, 0, },
107 { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18, 2, 2, 0, },
108 { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18, 4, 2, 0, },
109 { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18, 6, 2, 0, },
110 { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18, 8, 2, 0, },
111 { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x18, 10, 2, 0, },
112 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
113 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
114 { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
115 { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
116 { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
117 { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
118 { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
119 { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
120 { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
121 { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
122 { HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },
123 { HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, },
124 { HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, },
125 { HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },
126 { HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, },
127 { HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },
128 { HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, },
129 { HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },
130 { HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, },
131 { HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },
132 { HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, },
133 { HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },
134 { HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, },
135 { HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, },
136 { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },
137 };
138
139 static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
140 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
141 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
142 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
143 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
144 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
145 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
146 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
147 };
148
149 static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = {
150 { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
151 { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
152 { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
153 { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, },
154 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
155 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
156 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
157 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
158 { HI3620_GPIOCLK2, "gpioclk2", "pclk", CLK_SET_RATE_PARENT, 0x20, 10, 0, },
159 { HI3620_GPIOCLK3, "gpioclk3", "pclk", CLK_SET_RATE_PARENT, 0x20, 11, 0, },
160 { HI3620_GPIOCLK4, "gpioclk4", "pclk", CLK_SET_RATE_PARENT, 0x20, 12, 0, },
161 { HI3620_GPIOCLK5, "gpioclk5", "pclk", CLK_SET_RATE_PARENT, 0x20, 13, 0, },
162 { HI3620_GPIOCLK6, "gpioclk6", "pclk", CLK_SET_RATE_PARENT, 0x20, 14, 0, },
163 { HI3620_GPIOCLK7, "gpioclk7", "pclk", CLK_SET_RATE_PARENT, 0x20, 15, 0, },
164 { HI3620_GPIOCLK8, "gpioclk8", "pclk", CLK_SET_RATE_PARENT, 0x20, 16, 0, },
165 { HI3620_GPIOCLK9, "gpioclk9", "pclk", CLK_SET_RATE_PARENT, 0x20, 17, 0, },
166 { HI3620_GPIOCLK10, "gpioclk10", "pclk", CLK_SET_RATE_PARENT, 0x20, 18, 0, },
167 { HI3620_GPIOCLK11, "gpioclk11", "pclk", CLK_SET_RATE_PARENT, 0x20, 19, 0, },
168 { HI3620_GPIOCLK12, "gpioclk12", "pclk", CLK_SET_RATE_PARENT, 0x20, 20, 0, },
169 { HI3620_GPIOCLK13, "gpioclk13", "pclk", CLK_SET_RATE_PARENT, 0x20, 21, 0, },
170 { HI3620_GPIOCLK14, "gpioclk14", "pclk", CLK_SET_RATE_PARENT, 0x20, 22, 0, },
171 { HI3620_GPIOCLK15, "gpioclk15", "pclk", CLK_SET_RATE_PARENT, 0x20, 23, 0, },
172 { HI3620_GPIOCLK16, "gpioclk16", "pclk", CLK_SET_RATE_PARENT, 0x20, 24, 0, },
173 { HI3620_GPIOCLK17, "gpioclk17", "pclk", CLK_SET_RATE_PARENT, 0x20, 25, 0, },
174 { HI3620_GPIOCLK18, "gpioclk18", "pclk", CLK_SET_RATE_PARENT, 0x20, 26, 0, },
175 { HI3620_GPIOCLK19, "gpioclk19", "pclk", CLK_SET_RATE_PARENT, 0x20, 27, 0, },
176 { HI3620_GPIOCLK20, "gpioclk20", "pclk", CLK_SET_RATE_PARENT, 0x20, 28, 0, },
177 { HI3620_GPIOCLK21, "gpioclk21", "pclk", CLK_SET_RATE_PARENT, 0x20, 29, 0, },
178 { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 15, 0, },
179 { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 16, 0, },
180 { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 17, 0, },
181 { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", CLK_SET_RATE_PARENT, 0x30, 24, 0, },
182 { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x30, 28, 0, },
183 { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, },
184 { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, },
185 { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 5, 0, },
186 { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", CLK_SET_RATE_PARENT, 0x40, 7, 0, },
187 { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", CLK_SET_RATE_PARENT, 0x40, 8, 0, },
188 { HI3620_UARTCLK0, "uartclk0", "uart0_mux", CLK_SET_RATE_PARENT, 0x40, 16, 0, },
189 { HI3620_UARTCLK1, "uartclk1", "uart1_mux", CLK_SET_RATE_PARENT, 0x40, 17, 0, },
190 { HI3620_UARTCLK2, "uartclk2", "uart2_mux", CLK_SET_RATE_PARENT, 0x40, 18, 0, },
191 { HI3620_UARTCLK3, "uartclk3", "uart3_mux", CLK_SET_RATE_PARENT, 0x40, 19, 0, },
192 { HI3620_UARTCLK4, "uartclk4", "uart4_mux", CLK_SET_RATE_PARENT, 0x40, 20, 0, },
193 { HI3620_SPICLK0, "spiclk0", "spi0_mux", CLK_SET_RATE_PARENT, 0x40, 21, 0, },
194 { HI3620_SPICLK1, "spiclk1", "spi1_mux", CLK_SET_RATE_PARENT, 0x40, 22, 0, },
195 { HI3620_SPICLK2, "spiclk2", "spi2_mux", CLK_SET_RATE_PARENT, 0x40, 23, 0, },
196 { HI3620_I2CCLK0, "i2cclk0", "pclk", CLK_SET_RATE_PARENT, 0x40, 24, 0, },
197 { HI3620_I2CCLK1, "i2cclk1", "pclk", CLK_SET_RATE_PARENT, 0x40, 25, 0, },
198 { HI3620_SCI_CLK, "sci_clk", "osc26m", CLK_SET_RATE_PARENT, 0x40, 26, 0, },
199 { HI3620_I2CCLK2, "i2cclk2", "pclk", CLK_SET_RATE_PARENT, 0x40, 28, 0, },
200 { HI3620_I2CCLK3, "i2cclk3", "pclk", CLK_SET_RATE_PARENT, 0x40, 29, 0, },
201 { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 9, 0, },
202 { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 10, 0, },
203 { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
204 { HI3620_SD_CLK, "sd_clk", "sd_div", CLK_SET_RATE_PARENT, 0x50, 20, 0, },
205 { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, },
206 { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, },
207 { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, },
208 { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
209 };
210
211 static void __init hi3620_clk_init(struct device_node *np)
212 {
213 struct hisi_clock_data *clk_data;
214
215 clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
216 if (!clk_data)
217 return;
218
219 hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
220 ARRAY_SIZE(hi3620_fixed_rate_clks),
221 clk_data);
222 hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
223 ARRAY_SIZE(hi3620_fixed_factor_clks),
224 clk_data);
225 hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
226 clk_data);
227 hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
228 clk_data);
229 hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
230 ARRAY_SIZE(hi3620_seperated_gate_clks),
231 clk_data);
232 }
233 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
234
235 struct hisi_mmc_clock {
236 unsigned int id;
237 const char *name;
238 const char *parent_name;
239 unsigned long flags;
240 u32 clken_reg;
241 u32 clken_bit;
242 u32 div_reg;
243 u32 div_off;
244 u32 div_bits;
245 u32 drv_reg;
246 u32 drv_off;
247 u32 drv_bits;
248 u32 sam_reg;
249 u32 sam_off;
250 u32 sam_bits;
251 };
252
253 struct clk_mmc {
254 struct clk_hw hw;
255 u32 id;
256 void __iomem *clken_reg;
257 u32 clken_bit;
258 void __iomem *div_reg;
259 u32 div_off;
260 u32 div_bits;
261 void __iomem *drv_reg;
262 u32 drv_off;
263 u32 drv_bits;
264 void __iomem *sam_reg;
265 u32 sam_off;
266 u32 sam_bits;
267 };
268
269 #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw)
270
271 static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = {
272 { HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4},
273 { HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4},
274 { HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4},
275 { HI3620_MMC_CIUCLK3, "mmc_bclk3", "mmc_clk3", CLK_SET_RATE_PARENT, 0x1fc, 4, 0x1fc, 5, 3, 0x1fc, 8, 4, 0x1fc, 12, 4},
276 };
277
278 static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
279 unsigned long parent_rate)
280 {
281 switch (parent_rate) {
282 case 26000000:
283 return 13000000;
284 case 180000000:
285 return 25000000;
286 case 360000000:
287 return 50000000;
288 case 720000000:
289 return 100000000;
290 case 1440000000:
291 return 180000000;
292 default:
293 return parent_rate;
294 }
295 }
296
297 static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
298 unsigned long min_rate,
299 unsigned long max_rate,
300 unsigned long *best_parent_rate,
301 struct clk_hw **best_parent_p)
302 {
303 struct clk_mmc *mclk = to_mmc(hw);
304 unsigned long best = 0;
305
306 if ((rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
307 rate = 13000000;
308 best = 26000000;
309 } else if (rate <= 26000000) {
310 rate = 25000000;
311 best = 180000000;
312 } else if (rate <= 52000000) {
313 rate = 50000000;
314 best = 360000000;
315 } else if (rate <= 100000000) {
316 rate = 100000000;
317 best = 720000000;
318 } else {
319 /* max is 180M */
320 rate = 180000000;
321 best = 1440000000;
322 }
323 *best_parent_rate = best;
324 return rate;
325 }
326
327 static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len)
328 {
329 u32 i;
330
331 for (i = 0; i < len; i++) {
332 if (para % 2)
333 val |= 1 << (off + i);
334 else
335 val &= ~(1 << (off + i));
336 para = para >> 1;
337 }
338
339 return val;
340 }
341
342 static int mmc_clk_set_timing(struct clk_hw *hw, unsigned long rate)
343 {
344 struct clk_mmc *mclk = to_mmc(hw);
345 unsigned long flags;
346 u32 sam, drv, div, val;
347 static DEFINE_SPINLOCK(mmc_clk_lock);
348
349 switch (rate) {
350 case 13000000:
351 sam = 3;
352 drv = 1;
353 div = 1;
354 break;
355 case 25000000:
356 sam = 13;
357 drv = 6;
358 div = 6;
359 break;
360 case 50000000:
361 sam = 3;
362 drv = 6;
363 div = 6;
364 break;
365 case 100000000:
366 sam = 6;
367 drv = 4;
368 div = 6;
369 break;
370 case 180000000:
371 sam = 6;
372 drv = 4;
373 div = 7;
374 break;
375 default:
376 return -EINVAL;
377 }
378
379 spin_lock_irqsave(&mmc_clk_lock, flags);
380
381 val = readl_relaxed(mclk->clken_reg);
382 val &= ~(1 << mclk->clken_bit);
383 writel_relaxed(val, mclk->clken_reg);
384
385 val = readl_relaxed(mclk->sam_reg);
386 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);
387 writel_relaxed(val, mclk->sam_reg);
388
389 val = readl_relaxed(mclk->drv_reg);
390 val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits);
391 writel_relaxed(val, mclk->drv_reg);
392
393 val = readl_relaxed(mclk->div_reg);
394 val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits);
395 writel_relaxed(val, mclk->div_reg);
396
397 val = readl_relaxed(mclk->clken_reg);
398 val |= 1 << mclk->clken_bit;
399 writel_relaxed(val, mclk->clken_reg);
400
401 spin_unlock_irqrestore(&mmc_clk_lock, flags);
402
403 return 0;
404 }
405
406 static int mmc_clk_prepare(struct clk_hw *hw)
407 {
408 struct clk_mmc *mclk = to_mmc(hw);
409 unsigned long rate;
410
411 if (mclk->id == HI3620_MMC_CIUCLK1)
412 rate = 13000000;
413 else
414 rate = 25000000;
415
416 return mmc_clk_set_timing(hw, rate);
417 }
418
419 static int mmc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
420 unsigned long parent_rate)
421 {
422 return mmc_clk_set_timing(hw, rate);
423 }
424
425 static struct clk_ops clk_mmc_ops = {
426 .prepare = mmc_clk_prepare,
427 .determine_rate = mmc_clk_determine_rate,
428 .set_rate = mmc_clk_set_rate,
429 .recalc_rate = mmc_clk_recalc_rate,
430 };
431
432 static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
433 void __iomem *base, struct device_node *np)
434 {
435 struct clk_mmc *mclk;
436 struct clk *clk;
437 struct clk_init_data init;
438
439 mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
440 if (!mclk) {
441 pr_err("%s: fail to allocate mmc clk\n", __func__);
442 return ERR_PTR(-ENOMEM);
443 }
444
445 init.name = mmc_clk->name;
446 init.ops = &clk_mmc_ops;
447 init.flags = mmc_clk->flags | CLK_IS_BASIC;
448 init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);
449 init.num_parents = (mmc_clk->parent_name ? 1 : 0);
450 mclk->hw.init = &init;
451
452 mclk->id = mmc_clk->id;
453 mclk->clken_reg = base + mmc_clk->clken_reg;
454 mclk->clken_bit = mmc_clk->clken_bit;
455 mclk->div_reg = base + mmc_clk->div_reg;
456 mclk->div_off = mmc_clk->div_off;
457 mclk->div_bits = mmc_clk->div_bits;
458 mclk->drv_reg = base + mmc_clk->drv_reg;
459 mclk->drv_off = mmc_clk->drv_off;
460 mclk->drv_bits = mmc_clk->drv_bits;
461 mclk->sam_reg = base + mmc_clk->sam_reg;
462 mclk->sam_off = mmc_clk->sam_off;
463 mclk->sam_bits = mmc_clk->sam_bits;
464
465 clk = clk_register(NULL, &mclk->hw);
466 if (WARN_ON(IS_ERR(clk)))
467 kfree(mclk);
468 return clk;
469 }
470
471 static void __init hi3620_mmc_clk_init(struct device_node *node)
472 {
473 void __iomem *base;
474 int i, num = ARRAY_SIZE(hi3620_mmc_clks);
475 struct clk_onecell_data *clk_data;
476
477 if (!node) {
478 pr_err("failed to find pctrl node in DTS\n");
479 return;
480 }
481
482 base = of_iomap(node, 0);
483 if (!base) {
484 pr_err("failed to map pctrl\n");
485 return;
486 }
487
488 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
489 if (WARN_ON(!clk_data))
490 return;
491
492 clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL);
493 if (!clk_data->clks) {
494 pr_err("%s: fail to allocate mmc clk\n", __func__);
495 return;
496 }
497
498 for (i = 0; i < num; i++) {
499 struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
500 clk_data->clks[mmc_clk->id] =
501 hisi_register_clk_mmc(mmc_clk, base, node);
502 }
503
504 clk_data->clk_num = num;
505 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
506 }
507
508 CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);