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Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / pcmcia / synclink_cs.c
1 /*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
4 * $Id: synclink_cs.c,v 4.26 2004/08/11 19:30:02 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 #if defined(__i386__)
31 # define BREAKPOINT() asm(" int $3");
32 #else
33 # define BREAKPOINT() { }
34 #endif
35
36 #define MAX_DEVICE_COUNT 4
37
38 #include <linux/config.h>
39 #include <linux/module.h>
40 #include <linux/errno.h>
41 #include <linux/signal.h>
42 #include <linux/sched.h>
43 #include <linux/timer.h>
44 #include <linux/time.h>
45 #include <linux/interrupt.h>
46 #include <linux/pci.h>
47 #include <linux/tty.h>
48 #include <linux/tty_flip.h>
49 #include <linux/serial.h>
50 #include <linux/major.h>
51 #include <linux/string.h>
52 #include <linux/fcntl.h>
53 #include <linux/ptrace.h>
54 #include <linux/ioport.h>
55 #include <linux/mm.h>
56 #include <linux/slab.h>
57 #include <linux/netdevice.h>
58 #include <linux/vmalloc.h>
59 #include <linux/init.h>
60 #include <asm/serial.h>
61 #include <linux/delay.h>
62 #include <linux/ioctl.h>
63
64 #include <asm/system.h>
65 #include <asm/io.h>
66 #include <asm/irq.h>
67 #include <asm/dma.h>
68 #include <linux/bitops.h>
69 #include <asm/types.h>
70 #include <linux/termios.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73
74 #include <pcmcia/version.h>
75 #include <pcmcia/cs_types.h>
76 #include <pcmcia/cs.h>
77 #include <pcmcia/cistpl.h>
78 #include <pcmcia/cisreg.h>
79 #include <pcmcia/ds.h>
80
81 #ifdef CONFIG_HDLC_MODULE
82 #define CONFIG_HDLC 1
83 #endif
84
85 #define GET_USER(error,value,addr) error = get_user(value,addr)
86 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
87 #define PUT_USER(error,value,addr) error = put_user(value,addr)
88 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
89
90 #include <asm/uaccess.h>
91
92 #include "linux/synclink.h"
93
94 static MGSL_PARAMS default_params = {
95 MGSL_MODE_HDLC, /* unsigned long mode */
96 0, /* unsigned char loopback; */
97 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
98 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
99 0, /* unsigned long clock_speed; */
100 0xff, /* unsigned char addr_filter; */
101 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
102 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
103 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
104 9600, /* unsigned long data_rate; */
105 8, /* unsigned char data_bits; */
106 1, /* unsigned char stop_bits; */
107 ASYNC_PARITY_NONE /* unsigned char parity; */
108 };
109
110 typedef struct
111 {
112 int count;
113 unsigned char status;
114 char data[1];
115 } RXBUF;
116
117 /* The queue of BH actions to be performed */
118
119 #define BH_RECEIVE 1
120 #define BH_TRANSMIT 2
121 #define BH_STATUS 4
122
123 #define IO_PIN_SHUTDOWN_LIMIT 100
124
125 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
126
127 struct _input_signal_events {
128 int ri_up;
129 int ri_down;
130 int dsr_up;
131 int dsr_down;
132 int dcd_up;
133 int dcd_down;
134 int cts_up;
135 int cts_down;
136 };
137
138
139 /*
140 * Device instance data structure
141 */
142
143 typedef struct _mgslpc_info {
144 void *if_ptr; /* General purpose pointer (used by SPPP) */
145 int magic;
146 int flags;
147 int count; /* count of opens */
148 int line;
149 unsigned short close_delay;
150 unsigned short closing_wait; /* time to wait before closing */
151
152 struct mgsl_icount icount;
153
154 struct tty_struct *tty;
155 int timeout;
156 int x_char; /* xon/xoff character */
157 int blocked_open; /* # of blocked opens */
158 unsigned char read_status_mask;
159 unsigned char ignore_status_mask;
160
161 unsigned char *tx_buf;
162 int tx_put;
163 int tx_get;
164 int tx_count;
165
166 /* circular list of fixed length rx buffers */
167
168 unsigned char *rx_buf; /* memory allocated for all rx buffers */
169 int rx_buf_total_size; /* size of memory allocated for rx buffers */
170 int rx_put; /* index of next empty rx buffer */
171 int rx_get; /* index of next full rx buffer */
172 int rx_buf_size; /* size in bytes of single rx buffer */
173 int rx_buf_count; /* total number of rx buffers */
174 int rx_frame_count; /* number of full rx buffers */
175
176 wait_queue_head_t open_wait;
177 wait_queue_head_t close_wait;
178
179 wait_queue_head_t status_event_wait_q;
180 wait_queue_head_t event_wait_q;
181 struct timer_list tx_timer; /* HDLC transmit timeout timer */
182 struct _mgslpc_info *next_device; /* device list link */
183
184 unsigned short imra_value;
185 unsigned short imrb_value;
186 unsigned char pim_value;
187
188 spinlock_t lock;
189 struct work_struct task; /* task structure for scheduling bh */
190
191 u32 max_frame_size;
192
193 u32 pending_bh;
194
195 int bh_running;
196 int bh_requested;
197
198 int dcd_chkcount; /* check counts to prevent */
199 int cts_chkcount; /* too many IRQs if a signal */
200 int dsr_chkcount; /* is floating */
201 int ri_chkcount;
202
203 int rx_enabled;
204 int rx_overflow;
205
206 int tx_enabled;
207 int tx_active;
208 int tx_aborting;
209 u32 idle_mode;
210
211 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
212
213 char device_name[25]; /* device instance name */
214
215 unsigned int io_base; /* base I/O address of adapter */
216 unsigned int irq_level;
217
218 MGSL_PARAMS params; /* communications parameters */
219
220 unsigned char serial_signals; /* current serial signal states */
221
222 char irq_occurred; /* for diagnostics use */
223 char testing_irq;
224 unsigned int init_error; /* startup error (DIAGS) */
225
226 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
227 BOOLEAN drop_rts_on_tx_done;
228
229 struct _input_signal_events input_signal_events;
230
231 /* PCMCIA support */
232 dev_link_t link;
233 dev_node_t node;
234 int stop;
235
236 /* SPPP/Cisco HDLC device parts */
237 int netcount;
238 int dosyncppp;
239 spinlock_t netlock;
240
241 #ifdef CONFIG_HDLC
242 struct net_device *netdev;
243 #endif
244
245 } MGSLPC_INFO;
246
247 #define MGSLPC_MAGIC 0x5402
248
249 /*
250 * The size of the serial xmit buffer is 1 page, or 4096 bytes
251 */
252 #define TXBUFSIZE 4096
253
254
255 #define CHA 0x00 /* channel A offset */
256 #define CHB 0x40 /* channel B offset */
257
258 /*
259 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
260 */
261 #undef PVR
262
263 #define RXFIFO 0
264 #define TXFIFO 0
265 #define STAR 0x20
266 #define CMDR 0x20
267 #define RSTA 0x21
268 #define PRE 0x21
269 #define MODE 0x22
270 #define TIMR 0x23
271 #define XAD1 0x24
272 #define XAD2 0x25
273 #define RAH1 0x26
274 #define RAH2 0x27
275 #define DAFO 0x27
276 #define RAL1 0x28
277 #define RFC 0x28
278 #define RHCR 0x29
279 #define RAL2 0x29
280 #define RBCL 0x2a
281 #define XBCL 0x2a
282 #define RBCH 0x2b
283 #define XBCH 0x2b
284 #define CCR0 0x2c
285 #define CCR1 0x2d
286 #define CCR2 0x2e
287 #define CCR3 0x2f
288 #define VSTR 0x34
289 #define BGR 0x34
290 #define RLCR 0x35
291 #define AML 0x36
292 #define AMH 0x37
293 #define GIS 0x38
294 #define IVA 0x38
295 #define IPC 0x39
296 #define ISR 0x3a
297 #define IMR 0x3a
298 #define PVR 0x3c
299 #define PIS 0x3d
300 #define PIM 0x3d
301 #define PCR 0x3e
302 #define CCR4 0x3f
303
304 // IMR/ISR
305
306 #define IRQ_BREAK_ON BIT15 // rx break detected
307 #define IRQ_DATAOVERRUN BIT14 // receive data overflow
308 #define IRQ_ALLSENT BIT13 // all sent
309 #define IRQ_UNDERRUN BIT12 // transmit data underrun
310 #define IRQ_TIMER BIT11 // timer interrupt
311 #define IRQ_CTS BIT10 // CTS status change
312 #define IRQ_TXREPEAT BIT9 // tx message repeat
313 #define IRQ_TXFIFO BIT8 // transmit pool ready
314 #define IRQ_RXEOM BIT7 // receive message end
315 #define IRQ_EXITHUNT BIT6 // receive frame start
316 #define IRQ_RXTIME BIT6 // rx char timeout
317 #define IRQ_DCD BIT2 // carrier detect status change
318 #define IRQ_OVERRUN BIT1 // receive frame overflow
319 #define IRQ_RXFIFO BIT0 // receive pool full
320
321 // STAR
322
323 #define XFW BIT6 // transmit FIFO write enable
324 #define CEC BIT2 // command executing
325 #define CTS BIT1 // CTS state
326
327 #define PVR_DTR BIT0
328 #define PVR_DSR BIT1
329 #define PVR_RI BIT2
330 #define PVR_AUTOCTS BIT3
331 #define PVR_RS232 0x20 /* 0010b */
332 #define PVR_V35 0xe0 /* 1110b */
333 #define PVR_RS422 0x40 /* 0100b */
334
335 /* Register access functions */
336
337 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
338 #define read_reg(info, reg) inb((info)->io_base + (reg))
339
340 #define read_reg16(info, reg) inw((info)->io_base + (reg))
341 #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
342
343 #define set_reg_bits(info, reg, mask) \
344 write_reg(info, (reg), \
345 (unsigned char) (read_reg(info, (reg)) | (mask)))
346 #define clear_reg_bits(info, reg, mask) \
347 write_reg(info, (reg), \
348 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
349 /*
350 * interrupt enable/disable routines
351 */
352 static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
353 {
354 if (channel == CHA) {
355 info->imra_value |= mask;
356 write_reg16(info, CHA + IMR, info->imra_value);
357 } else {
358 info->imrb_value |= mask;
359 write_reg16(info, CHB + IMR, info->imrb_value);
360 }
361 }
362 static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
363 {
364 if (channel == CHA) {
365 info->imra_value &= ~mask;
366 write_reg16(info, CHA + IMR, info->imra_value);
367 } else {
368 info->imrb_value &= ~mask;
369 write_reg16(info, CHB + IMR, info->imrb_value);
370 }
371 }
372
373 #define port_irq_disable(info, mask) \
374 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
375
376 #define port_irq_enable(info, mask) \
377 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
378
379 static void rx_start(MGSLPC_INFO *info);
380 static void rx_stop(MGSLPC_INFO *info);
381
382 static void tx_start(MGSLPC_INFO *info);
383 static void tx_stop(MGSLPC_INFO *info);
384 static void tx_set_idle(MGSLPC_INFO *info);
385
386 static void get_signals(MGSLPC_INFO *info);
387 static void set_signals(MGSLPC_INFO *info);
388
389 static void reset_device(MGSLPC_INFO *info);
390
391 static void hdlc_mode(MGSLPC_INFO *info);
392 static void async_mode(MGSLPC_INFO *info);
393
394 static void tx_timeout(unsigned long context);
395
396 static int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg);
397
398 #ifdef CONFIG_HDLC
399 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
400 static void hdlcdev_tx_done(MGSLPC_INFO *info);
401 static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
402 static int hdlcdev_init(MGSLPC_INFO *info);
403 static void hdlcdev_exit(MGSLPC_INFO *info);
404 #endif
405
406 static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
407
408 static BOOLEAN register_test(MGSLPC_INFO *info);
409 static BOOLEAN irq_test(MGSLPC_INFO *info);
410 static int adapter_test(MGSLPC_INFO *info);
411
412 static int claim_resources(MGSLPC_INFO *info);
413 static void release_resources(MGSLPC_INFO *info);
414 static void mgslpc_add_device(MGSLPC_INFO *info);
415 static void mgslpc_remove_device(MGSLPC_INFO *info);
416
417 static int rx_get_frame(MGSLPC_INFO *info);
418 static void rx_reset_buffers(MGSLPC_INFO *info);
419 static int rx_alloc_buffers(MGSLPC_INFO *info);
420 static void rx_free_buffers(MGSLPC_INFO *info);
421
422 static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs);
423
424 /*
425 * Bottom half interrupt handlers
426 */
427 static void bh_handler(void* Context);
428 static void bh_transmit(MGSLPC_INFO *info);
429 static void bh_status(MGSLPC_INFO *info);
430
431 /*
432 * ioctl handlers
433 */
434 static int tiocmget(struct tty_struct *tty, struct file *file);
435 static int tiocmset(struct tty_struct *tty, struct file *file,
436 unsigned int set, unsigned int clear);
437 static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
438 static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
439 static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params);
440 static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
441 static int set_txidle(MGSLPC_INFO *info, int idle_mode);
442 static int set_txenable(MGSLPC_INFO *info, int enable);
443 static int tx_abort(MGSLPC_INFO *info);
444 static int set_rxenable(MGSLPC_INFO *info, int enable);
445 static int wait_events(MGSLPC_INFO *info, int __user *mask);
446
447 static MGSLPC_INFO *mgslpc_device_list = NULL;
448 static int mgslpc_device_count = 0;
449
450 /*
451 * Set this param to non-zero to load eax with the
452 * .text section address and breakpoint on module load.
453 * This is useful for use with gdb and add-symbol-file command.
454 */
455 static int break_on_load=0;
456
457 /*
458 * Driver major number, defaults to zero to get auto
459 * assigned major number. May be forced as module parameter.
460 */
461 static int ttymajor=0;
462
463 static int debug_level = 0;
464 static int maxframe[MAX_DEVICE_COUNT] = {0,};
465 static int dosyncppp[MAX_DEVICE_COUNT] = {1,1,1,1};
466
467 module_param(break_on_load, bool, 0);
468 module_param(ttymajor, int, 0);
469 module_param(debug_level, int, 0);
470 module_param_array(maxframe, int, NULL, 0);
471 module_param_array(dosyncppp, int, NULL, 0);
472
473 MODULE_LICENSE("GPL");
474
475 static char *driver_name = "SyncLink PC Card driver";
476 static char *driver_version = "$Revision: 4.26 $";
477
478 static struct tty_driver *serial_driver;
479
480 /* number of characters left in xmit buffer before we ask for more */
481 #define WAKEUP_CHARS 256
482
483 static void mgslpc_change_params(MGSLPC_INFO *info);
484 static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
485
486 /* PCMCIA prototypes */
487
488 static void mgslpc_config(dev_link_t *link);
489 static void mgslpc_release(u_long arg);
490 static int mgslpc_event(event_t event, int priority,
491 event_callback_args_t *args);
492 static dev_link_t *mgslpc_attach(void);
493 static void mgslpc_detach(dev_link_t *);
494
495 static dev_info_t dev_info = "synclink_cs";
496 static dev_link_t *dev_list = NULL;
497
498 /*
499 * 1st function defined in .text section. Calling this function in
500 * init_module() followed by a breakpoint allows a remote debugger
501 * (gdb) to get the .text address for the add-symbol-file command.
502 * This allows remote debugging of dynamically loadable modules.
503 */
504 static void* mgslpc_get_text_ptr(void)
505 {
506 return mgslpc_get_text_ptr;
507 }
508
509 /**
510 * line discipline callback wrappers
511 *
512 * The wrappers maintain line discipline references
513 * while calling into the line discipline.
514 *
515 * ldisc_flush_buffer - flush line discipline receive buffers
516 * ldisc_receive_buf - pass receive data to line discipline
517 */
518
519 static void ldisc_flush_buffer(struct tty_struct *tty)
520 {
521 struct tty_ldisc *ld = tty_ldisc_ref(tty);
522 if (ld) {
523 if (ld->flush_buffer)
524 ld->flush_buffer(tty);
525 tty_ldisc_deref(ld);
526 }
527 }
528
529 static void ldisc_receive_buf(struct tty_struct *tty,
530 const __u8 *data, char *flags, int count)
531 {
532 struct tty_ldisc *ld;
533 if (!tty)
534 return;
535 ld = tty_ldisc_ref(tty);
536 if (ld) {
537 if (ld->receive_buf)
538 ld->receive_buf(tty, data, flags, count);
539 tty_ldisc_deref(ld);
540 }
541 }
542
543 static dev_link_t *mgslpc_attach(void)
544 {
545 MGSLPC_INFO *info;
546 dev_link_t *link;
547 client_reg_t client_reg;
548 int ret;
549
550 if (debug_level >= DEBUG_LEVEL_INFO)
551 printk("mgslpc_attach\n");
552
553 info = (MGSLPC_INFO *)kmalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
554 if (!info) {
555 printk("Error can't allocate device instance data\n");
556 return NULL;
557 }
558
559 memset(info, 0, sizeof(MGSLPC_INFO));
560 info->magic = MGSLPC_MAGIC;
561 INIT_WORK(&info->task, bh_handler, info);
562 info->max_frame_size = 4096;
563 info->close_delay = 5*HZ/10;
564 info->closing_wait = 30*HZ;
565 init_waitqueue_head(&info->open_wait);
566 init_waitqueue_head(&info->close_wait);
567 init_waitqueue_head(&info->status_event_wait_q);
568 init_waitqueue_head(&info->event_wait_q);
569 spin_lock_init(&info->lock);
570 spin_lock_init(&info->netlock);
571 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
572 info->idle_mode = HDLC_TXIDLE_FLAGS;
573 info->imra_value = 0xffff;
574 info->imrb_value = 0xffff;
575 info->pim_value = 0xff;
576
577 link = &info->link;
578 link->priv = info;
579
580 /* Initialize the dev_link_t structure */
581
582 /* Interrupt setup */
583 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
584 link->irq.IRQInfo1 = IRQ_INFO2_VALID | IRQ_LEVEL_ID;
585 link->irq.Handler = NULL;
586
587 link->conf.Attributes = 0;
588 link->conf.Vcc = 50;
589 link->conf.IntType = INT_MEMORY_AND_IO;
590
591 /* Register with Card Services */
592 link->next = dev_list;
593 dev_list = link;
594
595 client_reg.dev_info = &dev_info;
596 client_reg.EventMask =
597 CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
598 CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
599 CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
600 client_reg.event_handler = &mgslpc_event;
601 client_reg.Version = 0x0210;
602 client_reg.event_callback_args.client_data = link;
603
604 ret = pcmcia_register_client(&link->handle, &client_reg);
605 if (ret != CS_SUCCESS) {
606 cs_error(link->handle, RegisterClient, ret);
607 mgslpc_detach(link);
608 return NULL;
609 }
610
611 mgslpc_add_device(info);
612
613 return link;
614 }
615
616 /* Card has been inserted.
617 */
618
619 #define CS_CHECK(fn, ret) \
620 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
621
622 static void mgslpc_config(dev_link_t *link)
623 {
624 client_handle_t handle = link->handle;
625 MGSLPC_INFO *info = link->priv;
626 tuple_t tuple;
627 cisparse_t parse;
628 int last_fn, last_ret;
629 u_char buf[64];
630 config_info_t conf;
631 cistpl_cftable_entry_t dflt = { 0 };
632 cistpl_cftable_entry_t *cfg;
633
634 if (debug_level >= DEBUG_LEVEL_INFO)
635 printk("mgslpc_config(0x%p)\n", link);
636
637 /* read CONFIG tuple to find its configuration registers */
638 tuple.DesiredTuple = CISTPL_CONFIG;
639 tuple.Attributes = 0;
640 tuple.TupleData = buf;
641 tuple.TupleDataMax = sizeof(buf);
642 tuple.TupleOffset = 0;
643 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
644 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
645 CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
646 link->conf.ConfigBase = parse.config.base;
647 link->conf.Present = parse.config.rmask[0];
648
649 /* Configure card */
650 link->state |= DEV_CONFIG;
651
652 /* Look up the current Vcc */
653 CS_CHECK(GetConfigurationInfo, pcmcia_get_configuration_info(handle, &conf));
654 link->conf.Vcc = conf.Vcc;
655
656 /* get CIS configuration entry */
657
658 tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
659 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
660
661 cfg = &(parse.cftable_entry);
662 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
663 CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
664
665 if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
666 if (cfg->index == 0)
667 goto cs_failed;
668
669 link->conf.ConfigIndex = cfg->index;
670 link->conf.Attributes |= CONF_ENABLE_IRQ;
671
672 /* IO window settings */
673 link->io.NumPorts1 = 0;
674 if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
675 cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
676 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
677 if (!(io->flags & CISTPL_IO_8BIT))
678 link->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
679 if (!(io->flags & CISTPL_IO_16BIT))
680 link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
681 link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
682 link->io.BasePort1 = io->win[0].base;
683 link->io.NumPorts1 = io->win[0].len;
684 CS_CHECK(RequestIO, pcmcia_request_io(link->handle, &link->io));
685 }
686
687 link->conf.Attributes = CONF_ENABLE_IRQ;
688 link->conf.Vcc = 50;
689 link->conf.IntType = INT_MEMORY_AND_IO;
690 link->conf.ConfigIndex = 8;
691 link->conf.Present = PRESENT_OPTION;
692
693 link->irq.Attributes |= IRQ_HANDLE_PRESENT;
694 link->irq.Handler = mgslpc_isr;
695 link->irq.Instance = info;
696 CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
697
698 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
699
700 info->io_base = link->io.BasePort1;
701 info->irq_level = link->irq.AssignedIRQ;
702
703 /* add to linked list of devices */
704 sprintf(info->node.dev_name, "mgslpc0");
705 info->node.major = info->node.minor = 0;
706 link->dev = &info->node;
707
708 printk(KERN_INFO "%s: index 0x%02x:",
709 info->node.dev_name, link->conf.ConfigIndex);
710 if (link->conf.Attributes & CONF_ENABLE_IRQ)
711 printk(", irq %d", link->irq.AssignedIRQ);
712 if (link->io.NumPorts1)
713 printk(", io 0x%04x-0x%04x", link->io.BasePort1,
714 link->io.BasePort1+link->io.NumPorts1-1);
715 printk("\n");
716
717 link->state &= ~DEV_CONFIG_PENDING;
718 return;
719
720 cs_failed:
721 cs_error(link->handle, last_fn, last_ret);
722 mgslpc_release((u_long)link);
723 }
724
725 /* Card has been removed.
726 * Unregister device and release PCMCIA configuration.
727 * If device is open, postpone until it is closed.
728 */
729 static void mgslpc_release(u_long arg)
730 {
731 dev_link_t *link = (dev_link_t *)arg;
732
733 if (debug_level >= DEBUG_LEVEL_INFO)
734 printk("mgslpc_release(0x%p)\n", link);
735
736 /* Unlink the device chain */
737 link->dev = NULL;
738 link->state &= ~DEV_CONFIG;
739
740 pcmcia_release_configuration(link->handle);
741 if (link->io.NumPorts1)
742 pcmcia_release_io(link->handle, &link->io);
743 if (link->irq.AssignedIRQ)
744 pcmcia_release_irq(link->handle, &link->irq);
745 if (link->state & DEV_STALE_LINK)
746 mgslpc_detach(link);
747 }
748
749 static void mgslpc_detach(dev_link_t *link)
750 {
751 dev_link_t **linkp;
752
753 if (debug_level >= DEBUG_LEVEL_INFO)
754 printk("mgslpc_detach(0x%p)\n", link);
755
756 /* find device */
757 for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
758 if (*linkp == link) break;
759 if (*linkp == NULL)
760 return;
761
762 if (link->state & DEV_CONFIG) {
763 /* device is configured/active, mark it so when
764 * release() is called a proper detach() occurs.
765 */
766 if (debug_level >= DEBUG_LEVEL_INFO)
767 printk(KERN_DEBUG "synclinkpc: detach postponed, '%s' "
768 "still locked\n", link->dev->dev_name);
769 link->state |= DEV_STALE_LINK;
770 return;
771 }
772
773 /* Break the link with Card Services */
774 if (link->handle)
775 pcmcia_deregister_client(link->handle);
776
777 /* Unlink device structure, and free it */
778 *linkp = link->next;
779 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
780 }
781
782 static int mgslpc_event(event_t event, int priority,
783 event_callback_args_t *args)
784 {
785 dev_link_t *link = args->client_data;
786 MGSLPC_INFO *info = link->priv;
787
788 if (debug_level >= DEBUG_LEVEL_INFO)
789 printk("mgslpc_event(0x%06x)\n", event);
790
791 switch (event) {
792 case CS_EVENT_CARD_REMOVAL:
793 link->state &= ~DEV_PRESENT;
794 if (link->state & DEV_CONFIG) {
795 ((MGSLPC_INFO *)link->priv)->stop = 1;
796 mgslpc_release((u_long)link);
797 }
798 break;
799 case CS_EVENT_CARD_INSERTION:
800 link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
801 mgslpc_config(link);
802 break;
803 case CS_EVENT_PM_SUSPEND:
804 link->state |= DEV_SUSPEND;
805 /* Fall through... */
806 case CS_EVENT_RESET_PHYSICAL:
807 /* Mark the device as stopped, to block IO until later */
808 info->stop = 1;
809 if (link->state & DEV_CONFIG)
810 pcmcia_release_configuration(link->handle);
811 break;
812 case CS_EVENT_PM_RESUME:
813 link->state &= ~DEV_SUSPEND;
814 /* Fall through... */
815 case CS_EVENT_CARD_RESET:
816 if (link->state & DEV_CONFIG)
817 pcmcia_request_configuration(link->handle, &link->conf);
818 info->stop = 0;
819 break;
820 }
821 return 0;
822 }
823
824 static inline int mgslpc_paranoia_check(MGSLPC_INFO *info,
825 char *name, const char *routine)
826 {
827 #ifdef MGSLPC_PARANOIA_CHECK
828 static const char *badmagic =
829 "Warning: bad magic number for mgsl struct (%s) in %s\n";
830 static const char *badinfo =
831 "Warning: null mgslpc_info for (%s) in %s\n";
832
833 if (!info) {
834 printk(badinfo, name, routine);
835 return 1;
836 }
837 if (info->magic != MGSLPC_MAGIC) {
838 printk(badmagic, name, routine);
839 return 1;
840 }
841 #else
842 if (!info)
843 return 1;
844 #endif
845 return 0;
846 }
847
848
849 #define CMD_RXFIFO BIT7 // release current rx FIFO
850 #define CMD_RXRESET BIT6 // receiver reset
851 #define CMD_RXFIFO_READ BIT5
852 #define CMD_START_TIMER BIT4
853 #define CMD_TXFIFO BIT3 // release current tx FIFO
854 #define CMD_TXEOM BIT1 // transmit end message
855 #define CMD_TXRESET BIT0 // transmit reset
856
857 static BOOLEAN wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
858 {
859 int i = 0;
860 /* wait for command completion */
861 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
862 udelay(1);
863 if (i++ == 1000)
864 return FALSE;
865 }
866 return TRUE;
867 }
868
869 static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
870 {
871 wait_command_complete(info, channel);
872 write_reg(info, (unsigned char) (channel + CMDR), cmd);
873 }
874
875 static void tx_pause(struct tty_struct *tty)
876 {
877 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
878 unsigned long flags;
879
880 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
881 return;
882 if (debug_level >= DEBUG_LEVEL_INFO)
883 printk("tx_pause(%s)\n",info->device_name);
884
885 spin_lock_irqsave(&info->lock,flags);
886 if (info->tx_enabled)
887 tx_stop(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 static void tx_release(struct tty_struct *tty)
892 {
893 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
894 unsigned long flags;
895
896 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
897 return;
898 if (debug_level >= DEBUG_LEVEL_INFO)
899 printk("tx_release(%s)\n",info->device_name);
900
901 spin_lock_irqsave(&info->lock,flags);
902 if (!info->tx_enabled)
903 tx_start(info);
904 spin_unlock_irqrestore(&info->lock,flags);
905 }
906
907 /* Return next bottom half action to perform.
908 * or 0 if nothing to do.
909 */
910 static int bh_action(MGSLPC_INFO *info)
911 {
912 unsigned long flags;
913 int rc = 0;
914
915 spin_lock_irqsave(&info->lock,flags);
916
917 if (info->pending_bh & BH_RECEIVE) {
918 info->pending_bh &= ~BH_RECEIVE;
919 rc = BH_RECEIVE;
920 } else if (info->pending_bh & BH_TRANSMIT) {
921 info->pending_bh &= ~BH_TRANSMIT;
922 rc = BH_TRANSMIT;
923 } else if (info->pending_bh & BH_STATUS) {
924 info->pending_bh &= ~BH_STATUS;
925 rc = BH_STATUS;
926 }
927
928 if (!rc) {
929 /* Mark BH routine as complete */
930 info->bh_running = 0;
931 info->bh_requested = 0;
932 }
933
934 spin_unlock_irqrestore(&info->lock,flags);
935
936 return rc;
937 }
938
939 void bh_handler(void* Context)
940 {
941 MGSLPC_INFO *info = (MGSLPC_INFO*)Context;
942 int action;
943
944 if (!info)
945 return;
946
947 if (debug_level >= DEBUG_LEVEL_BH)
948 printk( "%s(%d):bh_handler(%s) entry\n",
949 __FILE__,__LINE__,info->device_name);
950
951 info->bh_running = 1;
952
953 while((action = bh_action(info)) != 0) {
954
955 /* Process work item */
956 if ( debug_level >= DEBUG_LEVEL_BH )
957 printk( "%s(%d):bh_handler() work item action=%d\n",
958 __FILE__,__LINE__,action);
959
960 switch (action) {
961
962 case BH_RECEIVE:
963 while(rx_get_frame(info));
964 break;
965 case BH_TRANSMIT:
966 bh_transmit(info);
967 break;
968 case BH_STATUS:
969 bh_status(info);
970 break;
971 default:
972 /* unknown work item ID */
973 printk("Unknown work item ID=%08X!\n", action);
974 break;
975 }
976 }
977
978 if (debug_level >= DEBUG_LEVEL_BH)
979 printk( "%s(%d):bh_handler(%s) exit\n",
980 __FILE__,__LINE__,info->device_name);
981 }
982
983 void bh_transmit(MGSLPC_INFO *info)
984 {
985 struct tty_struct *tty = info->tty;
986 if (debug_level >= DEBUG_LEVEL_BH)
987 printk("bh_transmit() entry on %s\n", info->device_name);
988
989 if (tty) {
990 tty_wakeup(tty);
991 wake_up_interruptible(&tty->write_wait);
992 }
993 }
994
995 void bh_status(MGSLPC_INFO *info)
996 {
997 info->ri_chkcount = 0;
998 info->dsr_chkcount = 0;
999 info->dcd_chkcount = 0;
1000 info->cts_chkcount = 0;
1001 }
1002
1003 /* eom: non-zero = end of frame */
1004 static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
1005 {
1006 unsigned char data[2];
1007 unsigned char fifo_count, read_count, i;
1008 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
1009
1010 if (debug_level >= DEBUG_LEVEL_ISR)
1011 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
1012
1013 if (!info->rx_enabled)
1014 return;
1015
1016 if (info->rx_frame_count >= info->rx_buf_count) {
1017 /* no more free buffers */
1018 issue_command(info, CHA, CMD_RXRESET);
1019 info->pending_bh |= BH_RECEIVE;
1020 info->rx_overflow = 1;
1021 info->icount.buf_overrun++;
1022 return;
1023 }
1024
1025 if (eom) {
1026 /* end of frame, get FIFO count from RBCL register */
1027 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
1028 fifo_count = 32;
1029 } else
1030 fifo_count = 32;
1031
1032 do {
1033 if (fifo_count == 1) {
1034 read_count = 1;
1035 data[0] = read_reg(info, CHA + RXFIFO);
1036 } else {
1037 read_count = 2;
1038 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
1039 }
1040 fifo_count -= read_count;
1041 if (!fifo_count && eom)
1042 buf->status = data[--read_count];
1043
1044 for (i = 0; i < read_count; i++) {
1045 if (buf->count >= info->max_frame_size) {
1046 /* frame too large, reset receiver and reset current buffer */
1047 issue_command(info, CHA, CMD_RXRESET);
1048 buf->count = 0;
1049 return;
1050 }
1051 *(buf->data + buf->count) = data[i];
1052 buf->count++;
1053 }
1054 } while (fifo_count);
1055
1056 if (eom) {
1057 info->pending_bh |= BH_RECEIVE;
1058 info->rx_frame_count++;
1059 info->rx_put++;
1060 if (info->rx_put >= info->rx_buf_count)
1061 info->rx_put = 0;
1062 }
1063 issue_command(info, CHA, CMD_RXFIFO);
1064 }
1065
1066 static void rx_ready_async(MGSLPC_INFO *info, int tcd)
1067 {
1068 unsigned char data, status;
1069 int fifo_count;
1070 struct tty_struct *tty = info->tty;
1071 struct mgsl_icount *icount = &info->icount;
1072
1073 if (tcd) {
1074 /* early termination, get FIFO count from RBCL register */
1075 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
1076
1077 /* Zero fifo count could mean 0 or 32 bytes available.
1078 * If BIT5 of STAR is set then at least 1 byte is available.
1079 */
1080 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
1081 fifo_count = 32;
1082 } else
1083 fifo_count = 32;
1084
1085 /* Flush received async data to receive data buffer. */
1086 while (fifo_count) {
1087 data = read_reg(info, CHA + RXFIFO);
1088 status = read_reg(info, CHA + RXFIFO);
1089 fifo_count -= 2;
1090
1091 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1092 break;
1093
1094 *tty->flip.char_buf_ptr = data;
1095 icount->rx++;
1096
1097 *tty->flip.flag_buf_ptr = 0;
1098
1099 // if no frameing/crc error then save data
1100 // BIT7:parity error
1101 // BIT6:framing error
1102
1103 if (status & (BIT7 + BIT6)) {
1104 if (status & BIT7)
1105 icount->parity++;
1106 else
1107 icount->frame++;
1108
1109 /* discard char if tty control flags say so */
1110 if (status & info->ignore_status_mask)
1111 continue;
1112
1113 status &= info->read_status_mask;
1114
1115 if (status & BIT7)
1116 *tty->flip.flag_buf_ptr = TTY_PARITY;
1117 else if (status & BIT6)
1118 *tty->flip.flag_buf_ptr = TTY_FRAME;
1119 }
1120
1121 tty->flip.flag_buf_ptr++;
1122 tty->flip.char_buf_ptr++;
1123 tty->flip.count++;
1124 }
1125 issue_command(info, CHA, CMD_RXFIFO);
1126
1127 if (debug_level >= DEBUG_LEVEL_ISR) {
1128 printk("%s(%d):rx_ready_async count=%d\n",
1129 __FILE__,__LINE__,tty->flip.count);
1130 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1131 __FILE__,__LINE__,icount->rx,icount->brk,
1132 icount->parity,icount->frame,icount->overrun);
1133 }
1134
1135 if (tty->flip.count)
1136 tty_flip_buffer_push(tty);
1137 }
1138
1139
1140 static void tx_done(MGSLPC_INFO *info)
1141 {
1142 if (!info->tx_active)
1143 return;
1144
1145 info->tx_active = 0;
1146 info->tx_aborting = 0;
1147
1148 if (info->params.mode == MGSL_MODE_ASYNC)
1149 return;
1150
1151 info->tx_count = info->tx_put = info->tx_get = 0;
1152 del_timer(&info->tx_timer);
1153
1154 if (info->drop_rts_on_tx_done) {
1155 get_signals(info);
1156 if (info->serial_signals & SerialSignal_RTS) {
1157 info->serial_signals &= ~SerialSignal_RTS;
1158 set_signals(info);
1159 }
1160 info->drop_rts_on_tx_done = 0;
1161 }
1162
1163 #ifdef CONFIG_HDLC
1164 if (info->netcount)
1165 hdlcdev_tx_done(info);
1166 else
1167 #endif
1168 {
1169 if (info->tty->stopped || info->tty->hw_stopped) {
1170 tx_stop(info);
1171 return;
1172 }
1173 info->pending_bh |= BH_TRANSMIT;
1174 }
1175 }
1176
1177 static void tx_ready(MGSLPC_INFO *info)
1178 {
1179 unsigned char fifo_count = 32;
1180 int c;
1181
1182 if (debug_level >= DEBUG_LEVEL_ISR)
1183 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
1184
1185 if (info->params.mode == MGSL_MODE_HDLC) {
1186 if (!info->tx_active)
1187 return;
1188 } else {
1189 if (info->tty->stopped || info->tty->hw_stopped) {
1190 tx_stop(info);
1191 return;
1192 }
1193 if (!info->tx_count)
1194 info->tx_active = 0;
1195 }
1196
1197 if (!info->tx_count)
1198 return;
1199
1200 while (info->tx_count && fifo_count) {
1201 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
1202
1203 if (c == 1) {
1204 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1205 } else {
1206 write_reg16(info, CHA + TXFIFO,
1207 *((unsigned short*)(info->tx_buf + info->tx_get)));
1208 }
1209 info->tx_count -= c;
1210 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1211 fifo_count -= c;
1212 }
1213
1214 if (info->params.mode == MGSL_MODE_ASYNC) {
1215 if (info->tx_count < WAKEUP_CHARS)
1216 info->pending_bh |= BH_TRANSMIT;
1217 issue_command(info, CHA, CMD_TXFIFO);
1218 } else {
1219 if (info->tx_count)
1220 issue_command(info, CHA, CMD_TXFIFO);
1221 else
1222 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1223 }
1224 }
1225
1226 static void cts_change(MGSLPC_INFO *info)
1227 {
1228 get_signals(info);
1229 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1230 irq_disable(info, CHB, IRQ_CTS);
1231 info->icount.cts++;
1232 if (info->serial_signals & SerialSignal_CTS)
1233 info->input_signal_events.cts_up++;
1234 else
1235 info->input_signal_events.cts_down++;
1236 wake_up_interruptible(&info->status_event_wait_q);
1237 wake_up_interruptible(&info->event_wait_q);
1238
1239 if (info->flags & ASYNC_CTS_FLOW) {
1240 if (info->tty->hw_stopped) {
1241 if (info->serial_signals & SerialSignal_CTS) {
1242 if (debug_level >= DEBUG_LEVEL_ISR)
1243 printk("CTS tx start...");
1244 if (info->tty)
1245 info->tty->hw_stopped = 0;
1246 tx_start(info);
1247 info->pending_bh |= BH_TRANSMIT;
1248 return;
1249 }
1250 } else {
1251 if (!(info->serial_signals & SerialSignal_CTS)) {
1252 if (debug_level >= DEBUG_LEVEL_ISR)
1253 printk("CTS tx stop...");
1254 if (info->tty)
1255 info->tty->hw_stopped = 1;
1256 tx_stop(info);
1257 }
1258 }
1259 }
1260 info->pending_bh |= BH_STATUS;
1261 }
1262
1263 static void dcd_change(MGSLPC_INFO *info)
1264 {
1265 get_signals(info);
1266 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1267 irq_disable(info, CHB, IRQ_DCD);
1268 info->icount.dcd++;
1269 if (info->serial_signals & SerialSignal_DCD) {
1270 info->input_signal_events.dcd_up++;
1271 }
1272 else
1273 info->input_signal_events.dcd_down++;
1274 #ifdef CONFIG_HDLC
1275 if (info->netcount)
1276 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, info->netdev);
1277 #endif
1278 wake_up_interruptible(&info->status_event_wait_q);
1279 wake_up_interruptible(&info->event_wait_q);
1280
1281 if (info->flags & ASYNC_CHECK_CD) {
1282 if (debug_level >= DEBUG_LEVEL_ISR)
1283 printk("%s CD now %s...", info->device_name,
1284 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1285 if (info->serial_signals & SerialSignal_DCD)
1286 wake_up_interruptible(&info->open_wait);
1287 else {
1288 if (debug_level >= DEBUG_LEVEL_ISR)
1289 printk("doing serial hangup...");
1290 if (info->tty)
1291 tty_hangup(info->tty);
1292 }
1293 }
1294 info->pending_bh |= BH_STATUS;
1295 }
1296
1297 static void dsr_change(MGSLPC_INFO *info)
1298 {
1299 get_signals(info);
1300 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1301 port_irq_disable(info, PVR_DSR);
1302 info->icount.dsr++;
1303 if (info->serial_signals & SerialSignal_DSR)
1304 info->input_signal_events.dsr_up++;
1305 else
1306 info->input_signal_events.dsr_down++;
1307 wake_up_interruptible(&info->status_event_wait_q);
1308 wake_up_interruptible(&info->event_wait_q);
1309 info->pending_bh |= BH_STATUS;
1310 }
1311
1312 static void ri_change(MGSLPC_INFO *info)
1313 {
1314 get_signals(info);
1315 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1316 port_irq_disable(info, PVR_RI);
1317 info->icount.rng++;
1318 if (info->serial_signals & SerialSignal_RI)
1319 info->input_signal_events.ri_up++;
1320 else
1321 info->input_signal_events.ri_down++;
1322 wake_up_interruptible(&info->status_event_wait_q);
1323 wake_up_interruptible(&info->event_wait_q);
1324 info->pending_bh |= BH_STATUS;
1325 }
1326
1327 /* Interrupt service routine entry point.
1328 *
1329 * Arguments:
1330 *
1331 * irq interrupt number that caused interrupt
1332 * dev_id device ID supplied during interrupt registration
1333 * regs interrupted processor context
1334 */
1335 static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs)
1336 {
1337 MGSLPC_INFO * info = (MGSLPC_INFO *)dev_id;
1338 unsigned short isr;
1339 unsigned char gis, pis;
1340 int count=0;
1341
1342 if (debug_level >= DEBUG_LEVEL_ISR)
1343 printk("mgslpc_isr(%d) entry.\n", irq);
1344 if (!info)
1345 return IRQ_NONE;
1346
1347 if (!(info->link.state & DEV_CONFIG))
1348 return IRQ_HANDLED;
1349
1350 spin_lock(&info->lock);
1351
1352 while ((gis = read_reg(info, CHA + GIS))) {
1353 if (debug_level >= DEBUG_LEVEL_ISR)
1354 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1355
1356 if ((gis & 0x70) || count > 1000) {
1357 printk("synclink_cs:hardware failed or ejected\n");
1358 break;
1359 }
1360 count++;
1361
1362 if (gis & (BIT1 + BIT0)) {
1363 isr = read_reg16(info, CHB + ISR);
1364 if (isr & IRQ_DCD)
1365 dcd_change(info);
1366 if (isr & IRQ_CTS)
1367 cts_change(info);
1368 }
1369 if (gis & (BIT3 + BIT2))
1370 {
1371 isr = read_reg16(info, CHA + ISR);
1372 if (isr & IRQ_TIMER) {
1373 info->irq_occurred = 1;
1374 irq_disable(info, CHA, IRQ_TIMER);
1375 }
1376
1377 /* receive IRQs */
1378 if (isr & IRQ_EXITHUNT) {
1379 info->icount.exithunt++;
1380 wake_up_interruptible(&info->event_wait_q);
1381 }
1382 if (isr & IRQ_BREAK_ON) {
1383 info->icount.brk++;
1384 if (info->flags & ASYNC_SAK)
1385 do_SAK(info->tty);
1386 }
1387 if (isr & IRQ_RXTIME) {
1388 issue_command(info, CHA, CMD_RXFIFO_READ);
1389 }
1390 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1391 if (info->params.mode == MGSL_MODE_HDLC)
1392 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1393 else
1394 rx_ready_async(info, isr & IRQ_RXEOM);
1395 }
1396
1397 /* transmit IRQs */
1398 if (isr & IRQ_UNDERRUN) {
1399 if (info->tx_aborting)
1400 info->icount.txabort++;
1401 else
1402 info->icount.txunder++;
1403 tx_done(info);
1404 }
1405 else if (isr & IRQ_ALLSENT) {
1406 info->icount.txok++;
1407 tx_done(info);
1408 }
1409 else if (isr & IRQ_TXFIFO)
1410 tx_ready(info);
1411 }
1412 if (gis & BIT7) {
1413 pis = read_reg(info, CHA + PIS);
1414 if (pis & BIT1)
1415 dsr_change(info);
1416 if (pis & BIT2)
1417 ri_change(info);
1418 }
1419 }
1420
1421 /* Request bottom half processing if there's something
1422 * for it to do and the bh is not already running
1423 */
1424
1425 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
1426 if ( debug_level >= DEBUG_LEVEL_ISR )
1427 printk("%s(%d):%s queueing bh task.\n",
1428 __FILE__,__LINE__,info->device_name);
1429 schedule_work(&info->task);
1430 info->bh_requested = 1;
1431 }
1432
1433 spin_unlock(&info->lock);
1434
1435 if (debug_level >= DEBUG_LEVEL_ISR)
1436 printk("%s(%d):mgslpc_isr(%d)exit.\n",
1437 __FILE__,__LINE__,irq);
1438
1439 return IRQ_HANDLED;
1440 }
1441
1442 /* Initialize and start device.
1443 */
1444 static int startup(MGSLPC_INFO * info)
1445 {
1446 int retval = 0;
1447
1448 if (debug_level >= DEBUG_LEVEL_INFO)
1449 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
1450
1451 if (info->flags & ASYNC_INITIALIZED)
1452 return 0;
1453
1454 if (!info->tx_buf) {
1455 /* allocate a page of memory for a transmit buffer */
1456 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1457 if (!info->tx_buf) {
1458 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1459 __FILE__,__LINE__,info->device_name);
1460 return -ENOMEM;
1461 }
1462 }
1463
1464 info->pending_bh = 0;
1465
1466 init_timer(&info->tx_timer);
1467 info->tx_timer.data = (unsigned long)info;
1468 info->tx_timer.function = tx_timeout;
1469
1470 /* Allocate and claim adapter resources */
1471 retval = claim_resources(info);
1472
1473 /* perform existance check and diagnostics */
1474 if ( !retval )
1475 retval = adapter_test(info);
1476
1477 if ( retval ) {
1478 if (capable(CAP_SYS_ADMIN) && info->tty)
1479 set_bit(TTY_IO_ERROR, &info->tty->flags);
1480 release_resources(info);
1481 return retval;
1482 }
1483
1484 /* program hardware for current parameters */
1485 mgslpc_change_params(info);
1486
1487 if (info->tty)
1488 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1489
1490 info->flags |= ASYNC_INITIALIZED;
1491
1492 return 0;
1493 }
1494
1495 /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1496 */
1497 static void shutdown(MGSLPC_INFO * info)
1498 {
1499 unsigned long flags;
1500
1501 if (!(info->flags & ASYNC_INITIALIZED))
1502 return;
1503
1504 if (debug_level >= DEBUG_LEVEL_INFO)
1505 printk("%s(%d):mgslpc_shutdown(%s)\n",
1506 __FILE__,__LINE__, info->device_name );
1507
1508 /* clear status wait queue because status changes */
1509 /* can't happen after shutting down the hardware */
1510 wake_up_interruptible(&info->status_event_wait_q);
1511 wake_up_interruptible(&info->event_wait_q);
1512
1513 del_timer(&info->tx_timer);
1514
1515 if (info->tx_buf) {
1516 free_page((unsigned long) info->tx_buf);
1517 info->tx_buf = NULL;
1518 }
1519
1520 spin_lock_irqsave(&info->lock,flags);
1521
1522 rx_stop(info);
1523 tx_stop(info);
1524
1525 /* TODO:disable interrupts instead of reset to preserve signal states */
1526 reset_device(info);
1527
1528 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1529 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1530 set_signals(info);
1531 }
1532
1533 spin_unlock_irqrestore(&info->lock,flags);
1534
1535 release_resources(info);
1536
1537 if (info->tty)
1538 set_bit(TTY_IO_ERROR, &info->tty->flags);
1539
1540 info->flags &= ~ASYNC_INITIALIZED;
1541 }
1542
1543 static void mgslpc_program_hw(MGSLPC_INFO *info)
1544 {
1545 unsigned long flags;
1546
1547 spin_lock_irqsave(&info->lock,flags);
1548
1549 rx_stop(info);
1550 tx_stop(info);
1551 info->tx_count = info->tx_put = info->tx_get = 0;
1552
1553 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1554 hdlc_mode(info);
1555 else
1556 async_mode(info);
1557
1558 set_signals(info);
1559
1560 info->dcd_chkcount = 0;
1561 info->cts_chkcount = 0;
1562 info->ri_chkcount = 0;
1563 info->dsr_chkcount = 0;
1564
1565 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1566 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1567 get_signals(info);
1568
1569 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1570 rx_start(info);
1571
1572 spin_unlock_irqrestore(&info->lock,flags);
1573 }
1574
1575 /* Reconfigure adapter based on new parameters
1576 */
1577 static void mgslpc_change_params(MGSLPC_INFO *info)
1578 {
1579 unsigned cflag;
1580 int bits_per_char;
1581
1582 if (!info->tty || !info->tty->termios)
1583 return;
1584
1585 if (debug_level >= DEBUG_LEVEL_INFO)
1586 printk("%s(%d):mgslpc_change_params(%s)\n",
1587 __FILE__,__LINE__, info->device_name );
1588
1589 cflag = info->tty->termios->c_cflag;
1590
1591 /* if B0 rate (hangup) specified then negate DTR and RTS */
1592 /* otherwise assert DTR and RTS */
1593 if (cflag & CBAUD)
1594 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1595 else
1596 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1597
1598 /* byte size and parity */
1599
1600 switch (cflag & CSIZE) {
1601 case CS5: info->params.data_bits = 5; break;
1602 case CS6: info->params.data_bits = 6; break;
1603 case CS7: info->params.data_bits = 7; break;
1604 case CS8: info->params.data_bits = 8; break;
1605 default: info->params.data_bits = 7; break;
1606 }
1607
1608 if (cflag & CSTOPB)
1609 info->params.stop_bits = 2;
1610 else
1611 info->params.stop_bits = 1;
1612
1613 info->params.parity = ASYNC_PARITY_NONE;
1614 if (cflag & PARENB) {
1615 if (cflag & PARODD)
1616 info->params.parity = ASYNC_PARITY_ODD;
1617 else
1618 info->params.parity = ASYNC_PARITY_EVEN;
1619 #ifdef CMSPAR
1620 if (cflag & CMSPAR)
1621 info->params.parity = ASYNC_PARITY_SPACE;
1622 #endif
1623 }
1624
1625 /* calculate number of jiffies to transmit a full
1626 * FIFO (32 bytes) at specified data rate
1627 */
1628 bits_per_char = info->params.data_bits +
1629 info->params.stop_bits + 1;
1630
1631 /* if port data rate is set to 460800 or less then
1632 * allow tty settings to override, otherwise keep the
1633 * current data rate.
1634 */
1635 if (info->params.data_rate <= 460800) {
1636 info->params.data_rate = tty_get_baud_rate(info->tty);
1637 }
1638
1639 if ( info->params.data_rate ) {
1640 info->timeout = (32*HZ*bits_per_char) /
1641 info->params.data_rate;
1642 }
1643 info->timeout += HZ/50; /* Add .02 seconds of slop */
1644
1645 if (cflag & CRTSCTS)
1646 info->flags |= ASYNC_CTS_FLOW;
1647 else
1648 info->flags &= ~ASYNC_CTS_FLOW;
1649
1650 if (cflag & CLOCAL)
1651 info->flags &= ~ASYNC_CHECK_CD;
1652 else
1653 info->flags |= ASYNC_CHECK_CD;
1654
1655 /* process tty input control flags */
1656
1657 info->read_status_mask = 0;
1658 if (I_INPCK(info->tty))
1659 info->read_status_mask |= BIT7 | BIT6;
1660 if (I_IGNPAR(info->tty))
1661 info->ignore_status_mask |= BIT7 | BIT6;
1662
1663 mgslpc_program_hw(info);
1664 }
1665
1666 /* Add a character to the transmit buffer
1667 */
1668 static void mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1669 {
1670 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1671 unsigned long flags;
1672
1673 if (debug_level >= DEBUG_LEVEL_INFO) {
1674 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1675 __FILE__,__LINE__,ch,info->device_name);
1676 }
1677
1678 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
1679 return;
1680
1681 if (!tty || !info->tx_buf)
1682 return;
1683
1684 spin_lock_irqsave(&info->lock,flags);
1685
1686 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1687 if (info->tx_count < TXBUFSIZE - 1) {
1688 info->tx_buf[info->tx_put++] = ch;
1689 info->tx_put &= TXBUFSIZE-1;
1690 info->tx_count++;
1691 }
1692 }
1693
1694 spin_unlock_irqrestore(&info->lock,flags);
1695 }
1696
1697 /* Enable transmitter so remaining characters in the
1698 * transmit buffer are sent.
1699 */
1700 static void mgslpc_flush_chars(struct tty_struct *tty)
1701 {
1702 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1703 unsigned long flags;
1704
1705 if (debug_level >= DEBUG_LEVEL_INFO)
1706 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1707 __FILE__,__LINE__,info->device_name,info->tx_count);
1708
1709 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1710 return;
1711
1712 if (info->tx_count <= 0 || tty->stopped ||
1713 tty->hw_stopped || !info->tx_buf)
1714 return;
1715
1716 if (debug_level >= DEBUG_LEVEL_INFO)
1717 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1718 __FILE__,__LINE__,info->device_name);
1719
1720 spin_lock_irqsave(&info->lock,flags);
1721 if (!info->tx_active)
1722 tx_start(info);
1723 spin_unlock_irqrestore(&info->lock,flags);
1724 }
1725
1726 /* Send a block of data
1727 *
1728 * Arguments:
1729 *
1730 * tty pointer to tty information structure
1731 * buf pointer to buffer containing send data
1732 * count size of send data in bytes
1733 *
1734 * Returns: number of characters written
1735 */
1736 static int mgslpc_write(struct tty_struct * tty,
1737 const unsigned char *buf, int count)
1738 {
1739 int c, ret = 0;
1740 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1741 unsigned long flags;
1742
1743 if (debug_level >= DEBUG_LEVEL_INFO)
1744 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1745 __FILE__,__LINE__,info->device_name,count);
1746
1747 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
1748 !tty || !info->tx_buf)
1749 goto cleanup;
1750
1751 if (info->params.mode == MGSL_MODE_HDLC) {
1752 if (count > TXBUFSIZE) {
1753 ret = -EIO;
1754 goto cleanup;
1755 }
1756 if (info->tx_active)
1757 goto cleanup;
1758 else if (info->tx_count)
1759 goto start;
1760 }
1761
1762 for (;;) {
1763 c = min(count,
1764 min(TXBUFSIZE - info->tx_count - 1,
1765 TXBUFSIZE - info->tx_put));
1766 if (c <= 0)
1767 break;
1768
1769 memcpy(info->tx_buf + info->tx_put, buf, c);
1770
1771 spin_lock_irqsave(&info->lock,flags);
1772 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1773 info->tx_count += c;
1774 spin_unlock_irqrestore(&info->lock,flags);
1775
1776 buf += c;
1777 count -= c;
1778 ret += c;
1779 }
1780 start:
1781 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1782 spin_lock_irqsave(&info->lock,flags);
1783 if (!info->tx_active)
1784 tx_start(info);
1785 spin_unlock_irqrestore(&info->lock,flags);
1786 }
1787 cleanup:
1788 if (debug_level >= DEBUG_LEVEL_INFO)
1789 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1790 __FILE__,__LINE__,info->device_name,ret);
1791 return ret;
1792 }
1793
1794 /* Return the count of free bytes in transmit buffer
1795 */
1796 static int mgslpc_write_room(struct tty_struct *tty)
1797 {
1798 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1799 int ret;
1800
1801 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1802 return 0;
1803
1804 if (info->params.mode == MGSL_MODE_HDLC) {
1805 /* HDLC (frame oriented) mode */
1806 if (info->tx_active)
1807 return 0;
1808 else
1809 return HDLC_MAX_FRAME_SIZE;
1810 } else {
1811 ret = TXBUFSIZE - info->tx_count - 1;
1812 if (ret < 0)
1813 ret = 0;
1814 }
1815
1816 if (debug_level >= DEBUG_LEVEL_INFO)
1817 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1818 __FILE__,__LINE__, info->device_name, ret);
1819 return ret;
1820 }
1821
1822 /* Return the count of bytes in transmit buffer
1823 */
1824 static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1825 {
1826 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1827 int rc;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1831 __FILE__,__LINE__, info->device_name );
1832
1833 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1834 return 0;
1835
1836 if (info->params.mode == MGSL_MODE_HDLC)
1837 rc = info->tx_active ? info->max_frame_size : 0;
1838 else
1839 rc = info->tx_count;
1840
1841 if (debug_level >= DEBUG_LEVEL_INFO)
1842 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1843 __FILE__,__LINE__, info->device_name, rc);
1844
1845 return rc;
1846 }
1847
1848 /* Discard all data in the send buffer
1849 */
1850 static void mgslpc_flush_buffer(struct tty_struct *tty)
1851 {
1852 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1853 unsigned long flags;
1854
1855 if (debug_level >= DEBUG_LEVEL_INFO)
1856 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1857 __FILE__,__LINE__, info->device_name );
1858
1859 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1860 return;
1861
1862 spin_lock_irqsave(&info->lock,flags);
1863 info->tx_count = info->tx_put = info->tx_get = 0;
1864 del_timer(&info->tx_timer);
1865 spin_unlock_irqrestore(&info->lock,flags);
1866
1867 wake_up_interruptible(&tty->write_wait);
1868 tty_wakeup(tty);
1869 }
1870
1871 /* Send a high-priority XON/XOFF character
1872 */
1873 static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1874 {
1875 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1876 unsigned long flags;
1877
1878 if (debug_level >= DEBUG_LEVEL_INFO)
1879 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1880 __FILE__,__LINE__, info->device_name, ch );
1881
1882 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1883 return;
1884
1885 info->x_char = ch;
1886 if (ch) {
1887 spin_lock_irqsave(&info->lock,flags);
1888 if (!info->tx_enabled)
1889 tx_start(info);
1890 spin_unlock_irqrestore(&info->lock,flags);
1891 }
1892 }
1893
1894 /* Signal remote device to throttle send data (our receive data)
1895 */
1896 static void mgslpc_throttle(struct tty_struct * tty)
1897 {
1898 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1899 unsigned long flags;
1900
1901 if (debug_level >= DEBUG_LEVEL_INFO)
1902 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1903 __FILE__,__LINE__, info->device_name );
1904
1905 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1906 return;
1907
1908 if (I_IXOFF(tty))
1909 mgslpc_send_xchar(tty, STOP_CHAR(tty));
1910
1911 if (tty->termios->c_cflag & CRTSCTS) {
1912 spin_lock_irqsave(&info->lock,flags);
1913 info->serial_signals &= ~SerialSignal_RTS;
1914 set_signals(info);
1915 spin_unlock_irqrestore(&info->lock,flags);
1916 }
1917 }
1918
1919 /* Signal remote device to stop throttling send data (our receive data)
1920 */
1921 static void mgslpc_unthrottle(struct tty_struct * tty)
1922 {
1923 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1924 unsigned long flags;
1925
1926 if (debug_level >= DEBUG_LEVEL_INFO)
1927 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1928 __FILE__,__LINE__, info->device_name );
1929
1930 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1931 return;
1932
1933 if (I_IXOFF(tty)) {
1934 if (info->x_char)
1935 info->x_char = 0;
1936 else
1937 mgslpc_send_xchar(tty, START_CHAR(tty));
1938 }
1939
1940 if (tty->termios->c_cflag & CRTSCTS) {
1941 spin_lock_irqsave(&info->lock,flags);
1942 info->serial_signals |= SerialSignal_RTS;
1943 set_signals(info);
1944 spin_unlock_irqrestore(&info->lock,flags);
1945 }
1946 }
1947
1948 /* get the current serial statistics
1949 */
1950 static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1951 {
1952 int err;
1953 if (debug_level >= DEBUG_LEVEL_INFO)
1954 printk("get_params(%s)\n", info->device_name);
1955 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
1956 if (err)
1957 return -EFAULT;
1958 return 0;
1959 }
1960
1961 /* get the current serial parameters
1962 */
1963 static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1964 {
1965 int err;
1966 if (debug_level >= DEBUG_LEVEL_INFO)
1967 printk("get_params(%s)\n", info->device_name);
1968 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1969 if (err)
1970 return -EFAULT;
1971 return 0;
1972 }
1973
1974 /* set the serial parameters
1975 *
1976 * Arguments:
1977 *
1978 * info pointer to device instance data
1979 * new_params user buffer containing new serial params
1980 *
1981 * Returns: 0 if success, otherwise error code
1982 */
1983 static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params)
1984 {
1985 unsigned long flags;
1986 MGSL_PARAMS tmp_params;
1987 int err;
1988
1989 if (debug_level >= DEBUG_LEVEL_INFO)
1990 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1991 info->device_name );
1992 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1993 if (err) {
1994 if ( debug_level >= DEBUG_LEVEL_INFO )
1995 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1996 __FILE__,__LINE__,info->device_name);
1997 return -EFAULT;
1998 }
1999
2000 spin_lock_irqsave(&info->lock,flags);
2001 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2002 spin_unlock_irqrestore(&info->lock,flags);
2003
2004 mgslpc_change_params(info);
2005
2006 return 0;
2007 }
2008
2009 static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
2010 {
2011 int err;
2012 if (debug_level >= DEBUG_LEVEL_INFO)
2013 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
2014 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2015 if (err)
2016 return -EFAULT;
2017 return 0;
2018 }
2019
2020 static int set_txidle(MGSLPC_INFO * info, int idle_mode)
2021 {
2022 unsigned long flags;
2023 if (debug_level >= DEBUG_LEVEL_INFO)
2024 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
2025 spin_lock_irqsave(&info->lock,flags);
2026 info->idle_mode = idle_mode;
2027 tx_set_idle(info);
2028 spin_unlock_irqrestore(&info->lock,flags);
2029 return 0;
2030 }
2031
2032 static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
2033 {
2034 int err;
2035 if (debug_level >= DEBUG_LEVEL_INFO)
2036 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
2037 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
2038 if (err)
2039 return -EFAULT;
2040 return 0;
2041 }
2042
2043 static int set_interface(MGSLPC_INFO * info, int if_mode)
2044 {
2045 unsigned long flags;
2046 unsigned char val;
2047 if (debug_level >= DEBUG_LEVEL_INFO)
2048 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
2049 spin_lock_irqsave(&info->lock,flags);
2050 info->if_mode = if_mode;
2051
2052 val = read_reg(info, PVR) & 0x0f;
2053 switch (info->if_mode)
2054 {
2055 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
2056 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
2057 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
2058 }
2059 write_reg(info, PVR, val);
2060
2061 spin_unlock_irqrestore(&info->lock,flags);
2062 return 0;
2063 }
2064
2065 static int set_txenable(MGSLPC_INFO * info, int enable)
2066 {
2067 unsigned long flags;
2068
2069 if (debug_level >= DEBUG_LEVEL_INFO)
2070 printk("set_txenable(%s,%d)\n", info->device_name, enable);
2071
2072 spin_lock_irqsave(&info->lock,flags);
2073 if (enable) {
2074 if (!info->tx_enabled)
2075 tx_start(info);
2076 } else {
2077 if (info->tx_enabled)
2078 tx_stop(info);
2079 }
2080 spin_unlock_irqrestore(&info->lock,flags);
2081 return 0;
2082 }
2083
2084 static int tx_abort(MGSLPC_INFO * info)
2085 {
2086 unsigned long flags;
2087
2088 if (debug_level >= DEBUG_LEVEL_INFO)
2089 printk("tx_abort(%s)\n", info->device_name);
2090
2091 spin_lock_irqsave(&info->lock,flags);
2092 if (info->tx_active && info->tx_count &&
2093 info->params.mode == MGSL_MODE_HDLC) {
2094 /* clear data count so FIFO is not filled on next IRQ.
2095 * This results in underrun and abort transmission.
2096 */
2097 info->tx_count = info->tx_put = info->tx_get = 0;
2098 info->tx_aborting = TRUE;
2099 }
2100 spin_unlock_irqrestore(&info->lock,flags);
2101 return 0;
2102 }
2103
2104 static int set_rxenable(MGSLPC_INFO * info, int enable)
2105 {
2106 unsigned long flags;
2107
2108 if (debug_level >= DEBUG_LEVEL_INFO)
2109 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
2110
2111 spin_lock_irqsave(&info->lock,flags);
2112 if (enable) {
2113 if (!info->rx_enabled)
2114 rx_start(info);
2115 } else {
2116 if (info->rx_enabled)
2117 rx_stop(info);
2118 }
2119 spin_unlock_irqrestore(&info->lock,flags);
2120 return 0;
2121 }
2122
2123 /* wait for specified event to occur
2124 *
2125 * Arguments: info pointer to device instance data
2126 * mask pointer to bitmask of events to wait for
2127 * Return Value: 0 if successful and bit mask updated with
2128 * of events triggerred,
2129 * otherwise error code
2130 */
2131 static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
2132 {
2133 unsigned long flags;
2134 int s;
2135 int rc=0;
2136 struct mgsl_icount cprev, cnow;
2137 int events;
2138 int mask;
2139 struct _input_signal_events oldsigs, newsigs;
2140 DECLARE_WAITQUEUE(wait, current);
2141
2142 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2143 if (rc)
2144 return -EFAULT;
2145
2146 if (debug_level >= DEBUG_LEVEL_INFO)
2147 printk("wait_events(%s,%d)\n", info->device_name, mask);
2148
2149 spin_lock_irqsave(&info->lock,flags);
2150
2151 /* return immediately if state matches requested events */
2152 get_signals(info);
2153 s = info->serial_signals;
2154 events = mask &
2155 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2156 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2157 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2158 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2159 if (events) {
2160 spin_unlock_irqrestore(&info->lock,flags);
2161 goto exit;
2162 }
2163
2164 /* save current irq counts */
2165 cprev = info->icount;
2166 oldsigs = info->input_signal_events;
2167
2168 if ((info->params.mode == MGSL_MODE_HDLC) &&
2169 (mask & MgslEvent_ExitHuntMode))
2170 irq_enable(info, CHA, IRQ_EXITHUNT);
2171
2172 set_current_state(TASK_INTERRUPTIBLE);
2173 add_wait_queue(&info->event_wait_q, &wait);
2174
2175 spin_unlock_irqrestore(&info->lock,flags);
2176
2177
2178 for(;;) {
2179 schedule();
2180 if (signal_pending(current)) {
2181 rc = -ERESTARTSYS;
2182 break;
2183 }
2184
2185 /* get current irq counts */
2186 spin_lock_irqsave(&info->lock,flags);
2187 cnow = info->icount;
2188 newsigs = info->input_signal_events;
2189 set_current_state(TASK_INTERRUPTIBLE);
2190 spin_unlock_irqrestore(&info->lock,flags);
2191
2192 /* if no change, wait aborted for some reason */
2193 if (newsigs.dsr_up == oldsigs.dsr_up &&
2194 newsigs.dsr_down == oldsigs.dsr_down &&
2195 newsigs.dcd_up == oldsigs.dcd_up &&
2196 newsigs.dcd_down == oldsigs.dcd_down &&
2197 newsigs.cts_up == oldsigs.cts_up &&
2198 newsigs.cts_down == oldsigs.cts_down &&
2199 newsigs.ri_up == oldsigs.ri_up &&
2200 newsigs.ri_down == oldsigs.ri_down &&
2201 cnow.exithunt == cprev.exithunt &&
2202 cnow.rxidle == cprev.rxidle) {
2203 rc = -EIO;
2204 break;
2205 }
2206
2207 events = mask &
2208 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2209 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2210 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2211 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2212 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2213 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2214 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2215 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2216 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2217 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2218 if (events)
2219 break;
2220
2221 cprev = cnow;
2222 oldsigs = newsigs;
2223 }
2224
2225 remove_wait_queue(&info->event_wait_q, &wait);
2226 set_current_state(TASK_RUNNING);
2227
2228 if (mask & MgslEvent_ExitHuntMode) {
2229 spin_lock_irqsave(&info->lock,flags);
2230 if (!waitqueue_active(&info->event_wait_q))
2231 irq_disable(info, CHA, IRQ_EXITHUNT);
2232 spin_unlock_irqrestore(&info->lock,flags);
2233 }
2234 exit:
2235 if (rc == 0)
2236 PUT_USER(rc, events, mask_ptr);
2237 return rc;
2238 }
2239
2240 static int modem_input_wait(MGSLPC_INFO *info,int arg)
2241 {
2242 unsigned long flags;
2243 int rc;
2244 struct mgsl_icount cprev, cnow;
2245 DECLARE_WAITQUEUE(wait, current);
2246
2247 /* save current irq counts */
2248 spin_lock_irqsave(&info->lock,flags);
2249 cprev = info->icount;
2250 add_wait_queue(&info->status_event_wait_q, &wait);
2251 set_current_state(TASK_INTERRUPTIBLE);
2252 spin_unlock_irqrestore(&info->lock,flags);
2253
2254 for(;;) {
2255 schedule();
2256 if (signal_pending(current)) {
2257 rc = -ERESTARTSYS;
2258 break;
2259 }
2260
2261 /* get new irq counts */
2262 spin_lock_irqsave(&info->lock,flags);
2263 cnow = info->icount;
2264 set_current_state(TASK_INTERRUPTIBLE);
2265 spin_unlock_irqrestore(&info->lock,flags);
2266
2267 /* if no change, wait aborted for some reason */
2268 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2269 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2270 rc = -EIO;
2271 break;
2272 }
2273
2274 /* check for change in caller specified modem input */
2275 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2276 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2277 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2278 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2279 rc = 0;
2280 break;
2281 }
2282
2283 cprev = cnow;
2284 }
2285 remove_wait_queue(&info->status_event_wait_q, &wait);
2286 set_current_state(TASK_RUNNING);
2287 return rc;
2288 }
2289
2290 /* return the state of the serial control and status signals
2291 */
2292 static int tiocmget(struct tty_struct *tty, struct file *file)
2293 {
2294 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2295 unsigned int result;
2296 unsigned long flags;
2297
2298 spin_lock_irqsave(&info->lock,flags);
2299 get_signals(info);
2300 spin_unlock_irqrestore(&info->lock,flags);
2301
2302 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2303 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2304 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2305 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2306 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2307 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2308
2309 if (debug_level >= DEBUG_LEVEL_INFO)
2310 printk("%s(%d):%s tiocmget() value=%08X\n",
2311 __FILE__,__LINE__, info->device_name, result );
2312 return result;
2313 }
2314
2315 /* set modem control signals (DTR/RTS)
2316 */
2317 static int tiocmset(struct tty_struct *tty, struct file *file,
2318 unsigned int set, unsigned int clear)
2319 {
2320 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2321 unsigned long flags;
2322
2323 if (debug_level >= DEBUG_LEVEL_INFO)
2324 printk("%s(%d):%s tiocmset(%x,%x)\n",
2325 __FILE__,__LINE__,info->device_name, set, clear);
2326
2327 if (set & TIOCM_RTS)
2328 info->serial_signals |= SerialSignal_RTS;
2329 if (set & TIOCM_DTR)
2330 info->serial_signals |= SerialSignal_DTR;
2331 if (clear & TIOCM_RTS)
2332 info->serial_signals &= ~SerialSignal_RTS;
2333 if (clear & TIOCM_DTR)
2334 info->serial_signals &= ~SerialSignal_DTR;
2335
2336 spin_lock_irqsave(&info->lock,flags);
2337 set_signals(info);
2338 spin_unlock_irqrestore(&info->lock,flags);
2339
2340 return 0;
2341 }
2342
2343 /* Set or clear transmit break condition
2344 *
2345 * Arguments: tty pointer to tty instance data
2346 * break_state -1=set break condition, 0=clear
2347 */
2348 static void mgslpc_break(struct tty_struct *tty, int break_state)
2349 {
2350 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2351 unsigned long flags;
2352
2353 if (debug_level >= DEBUG_LEVEL_INFO)
2354 printk("%s(%d):mgslpc_break(%s,%d)\n",
2355 __FILE__,__LINE__, info->device_name, break_state);
2356
2357 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
2358 return;
2359
2360 spin_lock_irqsave(&info->lock,flags);
2361 if (break_state == -1)
2362 set_reg_bits(info, CHA+DAFO, BIT6);
2363 else
2364 clear_reg_bits(info, CHA+DAFO, BIT6);
2365 spin_unlock_irqrestore(&info->lock,flags);
2366 }
2367
2368 /* Service an IOCTL request
2369 *
2370 * Arguments:
2371 *
2372 * tty pointer to tty instance data
2373 * file pointer to associated file object for device
2374 * cmd IOCTL command code
2375 * arg command argument/context
2376 *
2377 * Return Value: 0 if success, otherwise error code
2378 */
2379 static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
2380 unsigned int cmd, unsigned long arg)
2381 {
2382 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2383
2384 if (debug_level >= DEBUG_LEVEL_INFO)
2385 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2386 info->device_name, cmd );
2387
2388 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2389 return -ENODEV;
2390
2391 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2392 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2393 if (tty->flags & (1 << TTY_IO_ERROR))
2394 return -EIO;
2395 }
2396
2397 return ioctl_common(info, cmd, arg);
2398 }
2399
2400 int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg)
2401 {
2402 int error;
2403 struct mgsl_icount cnow; /* kernel counter temps */
2404 struct serial_icounter_struct __user *p_cuser; /* user space */
2405 void __user *argp = (void __user *)arg;
2406 unsigned long flags;
2407
2408 switch (cmd) {
2409 case MGSL_IOCGPARAMS:
2410 return get_params(info, argp);
2411 case MGSL_IOCSPARAMS:
2412 return set_params(info, argp);
2413 case MGSL_IOCGTXIDLE:
2414 return get_txidle(info, argp);
2415 case MGSL_IOCSTXIDLE:
2416 return set_txidle(info, (int)arg);
2417 case MGSL_IOCGIF:
2418 return get_interface(info, argp);
2419 case MGSL_IOCSIF:
2420 return set_interface(info,(int)arg);
2421 case MGSL_IOCTXENABLE:
2422 return set_txenable(info,(int)arg);
2423 case MGSL_IOCRXENABLE:
2424 return set_rxenable(info,(int)arg);
2425 case MGSL_IOCTXABORT:
2426 return tx_abort(info);
2427 case MGSL_IOCGSTATS:
2428 return get_stats(info, argp);
2429 case MGSL_IOCWAITEVENT:
2430 return wait_events(info, argp);
2431 case TIOCMIWAIT:
2432 return modem_input_wait(info,(int)arg);
2433 case TIOCGICOUNT:
2434 spin_lock_irqsave(&info->lock,flags);
2435 cnow = info->icount;
2436 spin_unlock_irqrestore(&info->lock,flags);
2437 p_cuser = argp;
2438 PUT_USER(error,cnow.cts, &p_cuser->cts);
2439 if (error) return error;
2440 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
2441 if (error) return error;
2442 PUT_USER(error,cnow.rng, &p_cuser->rng);
2443 if (error) return error;
2444 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
2445 if (error) return error;
2446 PUT_USER(error,cnow.rx, &p_cuser->rx);
2447 if (error) return error;
2448 PUT_USER(error,cnow.tx, &p_cuser->tx);
2449 if (error) return error;
2450 PUT_USER(error,cnow.frame, &p_cuser->frame);
2451 if (error) return error;
2452 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
2453 if (error) return error;
2454 PUT_USER(error,cnow.parity, &p_cuser->parity);
2455 if (error) return error;
2456 PUT_USER(error,cnow.brk, &p_cuser->brk);
2457 if (error) return error;
2458 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
2459 if (error) return error;
2460 return 0;
2461 default:
2462 return -ENOIOCTLCMD;
2463 }
2464 return 0;
2465 }
2466
2467 /* Set new termios settings
2468 *
2469 * Arguments:
2470 *
2471 * tty pointer to tty structure
2472 * termios pointer to buffer to hold returned old termios
2473 */
2474 static void mgslpc_set_termios(struct tty_struct *tty, struct termios *old_termios)
2475 {
2476 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2477 unsigned long flags;
2478
2479 if (debug_level >= DEBUG_LEVEL_INFO)
2480 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2481 tty->driver->name );
2482
2483 /* just return if nothing has changed */
2484 if ((tty->termios->c_cflag == old_termios->c_cflag)
2485 && (RELEVANT_IFLAG(tty->termios->c_iflag)
2486 == RELEVANT_IFLAG(old_termios->c_iflag)))
2487 return;
2488
2489 mgslpc_change_params(info);
2490
2491 /* Handle transition to B0 status */
2492 if (old_termios->c_cflag & CBAUD &&
2493 !(tty->termios->c_cflag & CBAUD)) {
2494 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2495 spin_lock_irqsave(&info->lock,flags);
2496 set_signals(info);
2497 spin_unlock_irqrestore(&info->lock,flags);
2498 }
2499
2500 /* Handle transition away from B0 status */
2501 if (!(old_termios->c_cflag & CBAUD) &&
2502 tty->termios->c_cflag & CBAUD) {
2503 info->serial_signals |= SerialSignal_DTR;
2504 if (!(tty->termios->c_cflag & CRTSCTS) ||
2505 !test_bit(TTY_THROTTLED, &tty->flags)) {
2506 info->serial_signals |= SerialSignal_RTS;
2507 }
2508 spin_lock_irqsave(&info->lock,flags);
2509 set_signals(info);
2510 spin_unlock_irqrestore(&info->lock,flags);
2511 }
2512
2513 /* Handle turning off CRTSCTS */
2514 if (old_termios->c_cflag & CRTSCTS &&
2515 !(tty->termios->c_cflag & CRTSCTS)) {
2516 tty->hw_stopped = 0;
2517 tx_release(tty);
2518 }
2519 }
2520
2521 static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2522 {
2523 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2524
2525 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2526 return;
2527
2528 if (debug_level >= DEBUG_LEVEL_INFO)
2529 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
2530 __FILE__,__LINE__, info->device_name, info->count);
2531
2532 if (!info->count)
2533 return;
2534
2535 if (tty_hung_up_p(filp))
2536 goto cleanup;
2537
2538 if ((tty->count == 1) && (info->count != 1)) {
2539 /*
2540 * tty->count is 1 and the tty structure will be freed.
2541 * info->count should be one in this case.
2542 * if it's not, correct it so that the port is shutdown.
2543 */
2544 printk("mgslpc_close: bad refcount; tty->count is 1, "
2545 "info->count is %d\n", info->count);
2546 info->count = 1;
2547 }
2548
2549 info->count--;
2550
2551 /* if at least one open remaining, leave hardware active */
2552 if (info->count)
2553 goto cleanup;
2554
2555 info->flags |= ASYNC_CLOSING;
2556
2557 /* set tty->closing to notify line discipline to
2558 * only process XON/XOFF characters. Only the N_TTY
2559 * discipline appears to use this (ppp does not).
2560 */
2561 tty->closing = 1;
2562
2563 /* wait for transmit data to clear all layers */
2564
2565 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
2566 if (debug_level >= DEBUG_LEVEL_INFO)
2567 printk("%s(%d):mgslpc_close(%s) calling tty_wait_until_sent\n",
2568 __FILE__,__LINE__, info->device_name );
2569 tty_wait_until_sent(tty, info->closing_wait);
2570 }
2571
2572 if (info->flags & ASYNC_INITIALIZED)
2573 mgslpc_wait_until_sent(tty, info->timeout);
2574
2575 if (tty->driver->flush_buffer)
2576 tty->driver->flush_buffer(tty);
2577
2578 ldisc_flush_buffer(tty);
2579
2580 shutdown(info);
2581
2582 tty->closing = 0;
2583 info->tty = NULL;
2584
2585 if (info->blocked_open) {
2586 if (info->close_delay) {
2587 msleep_interruptible(jiffies_to_msecs(info->close_delay));
2588 }
2589 wake_up_interruptible(&info->open_wait);
2590 }
2591
2592 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
2593
2594 wake_up_interruptible(&info->close_wait);
2595
2596 cleanup:
2597 if (debug_level >= DEBUG_LEVEL_INFO)
2598 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
2599 tty->driver->name, info->count);
2600 }
2601
2602 /* Wait until the transmitter is empty.
2603 */
2604 static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2605 {
2606 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2607 unsigned long orig_jiffies, char_time;
2608
2609 if (!info )
2610 return;
2611
2612 if (debug_level >= DEBUG_LEVEL_INFO)
2613 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2614 __FILE__,__LINE__, info->device_name );
2615
2616 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2617 return;
2618
2619 if (!(info->flags & ASYNC_INITIALIZED))
2620 goto exit;
2621
2622 orig_jiffies = jiffies;
2623
2624 /* Set check interval to 1/5 of estimated time to
2625 * send a character, and make it at least 1. The check
2626 * interval should also be less than the timeout.
2627 * Note: use tight timings here to satisfy the NIST-PCTS.
2628 */
2629
2630 if ( info->params.data_rate ) {
2631 char_time = info->timeout/(32 * 5);
2632 if (!char_time)
2633 char_time++;
2634 } else
2635 char_time = 1;
2636
2637 if (timeout)
2638 char_time = min_t(unsigned long, char_time, timeout);
2639
2640 if (info->params.mode == MGSL_MODE_HDLC) {
2641 while (info->tx_active) {
2642 msleep_interruptible(jiffies_to_msecs(char_time));
2643 if (signal_pending(current))
2644 break;
2645 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2646 break;
2647 }
2648 } else {
2649 while ((info->tx_count || info->tx_active) &&
2650 info->tx_enabled) {
2651 msleep_interruptible(jiffies_to_msecs(char_time));
2652 if (signal_pending(current))
2653 break;
2654 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2655 break;
2656 }
2657 }
2658
2659 exit:
2660 if (debug_level >= DEBUG_LEVEL_INFO)
2661 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2662 __FILE__,__LINE__, info->device_name );
2663 }
2664
2665 /* Called by tty_hangup() when a hangup is signaled.
2666 * This is the same as closing all open files for the port.
2667 */
2668 static void mgslpc_hangup(struct tty_struct *tty)
2669 {
2670 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2671
2672 if (debug_level >= DEBUG_LEVEL_INFO)
2673 printk("%s(%d):mgslpc_hangup(%s)\n",
2674 __FILE__,__LINE__, info->device_name );
2675
2676 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2677 return;
2678
2679 mgslpc_flush_buffer(tty);
2680 shutdown(info);
2681
2682 info->count = 0;
2683 info->flags &= ~ASYNC_NORMAL_ACTIVE;
2684 info->tty = NULL;
2685
2686 wake_up_interruptible(&info->open_wait);
2687 }
2688
2689 /* Block the current process until the specified port
2690 * is ready to be opened.
2691 */
2692 static int block_til_ready(struct tty_struct *tty, struct file *filp,
2693 MGSLPC_INFO *info)
2694 {
2695 DECLARE_WAITQUEUE(wait, current);
2696 int retval;
2697 int do_clocal = 0, extra_count = 0;
2698 unsigned long flags;
2699
2700 if (debug_level >= DEBUG_LEVEL_INFO)
2701 printk("%s(%d):block_til_ready on %s\n",
2702 __FILE__,__LINE__, tty->driver->name );
2703
2704 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
2705 /* nonblock mode is set or port is not enabled */
2706 /* just verify that callout device is not active */
2707 info->flags |= ASYNC_NORMAL_ACTIVE;
2708 return 0;
2709 }
2710
2711 if (tty->termios->c_cflag & CLOCAL)
2712 do_clocal = 1;
2713
2714 /* Wait for carrier detect and the line to become
2715 * free (i.e., not in use by the callout). While we are in
2716 * this loop, info->count is dropped by one, so that
2717 * mgslpc_close() knows when to free things. We restore it upon
2718 * exit, either normal or abnormal.
2719 */
2720
2721 retval = 0;
2722 add_wait_queue(&info->open_wait, &wait);
2723
2724 if (debug_level >= DEBUG_LEVEL_INFO)
2725 printk("%s(%d):block_til_ready before block on %s count=%d\n",
2726 __FILE__,__LINE__, tty->driver->name, info->count );
2727
2728 spin_lock_irqsave(&info->lock, flags);
2729 if (!tty_hung_up_p(filp)) {
2730 extra_count = 1;
2731 info->count--;
2732 }
2733 spin_unlock_irqrestore(&info->lock, flags);
2734 info->blocked_open++;
2735
2736 while (1) {
2737 if ((tty->termios->c_cflag & CBAUD)) {
2738 spin_lock_irqsave(&info->lock,flags);
2739 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2740 set_signals(info);
2741 spin_unlock_irqrestore(&info->lock,flags);
2742 }
2743
2744 set_current_state(TASK_INTERRUPTIBLE);
2745
2746 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
2747 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
2748 -EAGAIN : -ERESTARTSYS;
2749 break;
2750 }
2751
2752 spin_lock_irqsave(&info->lock,flags);
2753 get_signals(info);
2754 spin_unlock_irqrestore(&info->lock,flags);
2755
2756 if (!(info->flags & ASYNC_CLOSING) &&
2757 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
2758 break;
2759 }
2760
2761 if (signal_pending(current)) {
2762 retval = -ERESTARTSYS;
2763 break;
2764 }
2765
2766 if (debug_level >= DEBUG_LEVEL_INFO)
2767 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
2768 __FILE__,__LINE__, tty->driver->name, info->count );
2769
2770 schedule();
2771 }
2772
2773 set_current_state(TASK_RUNNING);
2774 remove_wait_queue(&info->open_wait, &wait);
2775
2776 if (extra_count)
2777 info->count++;
2778 info->blocked_open--;
2779
2780 if (debug_level >= DEBUG_LEVEL_INFO)
2781 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
2782 __FILE__,__LINE__, tty->driver->name, info->count );
2783
2784 if (!retval)
2785 info->flags |= ASYNC_NORMAL_ACTIVE;
2786
2787 return retval;
2788 }
2789
2790 static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2791 {
2792 MGSLPC_INFO *info;
2793 int retval, line;
2794 unsigned long flags;
2795
2796 /* verify range of specified line number */
2797 line = tty->index;
2798 if ((line < 0) || (line >= mgslpc_device_count)) {
2799 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2800 __FILE__,__LINE__,line);
2801 return -ENODEV;
2802 }
2803
2804 /* find the info structure for the specified line */
2805 info = mgslpc_device_list;
2806 while(info && info->line != line)
2807 info = info->next_device;
2808 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2809 return -ENODEV;
2810
2811 tty->driver_data = info;
2812 info->tty = tty;
2813
2814 if (debug_level >= DEBUG_LEVEL_INFO)
2815 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
2816 __FILE__,__LINE__,tty->driver->name, info->count);
2817
2818 /* If port is closing, signal caller to try again */
2819 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
2820 if (info->flags & ASYNC_CLOSING)
2821 interruptible_sleep_on(&info->close_wait);
2822 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
2823 -EAGAIN : -ERESTARTSYS);
2824 goto cleanup;
2825 }
2826
2827 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
2828
2829 spin_lock_irqsave(&info->netlock, flags);
2830 if (info->netcount) {
2831 retval = -EBUSY;
2832 spin_unlock_irqrestore(&info->netlock, flags);
2833 goto cleanup;
2834 }
2835 info->count++;
2836 spin_unlock_irqrestore(&info->netlock, flags);
2837
2838 if (info->count == 1) {
2839 /* 1st open on this device, init hardware */
2840 retval = startup(info);
2841 if (retval < 0)
2842 goto cleanup;
2843 }
2844
2845 retval = block_til_ready(tty, filp, info);
2846 if (retval) {
2847 if (debug_level >= DEBUG_LEVEL_INFO)
2848 printk("%s(%d):block_til_ready(%s) returned %d\n",
2849 __FILE__,__LINE__, info->device_name, retval);
2850 goto cleanup;
2851 }
2852
2853 if (debug_level >= DEBUG_LEVEL_INFO)
2854 printk("%s(%d):mgslpc_open(%s) success\n",
2855 __FILE__,__LINE__, info->device_name);
2856 retval = 0;
2857
2858 cleanup:
2859 if (retval) {
2860 if (tty->count == 1)
2861 info->tty = NULL; /* tty layer will release tty struct */
2862 if(info->count)
2863 info->count--;
2864 }
2865
2866 return retval;
2867 }
2868
2869 /*
2870 * /proc fs routines....
2871 */
2872
2873 static inline int line_info(char *buf, MGSLPC_INFO *info)
2874 {
2875 char stat_buf[30];
2876 int ret;
2877 unsigned long flags;
2878
2879 ret = sprintf(buf, "%s:io:%04X irq:%d",
2880 info->device_name, info->io_base, info->irq_level);
2881
2882 /* output current serial signal states */
2883 spin_lock_irqsave(&info->lock,flags);
2884 get_signals(info);
2885 spin_unlock_irqrestore(&info->lock,flags);
2886
2887 stat_buf[0] = 0;
2888 stat_buf[1] = 0;
2889 if (info->serial_signals & SerialSignal_RTS)
2890 strcat(stat_buf, "|RTS");
2891 if (info->serial_signals & SerialSignal_CTS)
2892 strcat(stat_buf, "|CTS");
2893 if (info->serial_signals & SerialSignal_DTR)
2894 strcat(stat_buf, "|DTR");
2895 if (info->serial_signals & SerialSignal_DSR)
2896 strcat(stat_buf, "|DSR");
2897 if (info->serial_signals & SerialSignal_DCD)
2898 strcat(stat_buf, "|CD");
2899 if (info->serial_signals & SerialSignal_RI)
2900 strcat(stat_buf, "|RI");
2901
2902 if (info->params.mode == MGSL_MODE_HDLC) {
2903 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
2904 info->icount.txok, info->icount.rxok);
2905 if (info->icount.txunder)
2906 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
2907 if (info->icount.txabort)
2908 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
2909 if (info->icount.rxshort)
2910 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
2911 if (info->icount.rxlong)
2912 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
2913 if (info->icount.rxover)
2914 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
2915 if (info->icount.rxcrc)
2916 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
2917 } else {
2918 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
2919 info->icount.tx, info->icount.rx);
2920 if (info->icount.frame)
2921 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
2922 if (info->icount.parity)
2923 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
2924 if (info->icount.brk)
2925 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
2926 if (info->icount.overrun)
2927 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
2928 }
2929
2930 /* Append serial signal status to end */
2931 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
2932
2933 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
2934 info->tx_active,info->bh_requested,info->bh_running,
2935 info->pending_bh);
2936
2937 return ret;
2938 }
2939
2940 /* Called to print information about devices
2941 */
2942 static int mgslpc_read_proc(char *page, char **start, off_t off, int count,
2943 int *eof, void *data)
2944 {
2945 int len = 0, l;
2946 off_t begin = 0;
2947 MGSLPC_INFO *info;
2948
2949 len += sprintf(page, "synclink driver:%s\n", driver_version);
2950
2951 info = mgslpc_device_list;
2952 while( info ) {
2953 l = line_info(page + len, info);
2954 len += l;
2955 if (len+begin > off+count)
2956 goto done;
2957 if (len+begin < off) {
2958 begin += len;
2959 len = 0;
2960 }
2961 info = info->next_device;
2962 }
2963
2964 *eof = 1;
2965 done:
2966 if (off >= len+begin)
2967 return 0;
2968 *start = page + (off-begin);
2969 return ((count < begin+len-off) ? count : begin+len-off);
2970 }
2971
2972 int rx_alloc_buffers(MGSLPC_INFO *info)
2973 {
2974 /* each buffer has header and data */
2975 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2976
2977 /* calculate total allocation size for 8 buffers */
2978 info->rx_buf_total_size = info->rx_buf_size * 8;
2979
2980 /* limit total allocated memory */
2981 if (info->rx_buf_total_size > 0x10000)
2982 info->rx_buf_total_size = 0x10000;
2983
2984 /* calculate number of buffers */
2985 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2986
2987 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2988 if (info->rx_buf == NULL)
2989 return -ENOMEM;
2990
2991 rx_reset_buffers(info);
2992 return 0;
2993 }
2994
2995 void rx_free_buffers(MGSLPC_INFO *info)
2996 {
2997 if (info->rx_buf)
2998 kfree(info->rx_buf);
2999 info->rx_buf = NULL;
3000 }
3001
3002 int claim_resources(MGSLPC_INFO *info)
3003 {
3004 if (rx_alloc_buffers(info) < 0 ) {
3005 printk( "Cant allocate rx buffer %s\n", info->device_name);
3006 release_resources(info);
3007 return -ENODEV;
3008 }
3009 return 0;
3010 }
3011
3012 void release_resources(MGSLPC_INFO *info)
3013 {
3014 if (debug_level >= DEBUG_LEVEL_INFO)
3015 printk("release_resources(%s)\n", info->device_name);
3016 rx_free_buffers(info);
3017 }
3018
3019 /* Add the specified device instance data structure to the
3020 * global linked list of devices and increment the device count.
3021 *
3022 * Arguments: info pointer to device instance data
3023 */
3024 void mgslpc_add_device(MGSLPC_INFO *info)
3025 {
3026 info->next_device = NULL;
3027 info->line = mgslpc_device_count;
3028 sprintf(info->device_name,"ttySLP%d",info->line);
3029
3030 if (info->line < MAX_DEVICE_COUNT) {
3031 if (maxframe[info->line])
3032 info->max_frame_size = maxframe[info->line];
3033 info->dosyncppp = dosyncppp[info->line];
3034 }
3035
3036 mgslpc_device_count++;
3037
3038 if (!mgslpc_device_list)
3039 mgslpc_device_list = info;
3040 else {
3041 MGSLPC_INFO *current_dev = mgslpc_device_list;
3042 while( current_dev->next_device )
3043 current_dev = current_dev->next_device;
3044 current_dev->next_device = info;
3045 }
3046
3047 if (info->max_frame_size < 4096)
3048 info->max_frame_size = 4096;
3049 else if (info->max_frame_size > 65535)
3050 info->max_frame_size = 65535;
3051
3052 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
3053 info->device_name, info->io_base, info->irq_level);
3054
3055 #ifdef CONFIG_HDLC
3056 hdlcdev_init(info);
3057 #endif
3058 }
3059
3060 void mgslpc_remove_device(MGSLPC_INFO *remove_info)
3061 {
3062 MGSLPC_INFO *info = mgslpc_device_list;
3063 MGSLPC_INFO *last = NULL;
3064
3065 while(info) {
3066 if (info == remove_info) {
3067 if (last)
3068 last->next_device = info->next_device;
3069 else
3070 mgslpc_device_list = info->next_device;
3071 #ifdef CONFIG_HDLC
3072 hdlcdev_exit(info);
3073 #endif
3074 release_resources(info);
3075 kfree(info);
3076 mgslpc_device_count--;
3077 return;
3078 }
3079 last = info;
3080 info = info->next_device;
3081 }
3082 }
3083
3084 static struct pcmcia_driver mgslpc_driver = {
3085 .owner = THIS_MODULE,
3086 .drv = {
3087 .name = "synclink_cs",
3088 },
3089 .attach = mgslpc_attach,
3090 .detach = mgslpc_detach,
3091 };
3092
3093 static struct tty_operations mgslpc_ops = {
3094 .open = mgslpc_open,
3095 .close = mgslpc_close,
3096 .write = mgslpc_write,
3097 .put_char = mgslpc_put_char,
3098 .flush_chars = mgslpc_flush_chars,
3099 .write_room = mgslpc_write_room,
3100 .chars_in_buffer = mgslpc_chars_in_buffer,
3101 .flush_buffer = mgslpc_flush_buffer,
3102 .ioctl = mgslpc_ioctl,
3103 .throttle = mgslpc_throttle,
3104 .unthrottle = mgslpc_unthrottle,
3105 .send_xchar = mgslpc_send_xchar,
3106 .break_ctl = mgslpc_break,
3107 .wait_until_sent = mgslpc_wait_until_sent,
3108 .read_proc = mgslpc_read_proc,
3109 .set_termios = mgslpc_set_termios,
3110 .stop = tx_pause,
3111 .start = tx_release,
3112 .hangup = mgslpc_hangup,
3113 .tiocmget = tiocmget,
3114 .tiocmset = tiocmset,
3115 };
3116
3117 static void synclink_cs_cleanup(void)
3118 {
3119 int rc;
3120
3121 printk("Unloading %s: version %s\n", driver_name, driver_version);
3122
3123 while(mgslpc_device_list)
3124 mgslpc_remove_device(mgslpc_device_list);
3125
3126 if (serial_driver) {
3127 if ((rc = tty_unregister_driver(serial_driver)))
3128 printk("%s(%d) failed to unregister tty driver err=%d\n",
3129 __FILE__,__LINE__,rc);
3130 put_tty_driver(serial_driver);
3131 }
3132
3133 pcmcia_unregister_driver(&mgslpc_driver);
3134 BUG_ON(dev_list != NULL);
3135 }
3136
3137 static int __init synclink_cs_init(void)
3138 {
3139 int rc;
3140
3141 if (break_on_load) {
3142 mgslpc_get_text_ptr();
3143 BREAKPOINT();
3144 }
3145
3146 printk("%s %s\n", driver_name, driver_version);
3147
3148 if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
3149 return rc;
3150
3151 serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
3152 if (!serial_driver) {
3153 rc = -ENOMEM;
3154 goto error;
3155 }
3156
3157 /* Initialize the tty_driver structure */
3158
3159 serial_driver->owner = THIS_MODULE;
3160 serial_driver->driver_name = "synclink_cs";
3161 serial_driver->name = "ttySLP";
3162 serial_driver->major = ttymajor;
3163 serial_driver->minor_start = 64;
3164 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3165 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3166 serial_driver->init_termios = tty_std_termios;
3167 serial_driver->init_termios.c_cflag =
3168 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3169 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3170 tty_set_operations(serial_driver, &mgslpc_ops);
3171
3172 if ((rc = tty_register_driver(serial_driver)) < 0) {
3173 printk("%s(%d):Couldn't register serial driver\n",
3174 __FILE__,__LINE__);
3175 put_tty_driver(serial_driver);
3176 serial_driver = NULL;
3177 goto error;
3178 }
3179
3180 printk("%s %s, tty major#%d\n",
3181 driver_name, driver_version,
3182 serial_driver->major);
3183
3184 return 0;
3185
3186 error:
3187 synclink_cs_cleanup();
3188 return rc;
3189 }
3190
3191 static void __exit synclink_cs_exit(void)
3192 {
3193 synclink_cs_cleanup();
3194 }
3195
3196 module_init(synclink_cs_init);
3197 module_exit(synclink_cs_exit);
3198
3199 static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
3200 {
3201 unsigned int M, N;
3202 unsigned char val;
3203
3204 /* note:standard BRG mode is broken in V3.2 chip
3205 * so enhanced mode is always used
3206 */
3207
3208 if (rate) {
3209 N = 3686400 / rate;
3210 if (!N)
3211 N = 1;
3212 N >>= 1;
3213 for (M = 1; N > 64 && M < 16; M++)
3214 N >>= 1;
3215 N--;
3216
3217 /* BGR[5..0] = N
3218 * BGR[9..6] = M
3219 * BGR[7..0] contained in BGR register
3220 * BGR[9..8] contained in CCR2[7..6]
3221 * divisor = (N+1)*2^M
3222 *
3223 * Note: M *must* not be zero (causes asymetric duty cycle)
3224 */
3225 write_reg(info, (unsigned char) (channel + BGR),
3226 (unsigned char) ((M << 6) + N));
3227 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
3228 val |= ((M << 4) & 0xc0);
3229 write_reg(info, (unsigned char) (channel + CCR2), val);
3230 }
3231 }
3232
3233 /* Enabled the AUX clock output at the specified frequency.
3234 */
3235 static void enable_auxclk(MGSLPC_INFO *info)
3236 {
3237 unsigned char val;
3238
3239 /* MODE
3240 *
3241 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3242 * 05 ADM Address Mode, 0 = no addr recognition
3243 * 04 TMD Timer Mode, 0 = external
3244 * 03 RAC Receiver Active, 0 = inactive
3245 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3246 * 01 TRS Timer Resolution, 1=512
3247 * 00 TLP Test Loop, 0 = no loop
3248 *
3249 * 1000 0010
3250 */
3251 val = 0x82;
3252
3253 /* channel B RTS is used to enable AUXCLK driver on SP505 */
3254 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3255 val |= BIT2;
3256 write_reg(info, CHB + MODE, val);
3257
3258 /* CCR0
3259 *
3260 * 07 PU Power Up, 1=active, 0=power down
3261 * 06 MCE Master Clock Enable, 1=enabled
3262 * 05 Reserved, 0
3263 * 04..02 SC[2..0] Encoding
3264 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3265 *
3266 * 11000000
3267 */
3268 write_reg(info, CHB + CCR0, 0xc0);
3269
3270 /* CCR1
3271 *
3272 * 07 SFLG Shared Flag, 0 = disable shared flags
3273 * 06 GALP Go Active On Loop, 0 = not used
3274 * 05 GLP Go On Loop, 0 = not used
3275 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3276 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3277 * 02..00 CM[2..0] Clock Mode
3278 *
3279 * 0001 0111
3280 */
3281 write_reg(info, CHB + CCR1, 0x17);
3282
3283 /* CCR2 (Channel B)
3284 *
3285 * 07..06 BGR[9..8] Baud rate bits 9..8
3286 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3287 * 04 SSEL Clock source select, 1=submode b
3288 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
3289 * 02 RWX Read/Write Exchange 0=disabled
3290 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3291 * 00 DIV, data inversion 0=disabled, 1=enabled
3292 *
3293 * 0011 1000
3294 */
3295 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3296 write_reg(info, CHB + CCR2, 0x38);
3297 else
3298 write_reg(info, CHB + CCR2, 0x30);
3299
3300 /* CCR4
3301 *
3302 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3303 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3304 * 05 TST1 Test Pin, 0=normal operation
3305 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3306 * 03..02 Reserved, must be 0
3307 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3308 *
3309 * 0101 0000
3310 */
3311 write_reg(info, CHB + CCR4, 0x50);
3312
3313 /* if auxclk not enabled, set internal BRG so
3314 * CTS transitions can be detected (requires TxC)
3315 */
3316 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
3317 mgslpc_set_rate(info, CHB, info->params.clock_speed);
3318 else
3319 mgslpc_set_rate(info, CHB, 921600);
3320 }
3321
3322 static void loopback_enable(MGSLPC_INFO *info)
3323 {
3324 unsigned char val;
3325
3326 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
3327 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3328 write_reg(info, CHA + CCR1, val);
3329
3330 /* CCR2:04 SSEL Clock source select, 1=submode b */
3331 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3332 write_reg(info, CHA + CCR2, val);
3333
3334 /* set LinkSpeed if available, otherwise default to 2Mbps */
3335 if (info->params.clock_speed)
3336 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3337 else
3338 mgslpc_set_rate(info, CHA, 1843200);
3339
3340 /* MODE:00 TLP Test Loop, 1=loopback enabled */
3341 val = read_reg(info, CHA + MODE) | BIT0;
3342 write_reg(info, CHA + MODE, val);
3343 }
3344
3345 void hdlc_mode(MGSLPC_INFO *info)
3346 {
3347 unsigned char val;
3348 unsigned char clkmode, clksubmode;
3349
3350 /* disable all interrupts */
3351 irq_disable(info, CHA, 0xffff);
3352 irq_disable(info, CHB, 0xffff);
3353 port_irq_disable(info, 0xff);
3354
3355 /* assume clock mode 0a, rcv=RxC xmt=TxC */
3356 clkmode = clksubmode = 0;
3357 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3358 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
3359 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
3360 clkmode = 7;
3361 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3362 && info->params.flags & HDLC_FLAG_TXC_BRG) {
3363 /* clock mode 7b, rcv = BRG, xmt = BRG */
3364 clkmode = 7;
3365 clksubmode = 1;
3366 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3367 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
3368 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
3369 clkmode = 6;
3370 clksubmode = 1;
3371 } else {
3372 /* clock mode 6a, rcv = DPLL, xmt = TxC */
3373 clkmode = 6;
3374 }
3375 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
3376 /* clock mode 0b, rcv = RxC, xmt = BRG */
3377 clksubmode = 1;
3378 }
3379
3380 /* MODE
3381 *
3382 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3383 * 05 ADM Address Mode, 0 = no addr recognition
3384 * 04 TMD Timer Mode, 0 = external
3385 * 03 RAC Receiver Active, 0 = inactive
3386 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3387 * 01 TRS Timer Resolution, 1=512
3388 * 00 TLP Test Loop, 0 = no loop
3389 *
3390 * 1000 0010
3391 */
3392 val = 0x82;
3393 if (info->params.loopback)
3394 val |= BIT0;
3395
3396 /* preserve RTS state */
3397 if (info->serial_signals & SerialSignal_RTS)
3398 val |= BIT2;
3399 write_reg(info, CHA + MODE, val);
3400
3401 /* CCR0
3402 *
3403 * 07 PU Power Up, 1=active, 0=power down
3404 * 06 MCE Master Clock Enable, 1=enabled
3405 * 05 Reserved, 0
3406 * 04..02 SC[2..0] Encoding
3407 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3408 *
3409 * 11000000
3410 */
3411 val = 0xc0;
3412 switch (info->params.encoding)
3413 {
3414 case HDLC_ENCODING_NRZI:
3415 val |= BIT3;
3416 break;
3417 case HDLC_ENCODING_BIPHASE_SPACE:
3418 val |= BIT4;
3419 break; // FM0
3420 case HDLC_ENCODING_BIPHASE_MARK:
3421 val |= BIT4 + BIT2;
3422 break; // FM1
3423 case HDLC_ENCODING_BIPHASE_LEVEL:
3424 val |= BIT4 + BIT3;
3425 break; // Manchester
3426 }
3427 write_reg(info, CHA + CCR0, val);
3428
3429 /* CCR1
3430 *
3431 * 07 SFLG Shared Flag, 0 = disable shared flags
3432 * 06 GALP Go Active On Loop, 0 = not used
3433 * 05 GLP Go On Loop, 0 = not used
3434 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3435 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3436 * 02..00 CM[2..0] Clock Mode
3437 *
3438 * 0001 0000
3439 */
3440 val = 0x10 + clkmode;
3441 write_reg(info, CHA + CCR1, val);
3442
3443 /* CCR2
3444 *
3445 * 07..06 BGR[9..8] Baud rate bits 9..8
3446 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3447 * 04 SSEL Clock source select, 1=submode b
3448 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3449 * 02 RWX Read/Write Exchange 0=disabled
3450 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3451 * 00 DIV, data inversion 0=disabled, 1=enabled
3452 *
3453 * 0000 0000
3454 */
3455 val = 0x00;
3456 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3457 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3458 val |= BIT5;
3459 if (clksubmode)
3460 val |= BIT4;
3461 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3462 val |= BIT1;
3463 if (info->params.encoding == HDLC_ENCODING_NRZB)
3464 val |= BIT0;
3465 write_reg(info, CHA + CCR2, val);
3466
3467 /* CCR3
3468 *
3469 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3470 * 05 EPT Enable preamble transmission, 1=enabled
3471 * 04 RADD Receive address pushed to FIFO, 0=disabled
3472 * 03 CRL CRC Reset Level, 0=FFFF
3473 * 02 RCRC Rx CRC 0=On 1=Off
3474 * 01 TCRC Tx CRC 0=On 1=Off
3475 * 00 PSD DPLL Phase Shift Disable
3476 *
3477 * 0000 0000
3478 */
3479 val = 0x00;
3480 if (info->params.crc_type == HDLC_CRC_NONE)
3481 val |= BIT2 + BIT1;
3482 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3483 val |= BIT5;
3484 switch (info->params.preamble_length)
3485 {
3486 case HDLC_PREAMBLE_LENGTH_16BITS:
3487 val |= BIT6;
3488 break;
3489 case HDLC_PREAMBLE_LENGTH_32BITS:
3490 val |= BIT6;
3491 break;
3492 case HDLC_PREAMBLE_LENGTH_64BITS:
3493 val |= BIT7 + BIT6;
3494 break;
3495 }
3496 write_reg(info, CHA + CCR3, val);
3497
3498 /* PRE - Preamble pattern */
3499 val = 0;
3500 switch (info->params.preamble)
3501 {
3502 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3503 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3504 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3505 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3506 }
3507 write_reg(info, CHA + PRE, val);
3508
3509 /* CCR4
3510 *
3511 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3512 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3513 * 05 TST1 Test Pin, 0=normal operation
3514 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3515 * 03..02 Reserved, must be 0
3516 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3517 *
3518 * 0101 0000
3519 */
3520 val = 0x50;
3521 write_reg(info, CHA + CCR4, val);
3522 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3523 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3524 else
3525 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3526
3527 /* RLCR Receive length check register
3528 *
3529 * 7 1=enable receive length check
3530 * 6..0 Max frame length = (RL + 1) * 32
3531 */
3532 write_reg(info, CHA + RLCR, 0);
3533
3534 /* XBCH Transmit Byte Count High
3535 *
3536 * 07 DMA mode, 0 = interrupt driven
3537 * 06 NRM, 0=ABM (ignored)
3538 * 05 CAS Carrier Auto Start
3539 * 04 XC Transmit Continuously (ignored)
3540 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3541 *
3542 * 0000 0000
3543 */
3544 val = 0x00;
3545 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3546 val |= BIT5;
3547 write_reg(info, CHA + XBCH, val);
3548 enable_auxclk(info);
3549 if (info->params.loopback || info->testing_irq)
3550 loopback_enable(info);
3551 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3552 {
3553 irq_enable(info, CHB, IRQ_CTS);
3554 /* PVR[3] 1=AUTO CTS active */
3555 set_reg_bits(info, CHA + PVR, BIT3);
3556 } else
3557 clear_reg_bits(info, CHA + PVR, BIT3);
3558
3559 irq_enable(info, CHA,
3560 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3561 IRQ_UNDERRUN + IRQ_TXFIFO);
3562 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3563 wait_command_complete(info, CHA);
3564 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3565
3566 /* Master clock mode enabled above to allow reset commands
3567 * to complete even if no data clocks are present.
3568 *
3569 * Disable master clock mode for normal communications because
3570 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3571 * IRQ when in master clock mode.
3572 *
3573 * Leave master clock mode enabled for IRQ test because the
3574 * timer IRQ used by the test can only happen in master clock mode.
3575 */
3576 if (!info->testing_irq)
3577 clear_reg_bits(info, CHA + CCR0, BIT6);
3578
3579 tx_set_idle(info);
3580
3581 tx_stop(info);
3582 rx_stop(info);
3583 }
3584
3585 void rx_stop(MGSLPC_INFO *info)
3586 {
3587 if (debug_level >= DEBUG_LEVEL_ISR)
3588 printk("%s(%d):rx_stop(%s)\n",
3589 __FILE__,__LINE__, info->device_name );
3590
3591 /* MODE:03 RAC Receiver Active, 0=inactive */
3592 clear_reg_bits(info, CHA + MODE, BIT3);
3593
3594 info->rx_enabled = 0;
3595 info->rx_overflow = 0;
3596 }
3597
3598 void rx_start(MGSLPC_INFO *info)
3599 {
3600 if (debug_level >= DEBUG_LEVEL_ISR)
3601 printk("%s(%d):rx_start(%s)\n",
3602 __FILE__,__LINE__, info->device_name );
3603
3604 rx_reset_buffers(info);
3605 info->rx_enabled = 0;
3606 info->rx_overflow = 0;
3607
3608 /* MODE:03 RAC Receiver Active, 1=active */
3609 set_reg_bits(info, CHA + MODE, BIT3);
3610
3611 info->rx_enabled = 1;
3612 }
3613
3614 void tx_start(MGSLPC_INFO *info)
3615 {
3616 if (debug_level >= DEBUG_LEVEL_ISR)
3617 printk("%s(%d):tx_start(%s)\n",
3618 __FILE__,__LINE__, info->device_name );
3619
3620 if (info->tx_count) {
3621 /* If auto RTS enabled and RTS is inactive, then assert */
3622 /* RTS and set a flag indicating that the driver should */
3623 /* negate RTS when the transmission completes. */
3624 info->drop_rts_on_tx_done = 0;
3625
3626 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3627 get_signals(info);
3628 if (!(info->serial_signals & SerialSignal_RTS)) {
3629 info->serial_signals |= SerialSignal_RTS;
3630 set_signals(info);
3631 info->drop_rts_on_tx_done = 1;
3632 }
3633 }
3634
3635 if (info->params.mode == MGSL_MODE_ASYNC) {
3636 if (!info->tx_active) {
3637 info->tx_active = 1;
3638 tx_ready(info);
3639 }
3640 } else {
3641 info->tx_active = 1;
3642 tx_ready(info);
3643 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3644 add_timer(&info->tx_timer);
3645 }
3646 }
3647
3648 if (!info->tx_enabled)
3649 info->tx_enabled = 1;
3650 }
3651
3652 void tx_stop(MGSLPC_INFO *info)
3653 {
3654 if (debug_level >= DEBUG_LEVEL_ISR)
3655 printk("%s(%d):tx_stop(%s)\n",
3656 __FILE__,__LINE__, info->device_name );
3657
3658 del_timer(&info->tx_timer);
3659
3660 info->tx_enabled = 0;
3661 info->tx_active = 0;
3662 }
3663
3664 /* Reset the adapter to a known state and prepare it for further use.
3665 */
3666 void reset_device(MGSLPC_INFO *info)
3667 {
3668 /* power up both channels (set BIT7) */
3669 write_reg(info, CHA + CCR0, 0x80);
3670 write_reg(info, CHB + CCR0, 0x80);
3671 write_reg(info, CHA + MODE, 0);
3672 write_reg(info, CHB + MODE, 0);
3673
3674 /* disable all interrupts */
3675 irq_disable(info, CHA, 0xffff);
3676 irq_disable(info, CHB, 0xffff);
3677 port_irq_disable(info, 0xff);
3678
3679 /* PCR Port Configuration Register
3680 *
3681 * 07..04 DEC[3..0] Serial I/F select outputs
3682 * 03 output, 1=AUTO CTS control enabled
3683 * 02 RI Ring Indicator input 0=active
3684 * 01 DSR input 0=active
3685 * 00 DTR output 0=active
3686 *
3687 * 0000 0110
3688 */
3689 write_reg(info, PCR, 0x06);
3690
3691 /* PVR Port Value Register
3692 *
3693 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3694 * 03 AUTO CTS output 1=enabled
3695 * 02 RI Ring Indicator input
3696 * 01 DSR input
3697 * 00 DTR output (1=inactive)
3698 *
3699 * 0000 0001
3700 */
3701 // write_reg(info, PVR, PVR_DTR);
3702
3703 /* IPC Interrupt Port Configuration
3704 *
3705 * 07 VIS 1=Masked interrupts visible
3706 * 06..05 Reserved, 0
3707 * 04..03 SLA Slave address, 00 ignored
3708 * 02 CASM Cascading Mode, 1=daisy chain
3709 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3710 *
3711 * 0000 0101
3712 */
3713 write_reg(info, IPC, 0x05);
3714 }
3715
3716 void async_mode(MGSLPC_INFO *info)
3717 {
3718 unsigned char val;
3719
3720 /* disable all interrupts */
3721 irq_disable(info, CHA, 0xffff);
3722 irq_disable(info, CHB, 0xffff);
3723 port_irq_disable(info, 0xff);
3724
3725 /* MODE
3726 *
3727 * 07 Reserved, 0
3728 * 06 FRTS RTS State, 0=active
3729 * 05 FCTS Flow Control on CTS
3730 * 04 FLON Flow Control Enable
3731 * 03 RAC Receiver Active, 0 = inactive
3732 * 02 RTS 0=Auto RTS, 1=manual RTS
3733 * 01 TRS Timer Resolution, 1=512
3734 * 00 TLP Test Loop, 0 = no loop
3735 *
3736 * 0000 0110
3737 */
3738 val = 0x06;
3739 if (info->params.loopback)
3740 val |= BIT0;
3741
3742 /* preserve RTS state */
3743 if (!(info->serial_signals & SerialSignal_RTS))
3744 val |= BIT6;
3745 write_reg(info, CHA + MODE, val);
3746
3747 /* CCR0
3748 *
3749 * 07 PU Power Up, 1=active, 0=power down
3750 * 06 MCE Master Clock Enable, 1=enabled
3751 * 05 Reserved, 0
3752 * 04..02 SC[2..0] Encoding, 000=NRZ
3753 * 01..00 SM[1..0] Serial Mode, 11=Async
3754 *
3755 * 1000 0011
3756 */
3757 write_reg(info, CHA + CCR0, 0x83);
3758
3759 /* CCR1
3760 *
3761 * 07..05 Reserved, 0
3762 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3763 * 03 BCR Bit Clock Rate, 1=16x
3764 * 02..00 CM[2..0] Clock Mode, 111=BRG
3765 *
3766 * 0001 1111
3767 */
3768 write_reg(info, CHA + CCR1, 0x1f);
3769
3770 /* CCR2 (channel A)
3771 *
3772 * 07..06 BGR[9..8] Baud rate bits 9..8
3773 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3774 * 04 SSEL Clock source select, 1=submode b
3775 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3776 * 02 RWX Read/Write Exchange 0=disabled
3777 * 01 Reserved, 0
3778 * 00 DIV, data inversion 0=disabled, 1=enabled
3779 *
3780 * 0001 0000
3781 */
3782 write_reg(info, CHA + CCR2, 0x10);
3783
3784 /* CCR3
3785 *
3786 * 07..01 Reserved, 0
3787 * 00 PSD DPLL Phase Shift Disable
3788 *
3789 * 0000 0000
3790 */
3791 write_reg(info, CHA + CCR3, 0);
3792
3793 /* CCR4
3794 *
3795 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3796 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3797 * 05 TST1 Test Pin, 0=normal operation
3798 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3799 * 03..00 Reserved, must be 0
3800 *
3801 * 0101 0000
3802 */
3803 write_reg(info, CHA + CCR4, 0x50);
3804 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
3805
3806 /* DAFO Data Format
3807 *
3808 * 07 Reserved, 0
3809 * 06 XBRK transmit break, 0=normal operation
3810 * 05 Stop bits (0=1, 1=2)
3811 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3812 * 02 PAREN Parity Enable
3813 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3814 *
3815 */
3816 val = 0x00;
3817 if (info->params.data_bits != 8)
3818 val |= BIT0; /* 7 bits */
3819 if (info->params.stop_bits != 1)
3820 val |= BIT5;
3821 if (info->params.parity != ASYNC_PARITY_NONE)
3822 {
3823 val |= BIT2; /* Parity enable */
3824 if (info->params.parity == ASYNC_PARITY_ODD)
3825 val |= BIT3;
3826 else
3827 val |= BIT4;
3828 }
3829 write_reg(info, CHA + DAFO, val);
3830
3831 /* RFC Rx FIFO Control
3832 *
3833 * 07 Reserved, 0
3834 * 06 DPS, 1=parity bit not stored in data byte
3835 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3836 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3837 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3838 * 01 Reserved, 0
3839 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3840 *
3841 * 0101 1100
3842 */
3843 write_reg(info, CHA + RFC, 0x5c);
3844
3845 /* RLCR Receive length check register
3846 *
3847 * Max frame length = (RL + 1) * 32
3848 */
3849 write_reg(info, CHA + RLCR, 0);
3850
3851 /* XBCH Transmit Byte Count High
3852 *
3853 * 07 DMA mode, 0 = interrupt driven
3854 * 06 NRM, 0=ABM (ignored)
3855 * 05 CAS Carrier Auto Start
3856 * 04 XC Transmit Continuously (ignored)
3857 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3858 *
3859 * 0000 0000
3860 */
3861 val = 0x00;
3862 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3863 val |= BIT5;
3864 write_reg(info, CHA + XBCH, val);
3865 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3866 irq_enable(info, CHA, IRQ_CTS);
3867
3868 /* MODE:03 RAC Receiver Active, 1=active */
3869 set_reg_bits(info, CHA + MODE, BIT3);
3870 enable_auxclk(info);
3871 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3872 irq_enable(info, CHB, IRQ_CTS);
3873 /* PVR[3] 1=AUTO CTS active */
3874 set_reg_bits(info, CHA + PVR, BIT3);
3875 } else
3876 clear_reg_bits(info, CHA + PVR, BIT3);
3877 irq_enable(info, CHA,
3878 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3879 IRQ_ALLSENT + IRQ_TXFIFO);
3880 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3881 wait_command_complete(info, CHA);
3882 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3883 }
3884
3885 /* Set the HDLC idle mode for the transmitter.
3886 */
3887 void tx_set_idle(MGSLPC_INFO *info)
3888 {
3889 /* Note: ESCC2 only supports flags and one idle modes */
3890 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3891 set_reg_bits(info, CHA + CCR1, BIT3);
3892 else
3893 clear_reg_bits(info, CHA + CCR1, BIT3);
3894 }
3895
3896 /* get state of the V24 status (input) signals.
3897 */
3898 void get_signals(MGSLPC_INFO *info)
3899 {
3900 unsigned char status = 0;
3901
3902 /* preserve DTR and RTS */
3903 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3904
3905 if (read_reg(info, CHB + VSTR) & BIT7)
3906 info->serial_signals |= SerialSignal_DCD;
3907 if (read_reg(info, CHB + STAR) & BIT1)
3908 info->serial_signals |= SerialSignal_CTS;
3909
3910 status = read_reg(info, CHA + PVR);
3911 if (!(status & PVR_RI))
3912 info->serial_signals |= SerialSignal_RI;
3913 if (!(status & PVR_DSR))
3914 info->serial_signals |= SerialSignal_DSR;
3915 }
3916
3917 /* Set the state of DTR and RTS based on contents of
3918 * serial_signals member of device extension.
3919 */
3920 void set_signals(MGSLPC_INFO *info)
3921 {
3922 unsigned char val;
3923
3924 val = read_reg(info, CHA + MODE);
3925 if (info->params.mode == MGSL_MODE_ASYNC) {
3926 if (info->serial_signals & SerialSignal_RTS)
3927 val &= ~BIT6;
3928 else
3929 val |= BIT6;
3930 } else {
3931 if (info->serial_signals & SerialSignal_RTS)
3932 val |= BIT2;
3933 else
3934 val &= ~BIT2;
3935 }
3936 write_reg(info, CHA + MODE, val);
3937
3938 if (info->serial_signals & SerialSignal_DTR)
3939 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3940 else
3941 set_reg_bits(info, CHA + PVR, PVR_DTR);
3942 }
3943
3944 void rx_reset_buffers(MGSLPC_INFO *info)
3945 {
3946 RXBUF *buf;
3947 int i;
3948
3949 info->rx_put = 0;
3950 info->rx_get = 0;
3951 info->rx_frame_count = 0;
3952 for (i=0 ; i < info->rx_buf_count ; i++) {
3953 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3954 buf->status = buf->count = 0;
3955 }
3956 }
3957
3958 /* Attempt to return a received HDLC frame
3959 * Only frames received without errors are returned.
3960 *
3961 * Returns 1 if frame returned, otherwise 0
3962 */
3963 int rx_get_frame(MGSLPC_INFO *info)
3964 {
3965 unsigned short status;
3966 RXBUF *buf;
3967 unsigned int framesize = 0;
3968 unsigned long flags;
3969 struct tty_struct *tty = info->tty;
3970 int return_frame = 0;
3971
3972 if (info->rx_frame_count == 0)
3973 return 0;
3974
3975 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3976
3977 status = buf->status;
3978
3979 /* 07 VFR 1=valid frame
3980 * 06 RDO 1=data overrun
3981 * 05 CRC 1=OK, 0=error
3982 * 04 RAB 1=frame aborted
3983 */
3984 if ((status & 0xf0) != 0xA0) {
3985 if (!(status & BIT7) || (status & BIT4))
3986 info->icount.rxabort++;
3987 else if (status & BIT6)
3988 info->icount.rxover++;
3989 else if (!(status & BIT5)) {
3990 info->icount.rxcrc++;
3991 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
3992 return_frame = 1;
3993 }
3994 framesize = 0;
3995 #ifdef CONFIG_HDLC
3996 {
3997 struct net_device_stats *stats = hdlc_stats(info->netdev);
3998 stats->rx_errors++;
3999 stats->rx_frame_errors++;
4000 }
4001 #endif
4002 } else
4003 return_frame = 1;
4004
4005 if (return_frame)
4006 framesize = buf->count;
4007
4008 if (debug_level >= DEBUG_LEVEL_BH)
4009 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
4010 __FILE__,__LINE__,info->device_name,status,framesize);
4011
4012 if (debug_level >= DEBUG_LEVEL_DATA)
4013 trace_block(info, buf->data, framesize, 0);
4014
4015 if (framesize) {
4016 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
4017 framesize+1 > info->max_frame_size) ||
4018 framesize > info->max_frame_size)
4019 info->icount.rxlong++;
4020 else {
4021 if (status & BIT5)
4022 info->icount.rxok++;
4023
4024 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4025 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
4026 ++framesize;
4027 }
4028
4029 #ifdef CONFIG_HDLC
4030 if (info->netcount)
4031 hdlcdev_rx(info, buf->data, framesize);
4032 else
4033 #endif
4034 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
4035 }
4036 }
4037
4038 spin_lock_irqsave(&info->lock,flags);
4039 buf->status = buf->count = 0;
4040 info->rx_frame_count--;
4041 info->rx_get++;
4042 if (info->rx_get >= info->rx_buf_count)
4043 info->rx_get = 0;
4044 spin_unlock_irqrestore(&info->lock,flags);
4045
4046 return 1;
4047 }
4048
4049 BOOLEAN register_test(MGSLPC_INFO *info)
4050 {
4051 static unsigned char patterns[] =
4052 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
4053 static unsigned int count = sizeof(patterns) / sizeof(patterns[0]);
4054 unsigned int i;
4055 BOOLEAN rc = TRUE;
4056 unsigned long flags;
4057
4058 spin_lock_irqsave(&info->lock,flags);
4059 reset_device(info);
4060
4061 for (i = 0; i < count; i++) {
4062 write_reg(info, XAD1, patterns[i]);
4063 write_reg(info, XAD2, patterns[(i + 1) % count]);
4064 if ((read_reg(info, XAD1) != patterns[i]) ||
4065 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
4066 rc = FALSE;
4067 break;
4068 }
4069 }
4070
4071 spin_unlock_irqrestore(&info->lock,flags);
4072 return rc;
4073 }
4074
4075 BOOLEAN irq_test(MGSLPC_INFO *info)
4076 {
4077 unsigned long end_time;
4078 unsigned long flags;
4079
4080 spin_lock_irqsave(&info->lock,flags);
4081 reset_device(info);
4082
4083 info->testing_irq = TRUE;
4084 hdlc_mode(info);
4085
4086 info->irq_occurred = FALSE;
4087
4088 /* init hdlc mode */
4089
4090 irq_enable(info, CHA, IRQ_TIMER);
4091 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
4092 issue_command(info, CHA, CMD_START_TIMER);
4093
4094 spin_unlock_irqrestore(&info->lock,flags);
4095
4096 end_time=100;
4097 while(end_time-- && !info->irq_occurred) {
4098 msleep_interruptible(10);
4099 }
4100
4101 info->testing_irq = FALSE;
4102
4103 spin_lock_irqsave(&info->lock,flags);
4104 reset_device(info);
4105 spin_unlock_irqrestore(&info->lock,flags);
4106
4107 return info->irq_occurred ? TRUE : FALSE;
4108 }
4109
4110 int adapter_test(MGSLPC_INFO *info)
4111 {
4112 if (!register_test(info)) {
4113 info->init_error = DiagStatus_AddressFailure;
4114 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
4115 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
4116 return -ENODEV;
4117 }
4118
4119 if (!irq_test(info)) {
4120 info->init_error = DiagStatus_IrqFailure;
4121 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
4122 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
4123 return -ENODEV;
4124 }
4125
4126 if (debug_level >= DEBUG_LEVEL_INFO)
4127 printk("%s(%d):device %s passed diagnostics\n",
4128 __FILE__,__LINE__,info->device_name);
4129 return 0;
4130 }
4131
4132 void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
4133 {
4134 int i;
4135 int linecount;
4136 if (xmit)
4137 printk("%s tx data:\n",info->device_name);
4138 else
4139 printk("%s rx data:\n",info->device_name);
4140
4141 while(count) {
4142 if (count > 16)
4143 linecount = 16;
4144 else
4145 linecount = count;
4146
4147 for(i=0;i<linecount;i++)
4148 printk("%02X ",(unsigned char)data[i]);
4149 for(;i<17;i++)
4150 printk(" ");
4151 for(i=0;i<linecount;i++) {
4152 if (data[i]>=040 && data[i]<=0176)
4153 printk("%c",data[i]);
4154 else
4155 printk(".");
4156 }
4157 printk("\n");
4158
4159 data += linecount;
4160 count -= linecount;
4161 }
4162 }
4163
4164 /* HDLC frame time out
4165 * update stats and do tx completion processing
4166 */
4167 void tx_timeout(unsigned long context)
4168 {
4169 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
4170 unsigned long flags;
4171
4172 if ( debug_level >= DEBUG_LEVEL_INFO )
4173 printk( "%s(%d):tx_timeout(%s)\n",
4174 __FILE__,__LINE__,info->device_name);
4175 if(info->tx_active &&
4176 info->params.mode == MGSL_MODE_HDLC) {
4177 info->icount.txtimeout++;
4178 }
4179 spin_lock_irqsave(&info->lock,flags);
4180 info->tx_active = 0;
4181 info->tx_count = info->tx_put = info->tx_get = 0;
4182
4183 spin_unlock_irqrestore(&info->lock,flags);
4184
4185 #ifdef CONFIG_HDLC
4186 if (info->netcount)
4187 hdlcdev_tx_done(info);
4188 else
4189 #endif
4190 bh_transmit(info);
4191 }
4192
4193 #ifdef CONFIG_HDLC
4194
4195 /**
4196 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
4197 * set encoding and frame check sequence (FCS) options
4198 *
4199 * dev pointer to network device structure
4200 * encoding serial encoding setting
4201 * parity FCS setting
4202 *
4203 * returns 0 if success, otherwise error code
4204 */
4205 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
4206 unsigned short parity)
4207 {
4208 MGSLPC_INFO *info = dev_to_port(dev);
4209 unsigned char new_encoding;
4210 unsigned short new_crctype;
4211
4212 /* return error if TTY interface open */
4213 if (info->count)
4214 return -EBUSY;
4215
4216 switch (encoding)
4217 {
4218 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
4219 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
4220 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
4221 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
4222 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
4223 default: return -EINVAL;
4224 }
4225
4226 switch (parity)
4227 {
4228 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
4229 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
4230 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
4231 default: return -EINVAL;
4232 }
4233
4234 info->params.encoding = new_encoding;
4235 info->params.crc_type = new_crctype;;
4236
4237 /* if network interface up, reprogram hardware */
4238 if (info->netcount)
4239 mgslpc_program_hw(info);
4240
4241 return 0;
4242 }
4243
4244 /**
4245 * called by generic HDLC layer to send frame
4246 *
4247 * skb socket buffer containing HDLC frame
4248 * dev pointer to network device structure
4249 *
4250 * returns 0 if success, otherwise error code
4251 */
4252 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
4253 {
4254 MGSLPC_INFO *info = dev_to_port(dev);
4255 struct net_device_stats *stats = hdlc_stats(dev);
4256 unsigned long flags;
4257
4258 if (debug_level >= DEBUG_LEVEL_INFO)
4259 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
4260
4261 /* stop sending until this frame completes */
4262 netif_stop_queue(dev);
4263
4264 /* copy data to device buffers */
4265 memcpy(info->tx_buf, skb->data, skb->len);
4266 info->tx_get = 0;
4267 info->tx_put = info->tx_count = skb->len;
4268
4269 /* update network statistics */
4270 stats->tx_packets++;
4271 stats->tx_bytes += skb->len;
4272
4273 /* done with socket buffer, so free it */
4274 dev_kfree_skb(skb);
4275
4276 /* save start time for transmit timeout detection */
4277 dev->trans_start = jiffies;
4278
4279 /* start hardware transmitter if necessary */
4280 spin_lock_irqsave(&info->lock,flags);
4281 if (!info->tx_active)
4282 tx_start(info);
4283 spin_unlock_irqrestore(&info->lock,flags);
4284
4285 return 0;
4286 }
4287
4288 /**
4289 * called by network layer when interface enabled
4290 * claim resources and initialize hardware
4291 *
4292 * dev pointer to network device structure
4293 *
4294 * returns 0 if success, otherwise error code
4295 */
4296 static int hdlcdev_open(struct net_device *dev)
4297 {
4298 MGSLPC_INFO *info = dev_to_port(dev);
4299 int rc;
4300 unsigned long flags;
4301
4302 if (debug_level >= DEBUG_LEVEL_INFO)
4303 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
4304
4305 /* generic HDLC layer open processing */
4306 if ((rc = hdlc_open(dev)))
4307 return rc;
4308
4309 /* arbitrate between network and tty opens */
4310 spin_lock_irqsave(&info->netlock, flags);
4311 if (info->count != 0 || info->netcount != 0) {
4312 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4313 spin_unlock_irqrestore(&info->netlock, flags);
4314 return -EBUSY;
4315 }
4316 info->netcount=1;
4317 spin_unlock_irqrestore(&info->netlock, flags);
4318
4319 /* claim resources and init adapter */
4320 if ((rc = startup(info)) != 0) {
4321 spin_lock_irqsave(&info->netlock, flags);
4322 info->netcount=0;
4323 spin_unlock_irqrestore(&info->netlock, flags);
4324 return rc;
4325 }
4326
4327 /* assert DTR and RTS, apply hardware settings */
4328 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
4329 mgslpc_program_hw(info);
4330
4331 /* enable network layer transmit */
4332 dev->trans_start = jiffies;
4333 netif_start_queue(dev);
4334
4335 /* inform generic HDLC layer of current DCD status */
4336 spin_lock_irqsave(&info->lock, flags);
4337 get_signals(info);
4338 spin_unlock_irqrestore(&info->lock, flags);
4339 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
4340
4341 return 0;
4342 }
4343
4344 /**
4345 * called by network layer when interface is disabled
4346 * shutdown hardware and release resources
4347 *
4348 * dev pointer to network device structure
4349 *
4350 * returns 0 if success, otherwise error code
4351 */
4352 static int hdlcdev_close(struct net_device *dev)
4353 {
4354 MGSLPC_INFO *info = dev_to_port(dev);
4355 unsigned long flags;
4356
4357 if (debug_level >= DEBUG_LEVEL_INFO)
4358 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4359
4360 netif_stop_queue(dev);
4361
4362 /* shutdown adapter and release resources */
4363 shutdown(info);
4364
4365 hdlc_close(dev);
4366
4367 spin_lock_irqsave(&info->netlock, flags);
4368 info->netcount=0;
4369 spin_unlock_irqrestore(&info->netlock, flags);
4370
4371 return 0;
4372 }
4373
4374 /**
4375 * called by network layer to process IOCTL call to network device
4376 *
4377 * dev pointer to network device structure
4378 * ifr pointer to network interface request structure
4379 * cmd IOCTL command code
4380 *
4381 * returns 0 if success, otherwise error code
4382 */
4383 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4384 {
4385 const size_t size = sizeof(sync_serial_settings);
4386 sync_serial_settings new_line;
4387 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4388 MGSLPC_INFO *info = dev_to_port(dev);
4389 unsigned int flags;
4390
4391 if (debug_level >= DEBUG_LEVEL_INFO)
4392 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4393
4394 /* return error if TTY interface open */
4395 if (info->count)
4396 return -EBUSY;
4397
4398 if (cmd != SIOCWANDEV)
4399 return hdlc_ioctl(dev, ifr, cmd);
4400
4401 switch(ifr->ifr_settings.type) {
4402 case IF_GET_IFACE: /* return current sync_serial_settings */
4403
4404 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4405 if (ifr->ifr_settings.size < size) {
4406 ifr->ifr_settings.size = size; /* data size wanted */
4407 return -ENOBUFS;
4408 }
4409
4410 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4411 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4412 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4413 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4414
4415 switch (flags){
4416 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4417 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4418 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4419 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4420 default: new_line.clock_type = CLOCK_DEFAULT;
4421 }
4422
4423 new_line.clock_rate = info->params.clock_speed;
4424 new_line.loopback = info->params.loopback ? 1:0;
4425
4426 if (copy_to_user(line, &new_line, size))
4427 return -EFAULT;
4428 return 0;
4429
4430 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4431
4432 if(!capable(CAP_NET_ADMIN))
4433 return -EPERM;
4434 if (copy_from_user(&new_line, line, size))
4435 return -EFAULT;
4436
4437 switch (new_line.clock_type)
4438 {
4439 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4440 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4441 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4442 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4443 case CLOCK_DEFAULT: flags = info->params.flags &
4444 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4445 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4446 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4447 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4448 default: return -EINVAL;
4449 }
4450
4451 if (new_line.loopback != 0 && new_line.loopback != 1)
4452 return -EINVAL;
4453
4454 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4455 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4456 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4457 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4458 info->params.flags |= flags;
4459
4460 info->params.loopback = new_line.loopback;
4461
4462 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4463 info->params.clock_speed = new_line.clock_rate;
4464 else
4465 info->params.clock_speed = 0;
4466
4467 /* if network interface up, reprogram hardware */
4468 if (info->netcount)
4469 mgslpc_program_hw(info);
4470 return 0;
4471
4472 default:
4473 return hdlc_ioctl(dev, ifr, cmd);
4474 }
4475 }
4476
4477 /**
4478 * called by network layer when transmit timeout is detected
4479 *
4480 * dev pointer to network device structure
4481 */
4482 static void hdlcdev_tx_timeout(struct net_device *dev)
4483 {
4484 MGSLPC_INFO *info = dev_to_port(dev);
4485 struct net_device_stats *stats = hdlc_stats(dev);
4486 unsigned long flags;
4487
4488 if (debug_level >= DEBUG_LEVEL_INFO)
4489 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4490
4491 stats->tx_errors++;
4492 stats->tx_aborted_errors++;
4493
4494 spin_lock_irqsave(&info->lock,flags);
4495 tx_stop(info);
4496 spin_unlock_irqrestore(&info->lock,flags);
4497
4498 netif_wake_queue(dev);
4499 }
4500
4501 /**
4502 * called by device driver when transmit completes
4503 * reenable network layer transmit if stopped
4504 *
4505 * info pointer to device instance information
4506 */
4507 static void hdlcdev_tx_done(MGSLPC_INFO *info)
4508 {
4509 if (netif_queue_stopped(info->netdev))
4510 netif_wake_queue(info->netdev);
4511 }
4512
4513 /**
4514 * called by device driver when frame received
4515 * pass frame to network layer
4516 *
4517 * info pointer to device instance information
4518 * buf pointer to buffer contianing frame data
4519 * size count of data bytes in buf
4520 */
4521 static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4522 {
4523 struct sk_buff *skb = dev_alloc_skb(size);
4524 struct net_device *dev = info->netdev;
4525 struct net_device_stats *stats = hdlc_stats(dev);
4526
4527 if (debug_level >= DEBUG_LEVEL_INFO)
4528 printk("hdlcdev_rx(%s)\n",dev->name);
4529
4530 if (skb == NULL) {
4531 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
4532 stats->rx_dropped++;
4533 return;
4534 }
4535
4536 memcpy(skb_put(skb, size),buf,size);
4537
4538 skb->protocol = hdlc_type_trans(skb, info->netdev);
4539
4540 stats->rx_packets++;
4541 stats->rx_bytes += size;
4542
4543 netif_rx(skb);
4544
4545 info->netdev->last_rx = jiffies;
4546 }
4547
4548 /**
4549 * called by device driver when adding device instance
4550 * do generic HDLC initialization
4551 *
4552 * info pointer to device instance information
4553 *
4554 * returns 0 if success, otherwise error code
4555 */
4556 static int hdlcdev_init(MGSLPC_INFO *info)
4557 {
4558 int rc;
4559 struct net_device *dev;
4560 hdlc_device *hdlc;
4561
4562 /* allocate and initialize network and HDLC layer objects */
4563
4564 if (!(dev = alloc_hdlcdev(info))) {
4565 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4566 return -ENOMEM;
4567 }
4568
4569 /* for network layer reporting purposes only */
4570 dev->base_addr = info->io_base;
4571 dev->irq = info->irq_level;
4572
4573 /* network layer callbacks and settings */
4574 dev->do_ioctl = hdlcdev_ioctl;
4575 dev->open = hdlcdev_open;
4576 dev->stop = hdlcdev_close;
4577 dev->tx_timeout = hdlcdev_tx_timeout;
4578 dev->watchdog_timeo = 10*HZ;
4579 dev->tx_queue_len = 50;
4580
4581 /* generic HDLC layer callbacks and settings */
4582 hdlc = dev_to_hdlc(dev);
4583 hdlc->attach = hdlcdev_attach;
4584 hdlc->xmit = hdlcdev_xmit;
4585
4586 /* register objects with HDLC layer */
4587 if ((rc = register_hdlc_device(dev))) {
4588 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4589 free_netdev(dev);
4590 return rc;
4591 }
4592
4593 info->netdev = dev;
4594 return 0;
4595 }
4596
4597 /**
4598 * called by device driver when removing device instance
4599 * do generic HDLC cleanup
4600 *
4601 * info pointer to device instance information
4602 */
4603 static void hdlcdev_exit(MGSLPC_INFO *info)
4604 {
4605 unregister_hdlc_device(info->netdev);
4606 free_netdev(info->netdev);
4607 info->netdev = NULL;
4608 }
4609
4610 #endif /* CONFIG_HDLC */
4611
kernel source for telekom puls (alcatel/mediatek)