2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
15 #define MB (1024*1024)
23 #define MBCS_CM_ID 0x0000 /* Identification */
24 #define MBCS_CM_STATUS 0x0008 /* Status */
25 #define MBCS_CM_ERROR_DETAIL1 0x0010 /* Error Detail1 */
26 #define MBCS_CM_ERROR_DETAIL2 0x0018 /* Error Detail2 */
27 #define MBCS_CM_CONTROL 0x0020 /* Control */
28 #define MBCS_CM_REQ_TOUT 0x0028 /* Request Time-out */
29 #define MBCS_CM_ERR_INT_DEST 0x0038 /* Error Interrupt Destination */
30 #define MBCS_CM_TARG_FL 0x0050 /* Target Flush */
31 #define MBCS_CM_ERR_STAT 0x0060 /* Error Status */
32 #define MBCS_CM_CLR_ERR_STAT 0x0068 /* Clear Error Status */
33 #define MBCS_CM_ERR_INT_EN 0x0070 /* Error Interrupt Enable */
34 #define MBCS_RD_DMA_SYS_ADDR 0x0100 /* Read DMA System Address */
35 #define MBCS_RD_DMA_LOC_ADDR 0x0108 /* Read DMA Local Address */
36 #define MBCS_RD_DMA_CTRL 0x0110 /* Read DMA Control */
37 #define MBCS_RD_DMA_AMO_DEST 0x0118 /* Read DMA AMO Destination */
38 #define MBCS_RD_DMA_INT_DEST 0x0120 /* Read DMA Interrupt Destination */
39 #define MBCS_RD_DMA_AUX_STAT 0x0130 /* Read DMA Auxillary Status */
40 #define MBCS_WR_DMA_SYS_ADDR 0x0200 /* Write DMA System Address */
41 #define MBCS_WR_DMA_LOC_ADDR 0x0208 /* Write DMA Local Address */
42 #define MBCS_WR_DMA_CTRL 0x0210 /* Write DMA Control */
43 #define MBCS_WR_DMA_AMO_DEST 0x0218 /* Write DMA AMO Destination */
44 #define MBCS_WR_DMA_INT_DEST 0x0220 /* Write DMA Interrupt Destination */
45 #define MBCS_WR_DMA_AUX_STAT 0x0230 /* Write DMA Auxillary Status */
46 #define MBCS_ALG_AMO_DEST 0x0300 /* Algorithm AMO Destination */
47 #define MBCS_ALG_INT_DEST 0x0308 /* Algorithm Interrupt Destination */
48 #define MBCS_ALG_OFFSETS 0x0310
49 #define MBCS_ALG_STEP 0x0318 /* Algorithm Step */
51 #define MBCS_GSCR_START 0x0000000
52 #define MBCS_DEBUG_START 0x0100000
53 #define MBCS_RAM0_START 0x0200000
54 #define MBCS_RAM1_START 0x0400000
55 #define MBCS_RAM2_START 0x0600000
57 #define MBCS_CM_CONTROL_REQ_TOUT_MASK 0x0000000000ffffffUL
58 //#define PIO_BASE_ADDR_BASE_OFFSET_MASK 0x00fffffffff00000UL
60 #define MBCS_SRAM_SIZE (1024*1024)
61 #define MBCS_CACHELINE_SIZE 128
66 #define MBCS_MMR_ADDR(mmr_base, offset)((uint64_t *)(mmr_base + offset))
67 #define MBCS_MMR_SET(mmr_base, offset, value) { \
68 uint64_t *mbcs_mmr_set_u64p, readback; \
69 mbcs_mmr_set_u64p = (uint64_t *)(mmr_base + offset); \
70 *mbcs_mmr_set_u64p = value; \
71 readback = *mbcs_mmr_set_u64p; \
73 #define MBCS_MMR_GET(mmr_base, offset) *(uint64_t *)(mmr_base + offset)
74 #define MBCS_MMR_ZERO(mmr_base, offset) MBCS_MMR_SET(mmr_base, offset, 0)
82 uint64_t always_one
:1, // 0
85 bitstream_rev
:8, // 35:28
91 uint64_t cm_status_reg
;
93 uint64_t pending_reads
:8, // 7:0
94 pending_writes
:8, // 15:8
95 ice_rsp_credits
:8, // 23:16
96 ice_req_credits
:8, // 31:24
97 cm_req_credits
:8, // 39:32
99 rd_dma_in_progress
:1, // 41
102 wr_dma_in_progress
:1, // 44
105 alg_pipe_running
:1, // 47
108 pending_int_reqs
:8, // 59:52
110 alg_half_speed_sel
:1; // 63
114 union cm_error_detail1
{
115 uint64_t cm_error_detail1_reg
;
117 uint64_t packet_type
:4, // 3:0
121 byte_enable
:8, // 23:16
123 read_type
:2, // 33:32
124 pio_or_memory
:1, // 34
125 head_cw_error
:1, // 35
127 head_error_bit
:1, // 48
128 data_error_bit
:1, // 49
134 union cm_error_detail2
{
135 uint64_t cm_error_detail2_reg
;
137 uint64_t address
:56, // 55:0
143 uint64_t cm_control_reg
;
145 uint64_t cm_id
:2, // 1:0
149 address_mode
:1, // 12
151 credit_limit
:8, // 27:20
153 rearm_stat_regs
:1, // 33
154 prescalar_byp
:1, // 34
155 force_gap_war
:1, // 35
163 alg_wait_step
:1, // 44
164 alg_done_amo_en
:1, // 45
165 alg_done_int_en
:1, // 46
167 alg_sram0_locked
:1, // 48
168 alg_sram1_locked
:1, // 49
169 alg_sram2_locked
:1, // 50
170 alg_done_clr
:1, // 51
175 union cm_req_timeout
{
176 uint64_t cm_req_timeout_reg
;
178 uint64_t time_out
:24, // 23:0
184 uint64_t intr_dest_reg
;
186 uint64_t address
:56, // 55:0
187 int_vector
:8; // 63:56
191 union cm_error_status
{
192 uint64_t cm_error_status_reg
;
194 uint64_t ecc_sbe
:1, // 0
196 unsupported_req
:1, // 2
197 unexpected_rsp
:1, // 3
199 bad_datavalid
:1, // 5
200 buffer_overflow
:1, // 6
201 request_timeout
:1, // 7
203 head_inv_data_size
:1, // 16
204 rsp_pactype_inv
:1, // 17
206 missing_head
:1, // 19
207 head_inv_rd_type
:1, // 20
208 head_cmd_err_bit
:1, // 21
209 req_addr_align_inv
:1, // 22
210 pio_req_addr_inv
:1, // 23
211 req_range_dsize_inv
:1, // 24
214 missing_tail
:1, // 27
215 data_flit_sb_err
:1, // 28
216 cm2hcm_req_cred_of
:1, // 29
217 cm2hcm_rsp_cred_of
:1, // 30
219 rd_dma_err_rsp
:1, // 32
220 rd_dma_tnum_tout
:1, // 33
221 rd_dma_multi_tnum_tou
:1, // 34
222 wr_dma_err_rsp
:1, // 35
223 wr_dma_tnum_tout
:1, // 36
224 wr_dma_multi_tnum_tou
:1, // 37
225 alg_data_overflow
:1, // 38
226 alg_data_underflow
:1, // 39
227 ram0_access_conflict
:1, // 40
228 ram1_access_conflict
:1, // 41
229 ram2_access_conflict
:1, // 42
233 int_gen_rsp_err
:1, // 46
234 int_gen_tnum_tout
:1, // 47
235 rd_dma_prog_err
:1, // 48
236 wr_dma_prog_err
:1, // 49
241 union cm_clr_error_status
{
242 uint64_t cm_clr_error_status_reg
;
244 uint64_t clr_ecc_sbe
:1, // 0
246 clr_unsupported_req
:1, // 2
247 clr_unexpected_rsp
:1, // 3
248 clr_bad_length
:1, // 4
249 clr_bad_datavalid
:1, // 5
250 clr_buffer_overflow
:1, // 6
251 clr_request_timeout
:1, // 7
253 clr_head_inv_data_siz
:1, // 16
254 clr_rsp_pactype_inv
:1, // 17
255 clr_head_sb_err
:1, // 18
256 clr_missing_head
:1, // 19
257 clr_head_inv_rd_type
:1, // 20
258 clr_head_cmd_err_bit
:1, // 21
259 clr_req_addr_align_in
:1, // 22
260 clr_pio_req_addr_inv
:1, // 23
261 clr_req_range_dsize_i
:1, // 24
262 clr_early_term
:1, // 25
263 clr_early_tail
:1, // 26
264 clr_missing_tail
:1, // 27
265 clr_data_flit_sb_err
:1, // 28
266 clr_cm2hcm_req_cred_o
:1, // 29
267 clr_cm2hcm_rsp_cred_o
:1, // 30
268 clr_rx_bad_didn
:1, // 31
269 clr_rd_dma_err_rsp
:1, // 32
270 clr_rd_dma_tnum_tout
:1, // 33
271 clr_rd_dma_multi_tnum
:1, // 34
272 clr_wr_dma_err_rsp
:1, // 35
273 clr_wr_dma_tnum_tout
:1, // 36
274 clr_wr_dma_multi_tnum
:1, // 37
275 clr_alg_data_overflow
:1, // 38
276 clr_alg_data_underflo
:1, // 39
277 clr_ram0_access_confl
:1, // 40
278 clr_ram1_access_confl
:1, // 41
279 clr_ram2_access_confl
:1, // 42
280 clr_ram0_perr
:1, // 43
281 clr_ram1_perr
:1, // 44
282 clr_ram2_perr
:1, // 45
283 clr_int_gen_rsp_err
:1, // 46
284 clr_int_gen_tnum_tout
:1, // 47
285 clr_rd_dma_prog_err
:1, // 48
286 clr_wr_dma_prog_err
:1, // 49
291 union cm_error_intr_enable
{
292 uint64_t cm_error_intr_enable_reg
;
294 uint64_t int_en_ecc_sbe
:1, // 0
295 int_en_ecc_mbe
:1, // 1
296 int_en_unsupported_re
:1, // 2
297 int_en_unexpected_rsp
:1, // 3
298 int_en_bad_length
:1, // 4
299 int_en_bad_datavalid
:1, // 5
300 int_en_buffer_overflo
:1, // 6
301 int_en_request_timeou
:1, // 7
303 int_en_head_inv_data_
:1, // 16
304 int_en_rsp_pactype_in
:1, // 17
305 int_en_head_sb_err
:1, // 18
306 int_en_missing_head
:1, // 19
307 int_en_head_inv_rd_ty
:1, // 20
308 int_en_head_cmd_err_b
:1, // 21
309 int_en_req_addr_align
:1, // 22
310 int_en_pio_req_addr_i
:1, // 23
311 int_en_req_range_dsiz
:1, // 24
312 int_en_early_term
:1, // 25
313 int_en_early_tail
:1, // 26
314 int_en_missing_tail
:1, // 27
315 int_en_data_flit_sb_e
:1, // 28
316 int_en_cm2hcm_req_cre
:1, // 29
317 int_en_cm2hcm_rsp_cre
:1, // 30
318 int_en_rx_bad_didn
:1, // 31
319 int_en_rd_dma_err_rsp
:1, // 32
320 int_en_rd_dma_tnum_to
:1, // 33
321 int_en_rd_dma_multi_t
:1, // 34
322 int_en_wr_dma_err_rsp
:1, // 35
323 int_en_wr_dma_tnum_to
:1, // 36
324 int_en_wr_dma_multi_t
:1, // 37
325 int_en_alg_data_overf
:1, // 38
326 int_en_alg_data_under
:1, // 39
327 int_en_ram0_access_co
:1, // 40
328 int_en_ram1_access_co
:1, // 41
329 int_en_ram2_access_co
:1, // 42
330 int_en_ram0_perr
:1, // 43
331 int_en_ram1_perr
:1, // 44
332 int_en_ram2_perr
:1, // 45
333 int_en_int_gen_rsp_er
:1, // 46
334 int_en_int_gen_tnum_t
:1, // 47
335 int_en_rd_dma_prog_er
:1, // 48
336 int_en_wr_dma_prog_er
:1, // 49
343 union cm_status status
;
344 union cm_error_detail1 err_detail1
;
345 union cm_error_detail2 err_detail2
;
346 union cm_control control
;
347 union cm_req_timeout req_timeout
;
348 uint64_t reserved1
[1];
349 union intr_dest int_dest
;
350 uint64_t reserved2
[2];
352 uint64_t reserved3
[1];
353 union cm_error_status err_status
;
354 union cm_clr_error_status clr_err_status
;
355 union cm_error_intr_enable int_enable
;
359 uint64_t dma_hostaddr_reg
;
361 uint64_t dma_sys_addr
:56, // 55:0
366 union dma_localaddr
{
367 uint64_t dma_localaddr_reg
;
369 uint64_t dma_ram_addr
:21, // 20:0
370 dma_ram_sel
:2, // 22:21
376 uint64_t dma_control_reg
;
378 uint64_t dma_op_length
:16, // 15:0
389 uint64_t dma_amo_dest_reg
;
391 uint64_t dma_amo_sys_addr
:56, // 55:0
392 dma_amo_mod_type
:3, // 58:56
397 union rdma_aux_status
{
398 uint64_t rdma_aux_status_reg
;
400 uint64_t op_num_pacs_left
:17, // 16:0
402 lrsp_buff_empty
:1, // 22
404 pending_reqs_left
:6, // 45:40
410 union dma_hostaddr host_addr
;
411 union dma_localaddr local_addr
;
412 union dma_control control
;
413 union dma_amo_dest amo_dest
;
414 union intr_dest intr_dest
;
415 union rdma_aux_status aux_status
;
418 union wdma_aux_status
{
419 uint64_t wdma_aux_status_reg
;
421 uint64_t op_num_pacs_left
:17, // 16:0
423 lreq_buff_empty
:1, // 21
425 pending_reqs_left
:6, // 45:40
431 union dma_hostaddr host_addr
;
432 union dma_localaddr local_addr
;
433 union dma_control control
;
434 union dma_amo_dest amo_dest
;
435 union intr_dest intr_dest
;
436 union wdma_aux_status aux_status
;
440 uint64_t algo_step_reg
;
442 uint64_t alg_step_cnt
:16, // 15:0
448 union dma_amo_dest amo_dest
;
449 union intr_dest intr_dest
;
451 uint64_t algo_offset_reg
;
453 uint64_t sram0_offset
:7, // 6:0
455 sram1_offset
:7, // 14:8
457 sram2_offset
:7, // 22:16
458 reserved2
:14; // 63:23
461 union algo_step step
;
466 uint64_t reserved1
[17];
467 struct rdma_mmr rdDma
;
468 uint64_t reserved2
[25];
469 struct wdma_mmr wrDma
;
470 uint64_t reserved3
[25];
471 struct algo_mmr algo
;
472 uint64_t reserved4
[156];
478 #define DEVICE_NAME "mbcs"
479 #define MBCS_PART_NUM 0xfff0
480 #define MBCS_PART_NUM_ALG0 0xf001
481 #define MBCS_MFG_NUM 0x1
484 uint64_t amoHostDest
;
486 uint64_t intrHostDest
;
488 uint64_t algoStepCount
;
495 uint64_t DoneAmoEnable
;
496 uint64_t DoneIntEnable
;
498 uint64_t amoHostDest
;
500 uint64_t intrHostDest
;
508 uint64_t DoneAmoEnable
;
509 uint64_t DoneIntEnable
;
511 uint64_t amoHostDest
;
513 uint64_t intrHostDest
;
518 struct list_head list
;
519 struct cx_dev
*cxdev
;
523 wait_queue_head_t dmawrite_queue
;
524 wait_queue_head_t dmaread_queue
;
525 wait_queue_head_t algo_queue
;
526 struct sn_irq_info
*get_sn_irq
;
527 struct sn_irq_info
*put_sn_irq
;
528 struct sn_irq_info
*algo_sn_irq
;
529 struct getdma getdma
;
530 struct putdma putdma
;
531 struct algoblock algo
;
532 uint64_t gscr_addr
; // pio addr
533 uint64_t ram0_addr
; // pio addr
534 uint64_t ram1_addr
; // pio addr
535 uint64_t ram2_addr
; // pio addr
536 uint64_t debug_addr
; // pio addr
537 atomic_t dmawrite_done
;
538 atomic_t dmaread_done
;
540 struct mutex dmawritelock
;
541 struct semaphore dmareadlock
;
542 struct mutex algolock
;
545 static int mbcs_open(struct inode
*ip
, struct file
*fp
);
546 static ssize_t
mbcs_sram_read(struct file
*fp
, char __user
*buf
, size_t len
,
548 static ssize_t
mbcs_sram_write(struct file
*fp
, const char __user
*buf
, size_t len
,
550 static loff_t
mbcs_sram_llseek(struct file
*filp
, loff_t off
, int whence
);
551 static int mbcs_gscr_mmap(struct file
*fp
, struct vm_area_struct
*vma
);