1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
37 #define RADEON_FIFO_DEBUG 0
39 static int radeon_do_cleanup_cp(drm_device_t
* dev
);
41 /* CP microcode (from ATI) */
42 static u32 R200_cp_microcode
[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
301 static u32 radeon_cp_microcode
[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
560 static u32 R300_cp_microcode
[][2] = {
561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
819 static int RADEON_READ_PLL(drm_device_t
* dev
, int addr
)
821 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
823 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX
, addr
& 0x1f);
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA
);
827 static int RADEON_READ_PCIE(drm_radeon_private_t
* dev_priv
, int addr
)
829 RADEON_WRITE8(RADEON_PCIE_INDEX
, addr
& 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA
);
833 #if RADEON_FIFO_DEBUG
834 static void radeon_status(drm_radeon_private_t
* dev_priv
)
836 printk("%s:\n", __FUNCTION__
);
837 printk("RBBM_STATUS = 0x%08x\n",
838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS
));
839 printk("CP_RB_RTPR = 0x%08x\n",
840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR
));
841 printk("CP_RB_WTPR = 0x%08x\n",
842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR
));
843 printk("AIC_CNTL = 0x%08x\n",
844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL
));
845 printk("AIC_STAT = 0x%08x\n",
846 (unsigned int)RADEON_READ(RADEON_AIC_STAT
));
847 printk("AIC_PT_BASE = 0x%08x\n",
848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE
));
849 printk("TLB_ADDR = 0x%08x\n",
850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR
));
851 printk("TLB_DATA = 0x%08x\n",
852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA
));
856 /* ================================================================
857 * Engine, FIFO control
860 static int radeon_do_pixcache_flush(drm_radeon_private_t
* dev_priv
)
865 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
867 tmp
= RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT
);
868 tmp
|= RADEON_RB2D_DC_FLUSH_ALL
;
869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT
, tmp
);
871 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT
)
873 & RADEON_RB2D_DC_BUSY
)) {
879 #if RADEON_FIFO_DEBUG
880 DRM_ERROR("failed!\n");
881 radeon_status(dev_priv
);
883 return DRM_ERR(EBUSY
);
886 static int radeon_do_wait_for_fifo(drm_radeon_private_t
* dev_priv
, int entries
)
890 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
892 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
893 int slots
= (RADEON_READ(RADEON_RBBM_STATUS
)
894 & RADEON_RBBM_FIFOCNT_MASK
);
895 if (slots
>= entries
)
900 #if RADEON_FIFO_DEBUG
901 DRM_ERROR("failed!\n");
902 radeon_status(dev_priv
);
904 return DRM_ERR(EBUSY
);
907 static int radeon_do_wait_for_idle(drm_radeon_private_t
* dev_priv
)
911 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
913 ret
= radeon_do_wait_for_fifo(dev_priv
, 64);
917 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
918 if (!(RADEON_READ(RADEON_RBBM_STATUS
)
919 & RADEON_RBBM_ACTIVE
)) {
920 radeon_do_pixcache_flush(dev_priv
);
926 #if RADEON_FIFO_DEBUG
927 DRM_ERROR("failed!\n");
928 radeon_status(dev_priv
);
930 return DRM_ERR(EBUSY
);
933 /* ================================================================
934 * CP control, initialization
937 /* Load the microcode for the CP */
938 static void radeon_cp_load_microcode(drm_radeon_private_t
* dev_priv
)
943 radeon_do_wait_for_idle(dev_priv
);
945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR
, 0);
947 if (dev_priv
->microcode_version
== UCODE_R200
) {
948 DRM_INFO("Loading R200 Microcode\n");
949 for (i
= 0; i
< 256; i
++) {
950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
951 R200_cp_microcode
[i
][1]);
952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
953 R200_cp_microcode
[i
][0]);
955 } else if (dev_priv
->microcode_version
== UCODE_R300
) {
956 DRM_INFO("Loading R300 Microcode\n");
957 for (i
= 0; i
< 256; i
++) {
958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
959 R300_cp_microcode
[i
][1]);
960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
961 R300_cp_microcode
[i
][0]);
964 for (i
= 0; i
< 256; i
++) {
965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH
,
966 radeon_cp_microcode
[i
][1]);
967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL
,
968 radeon_cp_microcode
[i
][0]);
973 /* Flush any pending commands to the CP. This should only be used just
974 * prior to a wait for idle, as it informs the engine that the command
977 static void radeon_do_cp_flush(drm_radeon_private_t
* dev_priv
)
983 tmp
= RADEON_READ(RADEON_CP_RB_WPTR
) | (1 << 31);
984 RADEON_WRITE(RADEON_CP_RB_WPTR
, tmp
);
988 /* Wait for the CP to go idle.
990 int radeon_do_cp_idle(drm_radeon_private_t
* dev_priv
)
997 RADEON_PURGE_CACHE();
998 RADEON_PURGE_ZCACHE();
999 RADEON_WAIT_UNTIL_IDLE();
1004 return radeon_do_wait_for_idle(dev_priv
);
1007 /* Start the Command Processor.
1009 static void radeon_do_cp_start(drm_radeon_private_t
* dev_priv
)
1014 radeon_do_wait_for_idle(dev_priv
);
1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, dev_priv
->cp_mode
);
1018 dev_priv
->cp_running
= 1;
1022 RADEON_PURGE_CACHE();
1023 RADEON_PURGE_ZCACHE();
1024 RADEON_WAIT_UNTIL_IDLE();
1030 /* Reset the Command Processor. This will not flush any pending
1031 * commands, so you must wait for the CP command stream to complete
1032 * before calling this routine.
1034 static void radeon_do_cp_reset(drm_radeon_private_t
* dev_priv
)
1039 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
1040 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
1041 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
1042 dev_priv
->ring
.tail
= cur_read_ptr
;
1045 /* Stop the Command Processor. This will not flush any pending
1046 * commands, so you must flush the command stream and wait for the CP
1047 * to go idle before calling this routine.
1049 static void radeon_do_cp_stop(drm_radeon_private_t
* dev_priv
)
1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIDIS_INDDIS
);
1055 dev_priv
->cp_running
= 0;
1058 /* Reset the engine. This will stop the CP if it is running.
1060 static int radeon_do_engine_reset(drm_device_t
* dev
)
1062 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1063 u32 clock_cntl_index
, mclk_cntl
, rbbm_soft_reset
;
1066 radeon_do_pixcache_flush(dev_priv
);
1068 clock_cntl_index
= RADEON_READ(RADEON_CLOCK_CNTL_INDEX
);
1069 mclk_cntl
= RADEON_READ_PLL(dev
, RADEON_MCLK_CNTL
);
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, (mclk_cntl
|
1072 RADEON_FORCEON_MCLKA
|
1073 RADEON_FORCEON_MCLKB
|
1074 RADEON_FORCEON_YCLKA
|
1075 RADEON_FORCEON_YCLKB
|
1077 RADEON_FORCEON_AIC
));
1079 rbbm_soft_reset
= RADEON_READ(RADEON_RBBM_SOFT_RESET
);
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
|
1082 RADEON_SOFT_RESET_CP
|
1083 RADEON_SOFT_RESET_HI
|
1084 RADEON_SOFT_RESET_SE
|
1085 RADEON_SOFT_RESET_RE
|
1086 RADEON_SOFT_RESET_PP
|
1087 RADEON_SOFT_RESET_E2
|
1088 RADEON_SOFT_RESET_RB
));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, (rbbm_soft_reset
&
1091 ~(RADEON_SOFT_RESET_CP
|
1092 RADEON_SOFT_RESET_HI
|
1093 RADEON_SOFT_RESET_SE
|
1094 RADEON_SOFT_RESET_RE
|
1095 RADEON_SOFT_RESET_PP
|
1096 RADEON_SOFT_RESET_E2
|
1097 RADEON_SOFT_RESET_RB
)));
1098 RADEON_READ(RADEON_RBBM_SOFT_RESET
);
1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL
, mclk_cntl
);
1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX
, clock_cntl_index
);
1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET
, rbbm_soft_reset
);
1104 /* Reset the CP ring */
1105 radeon_do_cp_reset(dev_priv
);
1107 /* The CP is no longer running after an engine reset */
1108 dev_priv
->cp_running
= 0;
1110 /* Reset any pending vertex, indirect buffers */
1111 radeon_freelist_reset(dev
);
1116 static void radeon_cp_init_ring_buffer(drm_device_t
* dev
,
1117 drm_radeon_private_t
* dev_priv
)
1119 u32 ring_start
, cur_read_ptr
;
1122 /* Initialize the memory controller */
1123 RADEON_WRITE(RADEON_MC_FB_LOCATION
,
1124 ((dev_priv
->gart_vm_start
- 1) & 0xffff0000)
1125 | (dev_priv
->fb_location
>> 16));
1128 if (!dev_priv
->is_pci
) {
1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION
,
1130 (((dev_priv
->gart_vm_start
- 1 +
1131 dev_priv
->gart_size
) & 0xffff0000) |
1132 (dev_priv
->gart_vm_start
>> 16)));
1134 ring_start
= (dev_priv
->cp_ring
->offset
1136 + dev_priv
->gart_vm_start
);
1139 ring_start
= (dev_priv
->cp_ring
->offset
1140 - (unsigned long)dev
->sg
->virtual
1141 + dev_priv
->gart_vm_start
);
1143 RADEON_WRITE(RADEON_CP_RB_BASE
, ring_start
);
1145 /* Set the write pointer delay */
1146 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY
, 0);
1148 /* Initialize the ring buffer's read and write pointers */
1149 cur_read_ptr
= RADEON_READ(RADEON_CP_RB_RPTR
);
1150 RADEON_WRITE(RADEON_CP_RB_WPTR
, cur_read_ptr
);
1151 SET_RING_HEAD(dev_priv
, cur_read_ptr
);
1152 dev_priv
->ring
.tail
= cur_read_ptr
;
1155 if (!dev_priv
->is_pci
) {
1156 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1157 RADEON_WRITE(RADEON_AGP_BASE
, (unsigned int)dev
->agp
->base
);
1158 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
,
1159 dev_priv
->ring_rptr
->offset
1160 - dev
->agp
->base
+ dev_priv
->gart_vm_start
);
1164 drm_sg_mem_t
*entry
= dev
->sg
;
1165 unsigned long tmp_ofs
, page_ofs
;
1167 tmp_ofs
= dev_priv
->ring_rptr
->offset
-
1168 (unsigned long)dev
->sg
->virtual;
1169 page_ofs
= tmp_ofs
>> PAGE_SHIFT
;
1171 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR
, entry
->busaddr
[page_ofs
]);
1172 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1173 (unsigned long)entry
->busaddr
[page_ofs
],
1174 entry
->handle
+ tmp_ofs
);
1177 /* Initialize the scratch register pointer. This will cause
1178 * the scratch register values to be written out to memory
1179 * whenever they are updated.
1181 * We simply put this behind the ring read pointer, this works
1182 * with PCI GART as well as (whatever kind of) AGP GART
1184 RADEON_WRITE(RADEON_SCRATCH_ADDR
, RADEON_READ(RADEON_CP_RB_RPTR_ADDR
)
1185 + RADEON_SCRATCH_REG_OFFSET
);
1187 dev_priv
->scratch
= ((__volatile__ u32
*)
1188 dev_priv
->ring_rptr
->handle
+
1189 (RADEON_SCRATCH_REG_OFFSET
/ sizeof(u32
)));
1191 RADEON_WRITE(RADEON_SCRATCH_UMSK
, 0x7);
1193 /* Writeback doesn't seem to work everywhere, test it first */
1194 DRM_WRITE32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1), 0);
1195 RADEON_WRITE(RADEON_SCRATCH_REG1
, 0xdeadbeef);
1197 for (tmp
= 0; tmp
< dev_priv
->usec_timeout
; tmp
++) {
1198 if (DRM_READ32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1)) ==
1204 if (tmp
< dev_priv
->usec_timeout
) {
1205 dev_priv
->writeback_works
= 1;
1206 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp
);
1208 dev_priv
->writeback_works
= 0;
1209 DRM_DEBUG("writeback test failed\n");
1211 if (radeon_no_wb
== 1) {
1212 dev_priv
->writeback_works
= 0;
1213 DRM_DEBUG("writeback forced off\n");
1216 dev_priv
->sarea_priv
->last_frame
= dev_priv
->scratch
[0] = 0;
1217 RADEON_WRITE(RADEON_LAST_FRAME_REG
, dev_priv
->sarea_priv
->last_frame
);
1219 dev_priv
->sarea_priv
->last_dispatch
= dev_priv
->scratch
[1] = 0;
1220 RADEON_WRITE(RADEON_LAST_DISPATCH_REG
,
1221 dev_priv
->sarea_priv
->last_dispatch
);
1223 dev_priv
->sarea_priv
->last_clear
= dev_priv
->scratch
[2] = 0;
1224 RADEON_WRITE(RADEON_LAST_CLEAR_REG
, dev_priv
->sarea_priv
->last_clear
);
1226 /* Set ring buffer size */
1228 RADEON_WRITE(RADEON_CP_RB_CNTL
,
1229 dev_priv
->ring
.size_l2qw
| RADEON_BUF_SWAP_32BIT
);
1231 RADEON_WRITE(RADEON_CP_RB_CNTL
, dev_priv
->ring
.size_l2qw
);
1234 radeon_do_wait_for_idle(dev_priv
);
1236 /* Turn on bus mastering */
1237 tmp
= RADEON_READ(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
1238 RADEON_WRITE(RADEON_BUS_CNTL
, tmp
);
1240 /* Sync everything up */
1241 RADEON_WRITE(RADEON_ISYNC_CNTL
,
1242 (RADEON_ISYNC_ANY2D_IDLE3D
|
1243 RADEON_ISYNC_ANY3D_IDLE2D
|
1244 RADEON_ISYNC_WAIT_IDLEGUI
|
1245 RADEON_ISYNC_CPSCRATCH_IDLEGUI
));
1248 /* Enable or disable PCI-E GART on the chip */
1249 static void radeon_set_pciegart(drm_radeon_private_t
* dev_priv
, int on
)
1251 u32 tmp
= RADEON_READ_PCIE(dev_priv
, RADEON_PCIE_TX_GART_CNTL
);
1254 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1255 dev_priv
->gart_vm_start
,
1256 (long)dev_priv
->gart_info
.bus_addr
,
1257 dev_priv
->gart_size
);
1258 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
,
1259 dev_priv
->gart_vm_start
);
1260 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE
,
1261 dev_priv
->gart_info
.bus_addr
);
1262 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO
,
1263 dev_priv
->gart_vm_start
);
1264 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO
,
1265 dev_priv
->gart_vm_start
+
1266 dev_priv
->gart_size
- 1);
1268 RADEON_WRITE(RADEON_MC_AGP_LOCATION
, 0xffffffc0); /* ?? */
1270 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
1271 RADEON_PCIE_TX_GART_EN
);
1273 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL
,
1274 tmp
& ~RADEON_PCIE_TX_GART_EN
);
1278 /* Enable or disable PCI GART on the chip */
1279 static void radeon_set_pcigart(drm_radeon_private_t
* dev_priv
, int on
)
1281 u32 tmp
= RADEON_READ(RADEON_AIC_CNTL
);
1283 if (dev_priv
->flags
& CHIP_IS_PCIE
) {
1284 radeon_set_pciegart(dev_priv
, on
);
1289 RADEON_WRITE(RADEON_AIC_CNTL
,
1290 tmp
| RADEON_PCIGART_TRANSLATE_EN
);
1292 /* set PCI GART page-table base address
1294 RADEON_WRITE(RADEON_AIC_PT_BASE
, dev_priv
->gart_info
.bus_addr
);
1296 /* set address range for PCI address translate
1298 RADEON_WRITE(RADEON_AIC_LO_ADDR
, dev_priv
->gart_vm_start
);
1299 RADEON_WRITE(RADEON_AIC_HI_ADDR
, dev_priv
->gart_vm_start
1300 + dev_priv
->gart_size
- 1);
1302 /* Turn off AGP aperture -- is this required for PCI GART?
1304 RADEON_WRITE(RADEON_MC_AGP_LOCATION
, 0xffffffc0); /* ?? */
1305 RADEON_WRITE(RADEON_AGP_COMMAND
, 0); /* clear AGP_COMMAND */
1307 RADEON_WRITE(RADEON_AIC_CNTL
,
1308 tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
1312 static int radeon_do_init_cp(drm_device_t
* dev
, drm_radeon_init_t
* init
)
1314 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1317 dev_priv
->is_pci
= init
->is_pci
;
1319 if (dev_priv
->is_pci
&& !dev
->sg
) {
1320 DRM_ERROR("PCI GART memory not allocated!\n");
1321 dev
->dev_private
= (void *)dev_priv
;
1322 radeon_do_cleanup_cp(dev
);
1323 return DRM_ERR(EINVAL
);
1326 dev_priv
->usec_timeout
= init
->usec_timeout
;
1327 if (dev_priv
->usec_timeout
< 1 ||
1328 dev_priv
->usec_timeout
> RADEON_MAX_USEC_TIMEOUT
) {
1329 DRM_DEBUG("TIMEOUT problem!\n");
1330 dev
->dev_private
= (void *)dev_priv
;
1331 radeon_do_cleanup_cp(dev
);
1332 return DRM_ERR(EINVAL
);
1335 switch (init
->func
) {
1336 case RADEON_INIT_R200_CP
:
1337 dev_priv
->microcode_version
= UCODE_R200
;
1339 case RADEON_INIT_R300_CP
:
1340 dev_priv
->microcode_version
= UCODE_R300
;
1343 dev_priv
->microcode_version
= UCODE_R100
;
1346 dev_priv
->do_boxes
= 0;
1347 dev_priv
->cp_mode
= init
->cp_mode
;
1349 /* We don't support anything other than bus-mastering ring mode,
1350 * but the ring can be in either AGP or PCI space for the ring
1353 if ((init
->cp_mode
!= RADEON_CSQ_PRIBM_INDDIS
) &&
1354 (init
->cp_mode
!= RADEON_CSQ_PRIBM_INDBM
)) {
1355 DRM_DEBUG("BAD cp_mode (%x)!\n", init
->cp_mode
);
1356 dev
->dev_private
= (void *)dev_priv
;
1357 radeon_do_cleanup_cp(dev
);
1358 return DRM_ERR(EINVAL
);
1361 switch (init
->fb_bpp
) {
1363 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
1367 dev_priv
->color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
1370 dev_priv
->front_offset
= init
->front_offset
;
1371 dev_priv
->front_pitch
= init
->front_pitch
;
1372 dev_priv
->back_offset
= init
->back_offset
;
1373 dev_priv
->back_pitch
= init
->back_pitch
;
1375 switch (init
->depth_bpp
) {
1377 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
1381 dev_priv
->depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
1384 dev_priv
->depth_offset
= init
->depth_offset
;
1385 dev_priv
->depth_pitch
= init
->depth_pitch
;
1387 /* Hardware state for depth clears. Remove this if/when we no
1388 * longer clear the depth buffer with a 3D rectangle. Hard-code
1389 * all values to prevent unwanted 3D state from slipping through
1390 * and screwing with the clear operation.
1392 dev_priv
->depth_clear
.rb3d_cntl
= (RADEON_PLANE_MASK_ENABLE
|
1393 (dev_priv
->color_fmt
<< 10) |
1394 (dev_priv
->microcode_version
==
1395 UCODE_R100
? RADEON_ZBLOCK16
: 0));
1397 dev_priv
->depth_clear
.rb3d_zstencilcntl
=
1398 (dev_priv
->depth_fmt
|
1399 RADEON_Z_TEST_ALWAYS
|
1400 RADEON_STENCIL_TEST_ALWAYS
|
1401 RADEON_STENCIL_S_FAIL_REPLACE
|
1402 RADEON_STENCIL_ZPASS_REPLACE
|
1403 RADEON_STENCIL_ZFAIL_REPLACE
| RADEON_Z_WRITE_ENABLE
);
1405 dev_priv
->depth_clear
.se_cntl
= (RADEON_FFACE_CULL_CW
|
1406 RADEON_BFACE_SOLID
|
1407 RADEON_FFACE_SOLID
|
1408 RADEON_FLAT_SHADE_VTX_LAST
|
1409 RADEON_DIFFUSE_SHADE_FLAT
|
1410 RADEON_ALPHA_SHADE_FLAT
|
1411 RADEON_SPECULAR_SHADE_FLAT
|
1412 RADEON_FOG_SHADE_FLAT
|
1413 RADEON_VTX_PIX_CENTER_OGL
|
1414 RADEON_ROUND_MODE_TRUNC
|
1415 RADEON_ROUND_PREC_8TH_PIX
);
1419 dev_priv
->fb_offset
= init
->fb_offset
;
1420 dev_priv
->mmio_offset
= init
->mmio_offset
;
1421 dev_priv
->ring_offset
= init
->ring_offset
;
1422 dev_priv
->ring_rptr_offset
= init
->ring_rptr_offset
;
1423 dev_priv
->buffers_offset
= init
->buffers_offset
;
1424 dev_priv
->gart_textures_offset
= init
->gart_textures_offset
;
1426 if (!dev_priv
->sarea
) {
1427 DRM_ERROR("could not find sarea!\n");
1428 dev
->dev_private
= (void *)dev_priv
;
1429 radeon_do_cleanup_cp(dev
);
1430 return DRM_ERR(EINVAL
);
1433 dev_priv
->mmio
= drm_core_findmap(dev
, init
->mmio_offset
);
1434 if (!dev_priv
->mmio
) {
1435 DRM_ERROR("could not find mmio region!\n");
1436 dev
->dev_private
= (void *)dev_priv
;
1437 radeon_do_cleanup_cp(dev
);
1438 return DRM_ERR(EINVAL
);
1440 dev_priv
->cp_ring
= drm_core_findmap(dev
, init
->ring_offset
);
1441 if (!dev_priv
->cp_ring
) {
1442 DRM_ERROR("could not find cp ring region!\n");
1443 dev
->dev_private
= (void *)dev_priv
;
1444 radeon_do_cleanup_cp(dev
);
1445 return DRM_ERR(EINVAL
);
1447 dev_priv
->ring_rptr
= drm_core_findmap(dev
, init
->ring_rptr_offset
);
1448 if (!dev_priv
->ring_rptr
) {
1449 DRM_ERROR("could not find ring read pointer!\n");
1450 dev
->dev_private
= (void *)dev_priv
;
1451 radeon_do_cleanup_cp(dev
);
1452 return DRM_ERR(EINVAL
);
1454 dev
->agp_buffer_token
= init
->buffers_offset
;
1455 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
1456 if (!dev
->agp_buffer_map
) {
1457 DRM_ERROR("could not find dma buffer region!\n");
1458 dev
->dev_private
= (void *)dev_priv
;
1459 radeon_do_cleanup_cp(dev
);
1460 return DRM_ERR(EINVAL
);
1463 if (init
->gart_textures_offset
) {
1464 dev_priv
->gart_textures
=
1465 drm_core_findmap(dev
, init
->gart_textures_offset
);
1466 if (!dev_priv
->gart_textures
) {
1467 DRM_ERROR("could not find GART texture region!\n");
1468 dev
->dev_private
= (void *)dev_priv
;
1469 radeon_do_cleanup_cp(dev
);
1470 return DRM_ERR(EINVAL
);
1474 dev_priv
->sarea_priv
=
1475 (drm_radeon_sarea_t
*) ((u8
*) dev_priv
->sarea
->handle
+
1476 init
->sarea_priv_offset
);
1479 if (!dev_priv
->is_pci
) {
1480 drm_core_ioremap(dev_priv
->cp_ring
, dev
);
1481 drm_core_ioremap(dev_priv
->ring_rptr
, dev
);
1482 drm_core_ioremap(dev
->agp_buffer_map
, dev
);
1483 if (!dev_priv
->cp_ring
->handle
||
1484 !dev_priv
->ring_rptr
->handle
||
1485 !dev
->agp_buffer_map
->handle
) {
1486 DRM_ERROR("could not find ioremap agp regions!\n");
1487 dev
->dev_private
= (void *)dev_priv
;
1488 radeon_do_cleanup_cp(dev
);
1489 return DRM_ERR(EINVAL
);
1494 dev_priv
->cp_ring
->handle
= (void *)dev_priv
->cp_ring
->offset
;
1495 dev_priv
->ring_rptr
->handle
=
1496 (void *)dev_priv
->ring_rptr
->offset
;
1497 dev
->agp_buffer_map
->handle
=
1498 (void *)dev
->agp_buffer_map
->offset
;
1500 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1501 dev_priv
->cp_ring
->handle
);
1502 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1503 dev_priv
->ring_rptr
->handle
);
1504 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1505 dev
->agp_buffer_map
->handle
);
1508 dev_priv
->fb_location
= (RADEON_READ(RADEON_MC_FB_LOCATION
)
1511 dev_priv
->front_pitch_offset
= (((dev_priv
->front_pitch
/ 64) << 22) |
1512 ((dev_priv
->front_offset
1513 + dev_priv
->fb_location
) >> 10));
1515 dev_priv
->back_pitch_offset
= (((dev_priv
->back_pitch
/ 64) << 22) |
1516 ((dev_priv
->back_offset
1517 + dev_priv
->fb_location
) >> 10));
1519 dev_priv
->depth_pitch_offset
= (((dev_priv
->depth_pitch
/ 64) << 22) |
1520 ((dev_priv
->depth_offset
1521 + dev_priv
->fb_location
) >> 10));
1523 dev_priv
->gart_size
= init
->gart_size
;
1524 dev_priv
->gart_vm_start
= dev_priv
->fb_location
1525 + RADEON_READ(RADEON_CONFIG_APER_SIZE
);
1528 if (!dev_priv
->is_pci
)
1529 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1531 + dev_priv
->gart_vm_start
);
1534 dev_priv
->gart_buffers_offset
= (dev
->agp_buffer_map
->offset
1535 - (unsigned long)dev
->sg
->virtual
1536 + dev_priv
->gart_vm_start
);
1538 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv
->gart_size
);
1539 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv
->gart_vm_start
);
1540 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1541 dev_priv
->gart_buffers_offset
);
1543 dev_priv
->ring
.start
= (u32
*) dev_priv
->cp_ring
->handle
;
1544 dev_priv
->ring
.end
= ((u32
*) dev_priv
->cp_ring
->handle
1545 + init
->ring_size
/ sizeof(u32
));
1546 dev_priv
->ring
.size
= init
->ring_size
;
1547 dev_priv
->ring
.size_l2qw
= drm_order(init
->ring_size
/ 8);
1549 dev_priv
->ring
.tail_mask
= (dev_priv
->ring
.size
/ sizeof(u32
)) - 1;
1551 dev_priv
->ring
.high_mark
= RADEON_RING_HIGH_MARK
;
1554 if (!dev_priv
->is_pci
) {
1555 /* Turn off PCI GART */
1556 radeon_set_pcigart(dev_priv
, 0);
1560 /* if we have an offset set from userspace */
1561 if (dev_priv
->pcigart_offset
) {
1562 dev_priv
->gart_info
.bus_addr
=
1563 dev_priv
->pcigart_offset
+ dev_priv
->fb_location
;
1564 dev_priv
->gart_info
.addr
=
1565 (unsigned long)drm_ioremap(dev_priv
->gart_info
.
1567 RADEON_PCIGART_TABLE_SIZE
,
1570 dev_priv
->gart_info
.is_pcie
=
1571 !!(dev_priv
->flags
& CHIP_IS_PCIE
);
1572 dev_priv
->gart_info
.gart_table_location
=
1575 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n",
1576 dev_priv
->gart_info
.addr
,
1577 dev_priv
->pcigart_offset
);
1579 dev_priv
->gart_info
.gart_table_location
=
1581 dev_priv
->gart_info
.addr
=
1582 dev_priv
->gart_info
.bus_addr
= 0;
1583 if (dev_priv
->flags
& CHIP_IS_PCIE
) {
1585 ("Cannot use PCI Express without GART in FB memory\n");
1586 radeon_do_cleanup_cp(dev
);
1587 return DRM_ERR(EINVAL
);
1591 if (!drm_ati_pcigart_init(dev
, &dev_priv
->gart_info
)) {
1592 DRM_ERROR("failed to init PCI GART!\n");
1593 dev
->dev_private
= (void *)dev_priv
;
1594 radeon_do_cleanup_cp(dev
);
1595 return DRM_ERR(ENOMEM
);
1598 /* Turn on PCI GART */
1599 radeon_set_pcigart(dev_priv
, 1);
1602 radeon_cp_load_microcode(dev_priv
);
1603 radeon_cp_init_ring_buffer(dev
, dev_priv
);
1605 dev_priv
->last_buf
= 0;
1607 dev
->dev_private
= (void *)dev_priv
;
1609 radeon_do_engine_reset(dev
);
1614 static int radeon_do_cleanup_cp(drm_device_t
* dev
)
1616 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1619 /* Make sure interrupts are disabled here because the uninstall ioctl
1620 * may not have been called from userspace and after dev_private
1621 * is freed, it's too late.
1623 if (dev
->irq_enabled
)
1624 drm_irq_uninstall(dev
);
1627 if (!dev_priv
->is_pci
) {
1628 if (dev_priv
->cp_ring
!= NULL
)
1629 drm_core_ioremapfree(dev_priv
->cp_ring
, dev
);
1630 if (dev_priv
->ring_rptr
!= NULL
)
1631 drm_core_ioremapfree(dev_priv
->ring_rptr
, dev
);
1632 if (dev
->agp_buffer_map
!= NULL
) {
1633 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
1634 dev
->agp_buffer_map
= NULL
;
1639 if (dev_priv
->gart_info
.bus_addr
)
1640 if (!drm_ati_pcigart_cleanup(dev
, &dev_priv
->gart_info
))
1641 DRM_ERROR("failed to cleanup PCI GART!\n");
1643 if (dev_priv
->gart_info
.gart_table_location
== DRM_ATI_GART_FB
) {
1644 drm_ioremapfree((void *)dev_priv
->gart_info
.addr
,
1645 RADEON_PCIGART_TABLE_SIZE
, dev
);
1646 dev_priv
->gart_info
.addr
= 0;
1650 /* only clear to the start of flags */
1651 memset(dev_priv
, 0, offsetof(drm_radeon_private_t
, flags
));
1656 /* This code will reinit the Radeon CP hardware after a resume from disc.
1657 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1658 * here we make sure that all Radeon hardware initialisation is re-done without
1659 * affecting running applications.
1661 * Charl P. Botha <http://cpbotha.net>
1663 static int radeon_do_resume_cp(drm_device_t
* dev
)
1665 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1668 DRM_ERROR("Called with no initialization\n");
1669 return DRM_ERR(EINVAL
);
1672 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1675 if (!dev_priv
->is_pci
) {
1676 /* Turn off PCI GART */
1677 radeon_set_pcigart(dev_priv
, 0);
1681 /* Turn on PCI GART */
1682 radeon_set_pcigart(dev_priv
, 1);
1685 radeon_cp_load_microcode(dev_priv
);
1686 radeon_cp_init_ring_buffer(dev
, dev_priv
);
1688 radeon_do_engine_reset(dev
);
1690 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1695 int radeon_cp_init(DRM_IOCTL_ARGS
)
1698 drm_radeon_init_t init
;
1700 LOCK_TEST_WITH_RETURN(dev
, filp
);
1702 DRM_COPY_FROM_USER_IOCTL(init
, (drm_radeon_init_t __user
*) data
,
1705 if (init
.func
== RADEON_INIT_R300_CP
)
1706 r300_init_reg_flags();
1708 switch (init
.func
) {
1709 case RADEON_INIT_CP
:
1710 case RADEON_INIT_R200_CP
:
1711 case RADEON_INIT_R300_CP
:
1712 return radeon_do_init_cp(dev
, &init
);
1713 case RADEON_CLEANUP_CP
:
1714 return radeon_do_cleanup_cp(dev
);
1717 return DRM_ERR(EINVAL
);
1720 int radeon_cp_start(DRM_IOCTL_ARGS
)
1723 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1726 LOCK_TEST_WITH_RETURN(dev
, filp
);
1728 if (dev_priv
->cp_running
) {
1729 DRM_DEBUG("%s while CP running\n", __FUNCTION__
);
1732 if (dev_priv
->cp_mode
== RADEON_CSQ_PRIDIS_INDDIS
) {
1733 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1734 __FUNCTION__
, dev_priv
->cp_mode
);
1738 radeon_do_cp_start(dev_priv
);
1743 /* Stop the CP. The engine must have been idled before calling this
1746 int radeon_cp_stop(DRM_IOCTL_ARGS
)
1749 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1750 drm_radeon_cp_stop_t stop
;
1754 LOCK_TEST_WITH_RETURN(dev
, filp
);
1756 DRM_COPY_FROM_USER_IOCTL(stop
, (drm_radeon_cp_stop_t __user
*) data
,
1759 if (!dev_priv
->cp_running
)
1762 /* Flush any pending CP commands. This ensures any outstanding
1763 * commands are exectuted by the engine before we turn it off.
1766 radeon_do_cp_flush(dev_priv
);
1769 /* If we fail to make the engine go idle, we return an error
1770 * code so that the DRM ioctl wrapper can try again.
1773 ret
= radeon_do_cp_idle(dev_priv
);
1778 /* Finally, we can turn off the CP. If the engine isn't idle,
1779 * we will get some dropped triangles as they won't be fully
1780 * rendered before the CP is shut down.
1782 radeon_do_cp_stop(dev_priv
);
1784 /* Reset the engine */
1785 radeon_do_engine_reset(dev
);
1790 void radeon_do_release(drm_device_t
* dev
)
1792 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1796 if (dev_priv
->cp_running
) {
1798 while ((ret
= radeon_do_cp_idle(dev_priv
)) != 0) {
1799 DRM_DEBUG("radeon_do_cp_idle %d\n", ret
);
1803 tsleep(&ret
, PZERO
, "rdnrel", 1);
1806 radeon_do_cp_stop(dev_priv
);
1807 radeon_do_engine_reset(dev
);
1810 /* Disable *all* interrupts */
1811 if (dev_priv
->mmio
) /* remove this after permanent addmaps */
1812 RADEON_WRITE(RADEON_GEN_INT_CNTL
, 0);
1814 if (dev_priv
->mmio
) { /* remove all surfaces */
1815 for (i
= 0; i
< RADEON_MAX_SURFACES
; i
++) {
1816 RADEON_WRITE(RADEON_SURFACE0_INFO
+ 16 * i
, 0);
1817 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND
+
1819 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND
+
1824 /* Free memory heap structures */
1825 radeon_mem_takedown(&(dev_priv
->gart_heap
));
1826 radeon_mem_takedown(&(dev_priv
->fb_heap
));
1828 /* deallocate kernel resources */
1829 radeon_do_cleanup_cp(dev
);
1833 /* Just reset the CP ring. Called as part of an X Server engine reset.
1835 int radeon_cp_reset(DRM_IOCTL_ARGS
)
1838 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1841 LOCK_TEST_WITH_RETURN(dev
, filp
);
1844 DRM_DEBUG("%s called before init done\n", __FUNCTION__
);
1845 return DRM_ERR(EINVAL
);
1848 radeon_do_cp_reset(dev_priv
);
1850 /* The CP is no longer running after an engine reset */
1851 dev_priv
->cp_running
= 0;
1856 int radeon_cp_idle(DRM_IOCTL_ARGS
)
1859 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1862 LOCK_TEST_WITH_RETURN(dev
, filp
);
1864 return radeon_do_cp_idle(dev_priv
);
1867 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1869 int radeon_cp_resume(DRM_IOCTL_ARGS
)
1873 return radeon_do_resume_cp(dev
);
1876 int radeon_engine_reset(DRM_IOCTL_ARGS
)
1881 LOCK_TEST_WITH_RETURN(dev
, filp
);
1883 return radeon_do_engine_reset(dev
);
1886 /* ================================================================
1890 /* KW: Deprecated to say the least:
1892 int radeon_fullscreen(DRM_IOCTL_ARGS
)
1897 /* ================================================================
1898 * Freelist management
1901 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1902 * bufs until freelist code is used. Note this hides a problem with
1903 * the scratch register * (used to keep track of last buffer
1904 * completed) being written to before * the last buffer has actually
1905 * completed rendering.
1907 * KW: It's also a good way to find free buffers quickly.
1909 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1910 * sleep. However, bugs in older versions of radeon_accel.c mean that
1911 * we essentially have to do this, else old clients will break.
1913 * However, it does leave open a potential deadlock where all the
1914 * buffers are held by other clients, which can't release them because
1915 * they can't get the lock.
1918 drm_buf_t
*radeon_freelist_get(drm_device_t
* dev
)
1920 drm_device_dma_t
*dma
= dev
->dma
;
1921 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1922 drm_radeon_buf_priv_t
*buf_priv
;
1927 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1928 dev_priv
->last_buf
= 0;
1930 start
= dev_priv
->last_buf
;
1932 for (t
= 0; t
< dev_priv
->usec_timeout
; t
++) {
1933 u32 done_age
= GET_SCRATCH(1);
1934 DRM_DEBUG("done_age = %d\n", done_age
);
1935 for (i
= start
; i
< dma
->buf_count
; i
++) {
1936 buf
= dma
->buflist
[i
];
1937 buf_priv
= buf
->dev_private
;
1938 if (buf
->filp
== 0 || (buf
->pending
&&
1939 buf_priv
->age
<= done_age
)) {
1940 dev_priv
->stats
.requested_bufs
++;
1949 dev_priv
->stats
.freelist_loops
++;
1953 DRM_DEBUG("returning NULL!\n");
1958 drm_buf_t
*radeon_freelist_get(drm_device_t
* dev
)
1960 drm_device_dma_t
*dma
= dev
->dma
;
1961 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1962 drm_radeon_buf_priv_t
*buf_priv
;
1966 u32 done_age
= DRM_READ32(dev_priv
->ring_rptr
, RADEON_SCRATCHOFF(1));
1968 if (++dev_priv
->last_buf
>= dma
->buf_count
)
1969 dev_priv
->last_buf
= 0;
1971 start
= dev_priv
->last_buf
;
1972 dev_priv
->stats
.freelist_loops
++;
1974 for (t
= 0; t
< 2; t
++) {
1975 for (i
= start
; i
< dma
->buf_count
; i
++) {
1976 buf
= dma
->buflist
[i
];
1977 buf_priv
= buf
->dev_private
;
1978 if (buf
->filp
== 0 || (buf
->pending
&&
1979 buf_priv
->age
<= done_age
)) {
1980 dev_priv
->stats
.requested_bufs
++;
1992 void radeon_freelist_reset(drm_device_t
* dev
)
1994 drm_device_dma_t
*dma
= dev
->dma
;
1995 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
1998 dev_priv
->last_buf
= 0;
1999 for (i
= 0; i
< dma
->buf_count
; i
++) {
2000 drm_buf_t
*buf
= dma
->buflist
[i
];
2001 drm_radeon_buf_priv_t
*buf_priv
= buf
->dev_private
;
2006 /* ================================================================
2007 * CP command submission
2010 int radeon_wait_ring(drm_radeon_private_t
* dev_priv
, int n
)
2012 drm_radeon_ring_buffer_t
*ring
= &dev_priv
->ring
;
2014 u32 last_head
= GET_RING_HEAD(dev_priv
);
2016 for (i
= 0; i
< dev_priv
->usec_timeout
; i
++) {
2017 u32 head
= GET_RING_HEAD(dev_priv
);
2019 ring
->space
= (head
- ring
->tail
) * sizeof(u32
);
2020 if (ring
->space
<= 0)
2021 ring
->space
+= ring
->size
;
2022 if (ring
->space
> n
)
2025 dev_priv
->stats
.boxes
|= RADEON_BOX_WAIT_IDLE
;
2027 if (head
!= last_head
)
2034 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2035 #if RADEON_FIFO_DEBUG
2036 radeon_status(dev_priv
);
2037 DRM_ERROR("failed!\n");
2039 return DRM_ERR(EBUSY
);
2042 static int radeon_cp_get_buffers(DRMFILE filp
, drm_device_t
* dev
,
2048 for (i
= d
->granted_count
; i
< d
->request_count
; i
++) {
2049 buf
= radeon_freelist_get(dev
);
2051 return DRM_ERR(EBUSY
); /* NOTE: broken client */
2055 if (DRM_COPY_TO_USER(&d
->request_indices
[i
], &buf
->idx
,
2057 return DRM_ERR(EFAULT
);
2058 if (DRM_COPY_TO_USER(&d
->request_sizes
[i
], &buf
->total
,
2059 sizeof(buf
->total
)))
2060 return DRM_ERR(EFAULT
);
2067 int radeon_cp_buffers(DRM_IOCTL_ARGS
)
2070 drm_device_dma_t
*dma
= dev
->dma
;
2072 drm_dma_t __user
*argp
= (void __user
*)data
;
2075 LOCK_TEST_WITH_RETURN(dev
, filp
);
2077 DRM_COPY_FROM_USER_IOCTL(d
, argp
, sizeof(d
));
2079 /* Please don't send us buffers.
2081 if (d
.send_count
!= 0) {
2082 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2083 DRM_CURRENTPID
, d
.send_count
);
2084 return DRM_ERR(EINVAL
);
2087 /* We'll send you buffers.
2089 if (d
.request_count
< 0 || d
.request_count
> dma
->buf_count
) {
2090 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2091 DRM_CURRENTPID
, d
.request_count
, dma
->buf_count
);
2092 return DRM_ERR(EINVAL
);
2095 d
.granted_count
= 0;
2097 if (d
.request_count
) {
2098 ret
= radeon_cp_get_buffers(filp
, dev
, &d
);
2101 DRM_COPY_TO_USER_IOCTL(argp
, d
, sizeof(d
));
2106 int radeon_driver_preinit(struct drm_device
*dev
, unsigned long flags
)
2108 drm_radeon_private_t
*dev_priv
;
2111 dev_priv
= drm_alloc(sizeof(drm_radeon_private_t
), DRM_MEM_DRIVER
);
2112 if (dev_priv
== NULL
)
2113 return DRM_ERR(ENOMEM
);
2115 memset(dev_priv
, 0, sizeof(drm_radeon_private_t
));
2116 dev
->dev_private
= (void *)dev_priv
;
2117 dev_priv
->flags
= flags
;
2119 switch (flags
& CHIP_FAMILY_MASK
) {
2125 dev_priv
->flags
|= CHIP_HAS_HIERZ
;
2128 /* all other chips have no hierarchical z buffer */
2132 if (drm_device_is_agp(dev
))
2133 dev_priv
->flags
|= CHIP_IS_AGP
;
2135 if (drm_device_is_pcie(dev
))
2136 dev_priv
->flags
|= CHIP_IS_PCIE
;
2138 DRM_DEBUG("%s card detected\n",
2139 ((dev_priv
->flags
& CHIP_IS_AGP
) ? "AGP" : "PCI"));
2143 int radeon_presetup(struct drm_device
*dev
)
2146 drm_local_map_t
*map
;
2147 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2149 ret
= drm_addmap(dev
, drm_get_resource_start(dev
, 2),
2150 drm_get_resource_len(dev
, 2), _DRM_REGISTERS
,
2151 _DRM_READ_ONLY
, &dev_priv
->mmio
);
2155 ret
= drm_addmap(dev
, drm_get_resource_start(dev
, 0),
2156 drm_get_resource_len(dev
, 0), _DRM_FRAME_BUFFER
,
2157 _DRM_WRITE_COMBINING
, &map
);
2164 int radeon_driver_postcleanup(struct drm_device
*dev
)
2166 drm_radeon_private_t
*dev_priv
= dev
->dev_private
;
2170 drm_free(dev_priv
, sizeof(*dev_priv
), DRM_MEM_DRIVER
);
2172 dev
->dev_private
= NULL
;