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Merge branch 'for-linus' of git://oss.sgi.com:8090/xfs/xfs-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / drm / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 /* General customization:
34 */
35
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
37
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20060119"
41
42 /* Interface history:
43 *
44 * 1.1: Original.
45 * 1.2: Add Power Management
46 * 1.3: Add vblank support
47 * 1.4: Fix cmdbuffer path, add heap destroy
48 * 1.5: Add vblank pipe configuration
49 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
50 * - Support vertical blank on secondary display pipe
51 */
52 #define DRIVER_MAJOR 1
53 #define DRIVER_MINOR 6
54 #define DRIVER_PATCHLEVEL 0
55
56 typedef struct _drm_i915_ring_buffer {
57 int tail_mask;
58 unsigned long Start;
59 unsigned long End;
60 unsigned long Size;
61 u8 *virtual_start;
62 int head;
63 int tail;
64 int space;
65 drm_local_map_t map;
66 } drm_i915_ring_buffer_t;
67
68 struct mem_block {
69 struct mem_block *next;
70 struct mem_block *prev;
71 int start;
72 int size;
73 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
74 };
75
76 typedef struct _drm_i915_vbl_swap {
77 struct list_head head;
78 drm_drawable_t drw_id;
79 unsigned int pipe;
80 unsigned int sequence;
81 } drm_i915_vbl_swap_t;
82
83 typedef struct drm_i915_private {
84 drm_local_map_t *sarea;
85 drm_local_map_t *mmio_map;
86
87 drm_i915_sarea_t *sarea_priv;
88 drm_i915_ring_buffer_t ring;
89
90 drm_dma_handle_t *status_page_dmah;
91 void *hw_status_page;
92 dma_addr_t dma_status_page;
93 unsigned long counter;
94 unsigned int status_gfx_addr;
95 drm_local_map_t hws_map;
96
97 unsigned int cpp;
98 int back_offset;
99 int front_offset;
100 int current_page;
101 int page_flipping;
102 int use_mi_batchbuffer_start;
103
104 wait_queue_head_t irq_queue;
105 atomic_t irq_received;
106 atomic_t irq_emitted;
107
108 int tex_lru_log_granularity;
109 int allow_batchbuffer;
110 struct mem_block *agp_heap;
111 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
112 int vblank_pipe;
113
114 spinlock_t swaps_lock;
115 drm_i915_vbl_swap_t vbl_swaps;
116 unsigned int swaps_pending;
117
118 /* Register state */
119 u8 saveLBB;
120 u32 saveDSPACNTR;
121 u32 saveDSPBCNTR;
122 u32 savePIPEACONF;
123 u32 savePIPEBCONF;
124 u32 savePIPEASRC;
125 u32 savePIPEBSRC;
126 u32 saveFPA0;
127 u32 saveFPA1;
128 u32 saveDPLL_A;
129 u32 saveDPLL_A_MD;
130 u32 saveHTOTAL_A;
131 u32 saveHBLANK_A;
132 u32 saveHSYNC_A;
133 u32 saveVTOTAL_A;
134 u32 saveVBLANK_A;
135 u32 saveVSYNC_A;
136 u32 saveBCLRPAT_A;
137 u32 saveDSPASTRIDE;
138 u32 saveDSPASIZE;
139 u32 saveDSPAPOS;
140 u32 saveDSPABASE;
141 u32 saveDSPASURF;
142 u32 saveDSPATILEOFF;
143 u32 savePFIT_PGM_RATIOS;
144 u32 saveBLC_PWM_CTL;
145 u32 saveBLC_PWM_CTL2;
146 u32 saveFPB0;
147 u32 saveFPB1;
148 u32 saveDPLL_B;
149 u32 saveDPLL_B_MD;
150 u32 saveHTOTAL_B;
151 u32 saveHBLANK_B;
152 u32 saveHSYNC_B;
153 u32 saveVTOTAL_B;
154 u32 saveVBLANK_B;
155 u32 saveVSYNC_B;
156 u32 saveBCLRPAT_B;
157 u32 saveDSPBSTRIDE;
158 u32 saveDSPBSIZE;
159 u32 saveDSPBPOS;
160 u32 saveDSPBBASE;
161 u32 saveDSPBSURF;
162 u32 saveDSPBTILEOFF;
163 u32 saveVCLK_DIVISOR_VGA0;
164 u32 saveVCLK_DIVISOR_VGA1;
165 u32 saveVCLK_POST_DIV;
166 u32 saveVGACNTRL;
167 u32 saveADPA;
168 u32 saveLVDS;
169 u32 saveLVDSPP_ON;
170 u32 saveLVDSPP_OFF;
171 u32 saveDVOA;
172 u32 saveDVOB;
173 u32 saveDVOC;
174 u32 savePP_ON;
175 u32 savePP_OFF;
176 u32 savePP_CONTROL;
177 u32 savePP_CYCLE;
178 u32 savePFIT_CONTROL;
179 u32 save_palette_a[256];
180 u32 save_palette_b[256];
181 u32 saveFBC_CFB_BASE;
182 u32 saveFBC_LL_BASE;
183 u32 saveFBC_CONTROL;
184 u32 saveFBC_CONTROL2;
185 u32 saveSWF0[16];
186 u32 saveSWF1[16];
187 u32 saveSWF2[3];
188 u8 saveMSR;
189 u8 saveSR[8];
190 u8 saveGR[25];
191 u8 saveAR_INDEX;
192 u8 saveAR[20];
193 u8 saveDACMASK;
194 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
195 u8 saveCR[36];
196 } drm_i915_private_t;
197
198 extern struct drm_ioctl_desc i915_ioctls[];
199 extern int i915_max_ioctl;
200
201 /* i915_dma.c */
202 extern void i915_kernel_lost_context(struct drm_device * dev);
203 extern int i915_driver_load(struct drm_device *, unsigned long flags);
204 extern int i915_driver_unload(struct drm_device *);
205 extern void i915_driver_lastclose(struct drm_device * dev);
206 extern void i915_driver_preclose(struct drm_device *dev,
207 struct drm_file *file_priv);
208 extern int i915_driver_device_is_agp(struct drm_device * dev);
209 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
210 unsigned long arg);
211
212 /* i915_irq.c */
213 extern int i915_irq_emit(struct drm_device *dev, void *data,
214 struct drm_file *file_priv);
215 extern int i915_irq_wait(struct drm_device *dev, void *data,
216 struct drm_file *file_priv);
217
218 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
219 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
220 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
221 extern void i915_driver_irq_preinstall(struct drm_device * dev);
222 extern void i915_driver_irq_postinstall(struct drm_device * dev);
223 extern void i915_driver_irq_uninstall(struct drm_device * dev);
224 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
225 struct drm_file *file_priv);
226 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
227 struct drm_file *file_priv);
228 extern int i915_vblank_swap(struct drm_device *dev, void *data,
229 struct drm_file *file_priv);
230
231 /* i915_mem.c */
232 extern int i915_mem_alloc(struct drm_device *dev, void *data,
233 struct drm_file *file_priv);
234 extern int i915_mem_free(struct drm_device *dev, void *data,
235 struct drm_file *file_priv);
236 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
237 struct drm_file *file_priv);
238 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
239 struct drm_file *file_priv);
240 extern void i915_mem_takedown(struct mem_block **heap);
241 extern void i915_mem_release(struct drm_device * dev,
242 struct drm_file *file_priv, struct mem_block *heap);
243
244 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
245 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
246 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
247 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
248
249 #define I915_VERBOSE 0
250
251 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
252 volatile char *virt;
253
254 #define BEGIN_LP_RING(n) do { \
255 if (I915_VERBOSE) \
256 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
257 if (dev_priv->ring.space < (n)*4) \
258 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
259 outcount = 0; \
260 outring = dev_priv->ring.tail; \
261 ringmask = dev_priv->ring.tail_mask; \
262 virt = dev_priv->ring.virtual_start; \
263 } while (0)
264
265 #define OUT_RING(n) do { \
266 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
267 *(volatile unsigned int *)(virt + outring) = (n); \
268 outcount++; \
269 outring += 4; \
270 outring &= ringmask; \
271 } while (0)
272
273 #define ADVANCE_LP_RING() do { \
274 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
275 dev_priv->ring.tail = outring; \
276 dev_priv->ring.space -= outcount * 4; \
277 I915_WRITE(LP_RING + RING_TAIL, outring); \
278 } while(0)
279
280 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
281
282 /* Extended config space */
283 #define LBB 0xf4
284
285 /* VGA stuff */
286
287 #define VGA_ST01_MDA 0x3ba
288 #define VGA_ST01_CGA 0x3da
289
290 #define VGA_MSR_WRITE 0x3c2
291 #define VGA_MSR_READ 0x3cc
292 #define VGA_MSR_MEM_EN (1<<1)
293 #define VGA_MSR_CGA_MODE (1<<0)
294
295 #define VGA_SR_INDEX 0x3c4
296 #define VGA_SR_DATA 0x3c5
297
298 #define VGA_AR_INDEX 0x3c0
299 #define VGA_AR_VID_EN (1<<5)
300 #define VGA_AR_DATA_WRITE 0x3c0
301 #define VGA_AR_DATA_READ 0x3c1
302
303 #define VGA_GR_INDEX 0x3ce
304 #define VGA_GR_DATA 0x3cf
305 /* GR05 */
306 #define VGA_GR_MEM_READ_MODE_SHIFT 3
307 #define VGA_GR_MEM_READ_MODE_PLANE 1
308 /* GR06 */
309 #define VGA_GR_MEM_MODE_MASK 0xc
310 #define VGA_GR_MEM_MODE_SHIFT 2
311 #define VGA_GR_MEM_A0000_AFFFF 0
312 #define VGA_GR_MEM_A0000_BFFFF 1
313 #define VGA_GR_MEM_B0000_B7FFF 2
314 #define VGA_GR_MEM_B0000_BFFFF 3
315
316 #define VGA_DACMASK 0x3c6
317 #define VGA_DACRX 0x3c7
318 #define VGA_DACWX 0x3c8
319 #define VGA_DACDATA 0x3c9
320
321 #define VGA_CR_INDEX_MDA 0x3b4
322 #define VGA_CR_DATA_MDA 0x3b5
323 #define VGA_CR_INDEX_CGA 0x3d4
324 #define VGA_CR_DATA_CGA 0x3d5
325
326 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
327 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
328 #define CMD_REPORT_HEAD (7<<23)
329 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
330 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
331
332 #define INST_PARSER_CLIENT 0x00000000
333 #define INST_OP_FLUSH 0x02000000
334 #define INST_FLUSH_MAP_CACHE 0x00000001
335
336 #define BB1_START_ADDR_MASK (~0x7)
337 #define BB1_PROTECTED (1<<0)
338 #define BB1_UNPROTECTED (0<<0)
339 #define BB2_END_ADDR_MASK (~0x7)
340
341 /* Framebuffer compression */
342 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
343 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
344 #define FBC_CONTROL 0x03208
345 #define FBC_CTL_EN (1<<31)
346 #define FBC_CTL_PERIODIC (1<<30)
347 #define FBC_CTL_INTERVAL_SHIFT (16)
348 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
349 #define FBC_CTL_STRIDE_SHIFT (5)
350 #define FBC_CTL_FENCENO (1<<0)
351 #define FBC_COMMAND 0x0320c
352 #define FBC_CMD_COMPRESS (1<<0)
353 #define FBC_STATUS 0x03210
354 #define FBC_STAT_COMPRESSING (1<<31)
355 #define FBC_STAT_COMPRESSED (1<<30)
356 #define FBC_STAT_MODIFIED (1<<29)
357 #define FBC_STAT_CURRENT_LINE (1<<0)
358 #define FBC_CONTROL2 0x03214
359 #define FBC_CTL_FENCE_DBL (0<<4)
360 #define FBC_CTL_IDLE_IMM (0<<2)
361 #define FBC_CTL_IDLE_FULL (1<<2)
362 #define FBC_CTL_IDLE_LINE (2<<2)
363 #define FBC_CTL_IDLE_DEBUG (3<<2)
364 #define FBC_CTL_CPU_FENCE (1<<1)
365 #define FBC_CTL_PLANEA (0<<0)
366 #define FBC_CTL_PLANEB (1<<0)
367 #define FBC_FENCE_OFF 0x0321b
368
369 #define FBC_LL_SIZE (1536)
370 #define FBC_LL_PAD (32)
371
372 /* Interrupt bits:
373 */
374 #define USER_INT_FLAG (1<<1)
375 #define VSYNC_PIPEB_FLAG (1<<5)
376 #define VSYNC_PIPEA_FLAG (1<<7)
377 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */
378
379 #define I915REG_HWSTAM 0x02098
380 #define I915REG_INT_IDENTITY_R 0x020a4
381 #define I915REG_INT_MASK_R 0x020a8
382 #define I915REG_INT_ENABLE_R 0x020a0
383
384 #define I915REG_PIPEASTAT 0x70024
385 #define I915REG_PIPEBSTAT 0x71024
386
387 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
388 #define I915_VBLANK_CLEAR (1UL<<1)
389
390 #define SRX_INDEX 0x3c4
391 #define SRX_DATA 0x3c5
392 #define SR01 1
393 #define SR01_SCREEN_OFF (1<<5)
394
395 #define PPCR 0x61204
396 #define PPCR_ON (1<<0)
397
398 #define DVOB 0x61140
399 #define DVOB_ON (1<<31)
400 #define DVOC 0x61160
401 #define DVOC_ON (1<<31)
402 #define LVDS 0x61180
403 #define LVDS_ON (1<<31)
404
405 #define ADPA 0x61100
406 #define ADPA_DPMS_MASK (~(3<<10))
407 #define ADPA_DPMS_ON (0<<10)
408 #define ADPA_DPMS_SUSPEND (1<<10)
409 #define ADPA_DPMS_STANDBY (2<<10)
410 #define ADPA_DPMS_OFF (3<<10)
411
412 #define NOPID 0x2094
413 #define LP_RING 0x2030
414 #define HP_RING 0x2040
415 /* The binner has its own ring buffer:
416 */
417 #define HWB_RING 0x2400
418
419 #define RING_TAIL 0x00
420 #define TAIL_ADDR 0x001FFFF8
421 #define RING_HEAD 0x04
422 #define HEAD_WRAP_COUNT 0xFFE00000
423 #define HEAD_WRAP_ONE 0x00200000
424 #define HEAD_ADDR 0x001FFFFC
425 #define RING_START 0x08
426 #define START_ADDR 0x0xFFFFF000
427 #define RING_LEN 0x0C
428 #define RING_NR_PAGES 0x001FF000
429 #define RING_REPORT_MASK 0x00000006
430 #define RING_REPORT_64K 0x00000002
431 #define RING_REPORT_128K 0x00000004
432 #define RING_NO_REPORT 0x00000000
433 #define RING_VALID_MASK 0x00000001
434 #define RING_VALID 0x00000001
435 #define RING_INVALID 0x00000000
436
437 /* Instruction parser error reg:
438 */
439 #define IPEIR 0x2088
440
441 /* Scratch pad debug 0 reg:
442 */
443 #define SCPD0 0x209c
444
445 /* Error status reg:
446 */
447 #define ESR 0x20b8
448
449 /* Secondary DMA fetch address debug reg:
450 */
451 #define DMA_FADD_S 0x20d4
452
453 /* Cache mode 0 reg.
454 * - Manipulating render cache behaviour is central
455 * to the concept of zone rendering, tuning this reg can help avoid
456 * unnecessary render cache reads and even writes (for z/stencil)
457 * at beginning and end of scene.
458 *
459 * - To change a bit, write to this reg with a mask bit set and the
460 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
461 */
462 #define Cache_Mode_0 0x2120
463 #define CM0_MASK_SHIFT 16
464 #define CM0_IZ_OPT_DISABLE (1<<6)
465 #define CM0_ZR_OPT_DISABLE (1<<5)
466 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
467 #define CM0_COLOR_EVICT_DISABLE (1<<3)
468 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
469 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
470
471
472 /* Graphics flush control. A CPU write flushes the GWB of all writes.
473 * The data is discarded.
474 */
475 #define GFX_FLSH_CNTL 0x2170
476
477 /* Binner control. Defines the location of the bin pointer list:
478 */
479 #define BINCTL 0x2420
480 #define BC_MASK (1 << 9)
481
482 /* Binned scene info.
483 */
484 #define BINSCENE 0x2428
485 #define BS_OP_LOAD (1 << 8)
486 #define BS_MASK (1 << 22)
487
488 /* Bin command parser debug reg:
489 */
490 #define BCPD 0x2480
491
492 /* Bin memory control debug reg:
493 */
494 #define BMCD 0x2484
495
496 /* Bin data cache debug reg:
497 */
498 #define BDCD 0x2488
499
500 /* Binner pointer cache debug reg:
501 */
502 #define BPCD 0x248c
503
504 /* Binner scratch pad debug reg:
505 */
506 #define BINSKPD 0x24f0
507
508 /* HWB scratch pad debug reg:
509 */
510 #define HWBSKPD 0x24f4
511
512 /* Binner memory pool reg:
513 */
514 #define BMP_BUFFER 0x2430
515 #define BMP_PAGE_SIZE_4K (0 << 10)
516 #define BMP_BUFFER_SIZE_SHIFT 1
517 #define BMP_ENABLE (1 << 0)
518
519 /* Get/put memory from the binner memory pool:
520 */
521 #define BMP_GET 0x2438
522 #define BMP_PUT 0x2440
523 #define BMP_OFFSET_SHIFT 5
524
525 /* 3D state packets:
526 */
527 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
528
529 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
530 #define SC_UPDATE_SCISSOR (0x1<<1)
531 #define SC_ENABLE_MASK (0x1<<0)
532 #define SC_ENABLE (0x1<<0)
533
534 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
535
536 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
537 #define SCI_YMIN_MASK (0xffff<<16)
538 #define SCI_XMIN_MASK (0xffff<<0)
539 #define SCI_YMAX_MASK (0xffff<<16)
540 #define SCI_XMAX_MASK (0xffff<<0)
541
542 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
543 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
544 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
545 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
546 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
547 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
548 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
549
550 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
551
552 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
553 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
554 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
555 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
556
557 #define MI_BATCH_BUFFER ((0x30<<23)|1)
558 #define MI_BATCH_BUFFER_START (0x31<<23)
559 #define MI_BATCH_BUFFER_END (0xA<<23)
560 #define MI_BATCH_NON_SECURE (1)
561 #define MI_BATCH_NON_SECURE_I965 (1<<8)
562
563 #define MI_WAIT_FOR_EVENT ((0x3<<23))
564 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
565 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
566 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
567
568 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
569
570 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
571 #define ASYNC_FLIP (1<<22)
572 #define DISPLAY_PLANE_A (0<<20)
573 #define DISPLAY_PLANE_B (1<<20)
574
575 /* Display regs */
576 #define DSPACNTR 0x70180
577 #define DSPBCNTR 0x71180
578 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
579
580 /* Define the region of interest for the binner:
581 */
582 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
583
584 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
585
586 #define CMD_MI_FLUSH (0x04 << 23)
587 #define MI_NO_WRITE_FLUSH (1 << 2)
588 #define MI_READ_FLUSH (1 << 0)
589 #define MI_EXE_FLUSH (1 << 1)
590 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
591 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
592
593 #define BREADCRUMB_BITS 31
594 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
595
596 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
597 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
598
599 #define BLC_PWM_CTL 0x61254
600 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
601
602 #define BLC_PWM_CTL2 0x61250
603 /**
604 * This is the most significant 15 bits of the number of backlight cycles in a
605 * complete cycle of the modulated backlight control.
606 *
607 * The actual value is this field multiplied by two.
608 */
609 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
610 #define BLM_LEGACY_MODE (1 << 16)
611 /**
612 * This is the number of cycles out of the backlight modulation cycle for which
613 * the backlight is on.
614 *
615 * This field must be no greater than the number of cycles in the complete
616 * backlight modulation cycle.
617 */
618 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
619 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
620
621 #define I915_GCFGC 0xf0
622 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
623 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
624 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
625 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
626
627 #define I855_HPLLCC 0xc0
628 #define I855_CLOCK_CONTROL_MASK (3 << 0)
629 #define I855_CLOCK_133_200 (0 << 0)
630 #define I855_CLOCK_100_200 (1 << 0)
631 #define I855_CLOCK_100_133 (2 << 0)
632 #define I855_CLOCK_166_250 (3 << 0)
633
634 /* p317, 319
635 */
636 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
637 #define VCLK2_VCO_N 0x600a
638 #define VCLK2_VCO_DIV_SEL 0x6012
639
640 #define VCLK_DIVISOR_VGA0 0x6000
641 #define VCLK_DIVISOR_VGA1 0x6004
642 #define VCLK_POST_DIV 0x6010
643 /** Selects a post divisor of 4 instead of 2. */
644 # define VGA1_PD_P2_DIV_4 (1 << 15)
645 /** Overrides the p2 post divisor field */
646 # define VGA1_PD_P1_DIV_2 (1 << 13)
647 # define VGA1_PD_P1_SHIFT 8
648 /** P1 value is 2 greater than this field */
649 # define VGA1_PD_P1_MASK (0x1f << 8)
650 /** Selects a post divisor of 4 instead of 2. */
651 # define VGA0_PD_P2_DIV_4 (1 << 7)
652 /** Overrides the p2 post divisor field */
653 # define VGA0_PD_P1_DIV_2 (1 << 5)
654 # define VGA0_PD_P1_SHIFT 0
655 /** P1 value is 2 greater than this field */
656 # define VGA0_PD_P1_MASK (0x1f << 0)
657
658 /* I830 CRTC registers */
659 #define HTOTAL_A 0x60000
660 #define HBLANK_A 0x60004
661 #define HSYNC_A 0x60008
662 #define VTOTAL_A 0x6000c
663 #define VBLANK_A 0x60010
664 #define VSYNC_A 0x60014
665 #define PIPEASRC 0x6001c
666 #define BCLRPAT_A 0x60020
667 #define VSYNCSHIFT_A 0x60028
668
669 #define HTOTAL_B 0x61000
670 #define HBLANK_B 0x61004
671 #define HSYNC_B 0x61008
672 #define VTOTAL_B 0x6100c
673 #define VBLANK_B 0x61010
674 #define VSYNC_B 0x61014
675 #define PIPEBSRC 0x6101c
676 #define BCLRPAT_B 0x61020
677 #define VSYNCSHIFT_B 0x61028
678
679 #define PP_STATUS 0x61200
680 # define PP_ON (1 << 31)
681 /**
682 * Indicates that all dependencies of the panel are on:
683 *
684 * - PLL enabled
685 * - pipe enabled
686 * - LVDS/DVOB/DVOC on
687 */
688 # define PP_READY (1 << 30)
689 # define PP_SEQUENCE_NONE (0 << 28)
690 # define PP_SEQUENCE_ON (1 << 28)
691 # define PP_SEQUENCE_OFF (2 << 28)
692 # define PP_SEQUENCE_MASK 0x30000000
693 #define PP_CONTROL 0x61204
694 # define POWER_TARGET_ON (1 << 0)
695
696 #define LVDSPP_ON 0x61208
697 #define LVDSPP_OFF 0x6120c
698 #define PP_CYCLE 0x61210
699
700 #define PFIT_CONTROL 0x61230
701 # define PFIT_ENABLE (1 << 31)
702 # define PFIT_PIPE_MASK (3 << 29)
703 # define PFIT_PIPE_SHIFT 29
704 # define VERT_INTERP_DISABLE (0 << 10)
705 # define VERT_INTERP_BILINEAR (1 << 10)
706 # define VERT_INTERP_MASK (3 << 10)
707 # define VERT_AUTO_SCALE (1 << 9)
708 # define HORIZ_INTERP_DISABLE (0 << 6)
709 # define HORIZ_INTERP_BILINEAR (1 << 6)
710 # define HORIZ_INTERP_MASK (3 << 6)
711 # define HORIZ_AUTO_SCALE (1 << 5)
712 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
713
714 #define PFIT_PGM_RATIOS 0x61234
715 # define PFIT_VERT_SCALE_MASK 0xfff00000
716 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
717
718 #define PFIT_AUTO_RATIOS 0x61238
719
720
721 #define DPLL_A 0x06014
722 #define DPLL_B 0x06018
723 # define DPLL_VCO_ENABLE (1 << 31)
724 # define DPLL_DVO_HIGH_SPEED (1 << 30)
725 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
726 # define DPLL_VGA_MODE_DIS (1 << 28)
727 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
728 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
729 # define DPLL_MODE_MASK (3 << 26)
730 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
731 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
732 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
733 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
734 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
735 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
736 /**
737 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
738 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
739 */
740 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
741 /**
742 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
743 * this field (only one bit may be set).
744 */
745 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
746 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
747 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
748 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
749 # define PLL_REF_INPUT_DREFCLK (0 << 13)
750 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
751 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
752 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
753 # define PLL_REF_INPUT_MASK (3 << 13)
754 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
755 /*
756 * Parallel to Serial Load Pulse phase selection.
757 * Selects the phase for the 10X DPLL clock for the PCIe
758 * digital display port. The range is 4 to 13; 10 or more
759 * is just a flip delay. The default is 6
760 */
761 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
762 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
763
764 /**
765 * SDVO multiplier for 945G/GM. Not used on 965.
766 *
767 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
768 */
769 # define SDVO_MULTIPLIER_MASK 0x000000ff
770 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
771 # define SDVO_MULTIPLIER_SHIFT_VGA 0
772
773 /** @defgroup DPLL_MD
774 * @{
775 */
776 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
777 #define DPLL_A_MD 0x0601c
778 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
779 #define DPLL_B_MD 0x06020
780 /**
781 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
782 *
783 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
784 */
785 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
786 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
787 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
788 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
789 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
790 /**
791 * SDVO/UDI pixel multiplier.
792 *
793 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
794 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
795 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
796 * dummy bytes in the datastream at an increased clock rate, with both sides of
797 * the link knowing how many bytes are fill.
798 *
799 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
800 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
801 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
802 * through an SDVO command.
803 *
804 * This register field has values of multiplication factor minus 1, with
805 * a maximum multiplier of 5 for SDVO.
806 */
807 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
808 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
809 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
810 * This best be set to the default value (3) or the CRT won't work. No,
811 * I don't entirely understand what this does...
812 */
813 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
814 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
815 /** @} */
816
817 #define DPLL_TEST 0x606c
818 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
819 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
820 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
821 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
822 # define DPLLB_TEST_N_BYPASS (1 << 19)
823 # define DPLLB_TEST_M_BYPASS (1 << 18)
824 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
825 # define DPLLA_TEST_N_BYPASS (1 << 3)
826 # define DPLLA_TEST_M_BYPASS (1 << 2)
827 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
828
829 #define ADPA 0x61100
830 #define ADPA_DAC_ENABLE (1<<31)
831 #define ADPA_DAC_DISABLE 0
832 #define ADPA_PIPE_SELECT_MASK (1<<30)
833 #define ADPA_PIPE_A_SELECT 0
834 #define ADPA_PIPE_B_SELECT (1<<30)
835 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
836 #define ADPA_SETS_HVPOLARITY 0
837 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
838 #define ADPA_VSYNC_CNTL_ENABLE 0
839 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
840 #define ADPA_HSYNC_CNTL_ENABLE 0
841 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
842 #define ADPA_VSYNC_ACTIVE_LOW 0
843 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
844 #define ADPA_HSYNC_ACTIVE_LOW 0
845
846 #define FPA0 0x06040
847 #define FPA1 0x06044
848 #define FPB0 0x06048
849 #define FPB1 0x0604c
850 # define FP_N_DIV_MASK 0x003f0000
851 # define FP_N_DIV_SHIFT 16
852 # define FP_M1_DIV_MASK 0x00003f00
853 # define FP_M1_DIV_SHIFT 8
854 # define FP_M2_DIV_MASK 0x0000003f
855 # define FP_M2_DIV_SHIFT 0
856
857
858 #define PORT_HOTPLUG_EN 0x61110
859 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
860 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
861 # define TV_HOTPLUG_INT_EN (1 << 18)
862 # define CRT_HOTPLUG_INT_EN (1 << 9)
863 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
864
865 #define PORT_HOTPLUG_STAT 0x61114
866 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
867 # define TV_HOTPLUG_INT_STATUS (1 << 10)
868 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
869 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
870 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
871 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
872 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
873 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
874
875 #define SDVOB 0x61140
876 #define SDVOC 0x61160
877 #define SDVO_ENABLE (1 << 31)
878 #define SDVO_PIPE_B_SELECT (1 << 30)
879 #define SDVO_STALL_SELECT (1 << 29)
880 #define SDVO_INTERRUPT_ENABLE (1 << 26)
881 /**
882 * 915G/GM SDVO pixel multiplier.
883 *
884 * Programmed value is multiplier - 1, up to 5x.
885 *
886 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
887 */
888 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
889 #define SDVO_PORT_MULTIPLY_SHIFT 23
890 #define SDVO_PHASE_SELECT_MASK (15 << 19)
891 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
892 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
893 #define SDVOC_GANG_MODE (1 << 16)
894 #define SDVO_BORDER_ENABLE (1 << 7)
895 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
896 #define SDVO_DETECTED (1 << 2)
897 /* Bits to be preserved when writing */
898 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
899 #define SDVOC_PRESERVE_MASK (1 << 17)
900
901 /** @defgroup LVDS
902 * @{
903 */
904 /**
905 * This register controls the LVDS output enable, pipe selection, and data
906 * format selection.
907 *
908 * All of the clock/data pairs are force powered down by power sequencing.
909 */
910 #define LVDS 0x61180
911 /**
912 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
913 * the DPLL semantics change when the LVDS is assigned to that pipe.
914 */
915 # define LVDS_PORT_EN (1 << 31)
916 /** Selects pipe B for LVDS data. Must be set on pre-965. */
917 # define LVDS_PIPEB_SELECT (1 << 30)
918
919 /**
920 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
921 * pixel.
922 */
923 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
924 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
925 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
926 /**
927 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
928 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
929 * on.
930 */
931 # define LVDS_A3_POWER_MASK (3 << 6)
932 # define LVDS_A3_POWER_DOWN (0 << 6)
933 # define LVDS_A3_POWER_UP (3 << 6)
934 /**
935 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
936 * is set.
937 */
938 # define LVDS_CLKB_POWER_MASK (3 << 4)
939 # define LVDS_CLKB_POWER_DOWN (0 << 4)
940 # define LVDS_CLKB_POWER_UP (3 << 4)
941
942 /**
943 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
944 * setting for whether we are in dual-channel mode. The B3 pair will
945 * additionally only be powered up when LVDS_A3_POWER_UP is set.
946 */
947 # define LVDS_B0B3_POWER_MASK (3 << 2)
948 # define LVDS_B0B3_POWER_DOWN (0 << 2)
949 # define LVDS_B0B3_POWER_UP (3 << 2)
950
951 #define PIPEACONF 0x70008
952 #define PIPEACONF_ENABLE (1<<31)
953 #define PIPEACONF_DISABLE 0
954 #define PIPEACONF_DOUBLE_WIDE (1<<30)
955 #define I965_PIPECONF_ACTIVE (1<<30)
956 #define PIPEACONF_SINGLE_WIDE 0
957 #define PIPEACONF_PIPE_UNLOCKED 0
958 #define PIPEACONF_PIPE_LOCKED (1<<25)
959 #define PIPEACONF_PALETTE 0
960 #define PIPEACONF_GAMMA (1<<24)
961 #define PIPECONF_FORCE_BORDER (1<<25)
962 #define PIPECONF_PROGRESSIVE (0 << 21)
963 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
964 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
965
966 #define PIPEBCONF 0x71008
967 #define PIPEBCONF_ENABLE (1<<31)
968 #define PIPEBCONF_DISABLE 0
969 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
970 #define PIPEBCONF_DISABLE 0
971 #define PIPEBCONF_GAMMA (1<<24)
972 #define PIPEBCONF_PALETTE 0
973
974 #define PIPEBGCMAXRED 0x71010
975 #define PIPEBGCMAXGREEN 0x71014
976 #define PIPEBGCMAXBLUE 0x71018
977 #define PIPEBSTAT 0x71024
978 #define PIPEBFRAMEHIGH 0x71040
979 #define PIPEBFRAMEPIXEL 0x71044
980
981 #define DSPACNTR 0x70180
982 #define DSPBCNTR 0x71180
983 #define DISPLAY_PLANE_ENABLE (1<<31)
984 #define DISPLAY_PLANE_DISABLE 0
985 #define DISPPLANE_GAMMA_ENABLE (1<<30)
986 #define DISPPLANE_GAMMA_DISABLE 0
987 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
988 #define DISPPLANE_8BPP (0x2<<26)
989 #define DISPPLANE_15_16BPP (0x4<<26)
990 #define DISPPLANE_16BPP (0x5<<26)
991 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
992 #define DISPPLANE_32BPP (0x7<<26)
993 #define DISPPLANE_STEREO_ENABLE (1<<25)
994 #define DISPPLANE_STEREO_DISABLE 0
995 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
996 #define DISPPLANE_SEL_PIPE_A 0
997 #define DISPPLANE_SEL_PIPE_B (1<<24)
998 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
999 #define DISPPLANE_SRC_KEY_DISABLE 0
1000 #define DISPPLANE_LINE_DOUBLE (1<<20)
1001 #define DISPPLANE_NO_LINE_DOUBLE 0
1002 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1003 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1004 /* plane B only */
1005 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1006 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1007 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1008 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1009
1010 #define DSPABASE 0x70184
1011 #define DSPASTRIDE 0x70188
1012
1013 #define DSPBBASE 0x71184
1014 #define DSPBADDR DSPBBASE
1015 #define DSPBSTRIDE 0x71188
1016
1017 #define DSPAKEYVAL 0x70194
1018 #define DSPAKEYMASK 0x70198
1019
1020 #define DSPAPOS 0x7018C /* reserved */
1021 #define DSPASIZE 0x70190
1022 #define DSPBPOS 0x7118C
1023 #define DSPBSIZE 0x71190
1024
1025 #define DSPASURF 0x7019C
1026 #define DSPATILEOFF 0x701A4
1027
1028 #define DSPBSURF 0x7119C
1029 #define DSPBTILEOFF 0x711A4
1030
1031 #define VGACNTRL 0x71400
1032 # define VGA_DISP_DISABLE (1 << 31)
1033 # define VGA_2X_MODE (1 << 30)
1034 # define VGA_PIPE_B_SELECT (1 << 29)
1035
1036 /*
1037 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1038 * of video memory available to the BIOS in SWF1.
1039 */
1040
1041 #define SWF0 0x71410
1042
1043 /*
1044 * 855 scratch registers.
1045 */
1046 #define SWF10 0x70410
1047
1048 #define SWF30 0x72414
1049
1050 /*
1051 * Overlay registers. These are overlay registers accessed via MMIO.
1052 * Those loaded via the overlay register page are defined in i830_video.c.
1053 */
1054 #define OVADD 0x30000
1055
1056 #define DOVSTA 0x30008
1057 #define OC_BUF (0x3<<20)
1058
1059 #define OGAMC5 0x30010
1060 #define OGAMC4 0x30014
1061 #define OGAMC3 0x30018
1062 #define OGAMC2 0x3001c
1063 #define OGAMC1 0x30020
1064 #define OGAMC0 0x30024
1065 /*
1066 * Palette registers
1067 */
1068 #define PALETTE_A 0x0a000
1069 #define PALETTE_B 0x0a800
1070
1071 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1072 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1073 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1074 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
1075 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1076
1077 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
1078 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1079 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1080 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
1081
1082 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1083 (dev)->pci_device == 0x2982 || \
1084 (dev)->pci_device == 0x2992 || \
1085 (dev)->pci_device == 0x29A2 || \
1086 (dev)->pci_device == 0x2A02 || \
1087 (dev)->pci_device == 0x2A12 || \
1088 (dev)->pci_device == 0x2A42)
1089
1090 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1091
1092 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1093
1094 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1095 (dev)->pci_device == 0x29B2 || \
1096 (dev)->pci_device == 0x29D2)
1097
1098 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1099 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1100
1101 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1102 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1103
1104 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1105
1106 #endif
kernel source for telekom puls (alcatel/mediatek)