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[PATCH] fix remaining missing includes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / char / agp / amd64-agp.c
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/agp_backend.h>
16 #include <linux/mmzone.h>
17 #include <asm/page.h> /* PAGE_SIZE */
18 #include "agp.h"
19
20 /* Will need to be increased if AMD64 ever goes >8-way. */
21 #define MAX_HAMMER_GARTS 8
22
23 /* PTE bits. */
24 #define GPTE_VALID 1
25 #define GPTE_COHERENT 2
26
27 /* Aperture control register bits. */
28 #define GARTEN (1<<0)
29 #define DISGARTCPU (1<<4)
30 #define DISGARTIO (1<<5)
31
32 /* GART cache control register bits. */
33 #define INVGART (1<<0)
34 #define GARTPTEERR (1<<1)
35
36 /* K8 On-cpu GART registers */
37 #define AMD64_GARTAPERTURECTL 0x90
38 #define AMD64_GARTAPERTUREBASE 0x94
39 #define AMD64_GARTTABLEBASE 0x98
40 #define AMD64_GARTCACHECTL 0x9c
41 #define AMD64_GARTEN (1<<0)
42
43 /* NVIDIA K8 registers */
44 #define NVIDIA_X86_64_0_APBASE 0x10
45 #define NVIDIA_X86_64_1_APBASE1 0x50
46 #define NVIDIA_X86_64_1_APLIMIT1 0x54
47 #define NVIDIA_X86_64_1_APSIZE 0xa8
48 #define NVIDIA_X86_64_1_APBASE2 0xd8
49 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
50
51 /* ULi K8 registers */
52 #define ULI_X86_64_BASE_ADDR 0x10
53 #define ULI_X86_64_HTT_FEA_REG 0x50
54 #define ULI_X86_64_ENU_SCR_REG 0x54
55
56 static int nr_garts;
57 static struct pci_dev * hammers[MAX_HAMMER_GARTS];
58
59 static struct resource *aperture_resource;
60 static int __initdata agp_try_unsupported;
61
62 static int gart_iterator;
63 #define for_each_nb() for(gart_iterator=0;gart_iterator<nr_garts;gart_iterator++)
64
65 static void flush_amd64_tlb(struct pci_dev *dev)
66 {
67 u32 tmp;
68
69 pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp);
70 tmp |= INVGART;
71 pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp);
72 }
73
74 static void amd64_tlbflush(struct agp_memory *temp)
75 {
76 for_each_nb()
77 flush_amd64_tlb(hammers[gart_iterator]);
78 }
79
80 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
81 {
82 int i, j, num_entries;
83 long long tmp;
84 u32 pte;
85
86 num_entries = agp_num_entries();
87
88 if (type != 0 || mem->type != 0)
89 return -EINVAL;
90
91 /* Make sure we can fit the range in the gatt table. */
92 /* FIXME: could wrap */
93 if (((unsigned long)pg_start + mem->page_count) > num_entries)
94 return -EINVAL;
95
96 j = pg_start;
97
98 /* gatt table should be empty. */
99 while (j < (pg_start + mem->page_count)) {
100 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
101 return -EBUSY;
102 j++;
103 }
104
105 if (mem->is_flushed == FALSE) {
106 global_cache_flush();
107 mem->is_flushed = TRUE;
108 }
109
110 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
111 tmp = agp_bridge->driver->mask_memory(agp_bridge,
112 mem->memory[i], mem->type);
113
114 BUG_ON(tmp & 0xffffff0000000ffcULL);
115 pte = (tmp & 0x000000ff00000000ULL) >> 28;
116 pte |=(tmp & 0x00000000fffff000ULL);
117 pte |= GPTE_VALID | GPTE_COHERENT;
118
119 writel(pte, agp_bridge->gatt_table+j);
120 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
121 }
122 amd64_tlbflush(mem);
123 return 0;
124 }
125
126 /*
127 * This hack alters the order element according
128 * to the size of a long. It sucks. I totally disown this, even
129 * though it does appear to work for the most part.
130 */
131 static struct aper_size_info_32 amd64_aperture_sizes[7] =
132 {
133 {32, 8192, 3+(sizeof(long)/8), 0 },
134 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
135 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
136 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
137 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
138 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
139 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
140 };
141
142
143 /*
144 * Get the current Aperture size from the x86-64.
145 * Note, that there may be multiple x86-64's, but we just return
146 * the value from the first one we find. The set_size functions
147 * keep the rest coherent anyway. Or at least should do.
148 */
149 static int amd64_fetch_size(void)
150 {
151 struct pci_dev *dev;
152 int i;
153 u32 temp;
154 struct aper_size_info_32 *values;
155
156 dev = hammers[0];
157 if (dev==NULL)
158 return 0;
159
160 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
161 temp = (temp & 0xe);
162 values = A_SIZE_32(amd64_aperture_sizes);
163
164 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
165 if (temp == values[i].size_value) {
166 agp_bridge->previous_size =
167 agp_bridge->current_size = (void *) (values + i);
168
169 agp_bridge->aperture_size_idx = i;
170 return values[i].size;
171 }
172 }
173 return 0;
174 }
175
176 /*
177 * In a multiprocessor x86-64 system, this function gets
178 * called once for each CPU.
179 */
180 static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
181 {
182 u64 aperturebase;
183 u32 tmp;
184 u64 addr, aper_base;
185
186 /* Address to map to */
187 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
188 aperturebase = tmp << 25;
189 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
190
191 /* address of the mappings table */
192 addr = (u64) gatt_table;
193 addr >>= 12;
194 tmp = (u32) addr<<4;
195 tmp &= ~0xf;
196 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
197
198 /* Enable GART translation for this hammer. */
199 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
200 tmp |= GARTEN;
201 tmp &= ~(DISGARTCPU | DISGARTIO);
202 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
203
204 /* keep CPU's coherent. */
205 flush_amd64_tlb (hammer);
206
207 return aper_base;
208 }
209
210
211 static struct aper_size_info_32 amd_8151_sizes[7] =
212 {
213 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
214 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
215 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
216 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
217 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
218 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
219 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
220 };
221
222 static int amd_8151_configure(void)
223 {
224 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
225
226 /* Configure AGP regs in each x86-64 host bridge. */
227 for_each_nb() {
228 agp_bridge->gart_bus_addr =
229 amd64_configure(hammers[gart_iterator],gatt_bus);
230 }
231 return 0;
232 }
233
234
235 static void amd64_cleanup(void)
236 {
237 u32 tmp;
238
239 for_each_nb() {
240 /* disable gart translation */
241 pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp);
242 tmp &= ~AMD64_GARTEN;
243 pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp);
244 }
245 }
246
247
248 static struct agp_bridge_driver amd_8151_driver = {
249 .owner = THIS_MODULE,
250 .aperture_sizes = amd_8151_sizes,
251 .size_type = U32_APER_SIZE,
252 .num_aperture_sizes = 7,
253 .configure = amd_8151_configure,
254 .fetch_size = amd64_fetch_size,
255 .cleanup = amd64_cleanup,
256 .tlb_flush = amd64_tlbflush,
257 .mask_memory = agp_generic_mask_memory,
258 .masks = NULL,
259 .agp_enable = agp_generic_enable,
260 .cache_flush = global_cache_flush,
261 .create_gatt_table = agp_generic_create_gatt_table,
262 .free_gatt_table = agp_generic_free_gatt_table,
263 .insert_memory = amd64_insert_memory,
264 .remove_memory = agp_generic_remove_memory,
265 .alloc_by_type = agp_generic_alloc_by_type,
266 .free_by_type = agp_generic_free_by_type,
267 .agp_alloc_page = agp_generic_alloc_page,
268 .agp_destroy_page = agp_generic_destroy_page,
269 };
270
271 /* Some basic sanity checks for the aperture. */
272 static int __devinit aperture_valid(u64 aper, u32 size)
273 {
274 u32 pfn, c;
275 if (aper == 0) {
276 printk(KERN_ERR PFX "No aperture\n");
277 return 0;
278 }
279 if (size < 32*1024*1024) {
280 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
281 return 0;
282 }
283 if (aper + size > 0xffffffff) {
284 printk(KERN_ERR PFX "Aperture out of bounds\n");
285 return 0;
286 }
287 pfn = aper >> PAGE_SHIFT;
288 for (c = 0; c < size/PAGE_SIZE; c++) {
289 if (!pfn_valid(pfn + c))
290 break;
291 if (!PageReserved(pfn_to_page(pfn + c))) {
292 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
293 return 0;
294 }
295 }
296
297 /* Request the Aperture. This catches cases when someone else
298 already put a mapping in there - happens with some very broken BIOS
299
300 Maybe better to use pci_assign_resource/pci_enable_device instead
301 trusting the bridges? */
302 if (!aperture_resource &&
303 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
304 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
305 return 0;
306 }
307 return 1;
308 }
309
310 /*
311 * W*s centric BIOS sometimes only set up the aperture in the AGP
312 * bridge, not the northbridge. On AMD64 this is handled early
313 * in aperture.c, but when GART_IOMMU is not enabled or we run
314 * on a 32bit kernel this needs to be redone.
315 * Unfortunately it is impossible to fix the aperture here because it's too late
316 * to allocate that much memory. But at least error out cleanly instead of
317 * crashing.
318 */
319 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
320 u16 cap)
321 {
322 u32 aper_low, aper_hi;
323 u64 aper, nb_aper;
324 int order = 0;
325 u32 nb_order, nb_base;
326 u16 apsize;
327
328 pci_read_config_dword(nb, 0x90, &nb_order);
329 nb_order = (nb_order >> 1) & 7;
330 pci_read_config_dword(nb, 0x94, &nb_base);
331 nb_aper = nb_base << 25;
332 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
333 return 0;
334 }
335
336 /* Northbridge seems to contain crap. Try the AGP bridge. */
337
338 pci_read_config_word(agp, cap+0x14, &apsize);
339 if (apsize == 0xffff)
340 return -1;
341
342 apsize &= 0xfff;
343 /* Some BIOS use weird encodings not in the AGPv3 table. */
344 if (apsize & 0xff)
345 apsize |= 0xf00;
346 order = 7 - hweight16(apsize);
347
348 pci_read_config_dword(agp, 0x10, &aper_low);
349 pci_read_config_dword(agp, 0x14, &aper_hi);
350 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
351 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
352 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
353 return -1;
354
355 pci_write_config_dword(nb, 0x90, order << 1);
356 pci_write_config_dword(nb, 0x94, aper >> 25);
357
358 return 0;
359 }
360
361 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
362 {
363 struct pci_dev *loop_dev = NULL;
364 int i = 0;
365
366 /* cache pci_devs of northbridges. */
367 while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev))
368 != NULL) {
369 if (i == MAX_HAMMER_GARTS) {
370 printk(KERN_ERR PFX "Too many northbridges for AGP\n");
371 return -1;
372 }
373 if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) {
374 printk(KERN_ERR PFX "No usable aperture found.\n");
375 #ifdef __x86_64__
376 /* should port this to i386 */
377 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
378 #endif
379 return -1;
380 }
381 hammers[i++] = loop_dev;
382 }
383 nr_garts = i;
384 return i == 0 ? -1 : 0;
385 }
386
387 /* Handle AMD 8151 quirks */
388 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
389 {
390 char *revstring;
391 u8 rev_id;
392
393 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
394 switch (rev_id) {
395 case 0x01: revstring="A0"; break;
396 case 0x02: revstring="A1"; break;
397 case 0x11: revstring="B0"; break;
398 case 0x12: revstring="B1"; break;
399 case 0x13: revstring="B2"; break;
400 case 0x14: revstring="B3"; break;
401 default: revstring="??"; break;
402 }
403
404 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
405
406 /*
407 * Work around errata.
408 * Chips before B2 stepping incorrectly reporting v3.5
409 */
410 if (rev_id < 0x13) {
411 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
412 bridge->major_version = 3;
413 bridge->minor_version = 0;
414 }
415 }
416
417
418 static struct aper_size_info_32 uli_sizes[7] =
419 {
420 {256, 65536, 6, 10},
421 {128, 32768, 5, 9},
422 {64, 16384, 4, 8},
423 {32, 8192, 3, 7},
424 {16, 4096, 2, 6},
425 {8, 2048, 1, 4},
426 {4, 1024, 0, 3}
427 };
428 static int __devinit uli_agp_init(struct pci_dev *pdev)
429 {
430 u32 httfea,baseaddr,enuscr;
431 struct pci_dev *dev1;
432 int i;
433 unsigned size = amd64_fetch_size();
434 printk(KERN_INFO "Setting up ULi AGP.\n");
435 dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0));
436 if (dev1 == NULL) {
437 printk(KERN_INFO PFX "Detected a ULi chipset, "
438 "but could not fine the secondary device.\n");
439 return -ENODEV;
440 }
441
442 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
443 if (uli_sizes[i].size == size)
444 break;
445
446 if (i == ARRAY_SIZE(uli_sizes)) {
447 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
448 return -ENODEV;
449 }
450
451 /* shadow x86-64 registers into ULi registers */
452 pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea);
453
454 /* if x86-64 aperture base is beyond 4G, exit here */
455 if ((httfea & 0x7fff) >> (32 - 25))
456 return -ENODEV;
457
458 httfea = (httfea& 0x7fff) << 25;
459
460 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
461 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
462 baseaddr|= httfea;
463 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
464
465 enuscr= httfea+ (size * 1024 * 1024) - 1;
466 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
467 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
468 return 0;
469 }
470
471
472 static struct aper_size_info_32 nforce3_sizes[5] =
473 {
474 {512, 131072, 7, 0x00000000 },
475 {256, 65536, 6, 0x00000008 },
476 {128, 32768, 5, 0x0000000C },
477 {64, 16384, 4, 0x0000000E },
478 {32, 8192, 3, 0x0000000F }
479 };
480
481 /* Handle shadow device of the Nvidia NForce3 */
482 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
483 static int __devinit nforce3_agp_init(struct pci_dev *pdev)
484 {
485 u32 tmp, apbase, apbar, aplimit;
486 struct pci_dev *dev1;
487 int i;
488 unsigned size = amd64_fetch_size();
489
490 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
491
492 dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0));
493 if (dev1 == NULL) {
494 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
495 "nForce3 chipset, but could not find "
496 "the secondary device.\n");
497 return -ENODEV;
498 }
499
500 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
501 if (nforce3_sizes[i].size == size)
502 break;
503
504 if (i == ARRAY_SIZE(nforce3_sizes)) {
505 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
506 return -ENODEV;
507 }
508
509 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
510 tmp &= ~(0xf);
511 tmp |= nforce3_sizes[i].size_value;
512 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
513
514 /* shadow x86-64 registers into NVIDIA registers */
515 pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase);
516
517 /* if x86-64 aperture base is beyond 4G, exit here */
518 if ( (apbase & 0x7fff) >> (32 - 25) )
519 return -ENODEV;
520
521 apbase = (apbase & 0x7fff) << 25;
522
523 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
524 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
525 apbar |= apbase;
526 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
527
528 aplimit = apbase + (size * 1024 * 1024) - 1;
529 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
530 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
531 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
532 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
533
534 return 0;
535 }
536
537 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
538 const struct pci_device_id *ent)
539 {
540 struct agp_bridge_data *bridge;
541 u8 cap_ptr;
542
543 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
544 if (!cap_ptr)
545 return -ENODEV;
546
547 /* Could check for AGPv3 here */
548
549 bridge = agp_alloc_bridge();
550 if (!bridge)
551 return -ENOMEM;
552
553 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
554 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
555 amd8151_init(pdev, bridge);
556 } else {
557 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
558 }
559
560 bridge->driver = &amd_8151_driver;
561 bridge->dev = pdev;
562 bridge->capndx = cap_ptr;
563
564 /* Fill in the mode register */
565 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
566
567 if (cache_nbs(pdev, cap_ptr) == -1) {
568 agp_put_bridge(bridge);
569 return -ENODEV;
570 }
571
572 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
573 int ret = nforce3_agp_init(pdev);
574 if (ret) {
575 agp_put_bridge(bridge);
576 return ret;
577 }
578 }
579
580 if (pdev->vendor == PCI_VENDOR_ID_AL) {
581 int ret = uli_agp_init(pdev);
582 if (ret) {
583 agp_put_bridge(bridge);
584 return ret;
585 }
586 }
587
588 pci_set_drvdata(pdev, bridge);
589 return agp_add_bridge(bridge);
590 }
591
592 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
593 {
594 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
595
596 release_mem_region(virt_to_gart(bridge->gatt_table_real),
597 amd64_aperture_sizes[bridge->aperture_size_idx].size);
598 agp_remove_bridge(bridge);
599 agp_put_bridge(bridge);
600 }
601
602 static struct pci_device_id agp_amd64_pci_table[] = {
603 {
604 .class = (PCI_CLASS_BRIDGE_HOST << 8),
605 .class_mask = ~0,
606 .vendor = PCI_VENDOR_ID_AMD,
607 .device = PCI_DEVICE_ID_AMD_8151_0,
608 .subvendor = PCI_ANY_ID,
609 .subdevice = PCI_ANY_ID,
610 },
611 /* ULi M1689 */
612 {
613 .class = (PCI_CLASS_BRIDGE_HOST << 8),
614 .class_mask = ~0,
615 .vendor = PCI_VENDOR_ID_AL,
616 .device = PCI_DEVICE_ID_AL_M1689,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 },
620 /* VIA K8T800Pro */
621 {
622 .class = (PCI_CLASS_BRIDGE_HOST << 8),
623 .class_mask = ~0,
624 .vendor = PCI_VENDOR_ID_VIA,
625 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
626 .subvendor = PCI_ANY_ID,
627 .subdevice = PCI_ANY_ID,
628 },
629 /* VIA K8T800 */
630 {
631 .class = (PCI_CLASS_BRIDGE_HOST << 8),
632 .class_mask = ~0,
633 .vendor = PCI_VENDOR_ID_VIA,
634 .device = PCI_DEVICE_ID_VIA_8385_0,
635 .subvendor = PCI_ANY_ID,
636 .subdevice = PCI_ANY_ID,
637 },
638 /* VIA K8M800 / K8N800 */
639 {
640 .class = (PCI_CLASS_BRIDGE_HOST << 8),
641 .class_mask = ~0,
642 .vendor = PCI_VENDOR_ID_VIA,
643 .device = PCI_DEVICE_ID_VIA_8380_0,
644 .subvendor = PCI_ANY_ID,
645 .subdevice = PCI_ANY_ID,
646 },
647 /* VIA K8T890 */
648 {
649 .class = (PCI_CLASS_BRIDGE_HOST << 8),
650 .class_mask = ~0,
651 .vendor = PCI_VENDOR_ID_VIA,
652 .device = PCI_DEVICE_ID_VIA_3238_0,
653 .subvendor = PCI_ANY_ID,
654 .subdevice = PCI_ANY_ID,
655 },
656 /* VIA K8T800/K8M800/K8N800 */
657 {
658 .class = (PCI_CLASS_BRIDGE_HOST << 8),
659 .class_mask = ~0,
660 .vendor = PCI_VENDOR_ID_VIA,
661 .device = PCI_DEVICE_ID_VIA_838X_1,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 },
665 /* NForce3 */
666 {
667 .class = (PCI_CLASS_BRIDGE_HOST << 8),
668 .class_mask = ~0,
669 .vendor = PCI_VENDOR_ID_NVIDIA,
670 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
671 .subvendor = PCI_ANY_ID,
672 .subdevice = PCI_ANY_ID,
673 },
674 {
675 .class = (PCI_CLASS_BRIDGE_HOST << 8),
676 .class_mask = ~0,
677 .vendor = PCI_VENDOR_ID_NVIDIA,
678 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 },
682 /* SIS 755 */
683 {
684 .class = (PCI_CLASS_BRIDGE_HOST << 8),
685 .class_mask = ~0,
686 .vendor = PCI_VENDOR_ID_SI,
687 .device = PCI_DEVICE_ID_SI_755,
688 .subvendor = PCI_ANY_ID,
689 .subdevice = PCI_ANY_ID,
690 },
691 /* SIS 760 */
692 {
693 .class = (PCI_CLASS_BRIDGE_HOST << 8),
694 .class_mask = ~0,
695 .vendor = PCI_VENDOR_ID_SI,
696 .device = PCI_DEVICE_ID_SI_760,
697 .subvendor = PCI_ANY_ID,
698 .subdevice = PCI_ANY_ID,
699 },
700 { }
701 };
702
703 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
704
705 static struct pci_driver agp_amd64_pci_driver = {
706 .name = "agpgart-amd64",
707 .id_table = agp_amd64_pci_table,
708 .probe = agp_amd64_probe,
709 .remove = agp_amd64_remove,
710 };
711
712
713 /* Not static due to IOMMU code calling it early. */
714 int __init agp_amd64_init(void)
715 {
716 int err = 0;
717 static struct pci_device_id amd64nb[] = {
718 { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
719 { },
720 };
721
722 if (agp_off)
723 return -EINVAL;
724 if (pci_register_driver(&agp_amd64_pci_driver) > 0) {
725 struct pci_dev *dev;
726 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
727 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
728 #ifdef MODULE
729 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
730 #else
731 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
732 #endif
733 return -ENODEV;
734 }
735
736 /* First check that we have at least one AMD64 NB */
737 if (!pci_dev_present(amd64nb))
738 return -ENODEV;
739
740 /* Look for any AGP bridge */
741 dev = NULL;
742 err = -ENODEV;
743 for_each_pci_dev(dev) {
744 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
745 continue;
746 /* Only one bridge supported right now */
747 if (agp_amd64_probe(dev, NULL) == 0) {
748 err = 0;
749 break;
750 }
751 }
752 }
753 return err;
754 }
755
756 static void __exit agp_amd64_cleanup(void)
757 {
758 if (aperture_resource)
759 release_resource(aperture_resource);
760 pci_unregister_driver(&agp_amd64_pci_driver);
761 }
762
763 /* On AMD64 the PCI driver needs to initialize this driver early
764 for the IOMMU, so it has to be called via a backdoor. */
765 #ifndef CONFIG_GART_IOMMU
766 module_init(agp_amd64_init);
767 module_exit(agp_amd64_cleanup);
768 #endif
769
770 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
771 module_param(agp_try_unsupported, bool, 0);
772 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)