2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major
;
52 module_param(nvme_major
, int, 0);
54 static int use_threaded_interrupts
;
55 module_param(use_threaded_interrupts
, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock
);
58 static LIST_HEAD(dev_list
);
59 static struct task_struct
*nvme_thread
;
62 * An NVM Express queue. Each device has at least two (one for admin
63 * commands and one for I/O commands).
66 struct device
*q_dmadev
;
69 struct nvme_command
*sq_cmds
;
70 volatile struct nvme_completion
*cqes
;
71 dma_addr_t sq_dma_addr
;
72 dma_addr_t cq_dma_addr
;
73 wait_queue_head_t sq_full
;
74 wait_queue_t sq_cong_wait
;
75 struct bio_list sq_cong
;
83 unsigned long cmdid_data
[];
87 * Check we didin't inadvertently grow the command struct
89 static inline void _nvme_check_size(void)
91 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
92 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
93 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
94 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
98 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
99 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
100 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
101 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
104 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
105 struct nvme_completion
*);
107 struct nvme_cmd_info
{
108 nvme_completion_fn fn
;
110 unsigned long timeout
;
113 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
115 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
119 * alloc_cmdid() - Allocate a Command ID
120 * @nvmeq: The queue that will be used for this command
121 * @ctx: A pointer that will be passed to the handler
122 * @handler: The function to call on completion
124 * Allocate a Command ID for a queue. The data passed in will
125 * be passed to the completion handler. This is implemented by using
126 * the bottom two bits of the ctx pointer to store the handler ID.
127 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128 * We can change this if it becomes a problem.
130 * May be called with local interrupts disabled and the q_lock held,
131 * or with interrupts enabled and no locks held.
133 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
134 nvme_completion_fn handler
, unsigned timeout
)
136 int depth
= nvmeq
->q_depth
- 1;
137 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
141 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
144 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
146 info
[cmdid
].fn
= handler
;
147 info
[cmdid
].ctx
= ctx
;
148 info
[cmdid
].timeout
= jiffies
+ timeout
;
152 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
153 nvme_completion_fn handler
, unsigned timeout
)
156 wait_event_killable(nvmeq
->sq_full
,
157 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
158 return (cmdid
< 0) ? -EINTR
: cmdid
;
161 /* Special values must be less than 0x1000 */
162 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
163 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
164 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
165 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
166 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
168 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
169 struct nvme_completion
*cqe
)
171 if (ctx
== CMD_CTX_CANCELLED
)
173 if (ctx
== CMD_CTX_FLUSH
)
175 if (ctx
== CMD_CTX_COMPLETED
) {
176 dev_warn(&dev
->pci_dev
->dev
,
177 "completed id %d twice on queue %d\n",
178 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
181 if (ctx
== CMD_CTX_INVALID
) {
182 dev_warn(&dev
->pci_dev
->dev
,
183 "invalid id %d completed on queue %d\n",
184 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
188 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
192 * Called with local interrupts disabled and the q_lock held. May not sleep.
194 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
195 nvme_completion_fn
*fn
)
198 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
200 if (cmdid
>= nvmeq
->q_depth
) {
201 *fn
= special_completion
;
202 return CMD_CTX_INVALID
;
205 *fn
= info
[cmdid
].fn
;
206 ctx
= info
[cmdid
].ctx
;
207 info
[cmdid
].fn
= special_completion
;
208 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
209 clear_bit(cmdid
, nvmeq
->cmdid_data
);
210 wake_up(&nvmeq
->sq_full
);
214 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
215 nvme_completion_fn
*fn
)
218 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
220 *fn
= info
[cmdid
].fn
;
221 ctx
= info
[cmdid
].ctx
;
222 info
[cmdid
].fn
= special_completion
;
223 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
227 struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
229 return dev
->queues
[get_cpu() + 1];
232 void put_nvmeq(struct nvme_queue
*nvmeq
)
238 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
239 * @nvmeq: The queue to use
240 * @cmd: The command to send
242 * Safe to use from interrupt context
244 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
248 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
249 tail
= nvmeq
->sq_tail
;
250 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
251 if (++tail
== nvmeq
->q_depth
)
253 writel(tail
, nvmeq
->q_db
);
254 nvmeq
->sq_tail
= tail
;
255 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
260 static __le64
**iod_list(struct nvme_iod
*iod
)
262 return ((void *)iod
) + iod
->offset
;
266 * Will slightly overestimate the number of pages needed. This is OK
267 * as it only leads to a small amount of wasted memory for the lifetime of
270 static int nvme_npages(unsigned size
)
272 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
273 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
276 static struct nvme_iod
*
277 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
279 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
280 sizeof(__le64
*) * nvme_npages(nbytes
) +
281 sizeof(struct scatterlist
) * nseg
, gfp
);
284 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
286 iod
->length
= nbytes
;
293 void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
295 const int last_prp
= PAGE_SIZE
/ 8 - 1;
297 __le64
**list
= iod_list(iod
);
298 dma_addr_t prp_dma
= iod
->first_dma
;
300 if (iod
->npages
== 0)
301 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
302 for (i
= 0; i
< iod
->npages
; i
++) {
303 __le64
*prp_list
= list
[i
];
304 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
305 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
306 prp_dma
= next_prp_dma
;
311 static void requeue_bio(struct nvme_dev
*dev
, struct bio
*bio
)
313 struct nvme_queue
*nvmeq
= get_nvmeq(dev
);
314 if (bio_list_empty(&nvmeq
->sq_cong
))
315 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
316 bio_list_add(&nvmeq
->sq_cong
, bio
);
318 wake_up_process(nvme_thread
);
321 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
322 struct nvme_completion
*cqe
)
324 struct nvme_iod
*iod
= ctx
;
325 struct bio
*bio
= iod
->private;
326 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
329 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
330 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
331 nvme_free_iod(dev
, iod
);
333 bio_endio(bio
, -EIO
);
334 } else if (bio
->bi_vcnt
> bio
->bi_idx
) {
335 requeue_bio(dev
, bio
);
341 /* length is in bytes. gfp flags indicates whether we may sleep. */
342 int nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_common_command
*cmd
,
343 struct nvme_iod
*iod
, int total_len
, gfp_t gfp
)
345 struct dma_pool
*pool
;
346 int length
= total_len
;
347 struct scatterlist
*sg
= iod
->sg
;
348 int dma_len
= sg_dma_len(sg
);
349 u64 dma_addr
= sg_dma_address(sg
);
350 int offset
= offset_in_page(dma_addr
);
352 __le64
**list
= iod_list(iod
);
356 cmd
->prp1
= cpu_to_le64(dma_addr
);
357 length
-= (PAGE_SIZE
- offset
);
361 dma_len
-= (PAGE_SIZE
- offset
);
363 dma_addr
+= (PAGE_SIZE
- offset
);
366 dma_addr
= sg_dma_address(sg
);
367 dma_len
= sg_dma_len(sg
);
370 if (length
<= PAGE_SIZE
) {
371 cmd
->prp2
= cpu_to_le64(dma_addr
);
375 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
376 if (nprps
<= (256 / 8)) {
377 pool
= dev
->prp_small_pool
;
380 pool
= dev
->prp_page_pool
;
384 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
386 cmd
->prp2
= cpu_to_le64(dma_addr
);
388 return (total_len
- length
) + PAGE_SIZE
;
391 iod
->first_dma
= prp_dma
;
392 cmd
->prp2
= cpu_to_le64(prp_dma
);
395 if (i
== PAGE_SIZE
/ 8) {
396 __le64
*old_prp_list
= prp_list
;
397 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
399 return total_len
- length
;
400 list
[iod
->npages
++] = prp_list
;
401 prp_list
[0] = old_prp_list
[i
- 1];
402 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
405 prp_list
[i
++] = cpu_to_le64(dma_addr
);
406 dma_len
-= PAGE_SIZE
;
407 dma_addr
+= PAGE_SIZE
;
415 dma_addr
= sg_dma_address(sg
);
416 dma_len
= sg_dma_len(sg
);
422 /* NVMe scatterlists require no holes in the virtual address */
423 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
424 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
426 static int nvme_map_bio(struct device
*dev
, struct nvme_iod
*iod
,
427 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
429 struct bio_vec
*bvec
, *bvprv
= NULL
;
430 struct scatterlist
*sg
= NULL
;
431 int i
, old_idx
, length
= 0, nsegs
= 0;
433 sg_init_table(iod
->sg
, psegs
);
434 old_idx
= bio
->bi_idx
;
435 bio_for_each_segment(bvec
, bio
, i
) {
436 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
437 sg
->length
+= bvec
->bv_len
;
439 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
441 sg
= sg
? sg
+ 1 : iod
->sg
;
442 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
446 length
+= bvec
->bv_len
;
452 if (dma_map_sg(dev
, iod
->sg
, iod
->nents
, dma_dir
) == 0) {
453 bio
->bi_idx
= old_idx
;
460 * We reuse the small pool to allocate the 16-byte range here as it is not
461 * worth having a special pool for these or additional cases to handle freeing
464 static int nvme_submit_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
465 struct bio
*bio
, struct nvme_iod
*iod
, int cmdid
)
467 struct nvme_dsm_range
*range
;
468 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
470 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
475 iod_list(iod
)[0] = (__le64
*)range
;
478 range
->cattr
= cpu_to_le32(0);
479 range
->nlb
= cpu_to_le32(bio
->bi_size
>> ns
->lba_shift
);
480 range
->slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
482 memset(cmnd
, 0, sizeof(*cmnd
));
483 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
484 cmnd
->dsm
.command_id
= cmdid
;
485 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
486 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
488 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
490 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
492 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
497 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
500 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
502 memset(cmnd
, 0, sizeof(*cmnd
));
503 cmnd
->common
.opcode
= nvme_cmd_flush
;
504 cmnd
->common
.command_id
= cmdid
;
505 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
507 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
509 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
514 int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
516 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
517 special_completion
, NVME_IO_TIMEOUT
);
518 if (unlikely(cmdid
< 0))
521 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
525 * Called with local interrupts disabled and the q_lock held. May not sleep.
527 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
530 struct nvme_command
*cmnd
;
531 struct nvme_iod
*iod
;
532 enum dma_data_direction dma_dir
;
533 int cmdid
, length
, result
= -ENOMEM
;
536 int psegs
= bio_phys_segments(ns
->queue
, bio
);
538 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
539 result
= nvme_submit_flush_data(nvmeq
, ns
);
544 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
550 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
551 if (unlikely(cmdid
< 0))
554 if (bio
->bi_rw
& REQ_DISCARD
) {
555 result
= nvme_submit_discard(nvmeq
, ns
, bio
, iod
, cmdid
);
560 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
561 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
564 if (bio
->bi_rw
& REQ_FUA
)
565 control
|= NVME_RW_FUA
;
566 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
567 control
|= NVME_RW_LR
;
570 if (bio
->bi_rw
& REQ_RAHEAD
)
571 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
573 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
575 memset(cmnd
, 0, sizeof(*cmnd
));
576 if (bio_data_dir(bio
)) {
577 cmnd
->rw
.opcode
= nvme_cmd_write
;
578 dma_dir
= DMA_TO_DEVICE
;
580 cmnd
->rw
.opcode
= nvme_cmd_read
;
581 dma_dir
= DMA_FROM_DEVICE
;
584 result
= nvme_map_bio(nvmeq
->q_dmadev
, iod
, bio
, dma_dir
, psegs
);
589 cmnd
->rw
.command_id
= cmdid
;
590 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
591 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
593 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
594 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
595 cmnd
->rw
.control
= cpu_to_le16(control
);
596 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
598 bio
->bi_sector
+= length
>> 9;
600 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
602 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
607 free_cmdid(nvmeq
, cmdid
, NULL
);
609 nvme_free_iod(nvmeq
->dev
, iod
);
614 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
616 struct nvme_ns
*ns
= q
->queuedata
;
617 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
620 spin_lock_irq(&nvmeq
->q_lock
);
621 if (bio_list_empty(&nvmeq
->sq_cong
))
622 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
623 if (unlikely(result
)) {
624 if (bio_list_empty(&nvmeq
->sq_cong
))
625 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
626 bio_list_add(&nvmeq
->sq_cong
, bio
);
629 spin_unlock_irq(&nvmeq
->q_lock
);
633 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
637 head
= nvmeq
->cq_head
;
638 phase
= nvmeq
->cq_phase
;
642 nvme_completion_fn fn
;
643 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
644 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
646 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
647 if (++head
== nvmeq
->q_depth
) {
652 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
653 fn(nvmeq
->dev
, ctx
, &cqe
);
656 /* If the controller ignores the cq head doorbell and continuously
657 * writes to the queue, it is theoretically possible to wrap around
658 * the queue twice and mistakenly return IRQ_NONE. Linux only
659 * requires that 0.1% of your interrupts are handled, so this isn't
662 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
665 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
666 nvmeq
->cq_head
= head
;
667 nvmeq
->cq_phase
= phase
;
672 static irqreturn_t
nvme_irq(int irq
, void *data
)
675 struct nvme_queue
*nvmeq
= data
;
676 spin_lock(&nvmeq
->q_lock
);
677 result
= nvme_process_cq(nvmeq
);
678 spin_unlock(&nvmeq
->q_lock
);
682 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
684 struct nvme_queue
*nvmeq
= data
;
685 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
686 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
688 return IRQ_WAKE_THREAD
;
691 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
693 spin_lock_irq(&nvmeq
->q_lock
);
694 cancel_cmdid(nvmeq
, cmdid
, NULL
);
695 spin_unlock_irq(&nvmeq
->q_lock
);
698 struct sync_cmd_info
{
699 struct task_struct
*task
;
704 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
705 struct nvme_completion
*cqe
)
707 struct sync_cmd_info
*cmdinfo
= ctx
;
708 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
709 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
710 wake_up_process(cmdinfo
->task
);
714 * Returns 0 on success. If the result is negative, it's a Linux error code;
715 * if the result is positive, it's an NVM Express status code
717 int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
718 u32
*result
, unsigned timeout
)
721 struct sync_cmd_info cmdinfo
;
723 cmdinfo
.task
= current
;
724 cmdinfo
.status
= -EINTR
;
726 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
730 cmd
->common
.command_id
= cmdid
;
732 set_current_state(TASK_KILLABLE
);
733 nvme_submit_cmd(nvmeq
, cmd
);
736 if (cmdinfo
.status
== -EINTR
) {
737 nvme_abort_command(nvmeq
, cmdid
);
742 *result
= cmdinfo
.result
;
744 return cmdinfo
.status
;
747 int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
750 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
753 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
756 struct nvme_command c
;
758 memset(&c
, 0, sizeof(c
));
759 c
.delete_queue
.opcode
= opcode
;
760 c
.delete_queue
.qid
= cpu_to_le16(id
);
762 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
768 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
769 struct nvme_queue
*nvmeq
)
772 struct nvme_command c
;
773 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
775 memset(&c
, 0, sizeof(c
));
776 c
.create_cq
.opcode
= nvme_admin_create_cq
;
777 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
778 c
.create_cq
.cqid
= cpu_to_le16(qid
);
779 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
780 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
781 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
783 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
789 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
790 struct nvme_queue
*nvmeq
)
793 struct nvme_command c
;
794 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
796 memset(&c
, 0, sizeof(c
));
797 c
.create_sq
.opcode
= nvme_admin_create_sq
;
798 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
799 c
.create_sq
.sqid
= cpu_to_le16(qid
);
800 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
801 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
802 c
.create_sq
.cqid
= cpu_to_le16(qid
);
804 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
810 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
812 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
815 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
817 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
820 int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
823 struct nvme_command c
;
825 memset(&c
, 0, sizeof(c
));
826 c
.identify
.opcode
= nvme_admin_identify
;
827 c
.identify
.nsid
= cpu_to_le32(nsid
);
828 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
829 c
.identify
.cns
= cpu_to_le32(cns
);
831 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
834 int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
, unsigned nsid
,
835 dma_addr_t dma_addr
, u32
*result
)
837 struct nvme_command c
;
839 memset(&c
, 0, sizeof(c
));
840 c
.features
.opcode
= nvme_admin_get_features
;
841 c
.features
.nsid
= cpu_to_le32(nsid
);
842 c
.features
.prp1
= cpu_to_le64(dma_addr
);
843 c
.features
.fid
= cpu_to_le32(fid
);
845 return nvme_submit_admin_cmd(dev
, &c
, result
);
848 int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
, unsigned dword11
,
849 dma_addr_t dma_addr
, u32
*result
)
851 struct nvme_command c
;
853 memset(&c
, 0, sizeof(c
));
854 c
.features
.opcode
= nvme_admin_set_features
;
855 c
.features
.prp1
= cpu_to_le64(dma_addr
);
856 c
.features
.fid
= cpu_to_le32(fid
);
857 c
.features
.dword11
= cpu_to_le32(dword11
);
859 return nvme_submit_admin_cmd(dev
, &c
, result
);
863 * nvme_cancel_ios - Cancel outstanding I/Os
864 * @queue: The queue to cancel I/Os on
865 * @timeout: True to only cancel I/Os which have timed out
867 static void nvme_cancel_ios(struct nvme_queue
*nvmeq
, bool timeout
)
869 int depth
= nvmeq
->q_depth
- 1;
870 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
871 unsigned long now
= jiffies
;
874 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
876 nvme_completion_fn fn
;
877 static struct nvme_completion cqe
= {
878 .status
= cpu_to_le16(NVME_SC_ABORT_REQ
) << 1,
881 if (timeout
&& !time_after(now
, info
[cmdid
].timeout
))
883 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d\n", cmdid
);
884 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
885 fn(nvmeq
->dev
, ctx
, &cqe
);
889 static void nvme_free_queue_mem(struct nvme_queue
*nvmeq
)
891 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
892 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
893 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
894 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
898 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
900 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
901 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
903 spin_lock_irq(&nvmeq
->q_lock
);
904 nvme_cancel_ios(nvmeq
, false);
905 while (bio_list_peek(&nvmeq
->sq_cong
)) {
906 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
907 bio_endio(bio
, -EIO
);
909 spin_unlock_irq(&nvmeq
->q_lock
);
911 irq_set_affinity_hint(vector
, NULL
);
912 free_irq(vector
, nvmeq
);
914 /* Don't tell the adapter to delete the admin queue */
916 adapter_delete_sq(dev
, qid
);
917 adapter_delete_cq(dev
, qid
);
920 nvme_free_queue_mem(nvmeq
);
923 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
924 int depth
, int vector
)
926 struct device
*dmadev
= &dev
->pci_dev
->dev
;
927 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
928 sizeof(struct nvme_cmd_info
));
929 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
933 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
934 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
937 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
939 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
940 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
944 nvmeq
->q_dmadev
= dmadev
;
946 spin_lock_init(&nvmeq
->q_lock
);
949 init_waitqueue_head(&nvmeq
->sq_full
);
950 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
951 bio_list_init(&nvmeq
->sq_cong
);
952 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
953 nvmeq
->q_depth
= depth
;
954 nvmeq
->cq_vector
= vector
;
959 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
966 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
969 if (use_threaded_interrupts
)
970 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
971 nvme_irq_check
, nvme_irq
,
972 IRQF_DISABLED
| IRQF_SHARED
,
974 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
975 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
978 static struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
, int qid
,
979 int cq_size
, int vector
)
982 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
985 return ERR_PTR(-ENOMEM
);
987 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
991 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
995 result
= queue_request_irq(dev
, nvmeq
, "nvme");
1002 adapter_delete_sq(dev
, qid
);
1004 adapter_delete_cq(dev
, qid
);
1006 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1007 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1008 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1009 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1011 return ERR_PTR(result
);
1014 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1019 unsigned long timeout
;
1020 struct nvme_queue
*nvmeq
;
1022 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1024 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
1028 aqa
= nvmeq
->q_depth
- 1;
1031 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1032 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1033 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1034 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1036 writel(0, &dev
->bar
->cc
);
1037 writel(aqa
, &dev
->bar
->aqa
);
1038 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1039 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1040 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1042 cap
= readq(&dev
->bar
->cap
);
1043 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1044 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1046 while (!result
&& !(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1048 if (fatal_signal_pending(current
))
1050 if (time_after(jiffies
, timeout
)) {
1051 dev_err(&dev
->pci_dev
->dev
,
1052 "Device not ready; aborting initialisation\n");
1058 nvme_free_queue_mem(nvmeq
);
1062 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1063 dev
->queues
[0] = nvmeq
;
1067 struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1068 unsigned long addr
, unsigned length
)
1070 int i
, err
, count
, nents
, offset
;
1071 struct scatterlist
*sg
;
1072 struct page
**pages
;
1073 struct nvme_iod
*iod
;
1076 return ERR_PTR(-EINVAL
);
1078 return ERR_PTR(-EINVAL
);
1080 offset
= offset_in_page(addr
);
1081 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1082 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1084 return ERR_PTR(-ENOMEM
);
1086 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1093 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1095 sg_init_table(sg
, count
);
1096 for (i
= 0; i
< count
; i
++) {
1097 sg_set_page(&sg
[i
], pages
[i
],
1098 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1099 length
-= (PAGE_SIZE
- offset
);
1102 sg_mark_end(&sg
[i
- 1]);
1106 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1107 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1117 for (i
= 0; i
< count
; i
++)
1120 return ERR_PTR(err
);
1123 void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1124 struct nvme_iod
*iod
)
1128 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1129 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1131 for (i
= 0; i
< iod
->nents
; i
++)
1132 put_page(sg_page(&iod
->sg
[i
]));
1135 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1137 struct nvme_dev
*dev
= ns
->dev
;
1138 struct nvme_queue
*nvmeq
;
1139 struct nvme_user_io io
;
1140 struct nvme_command c
;
1143 struct nvme_iod
*iod
;
1145 if (copy_from_user(&io
, uio
, sizeof(io
)))
1147 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1149 switch (io
.opcode
) {
1150 case nvme_cmd_write
:
1152 case nvme_cmd_compare
:
1153 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1160 return PTR_ERR(iod
);
1162 memset(&c
, 0, sizeof(c
));
1163 c
.rw
.opcode
= io
.opcode
;
1164 c
.rw
.flags
= io
.flags
;
1165 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1166 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1167 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1168 c
.rw
.control
= cpu_to_le16(io
.control
);
1169 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
1170 c
.rw
.reftag
= io
.reftag
;
1171 c
.rw
.apptag
= io
.apptag
;
1172 c
.rw
.appmask
= io
.appmask
;
1174 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1176 nvmeq
= get_nvmeq(dev
);
1178 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1179 * disabled. We may be preempted at any point, and be rescheduled
1180 * to a different CPU. That will cause cacheline bouncing, but no
1181 * additional races since q_lock already protects against other CPUs.
1184 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1187 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1189 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1190 nvme_free_iod(dev
, iod
);
1194 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1195 struct nvme_admin_cmd __user
*ucmd
)
1197 struct nvme_admin_cmd cmd
;
1198 struct nvme_command c
;
1200 struct nvme_iod
*uninitialized_var(iod
);
1202 if (!capable(CAP_SYS_ADMIN
))
1204 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1207 memset(&c
, 0, sizeof(c
));
1208 c
.common
.opcode
= cmd
.opcode
;
1209 c
.common
.flags
= cmd
.flags
;
1210 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1211 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1212 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1213 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1214 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1215 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1216 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1217 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1218 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1220 length
= cmd
.data_len
;
1222 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1225 return PTR_ERR(iod
);
1226 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1230 if (length
!= cmd
.data_len
)
1233 status
= nvme_submit_admin_cmd(dev
, &c
, &cmd
.result
);
1236 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1237 nvme_free_iod(dev
, iod
);
1240 if (!status
&& copy_to_user(&ucmd
->result
, &cmd
.result
,
1241 sizeof(cmd
.result
)))
1247 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1250 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1255 case NVME_IOCTL_ADMIN_CMD
:
1256 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1257 case NVME_IOCTL_SUBMIT_IO
:
1258 return nvme_submit_io(ns
, (void __user
*)arg
);
1259 case SG_GET_VERSION_NUM
:
1260 return nvme_sg_get_version_num((void __user
*)arg
);
1262 return nvme_sg_io(ns
, (void __user
*)arg
);
1268 static const struct block_device_operations nvme_fops
= {
1269 .owner
= THIS_MODULE
,
1270 .ioctl
= nvme_ioctl
,
1271 .compat_ioctl
= nvme_ioctl
,
1274 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1276 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1277 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1278 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1279 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1280 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1283 if (bio_list_empty(&nvmeq
->sq_cong
))
1284 remove_wait_queue(&nvmeq
->sq_full
,
1285 &nvmeq
->sq_cong_wait
);
1289 static int nvme_kthread(void *data
)
1291 struct nvme_dev
*dev
;
1293 while (!kthread_should_stop()) {
1294 __set_current_state(TASK_RUNNING
);
1295 spin_lock(&dev_list_lock
);
1296 list_for_each_entry(dev
, &dev_list
, node
) {
1298 for (i
= 0; i
< dev
->queue_count
; i
++) {
1299 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1302 spin_lock_irq(&nvmeq
->q_lock
);
1303 if (nvme_process_cq(nvmeq
))
1304 printk("process_cq did something\n");
1305 nvme_cancel_ios(nvmeq
, true);
1306 nvme_resubmit_bios(nvmeq
);
1307 spin_unlock_irq(&nvmeq
->q_lock
);
1310 spin_unlock(&dev_list_lock
);
1311 set_current_state(TASK_INTERRUPTIBLE
);
1312 schedule_timeout(HZ
);
1317 static DEFINE_IDA(nvme_index_ida
);
1319 static int nvme_get_ns_idx(void)
1324 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1327 spin_lock(&dev_list_lock
);
1328 error
= ida_get_new(&nvme_index_ida
, &index
);
1329 spin_unlock(&dev_list_lock
);
1330 } while (error
== -EAGAIN
);
1337 static void nvme_put_ns_idx(int index
)
1339 spin_lock(&dev_list_lock
);
1340 ida_remove(&nvme_index_ida
, index
);
1341 spin_unlock(&dev_list_lock
);
1344 static void nvme_config_discard(struct nvme_ns
*ns
)
1346 u32 logical_block_size
= queue_logical_block_size(ns
->queue
);
1347 ns
->queue
->limits
.discard_zeroes_data
= 0;
1348 ns
->queue
->limits
.discard_alignment
= logical_block_size
;
1349 ns
->queue
->limits
.discard_granularity
= logical_block_size
;
1350 ns
->queue
->limits
.max_discard_sectors
= 0xffffffff;
1351 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD
, ns
->queue
);
1354 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1355 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1358 struct gendisk
*disk
;
1361 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1364 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1367 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1370 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1371 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1372 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1373 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1375 ns
->queue
->queuedata
= ns
;
1377 disk
= alloc_disk(NVME_MINORS
);
1379 goto out_free_queue
;
1382 lbaf
= id
->flbas
& 0xf;
1383 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1384 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1385 if (dev
->max_hw_sectors
)
1386 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1388 disk
->major
= nvme_major
;
1389 disk
->minors
= NVME_MINORS
;
1390 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1391 disk
->fops
= &nvme_fops
;
1392 disk
->private_data
= ns
;
1393 disk
->queue
= ns
->queue
;
1394 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1395 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1396 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1398 if (dev
->oncs
& NVME_CTRL_ONCS_DSM
)
1399 nvme_config_discard(ns
);
1404 blk_cleanup_queue(ns
->queue
);
1410 static void nvme_ns_free(struct nvme_ns
*ns
)
1412 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1414 nvme_put_ns_idx(index
);
1415 blk_cleanup_queue(ns
->queue
);
1419 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1423 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1425 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1429 return min(result
& 0xffff, result
>> 16) + 1;
1432 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1434 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1436 nr_io_queues
= num_online_cpus();
1437 result
= set_queue_count(dev
, nr_io_queues
);
1440 if (result
< nr_io_queues
)
1441 nr_io_queues
= result
;
1443 /* Deregister the admin queue's interrupt */
1444 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1446 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1447 if (db_bar_size
> 8192) {
1449 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1451 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1452 dev
->queues
[0]->q_db
= dev
->dbs
;
1455 for (i
= 0; i
< nr_io_queues
; i
++)
1456 dev
->entry
[i
].entry
= i
;
1458 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1462 } else if (result
> 0) {
1463 nr_io_queues
= result
;
1471 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1472 /* XXX: handle failure here */
1474 cpu
= cpumask_first(cpu_online_mask
);
1475 for (i
= 0; i
< nr_io_queues
; i
++) {
1476 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1477 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1480 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1482 for (i
= 0; i
< nr_io_queues
; i
++) {
1483 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1484 if (IS_ERR(dev
->queues
[i
+ 1]))
1485 return PTR_ERR(dev
->queues
[i
+ 1]);
1489 for (; i
< num_possible_cpus(); i
++) {
1490 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1491 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1497 static void nvme_free_queues(struct nvme_dev
*dev
)
1501 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1502 nvme_free_queue(dev
, i
);
1505 static int nvme_dev_add(struct nvme_dev
*dev
)
1508 struct nvme_ns
*ns
, *next
;
1509 struct nvme_id_ctrl
*ctrl
;
1510 struct nvme_id_ns
*id_ns
;
1512 dma_addr_t dma_addr
;
1514 res
= nvme_setup_io_queues(dev
);
1518 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1521 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1528 nn
= le32_to_cpup(&ctrl
->nn
);
1529 dev
->oncs
= le16_to_cpup(&ctrl
->oncs
);
1530 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1531 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1532 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1534 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1535 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1539 for (i
= 1; i
<= nn
; i
++) {
1540 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1544 if (id_ns
->ncap
== 0)
1547 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1548 dma_addr
+ 4096, NULL
);
1550 memset(mem
+ 4096, 0, 4096);
1552 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1554 list_add_tail(&ns
->list
, &dev
->namespaces
);
1556 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1562 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1563 list_del(&ns
->list
);
1568 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1572 static int nvme_dev_remove(struct nvme_dev
*dev
)
1574 struct nvme_ns
*ns
, *next
;
1576 spin_lock(&dev_list_lock
);
1577 list_del(&dev
->node
);
1578 spin_unlock(&dev_list_lock
);
1580 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1581 list_del(&ns
->list
);
1582 del_gendisk(ns
->disk
);
1586 nvme_free_queues(dev
);
1591 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1593 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1594 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1595 PAGE_SIZE
, PAGE_SIZE
, 0);
1596 if (!dev
->prp_page_pool
)
1599 /* Optimisation for I/Os between 4k and 128k */
1600 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1602 if (!dev
->prp_small_pool
) {
1603 dma_pool_destroy(dev
->prp_page_pool
);
1609 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1611 dma_pool_destroy(dev
->prp_page_pool
);
1612 dma_pool_destroy(dev
->prp_small_pool
);
1615 static DEFINE_IDA(nvme_instance_ida
);
1617 static int nvme_set_instance(struct nvme_dev
*dev
)
1619 int instance
, error
;
1622 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
1625 spin_lock(&dev_list_lock
);
1626 error
= ida_get_new(&nvme_instance_ida
, &instance
);
1627 spin_unlock(&dev_list_lock
);
1628 } while (error
== -EAGAIN
);
1633 dev
->instance
= instance
;
1637 static void nvme_release_instance(struct nvme_dev
*dev
)
1639 spin_lock(&dev_list_lock
);
1640 ida_remove(&nvme_instance_ida
, dev
->instance
);
1641 spin_unlock(&dev_list_lock
);
1644 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1646 int bars
, result
= -ENOMEM
;
1647 struct nvme_dev
*dev
;
1649 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1652 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1656 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1661 if (pci_enable_device_mem(pdev
))
1663 pci_set_master(pdev
);
1664 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1665 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1668 INIT_LIST_HEAD(&dev
->namespaces
);
1669 dev
->pci_dev
= pdev
;
1670 pci_set_drvdata(pdev
, dev
);
1671 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1672 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1673 result
= nvme_set_instance(dev
);
1677 dev
->entry
[0].vector
= pdev
->irq
;
1679 result
= nvme_setup_prp_pools(dev
);
1683 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1689 result
= nvme_configure_admin_queue(dev
);
1694 spin_lock(&dev_list_lock
);
1695 list_add(&dev
->node
, &dev_list
);
1696 spin_unlock(&dev_list_lock
);
1698 result
= nvme_dev_add(dev
);
1705 spin_lock(&dev_list_lock
);
1706 list_del(&dev
->node
);
1707 spin_unlock(&dev_list_lock
);
1709 nvme_free_queues(dev
);
1713 pci_disable_msix(pdev
);
1714 nvme_release_instance(dev
);
1715 nvme_release_prp_pools(dev
);
1717 pci_disable_device(pdev
);
1718 pci_release_regions(pdev
);
1726 static void nvme_remove(struct pci_dev
*pdev
)
1728 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1729 nvme_dev_remove(dev
);
1730 pci_disable_msix(pdev
);
1732 nvme_release_instance(dev
);
1733 nvme_release_prp_pools(dev
);
1734 pci_disable_device(pdev
);
1735 pci_release_regions(pdev
);
1741 /* These functions are yet to be implemented */
1742 #define nvme_error_detected NULL
1743 #define nvme_dump_registers NULL
1744 #define nvme_link_reset NULL
1745 #define nvme_slot_reset NULL
1746 #define nvme_error_resume NULL
1747 #define nvme_suspend NULL
1748 #define nvme_resume NULL
1750 static const struct pci_error_handlers nvme_err_handler
= {
1751 .error_detected
= nvme_error_detected
,
1752 .mmio_enabled
= nvme_dump_registers
,
1753 .link_reset
= nvme_link_reset
,
1754 .slot_reset
= nvme_slot_reset
,
1755 .resume
= nvme_error_resume
,
1758 /* Move to pci_ids.h later */
1759 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1761 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1762 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1765 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1767 static struct pci_driver nvme_driver
= {
1769 .id_table
= nvme_id_table
,
1770 .probe
= nvme_probe
,
1771 .remove
= nvme_remove
,
1772 .suspend
= nvme_suspend
,
1773 .resume
= nvme_resume
,
1774 .err_handler
= &nvme_err_handler
,
1777 static int __init
nvme_init(void)
1781 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1782 if (IS_ERR(nvme_thread
))
1783 return PTR_ERR(nvme_thread
);
1785 result
= register_blkdev(nvme_major
, "nvme");
1788 else if (result
> 0)
1789 nvme_major
= result
;
1791 result
= pci_register_driver(&nvme_driver
);
1793 goto unregister_blkdev
;
1797 unregister_blkdev(nvme_major
, "nvme");
1799 kthread_stop(nvme_thread
);
1803 static void __exit
nvme_exit(void)
1805 pci_unregister_driver(&nvme_driver
);
1806 unregister_blkdev(nvme_major
, "nvme");
1807 kthread_stop(nvme_thread
);
1810 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1811 MODULE_LICENSE("GPL");
1812 MODULE_VERSION("0.8");
1813 module_init(nvme_init
);
1814 module_exit(nvme_exit
);