projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
libata: kill ATA_LFLAG_SKIP_D2H_BSY
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
113
114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
119
120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
122
123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
128 /* 32 bit regs */
129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
150 PORT_CONTEXT = 0x1e04,
151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
183
184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
187
188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
220
221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
244
245 SIL24_MAX_CMDS = 31,
246
247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
250 BID_SIL3131 = 2,
251
252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
256 ATA_FLAG_AN | ATA_FLAG_PMP,
257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
258
259 IRQ_STAT_4PORTS = 0xf,
260 };
261
262 struct sil24_ata_block {
263 struct sil24_prb prb;
264 struct sil24_sge sge[SIL24_MAX_SGE];
265 };
266
267 struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
270 struct sil24_sge sge[SIL24_MAX_SGE];
271 };
272
273 union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276 };
277
278 static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281 } sil24_cerr_db[] = {
282 [0] = { AC_ERR_DEV, 0,
283 "device error" },
284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
285 "device error via D2H FIS" },
286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
287 "device error via SDB FIS" },
288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
289 "error in data FIS" },
290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
291 "failed to transmit command FIS" },
292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
293 "protocol mismatch" },
294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
295 "data directon mismatch" },
296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
297 "ran out of SGEs while writing" },
298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
299 "ran out of SGEs while reading" },
300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
301 "invalid data directon for ATAPI CDB" },
302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
303 "SGT not on qword boundary" },
304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
305 "PCI target abort while fetching SGT" },
306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
307 "PCI master abort while fetching SGT" },
308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
309 "PCI parity error while fetching SGT" },
310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
311 "PRB not on qword boundary" },
312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
313 "PCI target abort while fetching PRB" },
314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
315 "PCI master abort while fetching PRB" },
316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
317 "PCI parity error while fetching PRB" },
318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
319 "undefined error while transferring data" },
320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
321 "PCI target abort while transferring data" },
322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
323 "PCI master abort while transferring data" },
324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
325 "PCI parity error while transferring data" },
326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
327 "FIS received while sending service FIS" },
328 };
329
330 /*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336 struct sil24_port_priv {
337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
339 struct ata_taskfile tf; /* Cached taskfile registers */
340 int do_port_rst;
341 };
342
343 static void sil24_dev_config(struct ata_device *dev);
344 static u8 sil24_check_status(struct ata_port *ap);
345 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
346 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
347 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
348 static int sil24_qc_defer(struct ata_queued_cmd *qc);
349 static void sil24_qc_prep(struct ata_queued_cmd *qc);
350 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
351 static void sil24_irq_clear(struct ata_port *ap);
352 static void sil24_pmp_attach(struct ata_port *ap);
353 static void sil24_pmp_detach(struct ata_port *ap);
354 static void sil24_freeze(struct ata_port *ap);
355 static void sil24_thaw(struct ata_port *ap);
356 static void sil24_error_handler(struct ata_port *ap);
357 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
358 static int sil24_port_start(struct ata_port *ap);
359 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
360 #ifdef CONFIG_PM
361 static int sil24_pci_device_resume(struct pci_dev *pdev);
362 static int sil24_port_resume(struct ata_port *ap);
363 #endif
364
365 static const struct pci_device_id sil24_pci_tbl[] = {
366 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
367 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
368 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
369 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
370 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
371 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
372
373 { } /* terminate list */
374 };
375
376 static struct pci_driver sil24_pci_driver = {
377 .name = DRV_NAME,
378 .id_table = sil24_pci_tbl,
379 .probe = sil24_init_one,
380 .remove = ata_pci_remove_one,
381 #ifdef CONFIG_PM
382 .suspend = ata_pci_device_suspend,
383 .resume = sil24_pci_device_resume,
384 #endif
385 };
386
387 static struct scsi_host_template sil24_sht = {
388 .module = THIS_MODULE,
389 .name = DRV_NAME,
390 .ioctl = ata_scsi_ioctl,
391 .queuecommand = ata_scsi_queuecmd,
392 .change_queue_depth = ata_scsi_change_queue_depth,
393 .can_queue = SIL24_MAX_CMDS,
394 .this_id = ATA_SHT_THIS_ID,
395 .sg_tablesize = SIL24_MAX_SGE,
396 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
397 .emulated = ATA_SHT_EMULATED,
398 .use_clustering = ATA_SHT_USE_CLUSTERING,
399 .proc_name = DRV_NAME,
400 .dma_boundary = ATA_DMA_BOUNDARY,
401 .slave_configure = ata_scsi_slave_config,
402 .slave_destroy = ata_scsi_slave_destroy,
403 .bios_param = ata_std_bios_param,
404 };
405
406 static const struct ata_port_operations sil24_ops = {
407 .dev_config = sil24_dev_config,
408
409 .check_status = sil24_check_status,
410 .check_altstatus = sil24_check_status,
411 .dev_select = ata_noop_dev_select,
412
413 .tf_read = sil24_tf_read,
414
415 .qc_defer = sil24_qc_defer,
416 .qc_prep = sil24_qc_prep,
417 .qc_issue = sil24_qc_issue,
418
419 .irq_clear = sil24_irq_clear,
420
421 .scr_read = sil24_scr_read,
422 .scr_write = sil24_scr_write,
423
424 .pmp_attach = sil24_pmp_attach,
425 .pmp_detach = sil24_pmp_detach,
426
427 .freeze = sil24_freeze,
428 .thaw = sil24_thaw,
429 .error_handler = sil24_error_handler,
430 .post_internal_cmd = sil24_post_internal_cmd,
431
432 .port_start = sil24_port_start,
433
434 #ifdef CONFIG_PM
435 .port_resume = sil24_port_resume,
436 #endif
437 };
438
439 /*
440 * Use bits 30-31 of port_flags to encode available port numbers.
441 * Current maxium is 4.
442 */
443 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
444 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
445
446 static const struct ata_port_info sil24_port_info[] = {
447 /* sil_3124 */
448 {
449 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
450 SIL24_FLAG_PCIX_IRQ_WOC,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .mwdma_mask = 0x07, /* mwdma0-2 */
453 .udma_mask = ATA_UDMA5, /* udma0-5 */
454 .port_ops = &sil24_ops,
455 },
456 /* sil_3132 */
457 {
458 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
459 .pio_mask = 0x1f, /* pio0-4 */
460 .mwdma_mask = 0x07, /* mwdma0-2 */
461 .udma_mask = ATA_UDMA5, /* udma0-5 */
462 .port_ops = &sil24_ops,
463 },
464 /* sil_3131/sil_3531 */
465 {
466 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
467 .pio_mask = 0x1f, /* pio0-4 */
468 .mwdma_mask = 0x07, /* mwdma0-2 */
469 .udma_mask = ATA_UDMA5, /* udma0-5 */
470 .port_ops = &sil24_ops,
471 },
472 };
473
474 static int sil24_tag(int tag)
475 {
476 if (unlikely(ata_tag_internal(tag)))
477 return 0;
478 return tag;
479 }
480
481 static void sil24_dev_config(struct ata_device *dev)
482 {
483 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
484
485 if (dev->cdb_len == 16)
486 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
487 else
488 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
489 }
490
491 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
492 {
493 void __iomem *port = ap->ioaddr.cmd_addr;
494 struct sil24_prb __iomem *prb;
495 u8 fis[6 * 4];
496
497 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
498 memcpy_fromio(fis, prb->fis, sizeof(fis));
499 ata_tf_from_fis(fis, tf);
500 }
501
502 static u8 sil24_check_status(struct ata_port *ap)
503 {
504 struct sil24_port_priv *pp = ap->private_data;
505 return pp->tf.command;
506 }
507
508 static int sil24_scr_map[] = {
509 [SCR_CONTROL] = 0,
510 [SCR_STATUS] = 1,
511 [SCR_ERROR] = 2,
512 [SCR_ACTIVE] = 3,
513 };
514
515 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
516 {
517 void __iomem *scr_addr = ap->ioaddr.scr_addr;
518
519 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
520 void __iomem *addr;
521 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
522 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
523 return 0;
524 }
525 return -EINVAL;
526 }
527
528 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
529 {
530 void __iomem *scr_addr = ap->ioaddr.scr_addr;
531
532 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
533 void __iomem *addr;
534 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
535 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
536 return 0;
537 }
538 return -EINVAL;
539 }
540
541 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
542 {
543 struct sil24_port_priv *pp = ap->private_data;
544 *tf = pp->tf;
545 }
546
547 static void sil24_config_port(struct ata_port *ap)
548 {
549 void __iomem *port = ap->ioaddr.cmd_addr;
550
551 /* configure IRQ WoC */
552 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
553 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
554 else
555 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
556
557 /* zero error counters. */
558 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
559 writel(0x8000, port + PORT_CRC_ERR_THRESH);
560 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
561 writel(0x0000, port + PORT_DECODE_ERR_CNT);
562 writel(0x0000, port + PORT_CRC_ERR_CNT);
563 writel(0x0000, port + PORT_HSHK_ERR_CNT);
564
565 /* always use 64bit activation */
566 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
567
568 /* clear port multiplier enable and resume bits */
569 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
570 }
571
572 static void sil24_config_pmp(struct ata_port *ap, int attached)
573 {
574 void __iomem *port = ap->ioaddr.cmd_addr;
575
576 if (attached)
577 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
578 else
579 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
580 }
581
582 static void sil24_clear_pmp(struct ata_port *ap)
583 {
584 void __iomem *port = ap->ioaddr.cmd_addr;
585 int i;
586
587 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
588
589 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
590 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
591
592 writel(0, pmp_base + PORT_PMP_STATUS);
593 writel(0, pmp_base + PORT_PMP_QACTIVE);
594 }
595 }
596
597 static int sil24_init_port(struct ata_port *ap)
598 {
599 void __iomem *port = ap->ioaddr.cmd_addr;
600 struct sil24_port_priv *pp = ap->private_data;
601 u32 tmp;
602
603 /* clear PMP error status */
604 if (ap->nr_pmp_links)
605 sil24_clear_pmp(ap);
606
607 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
608 ata_wait_register(port + PORT_CTRL_STAT,
609 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
610 tmp = ata_wait_register(port + PORT_CTRL_STAT,
611 PORT_CS_RDY, 0, 10, 100);
612
613 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
614 pp->do_port_rst = 1;
615 ap->link.eh_context.i.action |= ATA_EH_RESET;
616 return -EIO;
617 }
618
619 return 0;
620 }
621
622 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
623 const struct ata_taskfile *tf,
624 int is_cmd, u32 ctrl,
625 unsigned long timeout_msec)
626 {
627 void __iomem *port = ap->ioaddr.cmd_addr;
628 struct sil24_port_priv *pp = ap->private_data;
629 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
630 dma_addr_t paddr = pp->cmd_block_dma;
631 u32 irq_enabled, irq_mask, irq_stat;
632 int rc;
633
634 prb->ctrl = cpu_to_le16(ctrl);
635 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
636
637 /* temporarily plug completion and error interrupts */
638 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
639 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
640
641 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
642 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
643
644 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
645 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
646 10, timeout_msec);
647
648 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
649 irq_stat >>= PORT_IRQ_RAW_SHIFT;
650
651 if (irq_stat & PORT_IRQ_COMPLETE)
652 rc = 0;
653 else {
654 /* force port into known state */
655 sil24_init_port(ap);
656
657 if (irq_stat & PORT_IRQ_ERROR)
658 rc = -EIO;
659 else
660 rc = -EBUSY;
661 }
662
663 /* restore IRQ enabled */
664 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
665
666 return rc;
667 }
668
669 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
670 int pmp, unsigned long deadline)
671 {
672 struct ata_port *ap = link->ap;
673 unsigned long timeout_msec = 0;
674 struct ata_taskfile tf;
675 const char *reason;
676 int rc;
677
678 DPRINTK("ENTER\n");
679
680 if (ata_link_offline(link)) {
681 DPRINTK("PHY reports no device\n");
682 *class = ATA_DEV_NONE;
683 goto out;
684 }
685
686 /* put the port into known state */
687 if (sil24_init_port(ap)) {
688 reason = "port not ready";
689 goto err;
690 }
691
692 /* do SRST */
693 if (time_after(deadline, jiffies))
694 timeout_msec = jiffies_to_msecs(deadline - jiffies);
695
696 ata_tf_init(link->device, &tf); /* doesn't really matter */
697 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
698 timeout_msec);
699 if (rc == -EBUSY) {
700 reason = "timeout";
701 goto err;
702 } else if (rc) {
703 reason = "SRST command error";
704 goto err;
705 }
706
707 sil24_read_tf(ap, 0, &tf);
708 *class = ata_dev_classify(&tf);
709
710 if (*class == ATA_DEV_UNKNOWN)
711 *class = ATA_DEV_NONE;
712
713 out:
714 DPRINTK("EXIT, class=%u\n", *class);
715 return 0;
716
717 err:
718 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
719 return -EIO;
720 }
721
722 static int sil24_softreset(struct ata_link *link, unsigned int *class,
723 unsigned long deadline)
724 {
725 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
726 }
727
728 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
729 unsigned long deadline)
730 {
731 struct ata_port *ap = link->ap;
732 void __iomem *port = ap->ioaddr.cmd_addr;
733 struct sil24_port_priv *pp = ap->private_data;
734 int did_port_rst = 0;
735 const char *reason;
736 int tout_msec, rc;
737 u32 tmp;
738
739 retry:
740 /* Sometimes, DEV_RST is not enough to recover the controller.
741 * This happens often after PM DMA CS errata.
742 */
743 if (pp->do_port_rst) {
744 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
745 "state, performing PORT_RST\n");
746
747 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
748 msleep(10);
749 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
750 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
751 10, 5000);
752
753 /* restore port configuration */
754 sil24_config_port(ap);
755 sil24_config_pmp(ap, ap->nr_pmp_links);
756
757 pp->do_port_rst = 0;
758 did_port_rst = 1;
759 }
760
761 /* sil24 does the right thing(tm) without any protection */
762 sata_set_spd(link);
763
764 tout_msec = 100;
765 if (ata_link_online(link))
766 tout_msec = 5000;
767
768 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
769 tmp = ata_wait_register(port + PORT_CTRL_STAT,
770 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
771 tout_msec);
772
773 /* SStatus oscillates between zero and valid status after
774 * DEV_RST, debounce it.
775 */
776 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
777 if (rc) {
778 reason = "PHY debouncing failed";
779 goto err;
780 }
781
782 if (tmp & PORT_CS_DEV_RST) {
783 if (ata_link_offline(link))
784 return 0;
785 reason = "link not ready";
786 goto err;
787 }
788
789 /* Sil24 doesn't store signature FIS after hardreset, so we
790 * can't wait for BSY to clear. Some devices take a long time
791 * to get ready and those devices will choke if we don't wait
792 * for BSY clearance here. Tell libata to perform follow-up
793 * softreset.
794 */
795 return -EAGAIN;
796
797 err:
798 if (!did_port_rst) {
799 pp->do_port_rst = 1;
800 goto retry;
801 }
802
803 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
804 return -EIO;
805 }
806
807 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
808 struct sil24_sge *sge)
809 {
810 struct scatterlist *sg;
811 struct sil24_sge *last_sge = NULL;
812 unsigned int si;
813
814 for_each_sg(qc->sg, sg, qc->n_elem, si) {
815 sge->addr = cpu_to_le64(sg_dma_address(sg));
816 sge->cnt = cpu_to_le32(sg_dma_len(sg));
817 sge->flags = 0;
818
819 last_sge = sge;
820 sge++;
821 }
822
823 last_sge->flags = cpu_to_le32(SGE_TRM);
824 }
825
826 static int sil24_qc_defer(struct ata_queued_cmd *qc)
827 {
828 struct ata_link *link = qc->dev->link;
829 struct ata_port *ap = link->ap;
830 u8 prot = qc->tf.protocol;
831
832 /*
833 * There is a bug in the chip:
834 * Port LRAM Causes the PRB/SGT Data to be Corrupted
835 * If the host issues a read request for LRAM and SActive registers
836 * while active commands are available in the port, PRB/SGT data in
837 * the LRAM can become corrupted. This issue applies only when
838 * reading from, but not writing to, the LRAM.
839 *
840 * Therefore, reading LRAM when there is no particular error [and
841 * other commands may be outstanding] is prohibited.
842 *
843 * To avoid this bug there are two situations where a command must run
844 * exclusive of any other commands on the port:
845 *
846 * - ATAPI commands which check the sense data
847 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
848 * set.
849 *
850 */
851 int is_excl = (ata_is_atapi(prot) ||
852 (qc->flags & ATA_QCFLAG_RESULT_TF));
853
854 if (unlikely(ap->excl_link)) {
855 if (link == ap->excl_link) {
856 if (ap->nr_active_links)
857 return ATA_DEFER_PORT;
858 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
859 } else
860 return ATA_DEFER_PORT;
861 } else if (unlikely(is_excl)) {
862 ap->excl_link = link;
863 if (ap->nr_active_links)
864 return ATA_DEFER_PORT;
865 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
866 }
867
868 return ata_std_qc_defer(qc);
869 }
870
871 static void sil24_qc_prep(struct ata_queued_cmd *qc)
872 {
873 struct ata_port *ap = qc->ap;
874 struct sil24_port_priv *pp = ap->private_data;
875 union sil24_cmd_block *cb;
876 struct sil24_prb *prb;
877 struct sil24_sge *sge;
878 u16 ctrl = 0;
879
880 cb = &pp->cmd_block[sil24_tag(qc->tag)];
881
882 if (!ata_is_atapi(qc->tf.protocol)) {
883 prb = &cb->ata.prb;
884 sge = cb->ata.sge;
885 } else {
886 prb = &cb->atapi.prb;
887 sge = cb->atapi.sge;
888 memset(cb->atapi.cdb, 0, 32);
889 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
890
891 if (ata_is_data(qc->tf.protocol)) {
892 if (qc->tf.flags & ATA_TFLAG_WRITE)
893 ctrl = PRB_CTRL_PACKET_WRITE;
894 else
895 ctrl = PRB_CTRL_PACKET_READ;
896 }
897 }
898
899 prb->ctrl = cpu_to_le16(ctrl);
900 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
901
902 if (qc->flags & ATA_QCFLAG_DMAMAP)
903 sil24_fill_sg(qc, sge);
904 }
905
906 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
907 {
908 struct ata_port *ap = qc->ap;
909 struct sil24_port_priv *pp = ap->private_data;
910 void __iomem *port = ap->ioaddr.cmd_addr;
911 unsigned int tag = sil24_tag(qc->tag);
912 dma_addr_t paddr;
913 void __iomem *activate;
914
915 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
916 activate = port + PORT_CMD_ACTIVATE + tag * 8;
917
918 writel((u32)paddr, activate);
919 writel((u64)paddr >> 32, activate + 4);
920
921 return 0;
922 }
923
924 static void sil24_irq_clear(struct ata_port *ap)
925 {
926 /* unused */
927 }
928
929 static void sil24_pmp_attach(struct ata_port *ap)
930 {
931 sil24_config_pmp(ap, 1);
932 sil24_init_port(ap);
933 }
934
935 static void sil24_pmp_detach(struct ata_port *ap)
936 {
937 sil24_init_port(ap);
938 sil24_config_pmp(ap, 0);
939 }
940
941 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
942 unsigned long deadline)
943 {
944 return sil24_do_softreset(link, class, link->pmp, deadline);
945 }
946
947 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
948 unsigned long deadline)
949 {
950 int rc;
951
952 rc = sil24_init_port(link->ap);
953 if (rc) {
954 ata_link_printk(link, KERN_ERR,
955 "hardreset failed (port not ready)\n");
956 return rc;
957 }
958
959 return sata_pmp_std_hardreset(link, class, deadline);
960 }
961
962 static void sil24_freeze(struct ata_port *ap)
963 {
964 void __iomem *port = ap->ioaddr.cmd_addr;
965
966 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
967 * PORT_IRQ_ENABLE instead.
968 */
969 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
970 }
971
972 static void sil24_thaw(struct ata_port *ap)
973 {
974 void __iomem *port = ap->ioaddr.cmd_addr;
975 u32 tmp;
976
977 /* clear IRQ */
978 tmp = readl(port + PORT_IRQ_STAT);
979 writel(tmp, port + PORT_IRQ_STAT);
980
981 /* turn IRQ back on */
982 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
983 }
984
985 static void sil24_error_intr(struct ata_port *ap)
986 {
987 void __iomem *port = ap->ioaddr.cmd_addr;
988 struct sil24_port_priv *pp = ap->private_data;
989 struct ata_queued_cmd *qc = NULL;
990 struct ata_link *link;
991 struct ata_eh_info *ehi;
992 int abort = 0, freeze = 0;
993 u32 irq_stat;
994
995 /* on error, we need to clear IRQ explicitly */
996 irq_stat = readl(port + PORT_IRQ_STAT);
997 writel(irq_stat, port + PORT_IRQ_STAT);
998
999 /* first, analyze and record host port events */
1000 link = &ap->link;
1001 ehi = &link->eh_info;
1002 ata_ehi_clear_desc(ehi);
1003
1004 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1005
1006 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
1007 ata_ehi_push_desc(ehi, "SDB notify");
1008 sata_async_notification(ap);
1009 }
1010
1011 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1012 ata_ehi_hotplugged(ehi);
1013 ata_ehi_push_desc(ehi, "%s",
1014 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1015 "PHY RDY changed" : "device exchanged");
1016 freeze = 1;
1017 }
1018
1019 if (irq_stat & PORT_IRQ_UNK_FIS) {
1020 ehi->err_mask |= AC_ERR_HSM;
1021 ehi->action |= ATA_EH_RESET;
1022 ata_ehi_push_desc(ehi, "unknown FIS");
1023 freeze = 1;
1024 }
1025
1026 /* deal with command error */
1027 if (irq_stat & PORT_IRQ_ERROR) {
1028 struct sil24_cerr_info *ci = NULL;
1029 unsigned int err_mask = 0, action = 0;
1030 u32 context, cerr;
1031 int pmp;
1032
1033 abort = 1;
1034
1035 /* DMA Context Switch Failure in Port Multiplier Mode
1036 * errata. If we have active commands to 3 or more
1037 * devices, any error condition on active devices can
1038 * corrupt DMA context switching.
1039 */
1040 if (ap->nr_active_links >= 3) {
1041 ehi->err_mask |= AC_ERR_OTHER;
1042 ehi->action |= ATA_EH_RESET;
1043 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1044 pp->do_port_rst = 1;
1045 freeze = 1;
1046 }
1047
1048 /* find out the offending link and qc */
1049 if (ap->nr_pmp_links) {
1050 context = readl(port + PORT_CONTEXT);
1051 pmp = (context >> 5) & 0xf;
1052
1053 if (pmp < ap->nr_pmp_links) {
1054 link = &ap->pmp_link[pmp];
1055 ehi = &link->eh_info;
1056 qc = ata_qc_from_tag(ap, link->active_tag);
1057
1058 ata_ehi_clear_desc(ehi);
1059 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1060 irq_stat);
1061 } else {
1062 err_mask |= AC_ERR_HSM;
1063 action |= ATA_EH_RESET;
1064 freeze = 1;
1065 }
1066 } else
1067 qc = ata_qc_from_tag(ap, link->active_tag);
1068
1069 /* analyze CMD_ERR */
1070 cerr = readl(port + PORT_CMD_ERR);
1071 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1072 ci = &sil24_cerr_db[cerr];
1073
1074 if (ci && ci->desc) {
1075 err_mask |= ci->err_mask;
1076 action |= ci->action;
1077 if (action & ATA_EH_RESET)
1078 freeze = 1;
1079 ata_ehi_push_desc(ehi, "%s", ci->desc);
1080 } else {
1081 err_mask |= AC_ERR_OTHER;
1082 action |= ATA_EH_RESET;
1083 freeze = 1;
1084 ata_ehi_push_desc(ehi, "unknown command error %d",
1085 cerr);
1086 }
1087
1088 /* record error info */
1089 if (qc) {
1090 sil24_read_tf(ap, qc->tag, &pp->tf);
1091 qc->err_mask |= err_mask;
1092 } else
1093 ehi->err_mask |= err_mask;
1094
1095 ehi->action |= action;
1096
1097 /* if PMP, resume */
1098 if (ap->nr_pmp_links)
1099 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1100 }
1101
1102 /* freeze or abort */
1103 if (freeze)
1104 ata_port_freeze(ap);
1105 else if (abort) {
1106 if (qc)
1107 ata_link_abort(qc->dev->link);
1108 else
1109 ata_port_abort(ap);
1110 }
1111 }
1112
1113 static void sil24_finish_qc(struct ata_queued_cmd *qc)
1114 {
1115 struct ata_port *ap = qc->ap;
1116 struct sil24_port_priv *pp = ap->private_data;
1117
1118 if (qc->flags & ATA_QCFLAG_RESULT_TF)
1119 sil24_read_tf(ap, qc->tag, &pp->tf);
1120 }
1121
1122 static inline void sil24_host_intr(struct ata_port *ap)
1123 {
1124 void __iomem *port = ap->ioaddr.cmd_addr;
1125 u32 slot_stat, qc_active;
1126 int rc;
1127
1128 /* If PCIX_IRQ_WOC, there's an inherent race window between
1129 * clearing IRQ pending status and reading PORT_SLOT_STAT
1130 * which may cause spurious interrupts afterwards. This is
1131 * unavoidable and much better than losing interrupts which
1132 * happens if IRQ pending is cleared after reading
1133 * PORT_SLOT_STAT.
1134 */
1135 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1136 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1137
1138 slot_stat = readl(port + PORT_SLOT_STAT);
1139
1140 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1141 sil24_error_intr(ap);
1142 return;
1143 }
1144
1145 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1146 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1147 if (rc > 0)
1148 return;
1149 if (rc < 0) {
1150 struct ata_eh_info *ehi = &ap->link.eh_info;
1151 ehi->err_mask |= AC_ERR_HSM;
1152 ehi->action |= ATA_EH_RESET;
1153 ata_port_freeze(ap);
1154 return;
1155 }
1156
1157 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1158 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1159 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1160 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1161 slot_stat, ap->link.active_tag, ap->link.sactive);
1162 }
1163
1164 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1165 {
1166 struct ata_host *host = dev_instance;
1167 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1168 unsigned handled = 0;
1169 u32 status;
1170 int i;
1171
1172 status = readl(host_base + HOST_IRQ_STAT);
1173
1174 if (status == 0xffffffff) {
1175 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1176 "PCI fault or device removal?\n");
1177 goto out;
1178 }
1179
1180 if (!(status & IRQ_STAT_4PORTS))
1181 goto out;
1182
1183 spin_lock(&host->lock);
1184
1185 for (i = 0; i < host->n_ports; i++)
1186 if (status & (1 << i)) {
1187 struct ata_port *ap = host->ports[i];
1188 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1189 sil24_host_intr(ap);
1190 handled++;
1191 } else
1192 printk(KERN_ERR DRV_NAME
1193 ": interrupt from disabled port %d\n", i);
1194 }
1195
1196 spin_unlock(&host->lock);
1197 out:
1198 return IRQ_RETVAL(handled);
1199 }
1200
1201 static void sil24_error_handler(struct ata_port *ap)
1202 {
1203 struct sil24_port_priv *pp = ap->private_data;
1204
1205 if (sil24_init_port(ap))
1206 ata_eh_freeze_port(ap);
1207
1208 /* perform recovery */
1209 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
1210 ata_std_postreset, sata_pmp_std_prereset,
1211 sil24_pmp_softreset, sil24_pmp_hardreset,
1212 sata_pmp_std_postreset);
1213
1214 pp->do_port_rst = 0;
1215 }
1216
1217 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1218 {
1219 struct ata_port *ap = qc->ap;
1220
1221 /* make DMA engine forget about the failed command */
1222 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1223 ata_eh_freeze_port(ap);
1224 }
1225
1226 static int sil24_port_start(struct ata_port *ap)
1227 {
1228 struct device *dev = ap->host->dev;
1229 struct sil24_port_priv *pp;
1230 union sil24_cmd_block *cb;
1231 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1232 dma_addr_t cb_dma;
1233
1234 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1235 if (!pp)
1236 return -ENOMEM;
1237
1238 pp->tf.command = ATA_DRDY;
1239
1240 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1241 if (!cb)
1242 return -ENOMEM;
1243 memset(cb, 0, cb_size);
1244
1245 pp->cmd_block = cb;
1246 pp->cmd_block_dma = cb_dma;
1247
1248 ap->private_data = pp;
1249
1250 return 0;
1251 }
1252
1253 static void sil24_init_controller(struct ata_host *host)
1254 {
1255 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1256 u32 tmp;
1257 int i;
1258
1259 /* GPIO off */
1260 writel(0, host_base + HOST_FLASH_CMD);
1261
1262 /* clear global reset & mask interrupts during initialization */
1263 writel(0, host_base + HOST_CTRL);
1264
1265 /* init ports */
1266 for (i = 0; i < host->n_ports; i++) {
1267 struct ata_port *ap = host->ports[i];
1268 void __iomem *port = ap->ioaddr.cmd_addr;
1269
1270 /* Initial PHY setting */
1271 writel(0x20c, port + PORT_PHY_CFG);
1272
1273 /* Clear port RST */
1274 tmp = readl(port + PORT_CTRL_STAT);
1275 if (tmp & PORT_CS_PORT_RST) {
1276 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1277 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1278 PORT_CS_PORT_RST,
1279 PORT_CS_PORT_RST, 10, 100);
1280 if (tmp & PORT_CS_PORT_RST)
1281 dev_printk(KERN_ERR, host->dev,
1282 "failed to clear port RST\n");
1283 }
1284
1285 /* configure port */
1286 sil24_config_port(ap);
1287 }
1288
1289 /* Turn on interrupts */
1290 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1291 }
1292
1293 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1294 {
1295 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1296 static int printed_version;
1297 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1298 const struct ata_port_info *ppi[] = { &pi, NULL };
1299 void __iomem * const *iomap;
1300 struct ata_host *host;
1301 int i, rc;
1302 u32 tmp;
1303
1304 /* cause link error if sil24_cmd_block is sized wrongly */
1305 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1306 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1307
1308 if (!printed_version++)
1309 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1310
1311 /* acquire resources */
1312 rc = pcim_enable_device(pdev);
1313 if (rc)
1314 return rc;
1315
1316 rc = pcim_iomap_regions(pdev,
1317 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1318 DRV_NAME);
1319 if (rc)
1320 return rc;
1321 iomap = pcim_iomap_table(pdev);
1322
1323 /* apply workaround for completion IRQ loss on PCI-X errata */
1324 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1325 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1326 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1327 dev_printk(KERN_INFO, &pdev->dev,
1328 "Applying completion IRQ loss on PCI-X "
1329 "errata fix\n");
1330 else
1331 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1332 }
1333
1334 /* allocate and fill host */
1335 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1336 SIL24_FLAG2NPORTS(ppi[0]->flags));
1337 if (!host)
1338 return -ENOMEM;
1339 host->iomap = iomap;
1340
1341 for (i = 0; i < host->n_ports; i++) {
1342 struct ata_port *ap = host->ports[i];
1343 size_t offset = ap->port_no * PORT_REGS_SIZE;
1344 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1345
1346 host->ports[i]->ioaddr.cmd_addr = port;
1347 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1348
1349 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1350 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1351 }
1352
1353 /* configure and activate the device */
1354 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1355 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1356 if (rc) {
1357 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1358 if (rc) {
1359 dev_printk(KERN_ERR, &pdev->dev,
1360 "64-bit DMA enable failed\n");
1361 return rc;
1362 }
1363 }
1364 } else {
1365 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1366 if (rc) {
1367 dev_printk(KERN_ERR, &pdev->dev,
1368 "32-bit DMA enable failed\n");
1369 return rc;
1370 }
1371 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1372 if (rc) {
1373 dev_printk(KERN_ERR, &pdev->dev,
1374 "32-bit consistent DMA enable failed\n");
1375 return rc;
1376 }
1377 }
1378
1379 sil24_init_controller(host);
1380
1381 pci_set_master(pdev);
1382 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1383 &sil24_sht);
1384 }
1385
1386 #ifdef CONFIG_PM
1387 static int sil24_pci_device_resume(struct pci_dev *pdev)
1388 {
1389 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1390 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1391 int rc;
1392
1393 rc = ata_pci_device_do_resume(pdev);
1394 if (rc)
1395 return rc;
1396
1397 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1398 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1399
1400 sil24_init_controller(host);
1401
1402 ata_host_resume(host);
1403
1404 return 0;
1405 }
1406
1407 static int sil24_port_resume(struct ata_port *ap)
1408 {
1409 sil24_config_pmp(ap, ap->nr_pmp_links);
1410 return 0;
1411 }
1412 #endif
1413
1414 static int __init sil24_init(void)
1415 {
1416 return pci_register_driver(&sil24_pci_driver);
1417 }
1418
1419 static void __exit sil24_exit(void)
1420 {
1421 pci_unregister_driver(&sil24_pci_driver);
1422 }
1423
1424 MODULE_AUTHOR("Tejun Heo");
1425 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1426 MODULE_LICENSE("GPL");
1427 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1428
1429 module_init(sil24_init);
1430 module_exit(sil24_exit);
kernel source for telekom puls (alcatel/mediatek)