2 * drivers/ata/sata_dwc_460ex.c
4 * Synopsys DesignWare Cores (DWC) SATA host driver
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
21 #ifdef CONFIG_SATA_DWC_DEBUG
25 #ifdef CONFIG_SATA_DWC_VDEBUG
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/device.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/platform_device.h>
37 #include <linux/libata.h>
38 #include <linux/slab.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
45 /* Supported DMA engine drivers */
46 #include <linux/platform_data/dma-dw.h>
47 #include <linux/dma/dw.h>
49 /* These two are defined in "libata.h" */
53 #define DRV_NAME "sata-dwc"
54 #define DRV_VERSION "1.3"
57 #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
61 #define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a)))
68 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
71 SATA_DWC_MAX_PORTS
= 1,
73 SATA_DWC_SCR_OFFSET
= 0x24,
74 SATA_DWC_REG_OFFSET
= 0x64,
77 /* DWC SATA Registers */
78 struct sata_dwc_regs
{
79 u32 fptagr
; /* 1st party DMA tag */
80 u32 fpbor
; /* 1st party DMA buffer offset */
81 u32 fptcr
; /* 1st party DMA Xfr count */
82 u32 dmacr
; /* DMA Control */
83 u32 dbtsr
; /* DMA Burst Transac size */
84 u32 intpr
; /* Interrupt Pending */
85 u32 intmr
; /* Interrupt Mask */
86 u32 errmr
; /* Error Mask */
87 u32 llcr
; /* Link Layer Control */
88 u32 phycr
; /* PHY Control */
89 u32 physr
; /* PHY Status */
90 u32 rxbistpd
; /* Recvd BIST pattern def register */
91 u32 rxbistpd1
; /* Recvd BIST data dword1 */
92 u32 rxbistpd2
; /* Recvd BIST pattern data dword2 */
93 u32 txbistpd
; /* Trans BIST pattern def register */
94 u32 txbistpd1
; /* Trans BIST data dword1 */
95 u32 txbistpd2
; /* Trans BIST data dword2 */
96 u32 bistcr
; /* BIST Control Register */
97 u32 bistfctr
; /* BIST FIS Count Register */
98 u32 bistsr
; /* BIST Status Register */
99 u32 bistdecr
; /* BIST Dword Error count register */
100 u32 res
[15]; /* Reserved locations */
101 u32 testr
; /* Test Register */
102 u32 versionr
; /* Version Register */
103 u32 idr
; /* ID Register */
104 u32 unimpl
[192]; /* Unimplemented */
105 u32 dmadr
[256]; /* FIFO Locations in DMA Mode */
109 SCR_SCONTROL_DET_ENABLE
= 0x00000001,
110 SCR_SSTATUS_DET_PRESENT
= 0x00000001,
111 SCR_SERROR_DIAG_X
= 0x04000000,
112 /* DWC SATA Register Operations */
113 SATA_DWC_TXFIFO_DEPTH
= 0x01FF,
114 SATA_DWC_RXFIFO_DEPTH
= 0x01FF,
115 SATA_DWC_DMACR_TMOD_TXCHEN
= 0x00000004,
116 SATA_DWC_DMACR_TXCHEN
= (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN
),
117 SATA_DWC_DMACR_RXCHEN
= (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN
),
118 SATA_DWC_DMACR_TXRXCH_CLEAR
= SATA_DWC_DMACR_TMOD_TXCHEN
,
119 SATA_DWC_INTPR_DMAT
= 0x00000001,
120 SATA_DWC_INTPR_NEWFP
= 0x00000002,
121 SATA_DWC_INTPR_PMABRT
= 0x00000004,
122 SATA_DWC_INTPR_ERR
= 0x00000008,
123 SATA_DWC_INTPR_NEWBIST
= 0x00000010,
124 SATA_DWC_INTPR_IPF
= 0x10000000,
125 SATA_DWC_INTMR_DMATM
= 0x00000001,
126 SATA_DWC_INTMR_NEWFPM
= 0x00000002,
127 SATA_DWC_INTMR_PMABRTM
= 0x00000004,
128 SATA_DWC_INTMR_ERRM
= 0x00000008,
129 SATA_DWC_INTMR_NEWBISTM
= 0x00000010,
130 SATA_DWC_LLCR_SCRAMEN
= 0x00000001,
131 SATA_DWC_LLCR_DESCRAMEN
= 0x00000002,
132 SATA_DWC_LLCR_RPDEN
= 0x00000004,
133 /* This is all error bits, zero's are reserved fields. */
134 SATA_DWC_SERROR_ERR_BITS
= 0x0FFF0F03
137 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
138 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
139 SATA_DWC_DMACR_TMOD_TXCHEN)
140 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
141 SATA_DWC_DMACR_TMOD_TXCHEN)
142 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
143 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
145 struct sata_dwc_device
{
146 struct device
*dev
; /* generic device struct */
147 struct ata_probe_ent
*pe
; /* ptr to probe-ent */
148 struct ata_host
*host
;
149 u8 __iomem
*reg_base
;
150 struct sata_dwc_regs
*sata_dwc_regs
; /* DW Synopsys SATA specific */
151 struct dw_dma_chip
*dma
;
154 #define SATA_DWC_QCMD_MAX 32
156 struct sata_dwc_device_port
{
157 struct sata_dwc_device
*hsdev
;
158 int cmd_issued
[SATA_DWC_QCMD_MAX
];
159 int dma_pending
[SATA_DWC_QCMD_MAX
];
162 struct dw_dma_slave
*dws
;
163 struct dma_chan
*chan
;
164 struct dma_async_tx_descriptor
*desc
[SATA_DWC_QCMD_MAX
];
165 u32 dma_interrupt_count
;
169 * Commonly used DWC SATA driver Macros
171 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
172 (host)->private_data)
173 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
174 (ap)->host->private_data)
175 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
177 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
178 (qc)->ap->host->private_data)
179 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
183 SATA_DWC_CMD_ISSUED_NOT
= 0,
184 SATA_DWC_CMD_ISSUED_PEND
= 1,
185 SATA_DWC_CMD_ISSUED_EXEC
= 2,
186 SATA_DWC_CMD_ISSUED_NODATA
= 3,
188 SATA_DWC_DMA_PENDING_NONE
= 0,
189 SATA_DWC_DMA_PENDING_TX
= 1,
190 SATA_DWC_DMA_PENDING_RX
= 2,
193 struct sata_dwc_host_priv
{
194 void __iomem
*scr_addr_sstatus
;
195 u32 sata_dwc_sactive_issued
;
196 u32 sata_dwc_sactive_queued
;
199 static struct sata_dwc_host_priv host_pvt
;
201 static struct dw_dma_slave sata_dwc_dma_dws
= {
211 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd
*qc
, u8 tag
);
212 static int sata_dwc_qc_complete(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
214 static void sata_dwc_dma_xfer_complete(struct ata_port
*ap
, u32 check_status
);
215 static void sata_dwc_port_stop(struct ata_port
*ap
);
216 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port
*hsdevp
, u8 tag
);
218 static const char *get_prot_descript(u8 protocol
)
220 switch ((enum ata_tf_protocols
)protocol
) {
221 case ATA_PROT_NODATA
:
222 return "ATA no data";
229 case ATAPI_PROT_NODATA
:
230 return "ATAPI no data";
240 static const char *get_dma_dir_descript(int dma_dir
)
242 switch ((enum dma_data_direction
)dma_dir
) {
243 case DMA_BIDIRECTIONAL
:
244 return "bidirectional";
247 case DMA_FROM_DEVICE
:
248 return "from device";
254 static void sata_dwc_tf_dump(struct ata_port
*ap
, struct ata_taskfile
*tf
)
257 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
258 tf
->command
, get_prot_descript(tf
->protocol
), tf
->flags
,
261 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
262 tf
->feature
, tf
->nsect
, tf
->lbal
, tf
->lbam
, tf
->lbah
);
264 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
265 tf
->hob_feature
, tf
->hob_nsect
, tf
->hob_lbal
, tf
->hob_lbam
,
269 static void dma_dwc_xfer_done(void *hsdev_instance
)
272 struct sata_dwc_device
*hsdev
= hsdev_instance
;
273 struct ata_host
*host
= (struct ata_host
*)hsdev
->host
;
275 struct sata_dwc_device_port
*hsdevp
;
277 unsigned int port
= 0;
279 spin_lock_irqsave(&host
->lock
, flags
);
280 ap
= host
->ports
[port
];
281 hsdevp
= HSDEVP_FROM_AP(ap
);
282 tag
= ap
->link
.active_tag
;
285 * Each DMA command produces 2 interrupts. Only
286 * complete the command after both interrupts have been
287 * seen. (See sata_dwc_isr())
289 hsdevp
->dma_interrupt_count
++;
290 sata_dwc_clear_dmacr(hsdevp
, tag
);
292 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_NONE
) {
293 dev_err(ap
->dev
, "DMA not pending tag=0x%02x pending=%d\n",
294 tag
, hsdevp
->dma_pending
[tag
]);
297 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
298 sata_dwc_dma_xfer_complete(ap
, 1);
300 spin_unlock_irqrestore(&host
->lock
, flags
);
303 static struct dma_async_tx_descriptor
*dma_dwc_xfer_setup(struct ata_queued_cmd
*qc
)
305 struct ata_port
*ap
= qc
->ap
;
306 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
307 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
308 dma_addr_t addr
= (dma_addr_t
)&hsdev
->sata_dwc_regs
->dmadr
;
309 struct dma_slave_config sconf
;
310 struct dma_async_tx_descriptor
*desc
;
312 if (qc
->dma_dir
== DMA_DEV_TO_MEM
) {
313 sconf
.src_addr
= addr
;
314 sconf
.device_fc
= true;
315 } else { /* DMA_MEM_TO_DEV */
316 sconf
.dst_addr
= addr
;
317 sconf
.device_fc
= false;
320 sconf
.direction
= qc
->dma_dir
;
321 sconf
.src_maxburst
= AHB_DMA_BRST_DFLT
;
322 sconf
.dst_maxburst
= AHB_DMA_BRST_DFLT
;
323 sconf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
324 sconf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
326 dmaengine_slave_config(hsdevp
->chan
, &sconf
);
328 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
329 desc
= dmaengine_prep_slave_sg(hsdevp
->chan
, qc
->sg
, qc
->n_elem
,
331 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
336 desc
->callback
= dma_dwc_xfer_done
;
337 desc
->callback_param
= hsdev
;
339 dev_dbg(hsdev
->dev
, "%s sg: 0x%p, count: %d addr: %pad\n",
340 __func__
, qc
->sg
, qc
->n_elem
, &addr
);
345 static int sata_dwc_scr_read(struct ata_link
*link
, unsigned int scr
, u32
*val
)
347 if (scr
> SCR_NOTIFICATION
) {
348 dev_err(link
->ap
->dev
, "%s: Incorrect SCR offset 0x%02x\n",
353 *val
= in_le32(link
->ap
->ioaddr
.scr_addr
+ (scr
* 4));
354 dev_dbg(link
->ap
->dev
, "%s: id=%d reg=%d val=val=0x%08x\n",
355 __func__
, link
->ap
->print_id
, scr
, *val
);
360 static int sata_dwc_scr_write(struct ata_link
*link
, unsigned int scr
, u32 val
)
362 dev_dbg(link
->ap
->dev
, "%s: id=%d reg=%d val=val=0x%08x\n",
363 __func__
, link
->ap
->print_id
, scr
, val
);
364 if (scr
> SCR_NOTIFICATION
) {
365 dev_err(link
->ap
->dev
, "%s: Incorrect SCR offset 0x%02x\n",
369 out_le32(link
->ap
->ioaddr
.scr_addr
+ (scr
* 4), val
);
374 static u32
core_scr_read(unsigned int scr
)
376 return in_le32(host_pvt
.scr_addr_sstatus
+ (scr
* 4));
379 static void core_scr_write(unsigned int scr
, u32 val
)
381 out_le32(host_pvt
.scr_addr_sstatus
+ (scr
* 4), val
);
384 static void clear_serror(void)
387 val
= core_scr_read(SCR_ERROR
);
388 core_scr_write(SCR_ERROR
, val
);
391 static void clear_interrupt_bit(struct sata_dwc_device
*hsdev
, u32 bit
)
393 out_le32(&hsdev
->sata_dwc_regs
->intpr
,
394 in_le32(&hsdev
->sata_dwc_regs
->intpr
));
397 static u32
qcmd_tag_to_mask(u8 tag
)
399 return 0x00000001 << (tag
& 0x1f);
403 static void sata_dwc_error_intr(struct ata_port
*ap
,
404 struct sata_dwc_device
*hsdev
, uint intpr
)
406 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
407 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
408 unsigned int err_mask
= 0, action
= 0;
409 struct ata_queued_cmd
*qc
;
413 ata_ehi_clear_desc(ehi
);
415 serror
= core_scr_read(SCR_ERROR
);
416 status
= ap
->ops
->sff_check_status(ap
);
418 tag
= ap
->link
.active_tag
;
421 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
422 __func__
, serror
, intpr
, status
, hsdevp
->dma_interrupt_count
,
423 hsdevp
->dma_pending
[tag
], hsdevp
->cmd_issued
[tag
]);
425 /* Clear error register and interrupt bit */
427 clear_interrupt_bit(hsdev
, SATA_DWC_INTPR_ERR
);
429 /* This is the only error happening now. TODO check for exact error */
431 err_mask
|= AC_ERR_HOST_BUS
;
432 action
|= ATA_EH_RESET
;
434 /* Pass this on to EH */
435 ehi
->serror
|= serror
;
436 ehi
->action
|= action
;
438 qc
= ata_qc_from_tag(ap
, tag
);
440 qc
->err_mask
|= err_mask
;
442 ehi
->err_mask
|= err_mask
;
448 * Function : sata_dwc_isr
449 * arguments : irq, void *dev_instance, struct pt_regs *regs
450 * Return value : irqreturn_t - status of IRQ
451 * This Interrupt handler called via port ops registered function.
452 * .irq_handler = sata_dwc_isr
454 static irqreturn_t
sata_dwc_isr(int irq
, void *dev_instance
)
456 struct ata_host
*host
= (struct ata_host
*)dev_instance
;
457 struct sata_dwc_device
*hsdev
= HSDEV_FROM_HOST(host
);
459 struct ata_queued_cmd
*qc
;
462 int handled
, num_processed
, port
= 0;
463 uint intpr
, sactive
, sactive2
, tag_mask
;
464 struct sata_dwc_device_port
*hsdevp
;
465 host_pvt
.sata_dwc_sactive_issued
= 0;
467 spin_lock_irqsave(&host
->lock
, flags
);
469 /* Read the interrupt register */
470 intpr
= in_le32(&hsdev
->sata_dwc_regs
->intpr
);
472 ap
= host
->ports
[port
];
473 hsdevp
= HSDEVP_FROM_AP(ap
);
475 dev_dbg(ap
->dev
, "%s intpr=0x%08x active_tag=%d\n", __func__
, intpr
,
476 ap
->link
.active_tag
);
478 /* Check for error interrupt */
479 if (intpr
& SATA_DWC_INTPR_ERR
) {
480 sata_dwc_error_intr(ap
, hsdev
, intpr
);
485 /* Check for DMA SETUP FIS (FP DMA) interrupt */
486 if (intpr
& SATA_DWC_INTPR_NEWFP
) {
487 clear_interrupt_bit(hsdev
, SATA_DWC_INTPR_NEWFP
);
489 tag
= (u8
)(in_le32(&hsdev
->sata_dwc_regs
->fptagr
));
490 dev_dbg(ap
->dev
, "%s: NEWFP tag=%d\n", __func__
, tag
);
491 if (hsdevp
->cmd_issued
[tag
] != SATA_DWC_CMD_ISSUED_PEND
)
492 dev_warn(ap
->dev
, "CMD tag=%d not pending?\n", tag
);
494 host_pvt
.sata_dwc_sactive_issued
|= qcmd_tag_to_mask(tag
);
496 qc
= ata_qc_from_tag(ap
, tag
);
498 * Start FP DMA for NCQ command. At this point the tag is the
499 * active tag. It is the tag that matches the command about to
502 qc
->ap
->link
.active_tag
= tag
;
503 sata_dwc_bmdma_start_by_tag(qc
, tag
);
508 sactive
= core_scr_read(SCR_ACTIVE
);
509 tag_mask
= (host_pvt
.sata_dwc_sactive_issued
| sactive
) ^ sactive
;
511 /* If no sactive issued and tag_mask is zero then this is not NCQ */
512 if (host_pvt
.sata_dwc_sactive_issued
== 0 && tag_mask
== 0) {
513 if (ap
->link
.active_tag
== ATA_TAG_POISON
)
516 tag
= ap
->link
.active_tag
;
517 qc
= ata_qc_from_tag(ap
, tag
);
519 /* DEV interrupt w/ no active qc? */
520 if (unlikely(!qc
|| (qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
522 "%s interrupt with no active qc qc=%p\n",
524 ap
->ops
->sff_check_status(ap
);
528 status
= ap
->ops
->sff_check_status(ap
);
530 qc
->ap
->link
.active_tag
= tag
;
531 hsdevp
->cmd_issued
[tag
] = SATA_DWC_CMD_ISSUED_NOT
;
533 if (status
& ATA_ERR
) {
534 dev_dbg(ap
->dev
, "interrupt ATA_ERR (0x%x)\n", status
);
535 sata_dwc_qc_complete(ap
, qc
, 1);
540 dev_dbg(ap
->dev
, "%s non-NCQ cmd interrupt, protocol: %s\n",
541 __func__
, get_prot_descript(qc
->tf
.protocol
));
543 if (ata_is_dma(qc
->tf
.protocol
)) {
545 * Each DMA transaction produces 2 interrupts. The DMAC
546 * transfer complete interrupt and the SATA controller
547 * operation done interrupt. The command should be
548 * completed only after both interrupts are seen.
550 hsdevp
->dma_interrupt_count
++;
551 if (hsdevp
->dma_pending
[tag
] == \
552 SATA_DWC_DMA_PENDING_NONE
) {
554 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
555 __func__
, intpr
, status
,
556 hsdevp
->dma_pending
[tag
]);
559 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
560 sata_dwc_dma_xfer_complete(ap
, 1);
561 } else if (ata_is_pio(qc
->tf
.protocol
)) {
562 ata_sff_hsm_move(ap
, qc
, status
, 0);
566 if (unlikely(sata_dwc_qc_complete(ap
, qc
, 1)))
575 * This is a NCQ command. At this point we need to figure out for which
576 * tags we have gotten a completion interrupt. One interrupt may serve
577 * as completion for more than one operation when commands are queued
578 * (NCQ). We need to process each completed command.
581 /* process completed commands */
582 sactive
= core_scr_read(SCR_ACTIVE
);
583 tag_mask
= (host_pvt
.sata_dwc_sactive_issued
| sactive
) ^ sactive
;
585 if (sactive
!= 0 || (host_pvt
.sata_dwc_sactive_issued
) > 1 || \
588 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
589 __func__
, sactive
, host_pvt
.sata_dwc_sactive_issued
,
593 if ((tag_mask
| (host_pvt
.sata_dwc_sactive_issued
)) != \
594 (host_pvt
.sata_dwc_sactive_issued
)) {
596 "Bad tag mask? sactive=0x%08x (host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask=0x%08x\n",
597 sactive
, host_pvt
.sata_dwc_sactive_issued
, tag_mask
);
600 /* read just to clear ... not bad if currently still busy */
601 status
= ap
->ops
->sff_check_status(ap
);
602 dev_dbg(ap
->dev
, "%s ATA status register=0x%x\n", __func__
, status
);
608 while (!(tag_mask
& 0x00000001)) {
613 tag_mask
&= (~0x00000001);
614 qc
= ata_qc_from_tag(ap
, tag
);
616 /* To be picked up by completion functions */
617 qc
->ap
->link
.active_tag
= tag
;
618 hsdevp
->cmd_issued
[tag
] = SATA_DWC_CMD_ISSUED_NOT
;
620 /* Let libata/scsi layers handle error */
621 if (status
& ATA_ERR
) {
622 dev_dbg(ap
->dev
, "%s ATA_ERR (0x%x)\n", __func__
,
624 sata_dwc_qc_complete(ap
, qc
, 1);
629 /* Process completed command */
630 dev_dbg(ap
->dev
, "%s NCQ command, protocol: %s\n", __func__
,
631 get_prot_descript(qc
->tf
.protocol
));
632 if (ata_is_dma(qc
->tf
.protocol
)) {
633 hsdevp
->dma_interrupt_count
++;
634 if (hsdevp
->dma_pending
[tag
] == \
635 SATA_DWC_DMA_PENDING_NONE
)
636 dev_warn(ap
->dev
, "%s: DMA not pending?\n",
638 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
639 sata_dwc_dma_xfer_complete(ap
, 1);
641 if (unlikely(sata_dwc_qc_complete(ap
, qc
, 1)))
647 ap
->stats
.idle_irq
++;
648 dev_warn(ap
->dev
, "STILL BUSY IRQ ata%d: irq trap\n",
650 } /* while tag_mask */
653 * Check to see if any commands completed while we were processing our
654 * initial set of completed commands (read status clears interrupts,
655 * so we might miss a completed command interrupt if one came in while
656 * we were processing --we read status as part of processing a completed
659 sactive2
= core_scr_read(SCR_ACTIVE
);
660 if (sactive2
!= sactive
) {
662 "More completed - sactive=0x%x sactive2=0x%x\n",
668 spin_unlock_irqrestore(&host
->lock
, flags
);
669 return IRQ_RETVAL(handled
);
672 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port
*hsdevp
, u8 tag
)
674 struct sata_dwc_device
*hsdev
= HSDEV_FROM_HSDEVP(hsdevp
);
676 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_RX
) {
677 out_le32(&(hsdev
->sata_dwc_regs
->dmacr
),
678 SATA_DWC_DMACR_RX_CLEAR(
679 in_le32(&(hsdev
->sata_dwc_regs
->dmacr
))));
680 } else if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_TX
) {
681 out_le32(&(hsdev
->sata_dwc_regs
->dmacr
),
682 SATA_DWC_DMACR_TX_CLEAR(
683 in_le32(&(hsdev
->sata_dwc_regs
->dmacr
))));
686 * This should not happen, it indicates the driver is out of
687 * sync. If it does happen, clear dmacr anyway.
690 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
691 __func__
, tag
, hsdevp
->dma_pending
[tag
],
692 in_le32(&hsdev
->sata_dwc_regs
->dmacr
));
693 out_le32(&(hsdev
->sata_dwc_regs
->dmacr
),
694 SATA_DWC_DMACR_TXRXCH_CLEAR
);
698 static void sata_dwc_dma_xfer_complete(struct ata_port
*ap
, u32 check_status
)
700 struct ata_queued_cmd
*qc
;
701 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
702 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
705 tag
= ap
->link
.active_tag
;
706 qc
= ata_qc_from_tag(ap
, tag
);
708 dev_err(ap
->dev
, "failed to get qc");
715 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
716 __func__
, qc
->tag
, qc
->tf
.command
,
717 get_dma_dir_descript(qc
->dma_dir
),
718 get_prot_descript(qc
->tf
.protocol
),
719 in_le32(&(hsdev
->sata_dwc_regs
->dmacr
)));
723 if (ata_is_dma(qc
->tf
.protocol
)) {
724 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_NONE
) {
726 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
728 in_le32(&(hsdev
->sata_dwc_regs
->dmacr
)));
731 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_NONE
;
732 sata_dwc_qc_complete(ap
, qc
, check_status
);
733 ap
->link
.active_tag
= ATA_TAG_POISON
;
735 sata_dwc_qc_complete(ap
, qc
, check_status
);
739 static int sata_dwc_qc_complete(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
745 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
746 host_pvt
.sata_dwc_sactive_queued
= 0;
747 dev_dbg(ap
->dev
, "%s checkstatus? %x\n", __func__
, check_status
);
749 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_TX
)
750 dev_err(ap
->dev
, "TX DMA PENDING\n");
751 else if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_RX
)
752 dev_err(ap
->dev
, "RX DMA PENDING\n");
754 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
755 qc
->tf
.command
, status
, ap
->print_id
, qc
->tf
.protocol
);
757 /* clear active bit */
758 mask
= (~(qcmd_tag_to_mask(tag
)));
759 host_pvt
.sata_dwc_sactive_queued
= (host_pvt
.sata_dwc_sactive_queued
) \
761 host_pvt
.sata_dwc_sactive_issued
= (host_pvt
.sata_dwc_sactive_issued
) \
767 static void sata_dwc_enable_interrupts(struct sata_dwc_device
*hsdev
)
769 /* Enable selective interrupts by setting the interrupt maskregister*/
770 out_le32(&hsdev
->sata_dwc_regs
->intmr
,
771 SATA_DWC_INTMR_ERRM
|
772 SATA_DWC_INTMR_NEWFPM
|
773 SATA_DWC_INTMR_PMABRTM
|
774 SATA_DWC_INTMR_DMATM
);
776 * Unmask the error bits that should trigger an error interrupt by
777 * setting the error mask register.
779 out_le32(&hsdev
->sata_dwc_regs
->errmr
, SATA_DWC_SERROR_ERR_BITS
);
781 dev_dbg(hsdev
->dev
, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
782 __func__
, in_le32(&hsdev
->sata_dwc_regs
->intmr
),
783 in_le32(&hsdev
->sata_dwc_regs
->errmr
));
786 static bool sata_dwc_dma_filter(struct dma_chan
*chan
, void *param
)
788 struct sata_dwc_device_port
*hsdevp
= param
;
789 struct dw_dma_slave
*dws
= hsdevp
->dws
;
791 if (dws
->dma_dev
!= chan
->device
->dev
)
798 static void sata_dwc_setup_port(struct ata_ioports
*port
, unsigned long base
)
800 port
->cmd_addr
= (void __iomem
*)base
+ 0x00;
801 port
->data_addr
= (void __iomem
*)base
+ 0x00;
803 port
->error_addr
= (void __iomem
*)base
+ 0x04;
804 port
->feature_addr
= (void __iomem
*)base
+ 0x04;
806 port
->nsect_addr
= (void __iomem
*)base
+ 0x08;
808 port
->lbal_addr
= (void __iomem
*)base
+ 0x0c;
809 port
->lbam_addr
= (void __iomem
*)base
+ 0x10;
810 port
->lbah_addr
= (void __iomem
*)base
+ 0x14;
812 port
->device_addr
= (void __iomem
*)base
+ 0x18;
813 port
->command_addr
= (void __iomem
*)base
+ 0x1c;
814 port
->status_addr
= (void __iomem
*)base
+ 0x1c;
816 port
->altstatus_addr
= (void __iomem
*)base
+ 0x20;
817 port
->ctl_addr
= (void __iomem
*)base
+ 0x20;
821 * Function : sata_dwc_port_start
822 * arguments : struct ata_ioports *port
823 * Return value : returns 0 if success, error code otherwise
824 * This function allocates the scatter gather LLI table for AHB DMA
826 static int sata_dwc_port_start(struct ata_port
*ap
)
829 struct sata_dwc_device
*hsdev
;
830 struct sata_dwc_device_port
*hsdevp
= NULL
;
835 hsdev
= HSDEV_FROM_AP(ap
);
837 dev_dbg(ap
->dev
, "%s: port_no=%d\n", __func__
, ap
->port_no
);
839 hsdev
->host
= ap
->host
;
840 pdev
= ap
->host
->dev
;
842 dev_err(ap
->dev
, "%s: no ap->host->dev\n", __func__
);
847 /* Allocate Port Struct */
848 hsdevp
= kzalloc(sizeof(*hsdevp
), GFP_KERNEL
);
850 dev_err(ap
->dev
, "%s: kmalloc failed for hsdevp\n", __func__
);
854 hsdevp
->hsdev
= hsdev
;
856 hsdevp
->dws
= &sata_dwc_dma_dws
;
857 hsdevp
->dws
->dma_dev
= hsdev
->dev
;
860 dma_cap_set(DMA_SLAVE
, mask
);
862 /* Acquire DMA channel */
863 hsdevp
->chan
= dma_request_channel(mask
, sata_dwc_dma_filter
, hsdevp
);
865 dev_err(hsdev
->dev
, "%s: dma channel unavailable\n",
871 for (i
= 0; i
< SATA_DWC_QCMD_MAX
; i
++)
872 hsdevp
->cmd_issued
[i
] = SATA_DWC_CMD_ISSUED_NOT
;
874 ap
->bmdma_prd
= NULL
; /* set these so libata doesn't use them */
875 ap
->bmdma_prd_dma
= 0;
877 if (ap
->port_no
== 0) {
878 dev_dbg(ap
->dev
, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
880 out_le32(&hsdev
->sata_dwc_regs
->dmacr
,
881 SATA_DWC_DMACR_TXRXCH_CLEAR
);
883 dev_dbg(ap
->dev
, "%s: setting burst size in DBTSR\n",
885 out_le32(&hsdev
->sata_dwc_regs
->dbtsr
,
886 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT
) |
887 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT
)));
890 /* Clear any error bits before libata starts issuing commands */
892 ap
->private_data
= hsdevp
;
893 dev_dbg(ap
->dev
, "%s: done\n", __func__
);
899 dev_dbg(ap
->dev
, "%s: fail. ap->id = %d\n", __func__
, ap
->print_id
);
903 static void sata_dwc_port_stop(struct ata_port
*ap
)
905 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
907 dev_dbg(ap
->dev
, "%s: ap->id = %d\n", __func__
, ap
->print_id
);
909 dmaengine_terminate_all(hsdevp
->chan
);
910 dma_release_channel(hsdevp
->chan
);
913 ap
->private_data
= NULL
;
917 * Function : sata_dwc_exec_command_by_tag
918 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
919 * Return value : None
920 * This function keeps track of individual command tag ids and calls
921 * ata_exec_command in libata
923 static void sata_dwc_exec_command_by_tag(struct ata_port
*ap
,
924 struct ata_taskfile
*tf
,
925 u8 tag
, u32 cmd_issued
)
927 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
929 dev_dbg(ap
->dev
, "%s cmd(0x%02x): %s tag=%d\n", __func__
, tf
->command
,
930 ata_get_cmd_descript(tf
->command
), tag
);
932 hsdevp
->cmd_issued
[tag
] = cmd_issued
;
935 * Clear SError before executing a new command.
936 * sata_dwc_scr_write and read can not be used here. Clearing the PM
937 * managed SError register for the disk needs to be done before the
938 * task file is loaded.
941 ata_sff_exec_command(ap
, tf
);
944 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd
*qc
, u8 tag
)
946 sata_dwc_exec_command_by_tag(qc
->ap
, &qc
->tf
, tag
,
947 SATA_DWC_CMD_ISSUED_PEND
);
950 static void sata_dwc_bmdma_setup(struct ata_queued_cmd
*qc
)
954 if (ata_is_ncq(qc
->tf
.protocol
)) {
955 dev_dbg(qc
->ap
->dev
, "%s: ap->link.sactive=0x%08x tag=%d\n",
956 __func__
, qc
->ap
->link
.sactive
, tag
);
960 sata_dwc_bmdma_setup_by_tag(qc
, tag
);
963 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd
*qc
, u8 tag
)
967 struct sata_dwc_device
*hsdev
= HSDEV_FROM_QC(qc
);
968 struct ata_port
*ap
= qc
->ap
;
969 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
970 struct dma_async_tx_descriptor
*desc
= hsdevp
->desc
[tag
];
971 int dir
= qc
->dma_dir
;
973 if (hsdevp
->cmd_issued
[tag
] != SATA_DWC_CMD_ISSUED_NOT
) {
975 if (dir
== DMA_TO_DEVICE
)
976 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_TX
;
978 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_RX
;
981 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
982 __func__
, hsdevp
->cmd_issued
[tag
], tag
);
987 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
988 __func__
, qc
, tag
, qc
->tf
.command
,
989 get_dma_dir_descript(qc
->dma_dir
), start_dma
);
990 sata_dwc_tf_dump(ap
, &qc
->tf
);
993 reg
= core_scr_read(SCR_ERROR
);
994 if (reg
& SATA_DWC_SERROR_ERR_BITS
) {
995 dev_err(ap
->dev
, "%s: ****** SError=0x%08x ******\n",
999 if (dir
== DMA_TO_DEVICE
)
1000 out_le32(&hsdev
->sata_dwc_regs
->dmacr
,
1001 SATA_DWC_DMACR_TXCHEN
);
1003 out_le32(&hsdev
->sata_dwc_regs
->dmacr
,
1004 SATA_DWC_DMACR_RXCHEN
);
1006 /* Enable AHB DMA transfer on the specified channel */
1007 dmaengine_submit(desc
);
1008 dma_async_issue_pending(hsdevp
->chan
);
1012 static void sata_dwc_bmdma_start(struct ata_queued_cmd
*qc
)
1016 if (ata_is_ncq(qc
->tf
.protocol
)) {
1017 dev_dbg(qc
->ap
->dev
, "%s: ap->link.sactive=0x%08x tag=%d\n",
1018 __func__
, qc
->ap
->link
.sactive
, tag
);
1022 dev_dbg(qc
->ap
->dev
, "%s\n", __func__
);
1023 sata_dwc_bmdma_start_by_tag(qc
, tag
);
1027 * Function : sata_dwc_qc_prep_by_tag
1028 * arguments : ata_queued_cmd *qc, u8 tag
1029 * Return value : None
1030 * qc_prep for a particular queued command based on tag
1032 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd
*qc
, u8 tag
)
1034 struct dma_async_tx_descriptor
*desc
;
1035 struct ata_port
*ap
= qc
->ap
;
1036 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
1038 dev_dbg(ap
->dev
, "%s: port=%d dma dir=%s n_elem=%d\n",
1039 __func__
, ap
->port_no
, get_dma_dir_descript(qc
->dma_dir
),
1042 desc
= dma_dwc_xfer_setup(qc
);
1044 dev_err(ap
->dev
, "%s: dma_dwc_xfer_setup returns NULL\n",
1048 hsdevp
->desc
[tag
] = desc
;
1051 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd
*qc
)
1055 struct ata_port
*ap
= qc
->ap
;
1058 if (qc
->tag
> 0 || ap
->link
.sactive
> 1)
1060 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1061 __func__
, ap
->print_id
, qc
->tf
.command
,
1062 ata_get_cmd_descript(qc
->tf
.command
),
1063 qc
->tag
, get_prot_descript(qc
->tf
.protocol
),
1064 ap
->link
.active_tag
, ap
->link
.sactive
);
1067 if (!ata_is_ncq(qc
->tf
.protocol
))
1069 sata_dwc_qc_prep_by_tag(qc
, tag
);
1071 if (ata_is_ncq(qc
->tf
.protocol
)) {
1072 sactive
= core_scr_read(SCR_ACTIVE
);
1073 sactive
|= (0x00000001 << tag
);
1074 core_scr_write(SCR_ACTIVE
, sactive
);
1076 dev_dbg(qc
->ap
->dev
,
1077 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1078 __func__
, tag
, qc
->ap
->link
.sactive
, sactive
);
1080 ap
->ops
->sff_tf_load(ap
, &qc
->tf
);
1081 sata_dwc_exec_command_by_tag(ap
, &qc
->tf
, qc
->tag
,
1082 SATA_DWC_CMD_ISSUED_PEND
);
1084 ata_sff_qc_issue(qc
);
1090 * Function : sata_dwc_qc_prep
1091 * arguments : ata_queued_cmd *qc
1092 * Return value : None
1093 * qc_prep for a particular queued command
1096 static void sata_dwc_qc_prep(struct ata_queued_cmd
*qc
)
1098 if ((qc
->dma_dir
== DMA_NONE
) || (qc
->tf
.protocol
== ATA_PROT_PIO
))
1103 dev_info(qc
->ap
->dev
, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1104 __func__
, qc
->tag
, qc
->ap
->link
.active_tag
);
1110 static void sata_dwc_error_handler(struct ata_port
*ap
)
1112 ata_sff_error_handler(ap
);
1115 static int sata_dwc_hardreset(struct ata_link
*link
, unsigned int *class,
1116 unsigned long deadline
)
1118 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(link
->ap
);
1121 ret
= sata_sff_hardreset(link
, class, deadline
);
1123 sata_dwc_enable_interrupts(hsdev
);
1125 /* Reconfigure the DMA control register */
1126 out_le32(&hsdev
->sata_dwc_regs
->dmacr
,
1127 SATA_DWC_DMACR_TXRXCH_CLEAR
);
1129 /* Reconfigure the DMA Burst Transaction Size register */
1130 out_le32(&hsdev
->sata_dwc_regs
->dbtsr
,
1131 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT
) |
1132 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT
));
1137 static void sata_dwc_dev_select(struct ata_port
*ap
, unsigned int device
)
1139 /* SATA DWC is master only */
1143 * scsi mid-layer and libata interface structures
1145 static struct scsi_host_template sata_dwc_sht
= {
1146 ATA_NCQ_SHT(DRV_NAME
),
1148 * test-only: Currently this driver doesn't handle NCQ
1149 * correctly. We enable NCQ but set the queue depth to a
1150 * max of 1. This will get fixed in in a future release.
1152 .sg_tablesize
= LIBATA_MAX_PRD
,
1153 /* .can_queue = ATA_MAX_QUEUE, */
1155 * Make sure a LLI block is not created that will span 8K max FIS
1156 * boundary. If the block spans such a FIS boundary, there is a chance
1157 * that a DMA burst will cross that boundary -- this results in an
1158 * error in the host controller.
1160 .dma_boundary
= 0x1fff /* ATA_DMA_BOUNDARY */,
1163 static struct ata_port_operations sata_dwc_ops
= {
1164 .inherits
= &ata_sff_port_ops
,
1166 .error_handler
= sata_dwc_error_handler
,
1167 .hardreset
= sata_dwc_hardreset
,
1169 .qc_prep
= sata_dwc_qc_prep
,
1170 .qc_issue
= sata_dwc_qc_issue
,
1172 .scr_read
= sata_dwc_scr_read
,
1173 .scr_write
= sata_dwc_scr_write
,
1175 .port_start
= sata_dwc_port_start
,
1176 .port_stop
= sata_dwc_port_stop
,
1178 .sff_dev_select
= sata_dwc_dev_select
,
1180 .bmdma_setup
= sata_dwc_bmdma_setup
,
1181 .bmdma_start
= sata_dwc_bmdma_start
,
1184 static const struct ata_port_info sata_dwc_port_info
[] = {
1186 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NCQ
,
1187 .pio_mask
= ATA_PIO4
,
1188 .udma_mask
= ATA_UDMA6
,
1189 .port_ops
= &sata_dwc_ops
,
1193 static int sata_dwc_probe(struct platform_device
*ofdev
)
1195 struct sata_dwc_device
*hsdev
;
1197 char *ver
= (char *)&versionr
;
1201 struct ata_host
*host
;
1202 struct ata_port_info pi
= sata_dwc_port_info
[0];
1203 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1204 struct device_node
*np
= ofdev
->dev
.of_node
;
1206 /* Allocate DWC SATA device */
1207 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_DWC_MAX_PORTS
);
1208 hsdev
= devm_kzalloc(&ofdev
->dev
, sizeof(*hsdev
), GFP_KERNEL
);
1209 if (!host
|| !hsdev
)
1212 host
->private_data
= hsdev
;
1214 /* Ioremap SATA registers */
1215 base
= of_iomap(np
, 0);
1217 dev_err(&ofdev
->dev
,
1218 "ioremap failed for SATA register address\n");
1221 hsdev
->reg_base
= base
;
1222 dev_dbg(&ofdev
->dev
, "ioremap done for SATA register address\n");
1224 /* Synopsys DWC SATA specific Registers */
1225 hsdev
->sata_dwc_regs
= (void *__iomem
)(base
+ SATA_DWC_REG_OFFSET
);
1228 host
->ports
[0]->ioaddr
.cmd_addr
= base
;
1229 host
->ports
[0]->ioaddr
.scr_addr
= base
+ SATA_DWC_SCR_OFFSET
;
1230 host_pvt
.scr_addr_sstatus
= base
+ SATA_DWC_SCR_OFFSET
;
1231 sata_dwc_setup_port(&host
->ports
[0]->ioaddr
, (unsigned long)base
);
1233 /* Read the ID and Version Registers */
1234 idr
= in_le32(&hsdev
->sata_dwc_regs
->idr
);
1235 versionr
= in_le32(&hsdev
->sata_dwc_regs
->versionr
);
1236 dev_notice(&ofdev
->dev
, "id %d, controller version %c.%c%c\n",
1237 idr
, ver
[0], ver
[1], ver
[2]);
1239 /* Get SATA DMA interrupt number */
1240 hsdev
->dma
->irq
= irq_of_parse_and_map(np
, 1);
1241 if (hsdev
->dma
->irq
== NO_IRQ
) {
1242 dev_err(&ofdev
->dev
, "no SATA DMA irq\n");
1247 /* Get physical SATA DMA register base address */
1248 hsdev
->dma
->regs
= of_iomap(np
, 1);
1249 if (!hsdev
->dma
->regs
) {
1250 dev_err(&ofdev
->dev
,
1251 "ioremap failed for AHBDMA register address\n");
1256 /* Save dev for later use in dev_xxx() routines */
1257 hsdev
->dev
= &ofdev
->dev
;
1259 hsdev
->dma
->dev
= &ofdev
->dev
;
1261 /* Initialize AHB DMAC */
1262 err
= dw_dma_probe(hsdev
->dma
);
1264 goto error_dma_iomap
;
1266 /* Enable SATA Interrupts */
1267 sata_dwc_enable_interrupts(hsdev
);
1269 /* Get SATA interrupt number */
1270 irq
= irq_of_parse_and_map(np
, 0);
1271 if (irq
== NO_IRQ
) {
1272 dev_err(&ofdev
->dev
, "no SATA DMA irq\n");
1278 * Now, register with libATA core, this will also initiate the
1279 * device discovery process, invoking our port_start() handler &
1280 * error_handler() to execute a dummy Softreset EH session
1282 err
= ata_host_activate(host
, irq
, sata_dwc_isr
, 0, &sata_dwc_sht
);
1284 dev_err(&ofdev
->dev
, "failed to activate host");
1286 dev_set_drvdata(&ofdev
->dev
, host
);
1290 /* Free SATA DMA resources */
1291 dw_dma_remove(hsdev
->dma
);
1293 iounmap(hsdev
->dma
->regs
);
1299 static int sata_dwc_remove(struct platform_device
*ofdev
)
1301 struct device
*dev
= &ofdev
->dev
;
1302 struct ata_host
*host
= dev_get_drvdata(dev
);
1303 struct sata_dwc_device
*hsdev
= host
->private_data
;
1305 ata_host_detach(host
);
1307 /* Free SATA DMA resources */
1308 dw_dma_remove(hsdev
->dma
);
1310 iounmap(hsdev
->dma
->regs
);
1311 iounmap(hsdev
->reg_base
);
1312 dev_dbg(&ofdev
->dev
, "done\n");
1316 static const struct of_device_id sata_dwc_match
[] = {
1317 { .compatible
= "amcc,sata-460ex", },
1320 MODULE_DEVICE_TABLE(of
, sata_dwc_match
);
1322 static struct platform_driver sata_dwc_driver
= {
1325 .of_match_table
= sata_dwc_match
,
1327 .probe
= sata_dwc_probe
,
1328 .remove
= sata_dwc_remove
,
1331 module_platform_driver(sata_dwc_driver
);
1333 MODULE_LICENSE("GPL");
1334 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1335 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1336 MODULE_VERSION(DRV_VERSION
);