2 * drivers/ata/sata_dwc_460ex.c
4 * Synopsys DesignWare Cores (DWC) SATA host driver
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
21 #ifdef CONFIG_SATA_DWC_DEBUG
25 #ifdef CONFIG_SATA_DWC_VDEBUG
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/device.h>
33 #include <linux/dmaengine.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/platform_device.h>
38 #include <linux/phy/phy.h>
39 #include <linux/libata.h>
40 #include <linux/slab.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
47 /* These two are defined in "libata.h" */
51 #define DRV_NAME "sata-dwc"
52 #define DRV_VERSION "1.3"
54 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
55 #define sata_dwc_readl(a) readl_relaxed(a)
61 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
64 SATA_DWC_MAX_PORTS
= 1,
66 SATA_DWC_SCR_OFFSET
= 0x24,
67 SATA_DWC_REG_OFFSET
= 0x64,
70 /* DWC SATA Registers */
71 struct sata_dwc_regs
{
72 u32 fptagr
; /* 1st party DMA tag */
73 u32 fpbor
; /* 1st party DMA buffer offset */
74 u32 fptcr
; /* 1st party DMA Xfr count */
75 u32 dmacr
; /* DMA Control */
76 u32 dbtsr
; /* DMA Burst Transac size */
77 u32 intpr
; /* Interrupt Pending */
78 u32 intmr
; /* Interrupt Mask */
79 u32 errmr
; /* Error Mask */
80 u32 llcr
; /* Link Layer Control */
81 u32 phycr
; /* PHY Control */
82 u32 physr
; /* PHY Status */
83 u32 rxbistpd
; /* Recvd BIST pattern def register */
84 u32 rxbistpd1
; /* Recvd BIST data dword1 */
85 u32 rxbistpd2
; /* Recvd BIST pattern data dword2 */
86 u32 txbistpd
; /* Trans BIST pattern def register */
87 u32 txbistpd1
; /* Trans BIST data dword1 */
88 u32 txbistpd2
; /* Trans BIST data dword2 */
89 u32 bistcr
; /* BIST Control Register */
90 u32 bistfctr
; /* BIST FIS Count Register */
91 u32 bistsr
; /* BIST Status Register */
92 u32 bistdecr
; /* BIST Dword Error count register */
93 u32 res
[15]; /* Reserved locations */
94 u32 testr
; /* Test Register */
95 u32 versionr
; /* Version Register */
96 u32 idr
; /* ID Register */
97 u32 unimpl
[192]; /* Unimplemented */
98 u32 dmadr
[256]; /* FIFO Locations in DMA Mode */
102 SCR_SCONTROL_DET_ENABLE
= 0x00000001,
103 SCR_SSTATUS_DET_PRESENT
= 0x00000001,
104 SCR_SERROR_DIAG_X
= 0x04000000,
105 /* DWC SATA Register Operations */
106 SATA_DWC_TXFIFO_DEPTH
= 0x01FF,
107 SATA_DWC_RXFIFO_DEPTH
= 0x01FF,
108 SATA_DWC_DMACR_TMOD_TXCHEN
= 0x00000004,
109 SATA_DWC_DMACR_TXCHEN
= (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN
),
110 SATA_DWC_DMACR_RXCHEN
= (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN
),
111 SATA_DWC_DMACR_TXRXCH_CLEAR
= SATA_DWC_DMACR_TMOD_TXCHEN
,
112 SATA_DWC_INTPR_DMAT
= 0x00000001,
113 SATA_DWC_INTPR_NEWFP
= 0x00000002,
114 SATA_DWC_INTPR_PMABRT
= 0x00000004,
115 SATA_DWC_INTPR_ERR
= 0x00000008,
116 SATA_DWC_INTPR_NEWBIST
= 0x00000010,
117 SATA_DWC_INTPR_IPF
= 0x10000000,
118 SATA_DWC_INTMR_DMATM
= 0x00000001,
119 SATA_DWC_INTMR_NEWFPM
= 0x00000002,
120 SATA_DWC_INTMR_PMABRTM
= 0x00000004,
121 SATA_DWC_INTMR_ERRM
= 0x00000008,
122 SATA_DWC_INTMR_NEWBISTM
= 0x00000010,
123 SATA_DWC_LLCR_SCRAMEN
= 0x00000001,
124 SATA_DWC_LLCR_DESCRAMEN
= 0x00000002,
125 SATA_DWC_LLCR_RPDEN
= 0x00000004,
126 /* This is all error bits, zero's are reserved fields. */
127 SATA_DWC_SERROR_ERR_BITS
= 0x0FFF0F03
130 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
131 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132 SATA_DWC_DMACR_TMOD_TXCHEN)
133 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134 SATA_DWC_DMACR_TMOD_TXCHEN)
135 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
138 struct sata_dwc_device
{
139 struct device
*dev
; /* generic device struct */
140 struct ata_probe_ent
*pe
; /* ptr to probe-ent */
141 struct ata_host
*host
;
142 u8 __iomem
*reg_base
;
143 struct sata_dwc_regs __iomem
*sata_dwc_regs
; /* DW SATA specific */
147 #ifdef CONFIG_SATA_DWC_OLD_DMA
148 struct dw_dma_chip
*dma
;
152 #define SATA_DWC_QCMD_MAX 32
154 struct sata_dwc_device_port
{
155 struct sata_dwc_device
*hsdev
;
156 int cmd_issued
[SATA_DWC_QCMD_MAX
];
157 int dma_pending
[SATA_DWC_QCMD_MAX
];
160 struct dma_chan
*chan
;
161 struct dma_async_tx_descriptor
*desc
[SATA_DWC_QCMD_MAX
];
162 u32 dma_interrupt_count
;
166 * Commonly used DWC SATA driver macros
168 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
175 SATA_DWC_CMD_ISSUED_NOT
= 0,
176 SATA_DWC_CMD_ISSUED_PEND
= 1,
177 SATA_DWC_CMD_ISSUED_EXEC
= 2,
178 SATA_DWC_CMD_ISSUED_NODATA
= 3,
180 SATA_DWC_DMA_PENDING_NONE
= 0,
181 SATA_DWC_DMA_PENDING_TX
= 1,
182 SATA_DWC_DMA_PENDING_RX
= 2,
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd
*qc
, u8 tag
);
189 static int sata_dwc_qc_complete(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
191 static void sata_dwc_dma_xfer_complete(struct ata_port
*ap
, u32 check_status
);
192 static void sata_dwc_port_stop(struct ata_port
*ap
);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port
*hsdevp
, u8 tag
);
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
200 static struct dw_dma_slave sata_dwc_dma_dws
= {
207 static bool sata_dwc_dma_filter(struct dma_chan
*chan
, void *param
)
209 struct dw_dma_slave
*dws
= &sata_dwc_dma_dws
;
211 if (dws
->dma_dev
!= chan
->device
->dev
)
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port
*hsdevp
)
220 struct sata_dwc_device
*hsdev
= hsdevp
->hsdev
;
221 struct dw_dma_slave
*dws
= &sata_dwc_dma_dws
;
224 dws
->dma_dev
= hsdev
->dev
;
227 dma_cap_set(DMA_SLAVE
, mask
);
229 /* Acquire DMA channel */
230 hsdevp
->chan
= dma_request_channel(mask
, sata_dwc_dma_filter
, hsdevp
);
232 dev_err(hsdev
->dev
, "%s: dma channel unavailable\n",
240 static int sata_dwc_dma_init_old(struct platform_device
*pdev
,
241 struct sata_dwc_device
*hsdev
)
243 struct device_node
*np
= pdev
->dev
.of_node
;
246 hsdev
->dma
= devm_kzalloc(&pdev
->dev
, sizeof(*hsdev
->dma
), GFP_KERNEL
);
250 hsdev
->dma
->dev
= &pdev
->dev
;
252 /* Get SATA DMA interrupt number */
253 hsdev
->dma
->irq
= irq_of_parse_and_map(np
, 1);
254 if (hsdev
->dma
->irq
== NO_IRQ
) {
255 dev_err(&pdev
->dev
, "no SATA DMA irq\n");
259 /* Get physical SATA DMA register base address */
260 hsdev
->dma
->regs
= of_iomap(np
, 1);
261 if (!hsdev
->dma
->regs
) {
263 "ioremap failed for AHBDMA register address\n");
267 /* Initialize AHB DMAC */
268 err
= dw_dma_probe(hsdev
->dma
);
270 iounmap(hsdev
->dma
->regs
);
277 static void sata_dwc_dma_exit_old(struct sata_dwc_device
*hsdev
)
282 dw_dma_remove(hsdev
->dma
);
283 iounmap(hsdev
->dma
->regs
);
288 static const char *get_prot_descript(u8 protocol
)
290 switch ((enum ata_tf_protocols
)protocol
) {
291 case ATA_PROT_NODATA
:
292 return "ATA no data";
299 case ATAPI_PROT_NODATA
:
300 return "ATAPI no data";
310 static const char *get_dma_dir_descript(int dma_dir
)
312 switch ((enum dma_data_direction
)dma_dir
) {
313 case DMA_BIDIRECTIONAL
:
314 return "bidirectional";
317 case DMA_FROM_DEVICE
:
318 return "from device";
324 static void sata_dwc_tf_dump(struct ata_port
*ap
, struct ata_taskfile
*tf
)
327 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
328 tf
->command
, get_prot_descript(tf
->protocol
), tf
->flags
,
331 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
332 tf
->feature
, tf
->nsect
, tf
->lbal
, tf
->lbam
, tf
->lbah
);
334 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
335 tf
->hob_feature
, tf
->hob_nsect
, tf
->hob_lbal
, tf
->hob_lbam
,
339 static void dma_dwc_xfer_done(void *hsdev_instance
)
342 struct sata_dwc_device
*hsdev
= hsdev_instance
;
343 struct ata_host
*host
= (struct ata_host
*)hsdev
->host
;
345 struct sata_dwc_device_port
*hsdevp
;
347 unsigned int port
= 0;
349 spin_lock_irqsave(&host
->lock
, flags
);
350 ap
= host
->ports
[port
];
351 hsdevp
= HSDEVP_FROM_AP(ap
);
352 tag
= ap
->link
.active_tag
;
355 * Each DMA command produces 2 interrupts. Only
356 * complete the command after both interrupts have been
357 * seen. (See sata_dwc_isr())
359 hsdevp
->dma_interrupt_count
++;
360 sata_dwc_clear_dmacr(hsdevp
, tag
);
362 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_NONE
) {
363 dev_err(ap
->dev
, "DMA not pending tag=0x%02x pending=%d\n",
364 tag
, hsdevp
->dma_pending
[tag
]);
367 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
368 sata_dwc_dma_xfer_complete(ap
, 1);
370 spin_unlock_irqrestore(&host
->lock
, flags
);
373 static struct dma_async_tx_descriptor
*dma_dwc_xfer_setup(struct ata_queued_cmd
*qc
)
375 struct ata_port
*ap
= qc
->ap
;
376 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
377 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
378 dma_addr_t addr
= (dma_addr_t
)&hsdev
->sata_dwc_regs
->dmadr
;
379 struct dma_slave_config sconf
;
380 struct dma_async_tx_descriptor
*desc
;
382 if (qc
->dma_dir
== DMA_DEV_TO_MEM
) {
383 sconf
.src_addr
= addr
;
384 sconf
.device_fc
= false;
385 } else { /* DMA_MEM_TO_DEV */
386 sconf
.dst_addr
= addr
;
387 sconf
.device_fc
= false;
390 sconf
.direction
= qc
->dma_dir
;
391 sconf
.src_maxburst
= AHB_DMA_BRST_DFLT
/ 4; /* in items */
392 sconf
.dst_maxburst
= AHB_DMA_BRST_DFLT
/ 4; /* in items */
393 sconf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
394 sconf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
396 dmaengine_slave_config(hsdevp
->chan
, &sconf
);
398 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
399 desc
= dmaengine_prep_slave_sg(hsdevp
->chan
, qc
->sg
, qc
->n_elem
,
401 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
406 desc
->callback
= dma_dwc_xfer_done
;
407 desc
->callback_param
= hsdev
;
409 dev_dbg(hsdev
->dev
, "%s sg: 0x%p, count: %d addr: %pad\n",
410 __func__
, qc
->sg
, qc
->n_elem
, &addr
);
415 static int sata_dwc_scr_read(struct ata_link
*link
, unsigned int scr
, u32
*val
)
417 if (scr
> SCR_NOTIFICATION
) {
418 dev_err(link
->ap
->dev
, "%s: Incorrect SCR offset 0x%02x\n",
423 *val
= sata_dwc_readl(link
->ap
->ioaddr
.scr_addr
+ (scr
* 4));
424 dev_dbg(link
->ap
->dev
, "%s: id=%d reg=%d val=val=0x%08x\n",
425 __func__
, link
->ap
->print_id
, scr
, *val
);
430 static int sata_dwc_scr_write(struct ata_link
*link
, unsigned int scr
, u32 val
)
432 dev_dbg(link
->ap
->dev
, "%s: id=%d reg=%d val=val=0x%08x\n",
433 __func__
, link
->ap
->print_id
, scr
, val
);
434 if (scr
> SCR_NOTIFICATION
) {
435 dev_err(link
->ap
->dev
, "%s: Incorrect SCR offset 0x%02x\n",
439 sata_dwc_writel(link
->ap
->ioaddr
.scr_addr
+ (scr
* 4), val
);
444 static void clear_serror(struct ata_port
*ap
)
447 sata_dwc_scr_read(&ap
->link
, SCR_ERROR
, &val
);
448 sata_dwc_scr_write(&ap
->link
, SCR_ERROR
, val
);
451 static void clear_interrupt_bit(struct sata_dwc_device
*hsdev
, u32 bit
)
453 sata_dwc_writel(&hsdev
->sata_dwc_regs
->intpr
,
454 sata_dwc_readl(&hsdev
->sata_dwc_regs
->intpr
));
457 static u32
qcmd_tag_to_mask(u8 tag
)
459 return 0x00000001 << (tag
& 0x1f);
463 static void sata_dwc_error_intr(struct ata_port
*ap
,
464 struct sata_dwc_device
*hsdev
, uint intpr
)
466 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
467 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
468 unsigned int err_mask
= 0, action
= 0;
469 struct ata_queued_cmd
*qc
;
473 ata_ehi_clear_desc(ehi
);
475 sata_dwc_scr_read(&ap
->link
, SCR_ERROR
, &serror
);
476 status
= ap
->ops
->sff_check_status(ap
);
478 tag
= ap
->link
.active_tag
;
481 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
482 __func__
, serror
, intpr
, status
, hsdevp
->dma_interrupt_count
,
483 hsdevp
->dma_pending
[tag
], hsdevp
->cmd_issued
[tag
]);
485 /* Clear error register and interrupt bit */
487 clear_interrupt_bit(hsdev
, SATA_DWC_INTPR_ERR
);
489 /* This is the only error happening now. TODO check for exact error */
491 err_mask
|= AC_ERR_HOST_BUS
;
492 action
|= ATA_EH_RESET
;
494 /* Pass this on to EH */
495 ehi
->serror
|= serror
;
496 ehi
->action
|= action
;
498 qc
= ata_qc_from_tag(ap
, tag
);
500 qc
->err_mask
|= err_mask
;
502 ehi
->err_mask
|= err_mask
;
508 * Function : sata_dwc_isr
509 * arguments : irq, void *dev_instance, struct pt_regs *regs
510 * Return value : irqreturn_t - status of IRQ
511 * This Interrupt handler called via port ops registered function.
512 * .irq_handler = sata_dwc_isr
514 static irqreturn_t
sata_dwc_isr(int irq
, void *dev_instance
)
516 struct ata_host
*host
= (struct ata_host
*)dev_instance
;
517 struct sata_dwc_device
*hsdev
= HSDEV_FROM_HOST(host
);
519 struct ata_queued_cmd
*qc
;
522 int handled
, num_processed
, port
= 0;
523 uint intpr
, sactive
, sactive2
, tag_mask
;
524 struct sata_dwc_device_port
*hsdevp
;
525 hsdev
->sactive_issued
= 0;
527 spin_lock_irqsave(&host
->lock
, flags
);
529 /* Read the interrupt register */
530 intpr
= sata_dwc_readl(&hsdev
->sata_dwc_regs
->intpr
);
532 ap
= host
->ports
[port
];
533 hsdevp
= HSDEVP_FROM_AP(ap
);
535 dev_dbg(ap
->dev
, "%s intpr=0x%08x active_tag=%d\n", __func__
, intpr
,
536 ap
->link
.active_tag
);
538 /* Check for error interrupt */
539 if (intpr
& SATA_DWC_INTPR_ERR
) {
540 sata_dwc_error_intr(ap
, hsdev
, intpr
);
545 /* Check for DMA SETUP FIS (FP DMA) interrupt */
546 if (intpr
& SATA_DWC_INTPR_NEWFP
) {
547 clear_interrupt_bit(hsdev
, SATA_DWC_INTPR_NEWFP
);
549 tag
= (u8
)(sata_dwc_readl(&hsdev
->sata_dwc_regs
->fptagr
));
550 dev_dbg(ap
->dev
, "%s: NEWFP tag=%d\n", __func__
, tag
);
551 if (hsdevp
->cmd_issued
[tag
] != SATA_DWC_CMD_ISSUED_PEND
)
552 dev_warn(ap
->dev
, "CMD tag=%d not pending?\n", tag
);
554 hsdev
->sactive_issued
|= qcmd_tag_to_mask(tag
);
556 qc
= ata_qc_from_tag(ap
, tag
);
558 * Start FP DMA for NCQ command. At this point the tag is the
559 * active tag. It is the tag that matches the command about to
562 qc
->ap
->link
.active_tag
= tag
;
563 sata_dwc_bmdma_start_by_tag(qc
, tag
);
568 sata_dwc_scr_read(&ap
->link
, SCR_ACTIVE
, &sactive
);
569 tag_mask
= (hsdev
->sactive_issued
| sactive
) ^ sactive
;
571 /* If no sactive issued and tag_mask is zero then this is not NCQ */
572 if (hsdev
->sactive_issued
== 0 && tag_mask
== 0) {
573 if (ap
->link
.active_tag
== ATA_TAG_POISON
)
576 tag
= ap
->link
.active_tag
;
577 qc
= ata_qc_from_tag(ap
, tag
);
579 /* DEV interrupt w/ no active qc? */
580 if (unlikely(!qc
|| (qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
582 "%s interrupt with no active qc qc=%p\n",
584 ap
->ops
->sff_check_status(ap
);
588 status
= ap
->ops
->sff_check_status(ap
);
590 qc
->ap
->link
.active_tag
= tag
;
591 hsdevp
->cmd_issued
[tag
] = SATA_DWC_CMD_ISSUED_NOT
;
593 if (status
& ATA_ERR
) {
594 dev_dbg(ap
->dev
, "interrupt ATA_ERR (0x%x)\n", status
);
595 sata_dwc_qc_complete(ap
, qc
, 1);
600 dev_dbg(ap
->dev
, "%s non-NCQ cmd interrupt, protocol: %s\n",
601 __func__
, get_prot_descript(qc
->tf
.protocol
));
603 if (ata_is_dma(qc
->tf
.protocol
)) {
605 * Each DMA transaction produces 2 interrupts. The DMAC
606 * transfer complete interrupt and the SATA controller
607 * operation done interrupt. The command should be
608 * completed only after both interrupts are seen.
610 hsdevp
->dma_interrupt_count
++;
611 if (hsdevp
->dma_pending
[tag
] == \
612 SATA_DWC_DMA_PENDING_NONE
) {
614 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
615 __func__
, intpr
, status
,
616 hsdevp
->dma_pending
[tag
]);
619 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
620 sata_dwc_dma_xfer_complete(ap
, 1);
621 } else if (ata_is_pio(qc
->tf
.protocol
)) {
622 ata_sff_hsm_move(ap
, qc
, status
, 0);
626 if (unlikely(sata_dwc_qc_complete(ap
, qc
, 1)))
635 * This is a NCQ command. At this point we need to figure out for which
636 * tags we have gotten a completion interrupt. One interrupt may serve
637 * as completion for more than one operation when commands are queued
638 * (NCQ). We need to process each completed command.
641 /* process completed commands */
642 sata_dwc_scr_read(&ap
->link
, SCR_ACTIVE
, &sactive
);
643 tag_mask
= (hsdev
->sactive_issued
| sactive
) ^ sactive
;
645 if (sactive
!= 0 || hsdev
->sactive_issued
> 1 || tag_mask
> 1) {
647 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
648 __func__
, sactive
, hsdev
->sactive_issued
, tag_mask
);
651 if ((tag_mask
| hsdev
->sactive_issued
) != hsdev
->sactive_issued
) {
653 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
654 sactive
, hsdev
->sactive_issued
, tag_mask
);
657 /* read just to clear ... not bad if currently still busy */
658 status
= ap
->ops
->sff_check_status(ap
);
659 dev_dbg(ap
->dev
, "%s ATA status register=0x%x\n", __func__
, status
);
665 while (!(tag_mask
& 0x00000001)) {
670 tag_mask
&= (~0x00000001);
671 qc
= ata_qc_from_tag(ap
, tag
);
673 /* To be picked up by completion functions */
674 qc
->ap
->link
.active_tag
= tag
;
675 hsdevp
->cmd_issued
[tag
] = SATA_DWC_CMD_ISSUED_NOT
;
677 /* Let libata/scsi layers handle error */
678 if (status
& ATA_ERR
) {
679 dev_dbg(ap
->dev
, "%s ATA_ERR (0x%x)\n", __func__
,
681 sata_dwc_qc_complete(ap
, qc
, 1);
686 /* Process completed command */
687 dev_dbg(ap
->dev
, "%s NCQ command, protocol: %s\n", __func__
,
688 get_prot_descript(qc
->tf
.protocol
));
689 if (ata_is_dma(qc
->tf
.protocol
)) {
690 hsdevp
->dma_interrupt_count
++;
691 if (hsdevp
->dma_pending
[tag
] == \
692 SATA_DWC_DMA_PENDING_NONE
)
693 dev_warn(ap
->dev
, "%s: DMA not pending?\n",
695 if ((hsdevp
->dma_interrupt_count
% 2) == 0)
696 sata_dwc_dma_xfer_complete(ap
, 1);
698 if (unlikely(sata_dwc_qc_complete(ap
, qc
, 1)))
704 ap
->stats
.idle_irq
++;
705 dev_warn(ap
->dev
, "STILL BUSY IRQ ata%d: irq trap\n",
707 } /* while tag_mask */
710 * Check to see if any commands completed while we were processing our
711 * initial set of completed commands (read status clears interrupts,
712 * so we might miss a completed command interrupt if one came in while
713 * we were processing --we read status as part of processing a completed
716 sata_dwc_scr_read(&ap
->link
, SCR_ACTIVE
, &sactive2
);
717 if (sactive2
!= sactive
) {
719 "More completed - sactive=0x%x sactive2=0x%x\n",
725 spin_unlock_irqrestore(&host
->lock
, flags
);
726 return IRQ_RETVAL(handled
);
729 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port
*hsdevp
, u8 tag
)
731 struct sata_dwc_device
*hsdev
= HSDEV_FROM_HSDEVP(hsdevp
);
733 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_RX
) {
734 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
735 SATA_DWC_DMACR_RX_CLEAR(
736 sata_dwc_readl(&hsdev
->sata_dwc_regs
->dmacr
)));
737 } else if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_TX
) {
738 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
739 SATA_DWC_DMACR_TX_CLEAR(
740 sata_dwc_readl(&hsdev
->sata_dwc_regs
->dmacr
)));
743 * This should not happen, it indicates the driver is out of
744 * sync. If it does happen, clear dmacr anyway.
747 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
748 __func__
, tag
, hsdevp
->dma_pending
[tag
],
749 sata_dwc_readl(&hsdev
->sata_dwc_regs
->dmacr
));
750 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
751 SATA_DWC_DMACR_TXRXCH_CLEAR
);
755 static void sata_dwc_dma_xfer_complete(struct ata_port
*ap
, u32 check_status
)
757 struct ata_queued_cmd
*qc
;
758 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
759 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
762 tag
= ap
->link
.active_tag
;
763 qc
= ata_qc_from_tag(ap
, tag
);
765 dev_err(ap
->dev
, "failed to get qc");
772 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
773 __func__
, qc
->tag
, qc
->tf
.command
,
774 get_dma_dir_descript(qc
->dma_dir
),
775 get_prot_descript(qc
->tf
.protocol
),
776 sata_dwc_readl(&hsdev
->sata_dwc_regs
->dmacr
));
780 if (ata_is_dma(qc
->tf
.protocol
)) {
781 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_NONE
) {
783 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
785 sata_dwc_readl(&hsdev
->sata_dwc_regs
->dmacr
));
788 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_NONE
;
789 sata_dwc_qc_complete(ap
, qc
, check_status
);
790 ap
->link
.active_tag
= ATA_TAG_POISON
;
792 sata_dwc_qc_complete(ap
, qc
, check_status
);
796 static int sata_dwc_qc_complete(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
802 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
803 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
804 hsdev
->sactive_queued
= 0;
805 dev_dbg(ap
->dev
, "%s checkstatus? %x\n", __func__
, check_status
);
807 if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_TX
)
808 dev_err(ap
->dev
, "TX DMA PENDING\n");
809 else if (hsdevp
->dma_pending
[tag
] == SATA_DWC_DMA_PENDING_RX
)
810 dev_err(ap
->dev
, "RX DMA PENDING\n");
812 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
813 qc
->tf
.command
, status
, ap
->print_id
, qc
->tf
.protocol
);
815 /* clear active bit */
816 mask
= (~(qcmd_tag_to_mask(tag
)));
817 hsdev
->sactive_queued
= hsdev
->sactive_queued
& mask
;
818 hsdev
->sactive_issued
= hsdev
->sactive_issued
& mask
;
823 static void sata_dwc_enable_interrupts(struct sata_dwc_device
*hsdev
)
825 /* Enable selective interrupts by setting the interrupt maskregister*/
826 sata_dwc_writel(&hsdev
->sata_dwc_regs
->intmr
,
827 SATA_DWC_INTMR_ERRM
|
828 SATA_DWC_INTMR_NEWFPM
|
829 SATA_DWC_INTMR_PMABRTM
|
830 SATA_DWC_INTMR_DMATM
);
832 * Unmask the error bits that should trigger an error interrupt by
833 * setting the error mask register.
835 sata_dwc_writel(&hsdev
->sata_dwc_regs
->errmr
, SATA_DWC_SERROR_ERR_BITS
);
837 dev_dbg(hsdev
->dev
, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
838 __func__
, sata_dwc_readl(&hsdev
->sata_dwc_regs
->intmr
),
839 sata_dwc_readl(&hsdev
->sata_dwc_regs
->errmr
));
842 static void sata_dwc_setup_port(struct ata_ioports
*port
, void __iomem
*base
)
844 port
->cmd_addr
= base
+ 0x00;
845 port
->data_addr
= base
+ 0x00;
847 port
->error_addr
= base
+ 0x04;
848 port
->feature_addr
= base
+ 0x04;
850 port
->nsect_addr
= base
+ 0x08;
852 port
->lbal_addr
= base
+ 0x0c;
853 port
->lbam_addr
= base
+ 0x10;
854 port
->lbah_addr
= base
+ 0x14;
856 port
->device_addr
= base
+ 0x18;
857 port
->command_addr
= base
+ 0x1c;
858 port
->status_addr
= base
+ 0x1c;
860 port
->altstatus_addr
= base
+ 0x20;
861 port
->ctl_addr
= base
+ 0x20;
864 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port
*hsdevp
)
866 struct sata_dwc_device
*hsdev
= hsdevp
->hsdev
;
867 struct device
*dev
= hsdev
->dev
;
869 #ifdef CONFIG_SATA_DWC_OLD_DMA
870 if (!of_find_property(dev
->of_node
, "dmas", NULL
))
871 return sata_dwc_dma_get_channel_old(hsdevp
);
874 hsdevp
->chan
= dma_request_chan(dev
, "sata-dma");
875 if (IS_ERR(hsdevp
->chan
)) {
876 dev_err(dev
, "failed to allocate dma channel: %ld\n",
877 PTR_ERR(hsdevp
->chan
));
878 return PTR_ERR(hsdevp
->chan
);
885 * Function : sata_dwc_port_start
886 * arguments : struct ata_ioports *port
887 * Return value : returns 0 if success, error code otherwise
888 * This function allocates the scatter gather LLI table for AHB DMA
890 static int sata_dwc_port_start(struct ata_port
*ap
)
893 struct sata_dwc_device
*hsdev
;
894 struct sata_dwc_device_port
*hsdevp
= NULL
;
898 hsdev
= HSDEV_FROM_AP(ap
);
900 dev_dbg(ap
->dev
, "%s: port_no=%d\n", __func__
, ap
->port_no
);
902 hsdev
->host
= ap
->host
;
903 pdev
= ap
->host
->dev
;
905 dev_err(ap
->dev
, "%s: no ap->host->dev\n", __func__
);
910 /* Allocate Port Struct */
911 hsdevp
= kzalloc(sizeof(*hsdevp
), GFP_KERNEL
);
913 dev_err(ap
->dev
, "%s: kmalloc failed for hsdevp\n", __func__
);
917 hsdevp
->hsdev
= hsdev
;
919 err
= sata_dwc_dma_get_channel(hsdevp
);
923 err
= phy_power_on(hsdev
->phy
);
927 for (i
= 0; i
< SATA_DWC_QCMD_MAX
; i
++)
928 hsdevp
->cmd_issued
[i
] = SATA_DWC_CMD_ISSUED_NOT
;
930 ap
->bmdma_prd
= NULL
; /* set these so libata doesn't use them */
931 ap
->bmdma_prd_dma
= 0;
933 if (ap
->port_no
== 0) {
934 dev_dbg(ap
->dev
, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
936 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
937 SATA_DWC_DMACR_TXRXCH_CLEAR
);
939 dev_dbg(ap
->dev
, "%s: setting burst size in DBTSR\n",
941 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dbtsr
,
942 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT
) |
943 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT
)));
946 /* Clear any error bits before libata starts issuing commands */
948 ap
->private_data
= hsdevp
;
949 dev_dbg(ap
->dev
, "%s: done\n", __func__
);
955 dev_dbg(ap
->dev
, "%s: fail. ap->id = %d\n", __func__
, ap
->print_id
);
959 static void sata_dwc_port_stop(struct ata_port
*ap
)
961 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
962 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(ap
);
964 dev_dbg(ap
->dev
, "%s: ap->id = %d\n", __func__
, ap
->print_id
);
966 dmaengine_terminate_sync(hsdevp
->chan
);
967 dma_release_channel(hsdevp
->chan
);
968 phy_power_off(hsdev
->phy
);
971 ap
->private_data
= NULL
;
975 * Function : sata_dwc_exec_command_by_tag
976 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
977 * Return value : None
978 * This function keeps track of individual command tag ids and calls
979 * ata_exec_command in libata
981 static void sata_dwc_exec_command_by_tag(struct ata_port
*ap
,
982 struct ata_taskfile
*tf
,
983 u8 tag
, u32 cmd_issued
)
985 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
987 dev_dbg(ap
->dev
, "%s cmd(0x%02x): %s tag=%d\n", __func__
, tf
->command
,
988 ata_get_cmd_descript(tf
->command
), tag
);
990 hsdevp
->cmd_issued
[tag
] = cmd_issued
;
993 * Clear SError before executing a new command.
994 * sata_dwc_scr_write and read can not be used here. Clearing the PM
995 * managed SError register for the disk needs to be done before the
996 * task file is loaded.
999 ata_sff_exec_command(ap
, tf
);
1002 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd
*qc
, u8 tag
)
1004 sata_dwc_exec_command_by_tag(qc
->ap
, &qc
->tf
, tag
,
1005 SATA_DWC_CMD_ISSUED_PEND
);
1008 static void sata_dwc_bmdma_setup(struct ata_queued_cmd
*qc
)
1012 if (ata_is_ncq(qc
->tf
.protocol
)) {
1013 dev_dbg(qc
->ap
->dev
, "%s: ap->link.sactive=0x%08x tag=%d\n",
1014 __func__
, qc
->ap
->link
.sactive
, tag
);
1018 sata_dwc_bmdma_setup_by_tag(qc
, tag
);
1021 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd
*qc
, u8 tag
)
1025 struct sata_dwc_device
*hsdev
= HSDEV_FROM_QC(qc
);
1026 struct ata_port
*ap
= qc
->ap
;
1027 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
1028 struct dma_async_tx_descriptor
*desc
= hsdevp
->desc
[tag
];
1029 int dir
= qc
->dma_dir
;
1031 if (hsdevp
->cmd_issued
[tag
] != SATA_DWC_CMD_ISSUED_NOT
) {
1033 if (dir
== DMA_TO_DEVICE
)
1034 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_TX
;
1036 hsdevp
->dma_pending
[tag
] = SATA_DWC_DMA_PENDING_RX
;
1039 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1040 __func__
, hsdevp
->cmd_issued
[tag
], tag
);
1045 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1046 __func__
, qc
, tag
, qc
->tf
.command
,
1047 get_dma_dir_descript(qc
->dma_dir
), start_dma
);
1048 sata_dwc_tf_dump(ap
, &qc
->tf
);
1051 sata_dwc_scr_read(&ap
->link
, SCR_ERROR
, ®
);
1052 if (reg
& SATA_DWC_SERROR_ERR_BITS
) {
1053 dev_err(ap
->dev
, "%s: ****** SError=0x%08x ******\n",
1057 if (dir
== DMA_TO_DEVICE
)
1058 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
1059 SATA_DWC_DMACR_TXCHEN
);
1061 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
1062 SATA_DWC_DMACR_RXCHEN
);
1064 /* Enable AHB DMA transfer on the specified channel */
1065 dmaengine_submit(desc
);
1066 dma_async_issue_pending(hsdevp
->chan
);
1070 static void sata_dwc_bmdma_start(struct ata_queued_cmd
*qc
)
1074 if (ata_is_ncq(qc
->tf
.protocol
)) {
1075 dev_dbg(qc
->ap
->dev
, "%s: ap->link.sactive=0x%08x tag=%d\n",
1076 __func__
, qc
->ap
->link
.sactive
, tag
);
1080 dev_dbg(qc
->ap
->dev
, "%s\n", __func__
);
1081 sata_dwc_bmdma_start_by_tag(qc
, tag
);
1084 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd
*qc
)
1088 struct ata_port
*ap
= qc
->ap
;
1089 struct sata_dwc_device_port
*hsdevp
= HSDEVP_FROM_AP(ap
);
1092 if (qc
->tag
> 0 || ap
->link
.sactive
> 1)
1094 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1095 __func__
, ap
->print_id
, qc
->tf
.command
,
1096 ata_get_cmd_descript(qc
->tf
.command
),
1097 qc
->tag
, get_prot_descript(qc
->tf
.protocol
),
1098 ap
->link
.active_tag
, ap
->link
.sactive
);
1101 if (!ata_is_ncq(qc
->tf
.protocol
))
1104 if (ata_is_dma(qc
->tf
.protocol
)) {
1105 hsdevp
->desc
[tag
] = dma_dwc_xfer_setup(qc
);
1106 if (!hsdevp
->desc
[tag
])
1107 return AC_ERR_SYSTEM
;
1109 hsdevp
->desc
[tag
] = NULL
;
1112 if (ata_is_ncq(qc
->tf
.protocol
)) {
1113 sata_dwc_scr_read(&ap
->link
, SCR_ACTIVE
, &sactive
);
1114 sactive
|= (0x00000001 << tag
);
1115 sata_dwc_scr_write(&ap
->link
, SCR_ACTIVE
, sactive
);
1117 dev_dbg(qc
->ap
->dev
,
1118 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1119 __func__
, tag
, qc
->ap
->link
.sactive
, sactive
);
1121 ap
->ops
->sff_tf_load(ap
, &qc
->tf
);
1122 sata_dwc_exec_command_by_tag(ap
, &qc
->tf
, tag
,
1123 SATA_DWC_CMD_ISSUED_PEND
);
1125 return ata_bmdma_qc_issue(qc
);
1130 static void sata_dwc_error_handler(struct ata_port
*ap
)
1132 ata_sff_error_handler(ap
);
1135 static int sata_dwc_hardreset(struct ata_link
*link
, unsigned int *class,
1136 unsigned long deadline
)
1138 struct sata_dwc_device
*hsdev
= HSDEV_FROM_AP(link
->ap
);
1141 ret
= sata_sff_hardreset(link
, class, deadline
);
1143 sata_dwc_enable_interrupts(hsdev
);
1145 /* Reconfigure the DMA control register */
1146 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dmacr
,
1147 SATA_DWC_DMACR_TXRXCH_CLEAR
);
1149 /* Reconfigure the DMA Burst Transaction Size register */
1150 sata_dwc_writel(&hsdev
->sata_dwc_regs
->dbtsr
,
1151 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT
) |
1152 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT
));
1157 static void sata_dwc_dev_select(struct ata_port
*ap
, unsigned int device
)
1159 /* SATA DWC is master only */
1163 * scsi mid-layer and libata interface structures
1165 static struct scsi_host_template sata_dwc_sht
= {
1166 ATA_NCQ_SHT(DRV_NAME
),
1168 * test-only: Currently this driver doesn't handle NCQ
1169 * correctly. We enable NCQ but set the queue depth to a
1170 * max of 1. This will get fixed in in a future release.
1172 .sg_tablesize
= LIBATA_MAX_PRD
,
1173 /* .can_queue = ATA_MAX_QUEUE, */
1175 * Make sure a LLI block is not created that will span 8K max FIS
1176 * boundary. If the block spans such a FIS boundary, there is a chance
1177 * that a DMA burst will cross that boundary -- this results in an
1178 * error in the host controller.
1180 .dma_boundary
= 0x1fff /* ATA_DMA_BOUNDARY */,
1183 static struct ata_port_operations sata_dwc_ops
= {
1184 .inherits
= &ata_sff_port_ops
,
1186 .error_handler
= sata_dwc_error_handler
,
1187 .hardreset
= sata_dwc_hardreset
,
1189 .qc_issue
= sata_dwc_qc_issue
,
1191 .scr_read
= sata_dwc_scr_read
,
1192 .scr_write
= sata_dwc_scr_write
,
1194 .port_start
= sata_dwc_port_start
,
1195 .port_stop
= sata_dwc_port_stop
,
1197 .sff_dev_select
= sata_dwc_dev_select
,
1199 .bmdma_setup
= sata_dwc_bmdma_setup
,
1200 .bmdma_start
= sata_dwc_bmdma_start
,
1203 static const struct ata_port_info sata_dwc_port_info
[] = {
1205 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NCQ
,
1206 .pio_mask
= ATA_PIO4
,
1207 .udma_mask
= ATA_UDMA6
,
1208 .port_ops
= &sata_dwc_ops
,
1212 static int sata_dwc_probe(struct platform_device
*ofdev
)
1214 struct sata_dwc_device
*hsdev
;
1216 char *ver
= (char *)&versionr
;
1220 struct ata_host
*host
;
1221 struct ata_port_info pi
= sata_dwc_port_info
[0];
1222 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1223 struct device_node
*np
= ofdev
->dev
.of_node
;
1225 /* Allocate DWC SATA device */
1226 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_DWC_MAX_PORTS
);
1227 hsdev
= devm_kzalloc(&ofdev
->dev
, sizeof(*hsdev
), GFP_KERNEL
);
1228 if (!host
|| !hsdev
)
1231 host
->private_data
= hsdev
;
1233 /* Ioremap SATA registers */
1234 base
= of_iomap(np
, 0);
1236 dev_err(&ofdev
->dev
,
1237 "ioremap failed for SATA register address\n");
1240 hsdev
->reg_base
= base
;
1241 dev_dbg(&ofdev
->dev
, "ioremap done for SATA register address\n");
1243 /* Synopsys DWC SATA specific Registers */
1244 hsdev
->sata_dwc_regs
= base
+ SATA_DWC_REG_OFFSET
;
1247 host
->ports
[0]->ioaddr
.cmd_addr
= base
;
1248 host
->ports
[0]->ioaddr
.scr_addr
= base
+ SATA_DWC_SCR_OFFSET
;
1249 sata_dwc_setup_port(&host
->ports
[0]->ioaddr
, base
);
1251 /* Read the ID and Version Registers */
1252 idr
= sata_dwc_readl(&hsdev
->sata_dwc_regs
->idr
);
1253 versionr
= sata_dwc_readl(&hsdev
->sata_dwc_regs
->versionr
);
1254 dev_notice(&ofdev
->dev
, "id %d, controller version %c.%c%c\n",
1255 idr
, ver
[0], ver
[1], ver
[2]);
1257 /* Save dev for later use in dev_xxx() routines */
1258 hsdev
->dev
= &ofdev
->dev
;
1260 /* Enable SATA Interrupts */
1261 sata_dwc_enable_interrupts(hsdev
);
1263 /* Get SATA interrupt number */
1264 irq
= irq_of_parse_and_map(np
, 0);
1265 if (irq
== NO_IRQ
) {
1266 dev_err(&ofdev
->dev
, "no SATA DMA irq\n");
1271 #ifdef CONFIG_SATA_DWC_OLD_DMA
1272 if (!of_find_property(np
, "dmas", NULL
)) {
1273 err
= sata_dwc_dma_init_old(ofdev
, hsdev
);
1279 hsdev
->phy
= devm_phy_optional_get(hsdev
->dev
, "sata-phy");
1280 if (IS_ERR(hsdev
->phy
)) {
1281 err
= PTR_ERR(hsdev
->phy
);
1286 err
= phy_init(hsdev
->phy
);
1291 * Now, register with libATA core, this will also initiate the
1292 * device discovery process, invoking our port_start() handler &
1293 * error_handler() to execute a dummy Softreset EH session
1295 err
= ata_host_activate(host
, irq
, sata_dwc_isr
, 0, &sata_dwc_sht
);
1297 dev_err(&ofdev
->dev
, "failed to activate host");
1299 dev_set_drvdata(&ofdev
->dev
, host
);
1303 phy_exit(hsdev
->phy
);
1308 static int sata_dwc_remove(struct platform_device
*ofdev
)
1310 struct device
*dev
= &ofdev
->dev
;
1311 struct ata_host
*host
= dev_get_drvdata(dev
);
1312 struct sata_dwc_device
*hsdev
= host
->private_data
;
1314 ata_host_detach(host
);
1316 phy_exit(hsdev
->phy
);
1318 #ifdef CONFIG_SATA_DWC_OLD_DMA
1319 /* Free SATA DMA resources */
1320 sata_dwc_dma_exit_old(hsdev
);
1323 iounmap(hsdev
->reg_base
);
1324 dev_dbg(&ofdev
->dev
, "done\n");
1328 static const struct of_device_id sata_dwc_match
[] = {
1329 { .compatible
= "amcc,sata-460ex", },
1332 MODULE_DEVICE_TABLE(of
, sata_dwc_match
);
1334 static struct platform_driver sata_dwc_driver
= {
1337 .of_match_table
= sata_dwc_match
,
1339 .probe
= sata_dwc_probe
,
1340 .remove
= sata_dwc_remove
,
1343 module_platform_driver(sata_dwc_driver
);
1345 MODULE_LICENSE("GPL");
1346 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1347 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1348 MODULE_VERSION(DRV_VERSION
);