ata: Switch all my stuff to a common address
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pata_ninja32.c
1 /*
2 * pata_ninja32.c - Ninja32 PATA for new ATA layer
3 * (C) 2007 Red Hat Inc
4 *
5 * Note: The controller like many controllers has shared timings for
6 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
7 * in the dma_stop function. Thus we actually don't need a set_dmamode
8 * method as the PIO method is always called and will set the right PIO
9 * timing parameters.
10 *
11 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
12 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
13 * driver and the extensive analysis done by the BSD developers, notably
14 * ITOH Yasufumi.
15 *
16 * Base + 0x00 IRQ Status
17 * Base + 0x01 IRQ control
18 * Base + 0x02 Chipset control
19 * Base + 0x03 Unknown
20 * Base + 0x04 VDMA and reset control + wait bits
21 * Base + 0x08 BMIMBA
22 * Base + 0x0C DMA Length
23 * Base + 0x10 Taskfile
24 * Base + 0x18 BMDMA Status ?
25 * Base + 0x1C
26 * Base + 0x1D Bus master control
27 * bit 0 = enable
28 * bit 1 = 0 write/1 read
29 * bit 2 = 1 sgtable
30 * bit 3 = go
31 * bit 4-6 wait bits
32 * bit 7 = done
33 * Base + 0x1E AltStatus
34 * Base + 0x1F timing register
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pata_ninja32"
47 #define DRV_VERSION "0.0.1"
48
49
50 /**
51 * ninja32_set_piomode - set initial PIO mode data
52 * @ap: ATA interface
53 * @adev: ATA device
54 *
55 * Called to do the PIO mode setup. Our timing registers are shared
56 * but we want to set the PIO timing by default.
57 */
58
59 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
60 {
61 static u16 pio_timing[5] = {
62 0xd6, 0x85, 0x44, 0x33, 0x13
63 };
64 iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
65 ap->ioaddr.bmdma_addr + 0x1f);
66 ap->private_data = adev;
67 }
68
69
70 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
71 {
72 struct ata_device *adev = &ap->link.device[device];
73 if (ap->private_data != adev) {
74 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
75 ata_sff_dev_select(ap, device);
76 ninja32_set_piomode(ap, adev);
77 }
78 }
79
80 static struct scsi_host_template ninja32_sht = {
81 ATA_BMDMA_SHT(DRV_NAME),
82 };
83
84 static struct ata_port_operations ninja32_port_ops = {
85 .inherits = &ata_bmdma_port_ops,
86 .sff_dev_select = ninja32_dev_select,
87 .cable_detect = ata_cable_40wire,
88 .set_piomode = ninja32_set_piomode,
89 };
90
91 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
92 {
93 struct ata_host *host;
94 struct ata_port *ap;
95 void __iomem *base;
96 int rc;
97
98 host = ata_host_alloc(&dev->dev, 1);
99 if (!host)
100 return -ENOMEM;
101 ap = host->ports[0];
102
103 /* Set up the PCI device */
104 rc = pcim_enable_device(dev);
105 if (rc)
106 return rc;
107 rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
108 if (rc == -EBUSY)
109 pcim_pin_device(dev);
110 if (rc)
111 return rc;
112
113 host->iomap = pcim_iomap_table(dev);
114 rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
115 if (rc)
116 return rc;
117 rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
118 if (rc)
119 return rc;
120 pci_set_master(dev);
121
122 /* Set up the register mappings */
123 base = host->iomap[0];
124 if (!base)
125 return -ENOMEM;
126 ap->ops = &ninja32_port_ops;
127 ap->pio_mask = 0x1F;
128 ap->flags |= ATA_FLAG_SLAVE_POSS;
129
130 ap->ioaddr.cmd_addr = base + 0x10;
131 ap->ioaddr.ctl_addr = base + 0x1E;
132 ap->ioaddr.altstatus_addr = base + 0x1E;
133 ap->ioaddr.bmdma_addr = base;
134 ata_sff_std_ports(&ap->ioaddr);
135
136 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
137 iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
138 iowrite8(0x01, base + 0x03); /* Unknown */
139 iowrite8(0x20, base + 0x04); /* WAIT0 */
140 iowrite8(0x8f, base + 0x05); /* Unknown */
141 iowrite8(0xa4, base + 0x1c); /* Unknown */
142 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
143 /* FIXME: Should we disable them at remove ? */
144 return ata_host_activate(host, dev->irq, ata_sff_interrupt,
145 IRQF_SHARED, &ninja32_sht);
146 }
147
148 static const struct pci_device_id ninja32[] = {
149 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { },
152 };
153
154 static struct pci_driver ninja32_pci_driver = {
155 .name = DRV_NAME,
156 .id_table = ninja32,
157 .probe = ninja32_init_one,
158 .remove = ata_pci_remove_one
159 };
160
161 static int __init ninja32_init(void)
162 {
163 return pci_register_driver(&ninja32_pci_driver);
164 }
165
166 static void __exit ninja32_exit(void)
167 {
168 pci_unregister_driver(&ninja32_pci_driver);
169 }
170
171 MODULE_AUTHOR("Alan Cox");
172 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
173 MODULE_LICENSE("GPL");
174 MODULE_DEVICE_TABLE(pci, ninja32);
175 MODULE_VERSION(DRV_VERSION);
176
177 module_init(ninja32_init);
178 module_exit(ninja32_exit);