drivers/ata/pata_legacy.c

   1 /*
   2  *   pata-legacy.c - Legacy port PATA/SATA controller driver.
   3  *   Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2, or (at your option)
   8  *  any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; see the file COPYING.  If not, write to
  17  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *   An ATA driver for the legacy ATA ports.
  20  *
  21  *   Data Sources:
  22  *      Opti 82C465/82C611 support: Data sheets at opti-inc.com
  23  *      HT6560 series:
  24  *      Promise 20230/20620:
  25  *              http://www.ryston.cz/petr/vlb/pdc20230b.html
  26  *              http://www.ryston.cz/petr/vlb/pdc20230c.html
  27  *              http://www.ryston.cz/petr/vlb/pdc20630.html
  28  *
  29  *  Unsupported but docs exist:
  30  *      Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  31  *      Winbond W83759A
  32  *
  33  *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
  34  *  on PC class systems. There are three hybrid devices that are exceptions
  35  *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  36  *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  37  *
  38  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  39  *  opti82c465mv/promise 20230c/20630
  40  *
  41  *  Use the autospeed and pio_mask options with:
  42  *      Appian ADI/2 aka CLPD7220 or AIC25VL01.
  43  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  44  *      Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  45  *      Winbond W83759A, Promise PDC20230-B
  46  *
  47  *  For now use autospeed and pio_mask as above with the W83759A. This may
  48  *  change.
  49  *
  50  *  TODO
  51  *      Merge existing pata_qdi driver
  52  *
  53  */
  54
  55 #include <linux/kernel.h>
  56 #include <linux/module.h>
  57 #include <linux/pci.h>
  58 #include <linux/init.h>
  59 #include <linux/blkdev.h>
  60 #include <linux/delay.h>
  61 #include <scsi/scsi_host.h>
  62 #include <linux/ata.h>
  63 #include <linux/libata.h>
  64 #include <linux/platform_device.h>
  65
  66 #define DRV_NAME "pata_legacy"
  67 #define DRV_VERSION "0.5.3"
  68
  69 #define NR_HOST 6
  70
  71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
  72 static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
  73
  74 struct legacy_data {
  75         unsigned long timing;
  76         u8 clock[2];
  77         u8 last;
  78         int fast;
  79         struct platform_device *platform_dev;
  80
  81 };
  82
  83 static struct legacy_data legacy_data[NR_HOST];
  84 static struct ata_host *legacy_host[NR_HOST];
  85 static int nr_legacy_host;
  86
  87
  88 static int probe_all;                   /* Set to check all ISA port ranges */
  89 static int ht6560a;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  90 static int ht6560b;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  91 static int opti82c611a;                 /* Opti82c611A on primary 1, secondary 2, both 3 */
  92 static int opti82c46x;          /* Opti 82c465MV present (pri/sec autodetect) */
  93 static int autospeed;                   /* Chip present which snoops speed changes */
  94 static int pio_mask = 0x1F;             /* PIO range for autospeed devices */
  95
  96 /**
  97  *      legacy_set_mode         -       mode setting
  98  *      @ap: IDE interface
  99  *
 100  *      Use a non standard set_mode function. We don't want to be tuned.
 101  *
 102  *      The BIOS configured everything. Our job is not to fiddle. Just use
 103  *      whatever PIO the hardware is using and leave it at that. When we
 104  *      get some kind of nice user driven API for control then we can
 105  *      expand on this as per hdparm in the base kernel.
 106  */
 107
 108 static void legacy_set_mode(struct ata_port *ap)
 109 {
 110         int i;
 111
 112         for (i = 0; i < ATA_MAX_DEVICES; i++) {
 113                 struct ata_device *dev = &ap->device[i];
 114                 if (ata_dev_enabled(dev)) {
 115                         dev->pio_mode = XFER_PIO_0;
 116                         dev->xfer_mode = XFER_PIO_0;
 117                         dev->xfer_shift = ATA_SHIFT_PIO;
 118                         dev->flags |= ATA_DFLAG_PIO;
 119                 }
 120         }
 121 }
 122
 123 static struct scsi_host_template legacy_sht = {
 124         .module                 = THIS_MODULE,
 125         .name                   = DRV_NAME,
 126         .ioctl                  = ata_scsi_ioctl,
 127         .queuecommand           = ata_scsi_queuecmd,
 128         .can_queue              = ATA_DEF_QUEUE,
 129         .this_id                = ATA_SHT_THIS_ID,
 130         .sg_tablesize           = LIBATA_MAX_PRD,
 131         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 132         .emulated               = ATA_SHT_EMULATED,
 133         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 134         .proc_name              = DRV_NAME,
 135         .dma_boundary           = ATA_DMA_BOUNDARY,
 136         .slave_configure        = ata_scsi_slave_config,
 137         .slave_destroy          = ata_scsi_slave_destroy,
 138         .bios_param             = ata_std_bios_param,
 139 };
 140
 141 /*
 142  *      These ops are used if the user indicates the hardware
 143  *      snoops the commands to decide on the mode and handles the
 144  *      mode selection "magically" itself. Several legacy controllers
 145  *      do this. The mode range can be set if it is not 0x1F by setting
 146  *      pio_mask as well.
 147  */
 148
 149 static struct ata_port_operations simple_port_ops = {
 150         .port_disable   = ata_port_disable,
 151         .tf_load        = ata_tf_load,
 152         .tf_read        = ata_tf_read,
 153         .check_status   = ata_check_status,
 154         .exec_command   = ata_exec_command,
 155         .dev_select     = ata_std_dev_select,
 156
 157         .freeze         = ata_bmdma_freeze,
 158         .thaw           = ata_bmdma_thaw,
 159         .error_handler  = ata_bmdma_error_handler,
 160         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 161
 162         .qc_prep        = ata_qc_prep,
 163         .qc_issue       = ata_qc_issue_prot,
 164
 165         .data_xfer      = ata_pio_data_xfer_noirq,
 166
 167         .irq_handler    = ata_interrupt,
 168         .irq_clear      = ata_bmdma_irq_clear,
 169
 170         .port_start     = ata_port_start,
 171         .port_stop      = ata_port_stop,
 172         .host_stop      = ata_host_stop
 173 };
 174
 175 static struct ata_port_operations legacy_port_ops = {
 176         .set_mode       = legacy_set_mode,
 177
 178         .port_disable   = ata_port_disable,
 179         .tf_load        = ata_tf_load,
 180         .tf_read        = ata_tf_read,
 181         .check_status   = ata_check_status,
 182         .exec_command   = ata_exec_command,
 183         .dev_select     = ata_std_dev_select,
 184
 185         .error_handler  = ata_bmdma_error_handler,
 186
 187         .qc_prep        = ata_qc_prep,
 188         .qc_issue       = ata_qc_issue_prot,
 189
 190         .data_xfer      = ata_pio_data_xfer_noirq,
 191
 192         .irq_handler    = ata_interrupt,
 193         .irq_clear      = ata_bmdma_irq_clear,
 194
 195         .port_start     = ata_port_start,
 196         .port_stop      = ata_port_stop,
 197         .host_stop      = ata_host_stop
 198 };
 199
 200 /*
 201  *      Promise 20230C and 20620 support
 202  *
 203  *      This controller supports PIO0 to PIO2. We set PIO timings conservatively to
 204  *      allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
 205  *      controller and PIO'd to the host and not supported.
 206  */
 207
 208 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 209 {
 210         int tries = 5;
 211         int pio = adev->pio_mode - XFER_PIO_0;
 212         u8 rt;
 213         unsigned long flags;
 214
 215         /* Safe as UP only. Force I/Os to occur together */
 216
 217         local_irq_save(flags);
 218
 219         /* Unlock the control interface */
 220         do
 221         {
 222                 inb(0x1F5);
 223                 outb(inb(0x1F2) | 0x80, 0x1F2);
 224                 inb(0x1F2);
 225                 inb(0x3F6);
 226                 inb(0x3F6);
 227                 inb(0x1F2);
 228                 inb(0x1F2);
 229         }
 230         while((inb(0x1F2) & 0x80) && --tries);
 231
 232         local_irq_restore(flags);
 233
 234         outb(inb(0x1F4) & 0x07, 0x1F4);
 235
 236         rt = inb(0x1F3);
 237         rt &= 0x07 << (3 * adev->devno);
 238         if (pio)
 239                 rt |= (1 + 3 * pio) << (3 * adev->devno);
 240
 241         udelay(100);
 242         outb(inb(0x1F2) | 0x01, 0x1F2);
 243         udelay(100);
 244         inb(0x1F5);
 245
 246 }
 247
 248 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
 249 {
 250         struct ata_port *ap = adev->ap;
 251         int slop = buflen & 3;
 252         unsigned long flags;
 253
 254         if (ata_id_has_dword_io(adev->id)) {
 255                 local_irq_save(flags);
 256
 257                 /* Perform the 32bit I/O synchronization sequence */
 258                 inb(ap->ioaddr.nsect_addr);
 259                 inb(ap->ioaddr.nsect_addr);
 260                 inb(ap->ioaddr.nsect_addr);
 261
 262                 /* Now the data */
 263
 264                 if (write_data)
 265                         outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
 266                 else
 267                         insl(ap->ioaddr.data_addr, buf, buflen >> 2);
 268
 269                 if (unlikely(slop)) {
 270                         u32 pad;
 271                         if (write_data) {
 272                                 memcpy(&pad, buf + buflen - slop, slop);
 273                                 outl(le32_to_cpu(pad), ap->ioaddr.data_addr);
 274                         } else {
 275                                 pad = cpu_to_le16(inl(ap->ioaddr.data_addr));
 276                                 memcpy(buf + buflen - slop, &pad, slop);
 277                         }
 278                 }
 279                 local_irq_restore(flags);
 280         }
 281         else
 282                 ata_pio_data_xfer_noirq(adev, buf, buflen, write_data);
 283 }
 284
 285 static struct ata_port_operations pdc20230_port_ops = {
 286         .set_piomode    = pdc20230_set_piomode,
 287
 288         .port_disable   = ata_port_disable,
 289         .tf_load        = ata_tf_load,
 290         .tf_read        = ata_tf_read,
 291         .check_status   = ata_check_status,
 292         .exec_command   = ata_exec_command,
 293         .dev_select     = ata_std_dev_select,
 294
 295         .error_handler  = ata_bmdma_error_handler,
 296
 297         .qc_prep        = ata_qc_prep,
 298         .qc_issue       = ata_qc_issue_prot,
 299
 300         .data_xfer      = pdc_data_xfer_vlb,
 301
 302         .irq_handler    = ata_interrupt,
 303         .irq_clear      = ata_bmdma_irq_clear,
 304
 305         .port_start     = ata_port_start,
 306         .port_stop      = ata_port_stop,
 307         .host_stop      = ata_host_stop
 308 };
 309
 310 /*
 311  *      Holtek 6560A support
 312  *
 313  *      This controller supports PIO0 to PIO2 (no IORDY even though higher timings
 314  *      can be loaded).
 315  */
 316
 317 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 318 {
 319         u8 active, recover;
 320         struct ata_timing t;
 321
 322         /* Get the timing data in cycles. For now play safe at 50Mhz */
 323         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 324
 325         active = FIT(t.active, 2, 15);
 326         recover = FIT(t.recover, 4, 15);
 327
 328         inb(0x3E6);
 329         inb(0x3E6);
 330         inb(0x3E6);
 331         inb(0x3E6);
 332
 333         outb(recover << 4 | active, ap->ioaddr.device_addr);
 334         inb(ap->ioaddr.status_addr);
 335 }
 336
 337 static struct ata_port_operations ht6560a_port_ops = {
 338         .set_piomode    = ht6560a_set_piomode,
 339
 340         .port_disable   = ata_port_disable,
 341         .tf_load        = ata_tf_load,
 342         .tf_read        = ata_tf_read,
 343         .check_status   = ata_check_status,
 344         .exec_command   = ata_exec_command,
 345         .dev_select     = ata_std_dev_select,
 346
 347         .error_handler  = ata_bmdma_error_handler,
 348
 349         .qc_prep        = ata_qc_prep,
 350         .qc_issue       = ata_qc_issue_prot,
 351
 352         .data_xfer      = ata_pio_data_xfer,    /* Check vlb/noirq */
 353
 354         .irq_handler    = ata_interrupt,
 355         .irq_clear      = ata_bmdma_irq_clear,
 356
 357         .port_start     = ata_port_start,
 358         .port_stop      = ata_port_stop,
 359         .host_stop      = ata_host_stop
 360 };
 361
 362 /*
 363  *      Holtek 6560B support
 364  *
 365  *      This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
 366  *      unless we see an ATAPI device in which case we force it off.
 367  *
 368  *      FIXME: need to implement 2nd channel support.
 369  */
 370
 371 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
 372 {
 373         u8 active, recover;
 374         struct ata_timing t;
 375
 376         /* Get the timing data in cycles. For now play safe at 50Mhz */
 377         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 378
 379         active = FIT(t.active, 2, 15);
 380         recover = FIT(t.recover, 2, 16);
 381         recover &= 0x15;
 382
 383         inb(0x3E6);
 384         inb(0x3E6);
 385         inb(0x3E6);
 386         inb(0x3E6);
 387
 388         outb(recover << 4 | active, ap->ioaddr.device_addr);
 389
 390         if (adev->class != ATA_DEV_ATA) {
 391                 u8 rconf = inb(0x3E6);
 392                 if (rconf & 0x24) {
 393                         rconf &= ~ 0x24;
 394                         outb(rconf, 0x3E6);
 395                 }
 396         }
 397         inb(ap->ioaddr.status_addr);
 398 }
 399
 400 static struct ata_port_operations ht6560b_port_ops = {
 401         .set_piomode    = ht6560b_set_piomode,
 402
 403         .port_disable   = ata_port_disable,
 404         .tf_load        = ata_tf_load,
 405         .tf_read        = ata_tf_read,
 406         .check_status   = ata_check_status,
 407         .exec_command   = ata_exec_command,
 408         .dev_select     = ata_std_dev_select,
 409
 410         .error_handler  = ata_bmdma_error_handler,
 411
 412         .qc_prep        = ata_qc_prep,
 413         .qc_issue       = ata_qc_issue_prot,
 414
 415         .data_xfer      = ata_pio_data_xfer,    /* FIXME: Check 32bit and noirq */
 416
 417         .irq_handler    = ata_interrupt,
 418         .irq_clear      = ata_bmdma_irq_clear,
 419
 420         .port_start     = ata_port_start,
 421         .port_stop      = ata_port_stop,
 422         .host_stop      = ata_host_stop
 423 };
 424
 425 /*
 426  *      Opti core chipset helpers
 427  */
 428
 429 /**
 430  *      opti_syscfg     -       read OPTI chipset configuration
 431  *      @reg: Configuration register to read
 432  *
 433  *      Returns the value of an OPTI system board configuration register.
 434  */
 435
 436 static u8 opti_syscfg(u8 reg)
 437 {
 438         unsigned long flags;
 439         u8 r;
 440
 441         /* Uniprocessor chipset and must force cycles adjancent */
 442         local_irq_save(flags);
 443         outb(reg, 0x22);
 444         r = inb(0x24);
 445         local_irq_restore(flags);
 446         return r;
 447 }
 448
 449 /*
 450  *      Opti 82C611A
 451  *
 452  *      This controller supports PIO0 to PIO3.
 453  */
 454
 455 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 456 {
 457         u8 active, recover, setup;
 458         struct ata_timing t;
 459         struct ata_device *pair = ata_dev_pair(adev);
 460         int clock;
 461         int khz[4] = { 50000, 40000, 33000, 25000 };
 462         u8 rc;
 463
 464         /* Enter configuration mode */
 465         inw(ap->ioaddr.error_addr);
 466         inw(ap->ioaddr.error_addr);
 467         outb(3, ap->ioaddr.nsect_addr);
 468
 469         /* Read VLB clock strapping */
 470         clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03];
 471
 472         /* Get the timing data in cycles */
 473         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 474
 475         /* Setup timing is shared */
 476         if (pair) {
 477                 struct ata_timing tp;
 478                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 479
 480                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 481         }
 482
 483         active = FIT(t.active, 2, 17) - 2;
 484         recover = FIT(t.recover, 1, 16) - 1;
 485         setup = FIT(t.setup, 1, 4) - 1;
 486
 487         /* Select the right timing bank for write timing */
 488         rc = inb(ap->ioaddr.lbal_addr);
 489         rc &= 0x7F;
 490         rc |= (adev->devno << 7);
 491         outb(rc, ap->ioaddr.lbal_addr);
 492
 493         /* Write the timings */
 494         outb(active << 4 | recover, ap->ioaddr.error_addr);
 495
 496         /* Select the right bank for read timings, also
 497            load the shared timings for address */
 498         rc = inb(ap->ioaddr.device_addr);
 499         rc &= 0xC0;
 500         rc |= adev->devno;      /* Index select */
 501         rc |= (setup << 4) | 0x04;
 502         outb(rc, ap->ioaddr.device_addr);
 503
 504         /* Load the read timings */
 505         outb(active << 4 | recover, ap->ioaddr.data_addr);
 506
 507         /* Ensure the timing register mode is right */
 508         rc = inb (ap->ioaddr.lbal_addr);
 509         rc &= 0x73;
 510         rc |= 0x84;
 511         outb(rc, ap->ioaddr.lbal_addr);
 512
 513         /* Exit command mode */
 514         outb(0x83,  ap->ioaddr.nsect_addr);
 515 }
 516
 517
 518 static struct ata_port_operations opti82c611a_port_ops = {
 519         .set_piomode    = opti82c611a_set_piomode,
 520
 521         .port_disable   = ata_port_disable,
 522         .tf_load        = ata_tf_load,
 523         .tf_read        = ata_tf_read,
 524         .check_status   = ata_check_status,
 525         .exec_command   = ata_exec_command,
 526         .dev_select     = ata_std_dev_select,
 527
 528         .error_handler  = ata_bmdma_error_handler,
 529
 530         .qc_prep        = ata_qc_prep,
 531         .qc_issue       = ata_qc_issue_prot,
 532
 533         .data_xfer      = ata_pio_data_xfer,
 534
 535         .irq_handler    = ata_interrupt,
 536         .irq_clear      = ata_bmdma_irq_clear,
 537
 538         .port_start     = ata_port_start,
 539         .port_stop      = ata_port_stop,
 540         .host_stop      = ata_host_stop
 541 };
 542
 543 /*
 544  *      Opti 82C465MV
 545  *
 546  *      This controller supports PIO0 to PIO3. Unlike the 611A the MVB
 547  *      version is dual channel but doesn't have a lot of unique registers.
 548  */
 549
 550 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 551 {
 552         u8 active, recover, setup;
 553         struct ata_timing t;
 554         struct ata_device *pair = ata_dev_pair(adev);
 555         int clock;
 556         int khz[4] = { 50000, 40000, 33000, 25000 };
 557         u8 rc;
 558         u8 sysclk;
 559
 560         /* Get the clock */
 561         sysclk = opti_syscfg(0xAC) & 0xC0;      /* BIOS set */
 562
 563         /* Enter configuration mode */
 564         inw(ap->ioaddr.error_addr);
 565         inw(ap->ioaddr.error_addr);
 566         outb(3, ap->ioaddr.nsect_addr);
 567
 568         /* Read VLB clock strapping */
 569         clock = 1000000000 / khz[sysclk];
 570
 571         /* Get the timing data in cycles */
 572         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 573
 574         /* Setup timing is shared */
 575         if (pair) {
 576                 struct ata_timing tp;
 577                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 578
 579                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 580         }
 581
 582         active = FIT(t.active, 2, 17) - 2;
 583         recover = FIT(t.recover, 1, 16) - 1;
 584         setup = FIT(t.setup, 1, 4) - 1;
 585
 586         /* Select the right timing bank for write timing */
 587         rc = inb(ap->ioaddr.lbal_addr);
 588         rc &= 0x7F;
 589         rc |= (adev->devno << 7);
 590         outb(rc, ap->ioaddr.lbal_addr);
 591
 592         /* Write the timings */
 593         outb(active << 4 | recover, ap->ioaddr.error_addr);
 594
 595         /* Select the right bank for read timings, also
 596            load the shared timings for address */
 597         rc = inb(ap->ioaddr.device_addr);
 598         rc &= 0xC0;
 599         rc |= adev->devno;      /* Index select */
 600         rc |= (setup << 4) | 0x04;
 601         outb(rc, ap->ioaddr.device_addr);
 602
 603         /* Load the read timings */
 604         outb(active << 4 | recover, ap->ioaddr.data_addr);
 605
 606         /* Ensure the timing register mode is right */
 607         rc = inb (ap->ioaddr.lbal_addr);
 608         rc &= 0x73;
 609         rc |= 0x84;
 610         outb(rc, ap->ioaddr.lbal_addr);
 611
 612         /* Exit command mode */
 613         outb(0x83,  ap->ioaddr.nsect_addr);
 614
 615         /* We need to know this for quad device on the MVB */
 616         ap->host->private_data = ap;
 617 }
 618
 619 /**
 620  *      opt82c465mv_qc_issue_prot       -       command issue
 621  *      @qc: command pending
 622  *
 623  *      Called when the libata layer is about to issue a command. We wrap
 624  *      this interface so that we can load the correct ATA timings. The
 625  *      MVB has a single set of timing registers and these are shared
 626  *      across channels. As there are two registers we really ought to
 627  *      track the last two used values as a sort of register window. For
 628  *      now we just reload on a channel switch. On the single channel
 629  *      setup this condition never fires so we do nothing extra.
 630  *
 631  *      FIXME: dual channel needs ->serialize support
 632  */
 633
 634 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
 635 {
 636         struct ata_port *ap = qc->ap;
 637         struct ata_device *adev = qc->dev;
 638
 639         /* If timings are set and for the wrong channel (2nd test is
 640            due to a libata shortcoming and will eventually go I hope) */
 641         if (ap->host->private_data != ap->host
 642             && ap->host->private_data != NULL)
 643                 opti82c46x_set_piomode(ap, adev);
 644
 645         return ata_qc_issue_prot(qc);
 646 }
 647
 648 static struct ata_port_operations opti82c46x_port_ops = {
 649         .set_piomode    = opti82c46x_set_piomode,
 650
 651         .port_disable   = ata_port_disable,
 652         .tf_load        = ata_tf_load,
 653         .tf_read        = ata_tf_read,
 654         .check_status   = ata_check_status,
 655         .exec_command   = ata_exec_command,
 656         .dev_select     = ata_std_dev_select,
 657
 658         .error_handler  = ata_bmdma_error_handler,
 659
 660         .qc_prep        = ata_qc_prep,
 661         .qc_issue       = opti82c46x_qc_issue_prot,
 662
 663         .data_xfer      = ata_pio_data_xfer,
 664
 665         .irq_handler    = ata_interrupt,
 666         .irq_clear      = ata_bmdma_irq_clear,
 667
 668         .port_start     = ata_port_start,
 669         .port_stop      = ata_port_stop,
 670         .host_stop      = ata_host_stop
 671 };
 672
 673
 674 /**
 675  *      legacy_init_one         -       attach a legacy interface
 676  *      @port: port number
 677  *      @io: I/O port start
 678  *      @ctrl: control port
 679  *      @irq: interrupt line
 680  *
 681  *      Register an ISA bus IDE interface. Such interfaces are PIO and we
 682  *      assume do not support IRQ sharing.
 683  */
 684
 685 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
 686 {
 687         struct legacy_data *ld = &legacy_data[nr_legacy_host];
 688         struct ata_probe_ent ae;
 689         struct platform_device *pdev;
 690         int ret = -EBUSY;
 691         struct ata_port_operations *ops = &legacy_port_ops;
 692         int pio_modes = pio_mask;
 693         u32 mask = (1 << port);
 694
 695         if (request_region(io, 8, "pata_legacy") == NULL)
 696                 return -EBUSY;
 697         if (request_region(ctrl, 1, "pata_legacy") == NULL)
 698                 goto fail_io;
 699
 700         pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
 701         if (IS_ERR(pdev)) {
 702                 ret = PTR_ERR(pdev);
 703                 goto fail_dev;
 704         }
 705
 706         if (ht6560a & mask) {
 707                 ops = &ht6560a_port_ops;
 708                 pio_modes = 0x07;
 709         }
 710         if (ht6560b & mask) {
 711                 ops = &ht6560b_port_ops;
 712                 pio_modes = 0x1F;
 713         }
 714         if (opti82c611a & mask) {
 715                 ops = &opti82c611a_port_ops;
 716                 pio_modes = 0x0F;
 717         }
 718         if (opti82c46x & mask) {
 719                 ops = &opti82c46x_port_ops;
 720                 pio_modes = 0x0F;
 721         }
 722
 723         /* Probe for automatically detectable controllers */
 724
 725         if (io == 0x1F0 && ops == &legacy_port_ops) {
 726                 unsigned long flags;
 727
 728                 local_irq_save(flags);
 729
 730                 /* Probes */
 731                 inb(0x1F5);
 732                 outb(inb(0x1F2) | 0x80, 0x1F2);
 733                 inb(0x1F2);
 734                 inb(0x3F6);
 735                 inb(0x3F6);
 736                 inb(0x1F2);
 737                 inb(0x1F2);
 738
 739                 if ((inb(0x1F2) & 0x80) == 0) {
 740                         /* PDC20230c or 20630 ? */
 741                         printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
 742                                 pio_modes = 0x07;
 743                         ops = &pdc20230_port_ops;
 744                         udelay(100);
 745                         inb(0x1F5);
 746                 } else {
 747                         outb(0x55, 0x1F2);
 748                         inb(0x1F2);
 749                         inb(0x1F2);
 750                         if (inb(0x1F2) == 0x00) {
 751                                 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
 752                         }
 753                 }
 754                 local_irq_restore(flags);
 755         }
 756
 757
 758         /* Chip does mode setting by command snooping */
 759         if (ops == &legacy_port_ops && (autospeed & mask))
 760                 ops = &simple_port_ops;
 761         memset(&ae, 0, sizeof(struct ata_probe_ent));
 762         INIT_LIST_HEAD(&ae.node);
 763         ae.dev = &pdev->dev;
 764         ae.port_ops = ops;
 765         ae.sht = &legacy_sht;
 766         ae.n_ports = 1;
 767         ae.pio_mask = pio_modes;
 768         ae.irq = irq;
 769         ae.irq_flags = 0;
 770         ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
 771         ae.port[0].cmd_addr = io;
 772         ae.port[0].altstatus_addr = ctrl;
 773         ae.port[0].ctl_addr =   ctrl;
 774         ata_std_ports(&ae.port[0]);
 775         ae.private_data = ld;
 776
 777         ret = ata_device_add(&ae);
 778         if (ret == 0) {
 779                 ret = -ENODEV;
 780                 goto fail;
 781         }
 782         legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
 783         ld->platform_dev = pdev;
 784         return 0;
 785
 786 fail:
 787         platform_device_unregister(pdev);
 788 fail_dev:
 789         release_region(ctrl, 1);
 790 fail_io:
 791         release_region(io, 8);
 792         return ret;
 793 }
 794
 795 /**
 796  *      legacy_check_special_cases      -       ATA special cases
 797  *      @p: PCI device to check
 798  *      @master: set this if we find an ATA master
 799  *      @master: set this if we find an ATA secondary
 800  *
 801  *      A small number of vendors implemented early PCI ATA interfaces on bridge logic
 802  *      without the ATA interface being PCI visible. Where we have a matching PCI driver
 803  *      we must skip the relevant device here. If we don't know about it then the legacy
 804  *      driver is the right driver anyway.
 805  */
 806
 807 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
 808 {
 809         /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
 810         if (p->vendor == 0x1078 && p->device == 0x0000) {
 811                 *primary = *secondary = 1;
 812                 return;
 813         }
 814         /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
 815         if (p->vendor == 0x1078 && p->device == 0x0002) {
 816                 *primary = *secondary = 1;
 817                 return;
 818         }
 819         /* Intel MPIIX - PIO ATA on non PCI side of bridge */
 820         if (p->vendor == 0x8086 && p->device == 0x1234) {
 821                 u16 r;
 822                 pci_read_config_word(p, 0x6C, &r);
 823                 if (r & 0x8000) {       /* ATA port enabled */
 824                         if (r & 0x4000)
 825                                 *secondary = 1;
 826                         else
 827                                 *primary = 1;
 828                 }
 829                 return;
 830         }
 831 }
 832
 833
 834 /**
 835  *      legacy_init             -       attach legacy interfaces
 836  *
 837  *      Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
 838  *      Right now we do not scan the ide0 and ide1 address but should do so
 839  *      for non PCI systems or systems with no PCI IDE legacy mode devices.
 840  *      If you fix that note there are special cases to consider like VLB
 841  *      drivers and CS5510/20.
 842  */
 843
 844 static __init int legacy_init(void)
 845 {
 846         int i;
 847         int ct = 0;
 848         int primary = 0;
 849         int secondary = 0;
 850         int last_port = NR_HOST;
 851
 852         struct pci_dev *p = NULL;
 853
 854         for_each_pci_dev(p) {
 855                 int r;
 856                 /* Check for any overlap of the system ATA mappings. Native mode controllers
 857                    stuck on these addresses or some devices in 'raid' mode won't be found by
 858                    the storage class test */
 859                 for (r = 0; r < 6; r++) {
 860                         if (pci_resource_start(p, r) == 0x1f0)
 861                                 primary = 1;
 862                         if (pci_resource_start(p, r) == 0x170)
 863                                 secondary = 1;
 864                 }
 865                 /* Check for special cases */
 866                 legacy_check_special_cases(p, &primary, &secondary);
 867
 868                 /* If PCI bus is present then don't probe for tertiary legacy ports */
 869                 if (probe_all == 0)
 870                         last_port = 2;
 871         }
 872
 873         /* If an OPTI 82C46X is present find out where the channels are */
 874         if (opti82c46x) {
 875                 static const char *optis[4] = {
 876                         "3/463MV", "5MV",
 877                         "5MVA", "5MVB"
 878                 };
 879                 u8 chans = 1;
 880                 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
 881
 882                 opti82c46x = 3; /* Assume master and slave first */
 883                 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
 884                 if (ctrl == 3)
 885                         chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
 886                 ctrl = opti_syscfg(0xAC);
 887                 /* Check enabled and this port is the 465MV port. On the
 888                    MVB we may have two channels */
 889                 if (ctrl & 8) {
 890                         if (ctrl & 4)
 891                                 opti82c46x = 2; /* Slave */
 892                         else
 893                                 opti82c46x = 1; /* Master */
 894                         if (chans == 2)
 895                                 opti82c46x = 3; /* Master and Slave */
 896                 }       /* Slave only */
 897                 else if (chans == 1)
 898                         opti82c46x = 1;
 899         }
 900
 901         for (i = 0; i < last_port; i++) {
 902                 /* Skip primary if we have seen a PCI one */
 903                 if (i == 0 && primary == 1)
 904                         continue;
 905                 /* Skip secondary if we have seen a PCI one */
 906                 if (i == 1 && secondary == 1)
 907                         continue;
 908                 if (legacy_init_one(i, legacy_port[i],
 909                                    legacy_port[i] + 0x0206,
 910                                    legacy_irq[i]) == 0)
 911                         ct++;
 912         }
 913         if (ct != 0)
 914                 return 0;
 915         return -ENODEV;
 916 }
 917
 918 static __exit void legacy_exit(void)
 919 {
 920         int i;
 921
 922         for (i = 0; i < nr_legacy_host; i++) {
 923                 struct legacy_data *ld = &legacy_data[i];
 924                 struct ata_port *ap =legacy_host[i]->ports[0];
 925                 unsigned long io = ap->ioaddr.cmd_addr;
 926                 unsigned long ctrl = ap->ioaddr.ctl_addr;
 927                 ata_host_remove(legacy_host[i]);
 928                 platform_device_unregister(ld->platform_dev);
 929                 if (ld->timing)
 930                         release_region(ld->timing, 2);
 931                 release_region(io, 8);
 932                 release_region(ctrl, 1);
 933         }
 934 }
 935
 936 MODULE_AUTHOR("Alan Cox");
 937 MODULE_DESCRIPTION("low-level driver for legacy ATA");
 938 MODULE_LICENSE("GPL");
 939 MODULE_VERSION(DRV_VERSION);
 940
 941 module_param(probe_all, int, 0);
 942 module_param(autospeed, int, 0);
 943 module_param(ht6560a, int, 0);
 944 module_param(ht6560b, int, 0);
 945 module_param(opti82c611a, int, 0);
 946 module_param(opti82c46x, int, 0);
 947 module_param(pio_mask, int, 0);
 948
 949 module_init(legacy_init);
 950 module_exit(legacy_exit);
 951