drivers/ata/pata_legacy.c

   1 /*
   2  *   pata-legacy.c - Legacy port PATA/SATA controller driver.
   3  *   Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2, or (at your option)
   8  *  any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; see the file COPYING.  If not, write to
  17  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *   An ATA driver for the legacy ATA ports.
  20  *
  21  *   Data Sources:
  22  *      Opti 82C465/82C611 support: Data sheets at opti-inc.com
  23  *      HT6560 series:
  24  *      Promise 20230/20620:
  25  *              http://www.ryston.cz/petr/vlb/pdc20230b.html
  26  *              http://www.ryston.cz/petr/vlb/pdc20230c.html
  27  *              http://www.ryston.cz/petr/vlb/pdc20630.html
  28  *
  29  *  Unsupported but docs exist:
  30  *      Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  31  *      Winbond W83759A
  32  *
  33  *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
  34  *  on PC class systems. There are three hybrid devices that are exceptions
  35  *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  36  *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  37  *
  38  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  39  *  opti82c465mv/promise 20230c/20630
  40  *
  41  *  Use the autospeed and pio_mask options with:
  42  *      Appian ADI/2 aka CLPD7220 or AIC25VL01.
  43  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  44  *      Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  45  *      Winbond W83759A, Promise PDC20230-B
  46  *
  47  *  For now use autospeed and pio_mask as above with the W83759A. This may
  48  *  change.
  49  *
  50  *  TODO
  51  *      Merge existing pata_qdi driver
  52  *
  53  */
  54
  55 #include <linux/kernel.h>
  56 #include <linux/module.h>
  57 #include <linux/pci.h>
  58 #include <linux/init.h>
  59 #include <linux/blkdev.h>
  60 #include <linux/delay.h>
  61 #include <scsi/scsi_host.h>
  62 #include <linux/ata.h>
  63 #include <linux/libata.h>
  64 #include <linux/platform_device.h>
  65
  66 #define DRV_NAME "pata_legacy"
  67 #define DRV_VERSION "0.5.3"
  68
  69 #define NR_HOST 6
  70
  71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
  72 static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
  73
  74 struct legacy_data {
  75         unsigned long timing;
  76         u8 clock[2];
  77         u8 last;
  78         int fast;
  79         struct platform_device *platform_dev;
  80
  81 };
  82
  83 static struct legacy_data legacy_data[NR_HOST];
  84 static struct ata_host *legacy_host[NR_HOST];
  85 static int nr_legacy_host;
  86
  87
  88 static int probe_all;                   /* Set to check all ISA port ranges */
  89 static int ht6560a;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  90 static int ht6560b;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  91 static int opti82c611a;                 /* Opti82c611A on primary 1, secondary 2, both 3 */
  92 static int opti82c46x;                  /* Opti 82c465MV present (pri/sec autodetect) */
  93 static int autospeed;                   /* Chip present which snoops speed changes */
  94 static int pio_mask = 0x1F;             /* PIO range for autospeed devices */
  95 static int iordy_mask = 0xFFFFFFFF;     /* Use iordy if available */
  96
  97 /**
  98  *      legacy_set_mode         -       mode setting
  99  *      @ap: IDE interface
 100  *      @unused: Device that failed when error is returned
 101  *
 102  *      Use a non standard set_mode function. We don't want to be tuned.
 103  *
 104  *      The BIOS configured everything. Our job is not to fiddle. Just use
 105  *      whatever PIO the hardware is using and leave it at that. When we
 106  *      get some kind of nice user driven API for control then we can
 107  *      expand on this as per hdparm in the base kernel.
 108  */
 109
 110 static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused)
 111 {
 112         int i;
 113
 114         for (i = 0; i < ATA_MAX_DEVICES; i++) {
 115                 struct ata_device *dev = &ap->device[i];
 116                 if (ata_dev_enabled(dev)) {
 117                         ata_dev_printk(dev, KERN_INFO, "configured for PIO\n");
 118                         dev->pio_mode = XFER_PIO_0;
 119                         dev->xfer_mode = XFER_PIO_0;
 120                         dev->xfer_shift = ATA_SHIFT_PIO;
 121                         dev->flags |= ATA_DFLAG_PIO;
 122                 }
 123         }
 124         return 0;
 125 }
 126
 127 static struct scsi_host_template legacy_sht = {
 128         .module                 = THIS_MODULE,
 129         .name                   = DRV_NAME,
 130         .ioctl                  = ata_scsi_ioctl,
 131         .queuecommand           = ata_scsi_queuecmd,
 132         .can_queue              = ATA_DEF_QUEUE,
 133         .this_id                = ATA_SHT_THIS_ID,
 134         .sg_tablesize           = LIBATA_MAX_PRD,
 135         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 136         .emulated               = ATA_SHT_EMULATED,
 137         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 138         .proc_name              = DRV_NAME,
 139         .dma_boundary           = ATA_DMA_BOUNDARY,
 140         .slave_configure        = ata_scsi_slave_config,
 141         .slave_destroy          = ata_scsi_slave_destroy,
 142         .bios_param             = ata_std_bios_param,
 143 };
 144
 145 /*
 146  *      These ops are used if the user indicates the hardware
 147  *      snoops the commands to decide on the mode and handles the
 148  *      mode selection "magically" itself. Several legacy controllers
 149  *      do this. The mode range can be set if it is not 0x1F by setting
 150  *      pio_mask as well.
 151  */
 152
 153 static struct ata_port_operations simple_port_ops = {
 154         .port_disable   = ata_port_disable,
 155         .tf_load        = ata_tf_load,
 156         .tf_read        = ata_tf_read,
 157         .check_status   = ata_check_status,
 158         .exec_command   = ata_exec_command,
 159         .dev_select     = ata_std_dev_select,
 160
 161         .freeze         = ata_bmdma_freeze,
 162         .thaw           = ata_bmdma_thaw,
 163         .error_handler  = ata_bmdma_error_handler,
 164         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 165
 166         .qc_prep        = ata_qc_prep,
 167         .qc_issue       = ata_qc_issue_prot,
 168
 169         .data_xfer      = ata_data_xfer_noirq,
 170
 171         .irq_handler    = ata_interrupt,
 172         .irq_clear      = ata_bmdma_irq_clear,
 173         .irq_on         = ata_irq_on,
 174         .irq_ack        = ata_irq_ack,
 175
 176         .port_start     = ata_port_start,
 177 };
 178
 179 static struct ata_port_operations legacy_port_ops = {
 180         .set_mode       = legacy_set_mode,
 181
 182         .port_disable   = ata_port_disable,
 183         .tf_load        = ata_tf_load,
 184         .tf_read        = ata_tf_read,
 185         .check_status   = ata_check_status,
 186         .exec_command   = ata_exec_command,
 187         .dev_select     = ata_std_dev_select,
 188
 189         .error_handler  = ata_bmdma_error_handler,
 190
 191         .qc_prep        = ata_qc_prep,
 192         .qc_issue       = ata_qc_issue_prot,
 193
 194         .data_xfer      = ata_data_xfer_noirq,
 195
 196         .irq_handler    = ata_interrupt,
 197         .irq_clear      = ata_bmdma_irq_clear,
 198         .irq_on         = ata_irq_on,
 199         .irq_ack        = ata_irq_ack,
 200
 201         .port_start     = ata_port_start,
 202 };
 203
 204 /*
 205  *      Promise 20230C and 20620 support
 206  *
 207  *      This controller supports PIO0 to PIO2. We set PIO timings conservatively to
 208  *      allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
 209  *      controller and PIO'd to the host and not supported.
 210  */
 211
 212 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 213 {
 214         int tries = 5;
 215         int pio = adev->pio_mode - XFER_PIO_0;
 216         u8 rt;
 217         unsigned long flags;
 218
 219         /* Safe as UP only. Force I/Os to occur together */
 220
 221         local_irq_save(flags);
 222
 223         /* Unlock the control interface */
 224         do
 225         {
 226                 inb(0x1F5);
 227                 outb(inb(0x1F2) | 0x80, 0x1F2);
 228                 inb(0x1F2);
 229                 inb(0x3F6);
 230                 inb(0x3F6);
 231                 inb(0x1F2);
 232                 inb(0x1F2);
 233         }
 234         while((inb(0x1F2) & 0x80) && --tries);
 235
 236         local_irq_restore(flags);
 237
 238         outb(inb(0x1F4) & 0x07, 0x1F4);
 239
 240         rt = inb(0x1F3);
 241         rt &= 0x07 << (3 * adev->devno);
 242         if (pio)
 243                 rt |= (1 + 3 * pio) << (3 * adev->devno);
 244
 245         udelay(100);
 246         outb(inb(0x1F2) | 0x01, 0x1F2);
 247         udelay(100);
 248         inb(0x1F5);
 249
 250 }
 251
 252 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
 253 {
 254         struct ata_port *ap = adev->ap;
 255         int slop = buflen & 3;
 256         unsigned long flags;
 257
 258         if (ata_id_has_dword_io(adev->id)) {
 259                 local_irq_save(flags);
 260
 261                 /* Perform the 32bit I/O synchronization sequence */
 262                 ioread8(ap->ioaddr.nsect_addr);
 263                 ioread8(ap->ioaddr.nsect_addr);
 264                 ioread8(ap->ioaddr.nsect_addr);
 265
 266                 /* Now the data */
 267
 268                 if (write_data)
 269                         iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 270                 else
 271                         ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 272
 273                 if (unlikely(slop)) {
 274                         u32 pad;
 275                         if (write_data) {
 276                                 memcpy(&pad, buf + buflen - slop, slop);
 277                                 pad = le32_to_cpu(pad);
 278                                 iowrite32(pad, ap->ioaddr.data_addr);
 279                         } else {
 280                                 pad = ioread32(ap->ioaddr.data_addr);
 281                                 pad = cpu_to_le16(pad);
 282                                 memcpy(buf + buflen - slop, &pad, slop);
 283                         }
 284                 }
 285                 local_irq_restore(flags);
 286         }
 287         else
 288                 ata_data_xfer_noirq(adev, buf, buflen, write_data);
 289 }
 290
 291 static struct ata_port_operations pdc20230_port_ops = {
 292         .set_piomode    = pdc20230_set_piomode,
 293
 294         .port_disable   = ata_port_disable,
 295         .tf_load        = ata_tf_load,
 296         .tf_read        = ata_tf_read,
 297         .check_status   = ata_check_status,
 298         .exec_command   = ata_exec_command,
 299         .dev_select     = ata_std_dev_select,
 300
 301         .error_handler  = ata_bmdma_error_handler,
 302
 303         .qc_prep        = ata_qc_prep,
 304         .qc_issue       = ata_qc_issue_prot,
 305
 306         .data_xfer      = pdc_data_xfer_vlb,
 307
 308         .irq_handler    = ata_interrupt,
 309         .irq_clear      = ata_bmdma_irq_clear,
 310         .irq_on         = ata_irq_on,
 311         .irq_ack        = ata_irq_ack,
 312
 313         .port_start     = ata_port_start,
 314 };
 315
 316 /*
 317  *      Holtek 6560A support
 318  *
 319  *      This controller supports PIO0 to PIO2 (no IORDY even though higher timings
 320  *      can be loaded).
 321  */
 322
 323 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 324 {
 325         u8 active, recover;
 326         struct ata_timing t;
 327
 328         /* Get the timing data in cycles. For now play safe at 50Mhz */
 329         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 330
 331         active = FIT(t.active, 2, 15);
 332         recover = FIT(t.recover, 4, 15);
 333
 334         inb(0x3E6);
 335         inb(0x3E6);
 336         inb(0x3E6);
 337         inb(0x3E6);
 338
 339         iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 340         ioread8(ap->ioaddr.status_addr);
 341 }
 342
 343 static struct ata_port_operations ht6560a_port_ops = {
 344         .set_piomode    = ht6560a_set_piomode,
 345
 346         .port_disable   = ata_port_disable,
 347         .tf_load        = ata_tf_load,
 348         .tf_read        = ata_tf_read,
 349         .check_status   = ata_check_status,
 350         .exec_command   = ata_exec_command,
 351         .dev_select     = ata_std_dev_select,
 352
 353         .error_handler  = ata_bmdma_error_handler,
 354
 355         .qc_prep        = ata_qc_prep,
 356         .qc_issue       = ata_qc_issue_prot,
 357
 358         .data_xfer      = ata_data_xfer,        /* Check vlb/noirq */
 359
 360         .irq_handler    = ata_interrupt,
 361         .irq_clear      = ata_bmdma_irq_clear,
 362         .irq_on         = ata_irq_on,
 363         .irq_ack        = ata_irq_ack,
 364
 365         .port_start     = ata_port_start,
 366 };
 367
 368 /*
 369  *      Holtek 6560B support
 370  *
 371  *      This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
 372  *      unless we see an ATAPI device in which case we force it off.
 373  *
 374  *      FIXME: need to implement 2nd channel support.
 375  */
 376
 377 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
 378 {
 379         u8 active, recover;
 380         struct ata_timing t;
 381
 382         /* Get the timing data in cycles. For now play safe at 50Mhz */
 383         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 384
 385         active = FIT(t.active, 2, 15);
 386         recover = FIT(t.recover, 2, 16);
 387         recover &= 0x15;
 388
 389         inb(0x3E6);
 390         inb(0x3E6);
 391         inb(0x3E6);
 392         inb(0x3E6);
 393
 394         iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 395
 396         if (adev->class != ATA_DEV_ATA) {
 397                 u8 rconf = inb(0x3E6);
 398                 if (rconf & 0x24) {
 399                         rconf &= ~ 0x24;
 400                         outb(rconf, 0x3E6);
 401                 }
 402         }
 403         ioread8(ap->ioaddr.status_addr);
 404 }
 405
 406 static struct ata_port_operations ht6560b_port_ops = {
 407         .set_piomode    = ht6560b_set_piomode,
 408
 409         .port_disable   = ata_port_disable,
 410         .tf_load        = ata_tf_load,
 411         .tf_read        = ata_tf_read,
 412         .check_status   = ata_check_status,
 413         .exec_command   = ata_exec_command,
 414         .dev_select     = ata_std_dev_select,
 415
 416         .error_handler  = ata_bmdma_error_handler,
 417
 418         .qc_prep        = ata_qc_prep,
 419         .qc_issue       = ata_qc_issue_prot,
 420
 421         .data_xfer      = ata_data_xfer,        /* FIXME: Check 32bit and noirq */
 422
 423         .irq_handler    = ata_interrupt,
 424         .irq_clear      = ata_bmdma_irq_clear,
 425         .irq_on         = ata_irq_on,
 426         .irq_ack        = ata_irq_ack,
 427
 428         .port_start     = ata_port_start,
 429 };
 430
 431 /*
 432  *      Opti core chipset helpers
 433  */
 434
 435 /**
 436  *      opti_syscfg     -       read OPTI chipset configuration
 437  *      @reg: Configuration register to read
 438  *
 439  *      Returns the value of an OPTI system board configuration register.
 440  */
 441
 442 static u8 opti_syscfg(u8 reg)
 443 {
 444         unsigned long flags;
 445         u8 r;
 446
 447         /* Uniprocessor chipset and must force cycles adjancent */
 448         local_irq_save(flags);
 449         outb(reg, 0x22);
 450         r = inb(0x24);
 451         local_irq_restore(flags);
 452         return r;
 453 }
 454
 455 /*
 456  *      Opti 82C611A
 457  *
 458  *      This controller supports PIO0 to PIO3.
 459  */
 460
 461 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 462 {
 463         u8 active, recover, setup;
 464         struct ata_timing t;
 465         struct ata_device *pair = ata_dev_pair(adev);
 466         int clock;
 467         int khz[4] = { 50000, 40000, 33000, 25000 };
 468         u8 rc;
 469
 470         /* Enter configuration mode */
 471         ioread16(ap->ioaddr.error_addr);
 472         ioread16(ap->ioaddr.error_addr);
 473         iowrite8(3, ap->ioaddr.nsect_addr);
 474
 475         /* Read VLB clock strapping */
 476         clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
 477
 478         /* Get the timing data in cycles */
 479         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 480
 481         /* Setup timing is shared */
 482         if (pair) {
 483                 struct ata_timing tp;
 484                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 485
 486                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 487         }
 488
 489         active = FIT(t.active, 2, 17) - 2;
 490         recover = FIT(t.recover, 1, 16) - 1;
 491         setup = FIT(t.setup, 1, 4) - 1;
 492
 493         /* Select the right timing bank for write timing */
 494         rc = ioread8(ap->ioaddr.lbal_addr);
 495         rc &= 0x7F;
 496         rc |= (adev->devno << 7);
 497         iowrite8(rc, ap->ioaddr.lbal_addr);
 498
 499         /* Write the timings */
 500         iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 501
 502         /* Select the right bank for read timings, also
 503            load the shared timings for address */
 504         rc = ioread8(ap->ioaddr.device_addr);
 505         rc &= 0xC0;
 506         rc |= adev->devno;      /* Index select */
 507         rc |= (setup << 4) | 0x04;
 508         iowrite8(rc, ap->ioaddr.device_addr);
 509
 510         /* Load the read timings */
 511         iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 512
 513         /* Ensure the timing register mode is right */
 514         rc = ioread8(ap->ioaddr.lbal_addr);
 515         rc &= 0x73;
 516         rc |= 0x84;
 517         iowrite8(rc, ap->ioaddr.lbal_addr);
 518
 519         /* Exit command mode */
 520         iowrite8(0x83,  ap->ioaddr.nsect_addr);
 521 }
 522
 523
 524 static struct ata_port_operations opti82c611a_port_ops = {
 525         .set_piomode    = opti82c611a_set_piomode,
 526
 527         .port_disable   = ata_port_disable,
 528         .tf_load        = ata_tf_load,
 529         .tf_read        = ata_tf_read,
 530         .check_status   = ata_check_status,
 531         .exec_command   = ata_exec_command,
 532         .dev_select     = ata_std_dev_select,
 533
 534         .error_handler  = ata_bmdma_error_handler,
 535
 536         .qc_prep        = ata_qc_prep,
 537         .qc_issue       = ata_qc_issue_prot,
 538
 539         .data_xfer      = ata_data_xfer,
 540
 541         .irq_handler    = ata_interrupt,
 542         .irq_clear      = ata_bmdma_irq_clear,
 543         .irq_on         = ata_irq_on,
 544         .irq_ack        = ata_irq_ack,
 545
 546         .port_start     = ata_port_start,
 547 };
 548
 549 /*
 550  *      Opti 82C465MV
 551  *
 552  *      This controller supports PIO0 to PIO3. Unlike the 611A the MVB
 553  *      version is dual channel but doesn't have a lot of unique registers.
 554  */
 555
 556 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 557 {
 558         u8 active, recover, setup;
 559         struct ata_timing t;
 560         struct ata_device *pair = ata_dev_pair(adev);
 561         int clock;
 562         int khz[4] = { 50000, 40000, 33000, 25000 };
 563         u8 rc;
 564         u8 sysclk;
 565
 566         /* Get the clock */
 567         sysclk = opti_syscfg(0xAC) & 0xC0;      /* BIOS set */
 568
 569         /* Enter configuration mode */
 570         ioread16(ap->ioaddr.error_addr);
 571         ioread16(ap->ioaddr.error_addr);
 572         iowrite8(3, ap->ioaddr.nsect_addr);
 573
 574         /* Read VLB clock strapping */
 575         clock = 1000000000 / khz[sysclk];
 576
 577         /* Get the timing data in cycles */
 578         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 579
 580         /* Setup timing is shared */
 581         if (pair) {
 582                 struct ata_timing tp;
 583                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 584
 585                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 586         }
 587
 588         active = FIT(t.active, 2, 17) - 2;
 589         recover = FIT(t.recover, 1, 16) - 1;
 590         setup = FIT(t.setup, 1, 4) - 1;
 591
 592         /* Select the right timing bank for write timing */
 593         rc = ioread8(ap->ioaddr.lbal_addr);
 594         rc &= 0x7F;
 595         rc |= (adev->devno << 7);
 596         iowrite8(rc, ap->ioaddr.lbal_addr);
 597
 598         /* Write the timings */
 599         iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 600
 601         /* Select the right bank for read timings, also
 602            load the shared timings for address */
 603         rc = ioread8(ap->ioaddr.device_addr);
 604         rc &= 0xC0;
 605         rc |= adev->devno;      /* Index select */
 606         rc |= (setup << 4) | 0x04;
 607         iowrite8(rc, ap->ioaddr.device_addr);
 608
 609         /* Load the read timings */
 610         iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 611
 612         /* Ensure the timing register mode is right */
 613         rc = ioread8(ap->ioaddr.lbal_addr);
 614         rc &= 0x73;
 615         rc |= 0x84;
 616         iowrite8(rc, ap->ioaddr.lbal_addr);
 617
 618         /* Exit command mode */
 619         iowrite8(0x83,  ap->ioaddr.nsect_addr);
 620
 621         /* We need to know this for quad device on the MVB */
 622         ap->host->private_data = ap;
 623 }
 624
 625 /**
 626  *      opt82c465mv_qc_issue_prot       -       command issue
 627  *      @qc: command pending
 628  *
 629  *      Called when the libata layer is about to issue a command. We wrap
 630  *      this interface so that we can load the correct ATA timings. The
 631  *      MVB has a single set of timing registers and these are shared
 632  *      across channels. As there are two registers we really ought to
 633  *      track the last two used values as a sort of register window. For
 634  *      now we just reload on a channel switch. On the single channel
 635  *      setup this condition never fires so we do nothing extra.
 636  *
 637  *      FIXME: dual channel needs ->serialize support
 638  */
 639
 640 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
 641 {
 642         struct ata_port *ap = qc->ap;
 643         struct ata_device *adev = qc->dev;
 644
 645         /* If timings are set and for the wrong channel (2nd test is
 646            due to a libata shortcoming and will eventually go I hope) */
 647         if (ap->host->private_data != ap->host
 648             && ap->host->private_data != NULL)
 649                 opti82c46x_set_piomode(ap, adev);
 650
 651         return ata_qc_issue_prot(qc);
 652 }
 653
 654 static struct ata_port_operations opti82c46x_port_ops = {
 655         .set_piomode    = opti82c46x_set_piomode,
 656
 657         .port_disable   = ata_port_disable,
 658         .tf_load        = ata_tf_load,
 659         .tf_read        = ata_tf_read,
 660         .check_status   = ata_check_status,
 661         .exec_command   = ata_exec_command,
 662         .dev_select     = ata_std_dev_select,
 663
 664         .error_handler  = ata_bmdma_error_handler,
 665
 666         .qc_prep        = ata_qc_prep,
 667         .qc_issue       = opti82c46x_qc_issue_prot,
 668
 669         .data_xfer      = ata_data_xfer,
 670
 671         .irq_handler    = ata_interrupt,
 672         .irq_clear      = ata_bmdma_irq_clear,
 673         .irq_on         = ata_irq_on,
 674         .irq_ack        = ata_irq_ack,
 675
 676         .port_start     = ata_port_start,
 677 };
 678
 679
 680 /**
 681  *      legacy_init_one         -       attach a legacy interface
 682  *      @port: port number
 683  *      @io: I/O port start
 684  *      @ctrl: control port
 685  *      @irq: interrupt line
 686  *
 687  *      Register an ISA bus IDE interface. Such interfaces are PIO and we
 688  *      assume do not support IRQ sharing.
 689  */
 690
 691 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
 692 {
 693         struct legacy_data *ld = &legacy_data[nr_legacy_host];
 694         struct ata_probe_ent ae;
 695         struct platform_device *pdev;
 696         struct ata_port_operations *ops = &legacy_port_ops;
 697         void __iomem *io_addr, *ctrl_addr;
 698         int pio_modes = pio_mask;
 699         u32 mask = (1 << port);
 700         u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
 701         int ret;
 702
 703         pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
 704         if (IS_ERR(pdev))
 705                 return PTR_ERR(pdev);
 706
 707         ret = -EBUSY;
 708         if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
 709             devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
 710                 goto fail;
 711
 712         ret = -ENOMEM;
 713         io_addr = devm_ioport_map(&pdev->dev, io, 8);
 714         ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
 715         if (!io_addr || !ctrl_addr)
 716                 goto fail;
 717
 718         if (ht6560a & mask) {
 719                 ops = &ht6560a_port_ops;
 720                 pio_modes = 0x07;
 721                 iordy = ATA_FLAG_NO_IORDY;
 722         }
 723         if (ht6560b & mask) {
 724                 ops = &ht6560b_port_ops;
 725                 pio_modes = 0x1F;
 726         }
 727         if (opti82c611a & mask) {
 728                 ops = &opti82c611a_port_ops;
 729                 pio_modes = 0x0F;
 730         }
 731         if (opti82c46x & mask) {
 732                 ops = &opti82c46x_port_ops;
 733                 pio_modes = 0x0F;
 734         }
 735
 736         /* Probe for automatically detectable controllers */
 737
 738         if (io == 0x1F0 && ops == &legacy_port_ops) {
 739                 unsigned long flags;
 740
 741                 local_irq_save(flags);
 742
 743                 /* Probes */
 744                 inb(0x1F5);
 745                 outb(inb(0x1F2) | 0x80, 0x1F2);
 746                 inb(0x1F2);
 747                 inb(0x3F6);
 748                 inb(0x3F6);
 749                 inb(0x1F2);
 750                 inb(0x1F2);
 751
 752                 if ((inb(0x1F2) & 0x80) == 0) {
 753                         /* PDC20230c or 20630 ? */
 754                         printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
 755                                 pio_modes = 0x07;
 756                         ops = &pdc20230_port_ops;
 757                         iordy = ATA_FLAG_NO_IORDY;
 758                         udelay(100);
 759                         inb(0x1F5);
 760                 } else {
 761                         outb(0x55, 0x1F2);
 762                         inb(0x1F2);
 763                         inb(0x1F2);
 764                         if (inb(0x1F2) == 0x00) {
 765                                 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
 766                         }
 767                 }
 768                 local_irq_restore(flags);
 769         }
 770
 771
 772         /* Chip does mode setting by command snooping */
 773         if (ops == &legacy_port_ops && (autospeed & mask))
 774                 ops = &simple_port_ops;
 775
 776         memset(&ae, 0, sizeof(struct ata_probe_ent));
 777         INIT_LIST_HEAD(&ae.node);
 778         ae.dev = &pdev->dev;
 779         ae.port_ops = ops;
 780         ae.sht = &legacy_sht;
 781         ae.n_ports = 1;
 782         ae.pio_mask = pio_modes;
 783         ae.irq = irq;
 784         ae.irq_flags = 0;
 785         ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST|iordy;
 786         ae.port[0].cmd_addr = io_addr;
 787         ae.port[0].altstatus_addr = ctrl_addr;
 788         ae.port[0].ctl_addr = ctrl_addr;
 789         ata_std_ports(&ae.port[0]);
 790         ae.private_data = ld;
 791
 792         ret = -ENODEV;
 793         if (!ata_device_add(&ae))
 794                 goto fail;
 795
 796         legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
 797         ld->platform_dev = pdev;
 798         return 0;
 799
 800 fail:
 801         platform_device_unregister(pdev);
 802         return ret;
 803 }
 804
 805 /**
 806  *      legacy_check_special_cases      -       ATA special cases
 807  *      @p: PCI device to check
 808  *      @master: set this if we find an ATA master
 809  *      @master: set this if we find an ATA secondary
 810  *
 811  *      A small number of vendors implemented early PCI ATA interfaces on bridge logic
 812  *      without the ATA interface being PCI visible. Where we have a matching PCI driver
 813  *      we must skip the relevant device here. If we don't know about it then the legacy
 814  *      driver is the right driver anyway.
 815  */
 816
 817 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
 818 {
 819         /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
 820         if (p->vendor == 0x1078 && p->device == 0x0000) {
 821                 *primary = *secondary = 1;
 822                 return;
 823         }
 824         /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
 825         if (p->vendor == 0x1078 && p->device == 0x0002) {
 826                 *primary = *secondary = 1;
 827                 return;
 828         }
 829         /* Intel MPIIX - PIO ATA on non PCI side of bridge */
 830         if (p->vendor == 0x8086 && p->device == 0x1234) {
 831                 u16 r;
 832                 pci_read_config_word(p, 0x6C, &r);
 833                 if (r & 0x8000) {       /* ATA port enabled */
 834                         if (r & 0x4000)
 835                                 *secondary = 1;
 836                         else
 837                                 *primary = 1;
 838                 }
 839                 return;
 840         }
 841 }
 842
 843
 844 /**
 845  *      legacy_init             -       attach legacy interfaces
 846  *
 847  *      Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
 848  *      Right now we do not scan the ide0 and ide1 address but should do so
 849  *      for non PCI systems or systems with no PCI IDE legacy mode devices.
 850  *      If you fix that note there are special cases to consider like VLB
 851  *      drivers and CS5510/20.
 852  */
 853
 854 static __init int legacy_init(void)
 855 {
 856         int i;
 857         int ct = 0;
 858         int primary = 0;
 859         int secondary = 0;
 860         int last_port = NR_HOST;
 861
 862         struct pci_dev *p = NULL;
 863
 864         for_each_pci_dev(p) {
 865                 int r;
 866                 /* Check for any overlap of the system ATA mappings. Native mode controllers
 867                    stuck on these addresses or some devices in 'raid' mode won't be found by
 868                    the storage class test */
 869                 for (r = 0; r < 6; r++) {
 870                         if (pci_resource_start(p, r) == 0x1f0)
 871                                 primary = 1;
 872                         if (pci_resource_start(p, r) == 0x170)
 873                                 secondary = 1;
 874                 }
 875                 /* Check for special cases */
 876                 legacy_check_special_cases(p, &primary, &secondary);
 877
 878                 /* If PCI bus is present then don't probe for tertiary legacy ports */
 879                 if (probe_all == 0)
 880                         last_port = 2;
 881         }
 882
 883         /* If an OPTI 82C46X is present find out where the channels are */
 884         if (opti82c46x) {
 885                 static const char *optis[4] = {
 886                         "3/463MV", "5MV",
 887                         "5MVA", "5MVB"
 888                 };
 889                 u8 chans = 1;
 890                 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
 891
 892                 opti82c46x = 3; /* Assume master and slave first */
 893                 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
 894                 if (ctrl == 3)
 895                         chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
 896                 ctrl = opti_syscfg(0xAC);
 897                 /* Check enabled and this port is the 465MV port. On the
 898                    MVB we may have two channels */
 899                 if (ctrl & 8) {
 900                         if (ctrl & 4)
 901                                 opti82c46x = 2; /* Slave */
 902                         else
 903                                 opti82c46x = 1; /* Master */
 904                         if (chans == 2)
 905                                 opti82c46x = 3; /* Master and Slave */
 906                 }       /* Slave only */
 907                 else if (chans == 1)
 908                         opti82c46x = 1;
 909         }
 910
 911         for (i = 0; i < last_port; i++) {
 912                 /* Skip primary if we have seen a PCI one */
 913                 if (i == 0 && primary == 1)
 914                         continue;
 915                 /* Skip secondary if we have seen a PCI one */
 916                 if (i == 1 && secondary == 1)
 917                         continue;
 918                 if (legacy_init_one(i, legacy_port[i],
 919                                    legacy_port[i] + 0x0206,
 920                                    legacy_irq[i]) == 0)
 921                         ct++;
 922         }
 923         if (ct != 0)
 924                 return 0;
 925         return -ENODEV;
 926 }
 927
 928 static __exit void legacy_exit(void)
 929 {
 930         int i;
 931
 932         for (i = 0; i < nr_legacy_host; i++) {
 933                 struct legacy_data *ld = &legacy_data[i];
 934
 935                 ata_host_detach(legacy_host[i]);
 936                 platform_device_unregister(ld->platform_dev);
 937                 if (ld->timing)
 938                         release_region(ld->timing, 2);
 939         }
 940 }
 941
 942 MODULE_AUTHOR("Alan Cox");
 943 MODULE_DESCRIPTION("low-level driver for legacy ATA");
 944 MODULE_LICENSE("GPL");
 945 MODULE_VERSION(DRV_VERSION);
 946
 947 module_param(probe_all, int, 0);
 948 module_param(autospeed, int, 0);
 949 module_param(ht6560a, int, 0);
 950 module_param(ht6560b, int, 0);
 951 module_param(opti82c611a, int, 0);
 952 module_param(opti82c46x, int, 0);
 953 module_param(pio_mask, int, 0);
 954 module_param(iordy_mask, int, 0);
 955
 956 module_init(legacy_init);
 957 module_exit(legacy_exit);
 958