drivers/ata/pata_legacy.c

   1 /*
   2  *   pata-legacy.c - Legacy port PATA/SATA controller driver.
   3  *   Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2, or (at your option)
   8  *  any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; see the file COPYING.  If not, write to
  17  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *   An ATA driver for the legacy ATA ports.
  20  *
  21  *   Data Sources:
  22  *      Opti 82C465/82C611 support: Data sheets at opti-inc.com
  23  *      HT6560 series:
  24  *      Promise 20230/20620:
  25  *              http://www.ryston.cz/petr/vlb/pdc20230b.html
  26  *              http://www.ryston.cz/petr/vlb/pdc20230c.html
  27  *              http://www.ryston.cz/petr/vlb/pdc20630.html
  28  *
  29  *  Unsupported but docs exist:
  30  *      Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  31  *      Winbond W83759A
  32  *
  33  *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
  34  *  on PC class systems. There are three hybrid devices that are exceptions
  35  *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  36  *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  37  *
  38  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  39  *  opti82c465mv/promise 20230c/20630
  40  *
  41  *  Use the autospeed and pio_mask options with:
  42  *      Appian ADI/2 aka CLPD7220 or AIC25VL01.
  43  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  44  *      Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  45  *      Winbond W83759A, Promise PDC20230-B
  46  *
  47  *  For now use autospeed and pio_mask as above with the W83759A. This may
  48  *  change.
  49  *
  50  *  TODO
  51  *      Merge existing pata_qdi driver
  52  *
  53  */
  54
  55 #include <linux/kernel.h>
  56 #include <linux/module.h>
  57 #include <linux/pci.h>
  58 #include <linux/init.h>
  59 #include <linux/blkdev.h>
  60 #include <linux/delay.h>
  61 #include <scsi/scsi_host.h>
  62 #include <linux/ata.h>
  63 #include <linux/libata.h>
  64 #include <linux/platform_device.h>
  65
  66 #define DRV_NAME "pata_legacy"
  67 #define DRV_VERSION "0.5.3"
  68
  69 #define NR_HOST 6
  70
  71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
  72 static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
  73
  74 struct legacy_data {
  75         unsigned long timing;
  76         u8 clock[2];
  77         u8 last;
  78         int fast;
  79         struct platform_device *platform_dev;
  80
  81 };
  82
  83 static struct legacy_data legacy_data[NR_HOST];
  84 static struct ata_host *legacy_host[NR_HOST];
  85 static int nr_legacy_host;
  86
  87
  88 static int probe_all;                   /* Set to check all ISA port ranges */
  89 static int ht6560a;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  90 static int ht6560b;                     /* HT 6560A on primary 1, secondary 2, both 3 */
  91 static int opti82c611a;                 /* Opti82c611A on primary 1, secondary 2, both 3 */
  92 static int opti82c46x;          /* Opti 82c465MV present (pri/sec autodetect) */
  93 static int autospeed;                   /* Chip present which snoops speed changes */
  94 static int pio_mask = 0x1F;             /* PIO range for autospeed devices */
  95
  96 /**
  97  *      legacy_set_mode         -       mode setting
  98  *      @ap: IDE interface
  99  *      @unused: Device that failed when error is returned
 100  *
 101  *      Use a non standard set_mode function. We don't want to be tuned.
 102  *
 103  *      The BIOS configured everything. Our job is not to fiddle. Just use
 104  *      whatever PIO the hardware is using and leave it at that. When we
 105  *      get some kind of nice user driven API for control then we can
 106  *      expand on this as per hdparm in the base kernel.
 107  */
 108
 109 static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused)
 110 {
 111         int i;
 112
 113         for (i = 0; i < ATA_MAX_DEVICES; i++) {
 114                 struct ata_device *dev = &ap->device[i];
 115                 if (ata_dev_enabled(dev)) {
 116                         dev->pio_mode = XFER_PIO_0;
 117                         dev->xfer_mode = XFER_PIO_0;
 118                         dev->xfer_shift = ATA_SHIFT_PIO;
 119                         dev->flags |= ATA_DFLAG_PIO;
 120                 }
 121         }
 122         return 0;
 123 }
 124
 125 static struct scsi_host_template legacy_sht = {
 126         .module                 = THIS_MODULE,
 127         .name                   = DRV_NAME,
 128         .ioctl                  = ata_scsi_ioctl,
 129         .queuecommand           = ata_scsi_queuecmd,
 130         .can_queue              = ATA_DEF_QUEUE,
 131         .this_id                = ATA_SHT_THIS_ID,
 132         .sg_tablesize           = LIBATA_MAX_PRD,
 133         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 134         .emulated               = ATA_SHT_EMULATED,
 135         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 136         .proc_name              = DRV_NAME,
 137         .dma_boundary           = ATA_DMA_BOUNDARY,
 138         .slave_configure        = ata_scsi_slave_config,
 139         .slave_destroy          = ata_scsi_slave_destroy,
 140         .bios_param             = ata_std_bios_param,
 141 };
 142
 143 /*
 144  *      These ops are used if the user indicates the hardware
 145  *      snoops the commands to decide on the mode and handles the
 146  *      mode selection "magically" itself. Several legacy controllers
 147  *      do this. The mode range can be set if it is not 0x1F by setting
 148  *      pio_mask as well.
 149  */
 150
 151 static struct ata_port_operations simple_port_ops = {
 152         .port_disable   = ata_port_disable,
 153         .tf_load        = ata_tf_load,
 154         .tf_read        = ata_tf_read,
 155         .check_status   = ata_check_status,
 156         .exec_command   = ata_exec_command,
 157         .dev_select     = ata_std_dev_select,
 158
 159         .freeze         = ata_bmdma_freeze,
 160         .thaw           = ata_bmdma_thaw,
 161         .error_handler  = ata_bmdma_error_handler,
 162         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 163
 164         .qc_prep        = ata_qc_prep,
 165         .qc_issue       = ata_qc_issue_prot,
 166
 167         .data_xfer      = ata_data_xfer_noirq,
 168
 169         .irq_handler    = ata_interrupt,
 170         .irq_clear      = ata_bmdma_irq_clear,
 171         .irq_on         = ata_irq_on,
 172         .irq_ack        = ata_irq_ack,
 173
 174         .port_start     = ata_port_start,
 175 };
 176
 177 static struct ata_port_operations legacy_port_ops = {
 178         .set_mode       = legacy_set_mode,
 179
 180         .port_disable   = ata_port_disable,
 181         .tf_load        = ata_tf_load,
 182         .tf_read        = ata_tf_read,
 183         .check_status   = ata_check_status,
 184         .exec_command   = ata_exec_command,
 185         .dev_select     = ata_std_dev_select,
 186
 187         .error_handler  = ata_bmdma_error_handler,
 188
 189         .qc_prep        = ata_qc_prep,
 190         .qc_issue       = ata_qc_issue_prot,
 191
 192         .data_xfer      = ata_data_xfer_noirq,
 193
 194         .irq_handler    = ata_interrupt,
 195         .irq_clear      = ata_bmdma_irq_clear,
 196         .irq_on         = ata_irq_on,
 197         .irq_ack        = ata_irq_ack,
 198
 199         .port_start     = ata_port_start,
 200 };
 201
 202 /*
 203  *      Promise 20230C and 20620 support
 204  *
 205  *      This controller supports PIO0 to PIO2. We set PIO timings conservatively to
 206  *      allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
 207  *      controller and PIO'd to the host and not supported.
 208  */
 209
 210 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 211 {
 212         int tries = 5;
 213         int pio = adev->pio_mode - XFER_PIO_0;
 214         u8 rt;
 215         unsigned long flags;
 216
 217         /* Safe as UP only. Force I/Os to occur together */
 218
 219         local_irq_save(flags);
 220
 221         /* Unlock the control interface */
 222         do
 223         {
 224                 inb(0x1F5);
 225                 outb(inb(0x1F2) | 0x80, 0x1F2);
 226                 inb(0x1F2);
 227                 inb(0x3F6);
 228                 inb(0x3F6);
 229                 inb(0x1F2);
 230                 inb(0x1F2);
 231         }
 232         while((inb(0x1F2) & 0x80) && --tries);
 233
 234         local_irq_restore(flags);
 235
 236         outb(inb(0x1F4) & 0x07, 0x1F4);
 237
 238         rt = inb(0x1F3);
 239         rt &= 0x07 << (3 * adev->devno);
 240         if (pio)
 241                 rt |= (1 + 3 * pio) << (3 * adev->devno);
 242
 243         udelay(100);
 244         outb(inb(0x1F2) | 0x01, 0x1F2);
 245         udelay(100);
 246         inb(0x1F5);
 247
 248 }
 249
 250 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
 251 {
 252         struct ata_port *ap = adev->ap;
 253         int slop = buflen & 3;
 254         unsigned long flags;
 255
 256         if (ata_id_has_dword_io(adev->id)) {
 257                 local_irq_save(flags);
 258
 259                 /* Perform the 32bit I/O synchronization sequence */
 260                 ioread8(ap->ioaddr.nsect_addr);
 261                 ioread8(ap->ioaddr.nsect_addr);
 262                 ioread8(ap->ioaddr.nsect_addr);
 263
 264                 /* Now the data */
 265
 266                 if (write_data)
 267                         iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 268                 else
 269                         ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 270
 271                 if (unlikely(slop)) {
 272                         u32 pad;
 273                         if (write_data) {
 274                                 memcpy(&pad, buf + buflen - slop, slop);
 275                                 pad = le32_to_cpu(pad);
 276                                 iowrite32(pad, ap->ioaddr.data_addr);
 277                         } else {
 278                                 pad = ioread32(ap->ioaddr.data_addr);
 279                                 pad = cpu_to_le16(pad);
 280                                 memcpy(buf + buflen - slop, &pad, slop);
 281                         }
 282                 }
 283                 local_irq_restore(flags);
 284         }
 285         else
 286                 ata_data_xfer_noirq(adev, buf, buflen, write_data);
 287 }
 288
 289 static struct ata_port_operations pdc20230_port_ops = {
 290         .set_piomode    = pdc20230_set_piomode,
 291
 292         .port_disable   = ata_port_disable,
 293         .tf_load        = ata_tf_load,
 294         .tf_read        = ata_tf_read,
 295         .check_status   = ata_check_status,
 296         .exec_command   = ata_exec_command,
 297         .dev_select     = ata_std_dev_select,
 298
 299         .error_handler  = ata_bmdma_error_handler,
 300
 301         .qc_prep        = ata_qc_prep,
 302         .qc_issue       = ata_qc_issue_prot,
 303
 304         .data_xfer      = pdc_data_xfer_vlb,
 305
 306         .irq_handler    = ata_interrupt,
 307         .irq_clear      = ata_bmdma_irq_clear,
 308         .irq_on         = ata_irq_on,
 309         .irq_ack        = ata_irq_ack,
 310
 311         .port_start     = ata_port_start,
 312 };
 313
 314 /*
 315  *      Holtek 6560A support
 316  *
 317  *      This controller supports PIO0 to PIO2 (no IORDY even though higher timings
 318  *      can be loaded).
 319  */
 320
 321 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 322 {
 323         u8 active, recover;
 324         struct ata_timing t;
 325
 326         /* Get the timing data in cycles. For now play safe at 50Mhz */
 327         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 328
 329         active = FIT(t.active, 2, 15);
 330         recover = FIT(t.recover, 4, 15);
 331
 332         inb(0x3E6);
 333         inb(0x3E6);
 334         inb(0x3E6);
 335         inb(0x3E6);
 336
 337         iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 338         ioread8(ap->ioaddr.status_addr);
 339 }
 340
 341 static struct ata_port_operations ht6560a_port_ops = {
 342         .set_piomode    = ht6560a_set_piomode,
 343
 344         .port_disable   = ata_port_disable,
 345         .tf_load        = ata_tf_load,
 346         .tf_read        = ata_tf_read,
 347         .check_status   = ata_check_status,
 348         .exec_command   = ata_exec_command,
 349         .dev_select     = ata_std_dev_select,
 350
 351         .error_handler  = ata_bmdma_error_handler,
 352
 353         .qc_prep        = ata_qc_prep,
 354         .qc_issue       = ata_qc_issue_prot,
 355
 356         .data_xfer      = ata_data_xfer,        /* Check vlb/noirq */
 357
 358         .irq_handler    = ata_interrupt,
 359         .irq_clear      = ata_bmdma_irq_clear,
 360         .irq_on         = ata_irq_on,
 361         .irq_ack        = ata_irq_ack,
 362
 363         .port_start     = ata_port_start,
 364 };
 365
 366 /*
 367  *      Holtek 6560B support
 368  *
 369  *      This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
 370  *      unless we see an ATAPI device in which case we force it off.
 371  *
 372  *      FIXME: need to implement 2nd channel support.
 373  */
 374
 375 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
 376 {
 377         u8 active, recover;
 378         struct ata_timing t;
 379
 380         /* Get the timing data in cycles. For now play safe at 50Mhz */
 381         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 382
 383         active = FIT(t.active, 2, 15);
 384         recover = FIT(t.recover, 2, 16);
 385         recover &= 0x15;
 386
 387         inb(0x3E6);
 388         inb(0x3E6);
 389         inb(0x3E6);
 390         inb(0x3E6);
 391
 392         iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 393
 394         if (adev->class != ATA_DEV_ATA) {
 395                 u8 rconf = inb(0x3E6);
 396                 if (rconf & 0x24) {
 397                         rconf &= ~ 0x24;
 398                         outb(rconf, 0x3E6);
 399                 }
 400         }
 401         ioread8(ap->ioaddr.status_addr);
 402 }
 403
 404 static struct ata_port_operations ht6560b_port_ops = {
 405         .set_piomode    = ht6560b_set_piomode,
 406
 407         .port_disable   = ata_port_disable,
 408         .tf_load        = ata_tf_load,
 409         .tf_read        = ata_tf_read,
 410         .check_status   = ata_check_status,
 411         .exec_command   = ata_exec_command,
 412         .dev_select     = ata_std_dev_select,
 413
 414         .error_handler  = ata_bmdma_error_handler,
 415
 416         .qc_prep        = ata_qc_prep,
 417         .qc_issue       = ata_qc_issue_prot,
 418
 419         .data_xfer      = ata_data_xfer,        /* FIXME: Check 32bit and noirq */
 420
 421         .irq_handler    = ata_interrupt,
 422         .irq_clear      = ata_bmdma_irq_clear,
 423         .irq_on         = ata_irq_on,
 424         .irq_ack        = ata_irq_ack,
 425
 426         .port_start     = ata_port_start,
 427 };
 428
 429 /*
 430  *      Opti core chipset helpers
 431  */
 432
 433 /**
 434  *      opti_syscfg     -       read OPTI chipset configuration
 435  *      @reg: Configuration register to read
 436  *
 437  *      Returns the value of an OPTI system board configuration register.
 438  */
 439
 440 static u8 opti_syscfg(u8 reg)
 441 {
 442         unsigned long flags;
 443         u8 r;
 444
 445         /* Uniprocessor chipset and must force cycles adjancent */
 446         local_irq_save(flags);
 447         outb(reg, 0x22);
 448         r = inb(0x24);
 449         local_irq_restore(flags);
 450         return r;
 451 }
 452
 453 /*
 454  *      Opti 82C611A
 455  *
 456  *      This controller supports PIO0 to PIO3.
 457  */
 458
 459 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 460 {
 461         u8 active, recover, setup;
 462         struct ata_timing t;
 463         struct ata_device *pair = ata_dev_pair(adev);
 464         int clock;
 465         int khz[4] = { 50000, 40000, 33000, 25000 };
 466         u8 rc;
 467
 468         /* Enter configuration mode */
 469         ioread16(ap->ioaddr.error_addr);
 470         ioread16(ap->ioaddr.error_addr);
 471         iowrite8(3, ap->ioaddr.nsect_addr);
 472
 473         /* Read VLB clock strapping */
 474         clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
 475
 476         /* Get the timing data in cycles */
 477         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 478
 479         /* Setup timing is shared */
 480         if (pair) {
 481                 struct ata_timing tp;
 482                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 483
 484                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 485         }
 486
 487         active = FIT(t.active, 2, 17) - 2;
 488         recover = FIT(t.recover, 1, 16) - 1;
 489         setup = FIT(t.setup, 1, 4) - 1;
 490
 491         /* Select the right timing bank for write timing */
 492         rc = ioread8(ap->ioaddr.lbal_addr);
 493         rc &= 0x7F;
 494         rc |= (adev->devno << 7);
 495         iowrite8(rc, ap->ioaddr.lbal_addr);
 496
 497         /* Write the timings */
 498         iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 499
 500         /* Select the right bank for read timings, also
 501            load the shared timings for address */
 502         rc = ioread8(ap->ioaddr.device_addr);
 503         rc &= 0xC0;
 504         rc |= adev->devno;      /* Index select */
 505         rc |= (setup << 4) | 0x04;
 506         iowrite8(rc, ap->ioaddr.device_addr);
 507
 508         /* Load the read timings */
 509         iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 510
 511         /* Ensure the timing register mode is right */
 512         rc = ioread8(ap->ioaddr.lbal_addr);
 513         rc &= 0x73;
 514         rc |= 0x84;
 515         iowrite8(rc, ap->ioaddr.lbal_addr);
 516
 517         /* Exit command mode */
 518         iowrite8(0x83,  ap->ioaddr.nsect_addr);
 519 }
 520
 521
 522 static struct ata_port_operations opti82c611a_port_ops = {
 523         .set_piomode    = opti82c611a_set_piomode,
 524
 525         .port_disable   = ata_port_disable,
 526         .tf_load        = ata_tf_load,
 527         .tf_read        = ata_tf_read,
 528         .check_status   = ata_check_status,
 529         .exec_command   = ata_exec_command,
 530         .dev_select     = ata_std_dev_select,
 531
 532         .error_handler  = ata_bmdma_error_handler,
 533
 534         .qc_prep        = ata_qc_prep,
 535         .qc_issue       = ata_qc_issue_prot,
 536
 537         .data_xfer      = ata_data_xfer,
 538
 539         .irq_handler    = ata_interrupt,
 540         .irq_clear      = ata_bmdma_irq_clear,
 541         .irq_on         = ata_irq_on,
 542         .irq_ack        = ata_irq_ack,
 543
 544         .port_start     = ata_port_start,
 545 };
 546
 547 /*
 548  *      Opti 82C465MV
 549  *
 550  *      This controller supports PIO0 to PIO3. Unlike the 611A the MVB
 551  *      version is dual channel but doesn't have a lot of unique registers.
 552  */
 553
 554 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 555 {
 556         u8 active, recover, setup;
 557         struct ata_timing t;
 558         struct ata_device *pair = ata_dev_pair(adev);
 559         int clock;
 560         int khz[4] = { 50000, 40000, 33000, 25000 };
 561         u8 rc;
 562         u8 sysclk;
 563
 564         /* Get the clock */
 565         sysclk = opti_syscfg(0xAC) & 0xC0;      /* BIOS set */
 566
 567         /* Enter configuration mode */
 568         ioread16(ap->ioaddr.error_addr);
 569         ioread16(ap->ioaddr.error_addr);
 570         iowrite8(3, ap->ioaddr.nsect_addr);
 571
 572         /* Read VLB clock strapping */
 573         clock = 1000000000 / khz[sysclk];
 574
 575         /* Get the timing data in cycles */
 576         ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 577
 578         /* Setup timing is shared */
 579         if (pair) {
 580                 struct ata_timing tp;
 581                 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 582
 583                 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 584         }
 585
 586         active = FIT(t.active, 2, 17) - 2;
 587         recover = FIT(t.recover, 1, 16) - 1;
 588         setup = FIT(t.setup, 1, 4) - 1;
 589
 590         /* Select the right timing bank for write timing */
 591         rc = ioread8(ap->ioaddr.lbal_addr);
 592         rc &= 0x7F;
 593         rc |= (adev->devno << 7);
 594         iowrite8(rc, ap->ioaddr.lbal_addr);
 595
 596         /* Write the timings */
 597         iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 598
 599         /* Select the right bank for read timings, also
 600            load the shared timings for address */
 601         rc = ioread8(ap->ioaddr.device_addr);
 602         rc &= 0xC0;
 603         rc |= adev->devno;      /* Index select */
 604         rc |= (setup << 4) | 0x04;
 605         iowrite8(rc, ap->ioaddr.device_addr);
 606
 607         /* Load the read timings */
 608         iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 609
 610         /* Ensure the timing register mode is right */
 611         rc = ioread8(ap->ioaddr.lbal_addr);
 612         rc &= 0x73;
 613         rc |= 0x84;
 614         iowrite8(rc, ap->ioaddr.lbal_addr);
 615
 616         /* Exit command mode */
 617         iowrite8(0x83,  ap->ioaddr.nsect_addr);
 618
 619         /* We need to know this for quad device on the MVB */
 620         ap->host->private_data = ap;
 621 }
 622
 623 /**
 624  *      opt82c465mv_qc_issue_prot       -       command issue
 625  *      @qc: command pending
 626  *
 627  *      Called when the libata layer is about to issue a command. We wrap
 628  *      this interface so that we can load the correct ATA timings. The
 629  *      MVB has a single set of timing registers and these are shared
 630  *      across channels. As there are two registers we really ought to
 631  *      track the last two used values as a sort of register window. For
 632  *      now we just reload on a channel switch. On the single channel
 633  *      setup this condition never fires so we do nothing extra.
 634  *
 635  *      FIXME: dual channel needs ->serialize support
 636  */
 637
 638 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
 639 {
 640         struct ata_port *ap = qc->ap;
 641         struct ata_device *adev = qc->dev;
 642
 643         /* If timings are set and for the wrong channel (2nd test is
 644            due to a libata shortcoming and will eventually go I hope) */
 645         if (ap->host->private_data != ap->host
 646             && ap->host->private_data != NULL)
 647                 opti82c46x_set_piomode(ap, adev);
 648
 649         return ata_qc_issue_prot(qc);
 650 }
 651
 652 static struct ata_port_operations opti82c46x_port_ops = {
 653         .set_piomode    = opti82c46x_set_piomode,
 654
 655         .port_disable   = ata_port_disable,
 656         .tf_load        = ata_tf_load,
 657         .tf_read        = ata_tf_read,
 658         .check_status   = ata_check_status,
 659         .exec_command   = ata_exec_command,
 660         .dev_select     = ata_std_dev_select,
 661
 662         .error_handler  = ata_bmdma_error_handler,
 663
 664         .qc_prep        = ata_qc_prep,
 665         .qc_issue       = opti82c46x_qc_issue_prot,
 666
 667         .data_xfer      = ata_data_xfer,
 668
 669         .irq_handler    = ata_interrupt,
 670         .irq_clear      = ata_bmdma_irq_clear,
 671         .irq_on         = ata_irq_on,
 672         .irq_ack        = ata_irq_ack,
 673
 674         .port_start     = ata_port_start,
 675 };
 676
 677
 678 /**
 679  *      legacy_init_one         -       attach a legacy interface
 680  *      @port: port number
 681  *      @io: I/O port start
 682  *      @ctrl: control port
 683  *      @irq: interrupt line
 684  *
 685  *      Register an ISA bus IDE interface. Such interfaces are PIO and we
 686  *      assume do not support IRQ sharing.
 687  */
 688
 689 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
 690 {
 691         struct legacy_data *ld = &legacy_data[nr_legacy_host];
 692         struct ata_probe_ent ae;
 693         struct platform_device *pdev;
 694         struct ata_port_operations *ops = &legacy_port_ops;
 695         void __iomem *io_addr, *ctrl_addr;
 696         int pio_modes = pio_mask;
 697         u32 mask = (1 << port);
 698         int ret;
 699
 700         pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
 701         if (IS_ERR(pdev))
 702                 return PTR_ERR(pdev);
 703
 704         ret = -EBUSY;
 705         if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
 706             devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
 707                 goto fail;
 708
 709         ret = -ENOMEM;
 710         io_addr = devm_ioport_map(&pdev->dev, io, 8);
 711         ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
 712         if (!io_addr || !ctrl_addr)
 713                 goto fail;
 714
 715         if (ht6560a & mask) {
 716                 ops = &ht6560a_port_ops;
 717                 pio_modes = 0x07;
 718         }
 719         if (ht6560b & mask) {
 720                 ops = &ht6560b_port_ops;
 721                 pio_modes = 0x1F;
 722         }
 723         if (opti82c611a & mask) {
 724                 ops = &opti82c611a_port_ops;
 725                 pio_modes = 0x0F;
 726         }
 727         if (opti82c46x & mask) {
 728                 ops = &opti82c46x_port_ops;
 729                 pio_modes = 0x0F;
 730         }
 731
 732         /* Probe for automatically detectable controllers */
 733
 734         if (io == 0x1F0 && ops == &legacy_port_ops) {
 735                 unsigned long flags;
 736
 737                 local_irq_save(flags);
 738
 739                 /* Probes */
 740                 inb(0x1F5);
 741                 outb(inb(0x1F2) | 0x80, 0x1F2);
 742                 inb(0x1F2);
 743                 inb(0x3F6);
 744                 inb(0x3F6);
 745                 inb(0x1F2);
 746                 inb(0x1F2);
 747
 748                 if ((inb(0x1F2) & 0x80) == 0) {
 749                         /* PDC20230c or 20630 ? */
 750                         printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
 751                                 pio_modes = 0x07;
 752                         ops = &pdc20230_port_ops;
 753                         udelay(100);
 754                         inb(0x1F5);
 755                 } else {
 756                         outb(0x55, 0x1F2);
 757                         inb(0x1F2);
 758                         inb(0x1F2);
 759                         if (inb(0x1F2) == 0x00) {
 760                                 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
 761                         }
 762                 }
 763                 local_irq_restore(flags);
 764         }
 765
 766
 767         /* Chip does mode setting by command snooping */
 768         if (ops == &legacy_port_ops && (autospeed & mask))
 769                 ops = &simple_port_ops;
 770         memset(&ae, 0, sizeof(struct ata_probe_ent));
 771         INIT_LIST_HEAD(&ae.node);
 772         ae.dev = &pdev->dev;
 773         ae.port_ops = ops;
 774         ae.sht = &legacy_sht;
 775         ae.n_ports = 1;
 776         ae.pio_mask = pio_modes;
 777         ae.irq = irq;
 778         ae.irq_flags = 0;
 779         ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
 780         ae.port[0].cmd_addr = io_addr;
 781         ae.port[0].altstatus_addr = ctrl_addr;
 782         ae.port[0].ctl_addr = ctrl_addr;
 783         ata_std_ports(&ae.port[0]);
 784         ae.private_data = ld;
 785
 786         ret = -ENODEV;
 787         if (!ata_device_add(&ae))
 788                 goto fail;
 789
 790         legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
 791         ld->platform_dev = pdev;
 792         return 0;
 793
 794 fail:
 795         platform_device_unregister(pdev);
 796         return ret;
 797 }
 798
 799 /**
 800  *      legacy_check_special_cases      -       ATA special cases
 801  *      @p: PCI device to check
 802  *      @master: set this if we find an ATA master
 803  *      @master: set this if we find an ATA secondary
 804  *
 805  *      A small number of vendors implemented early PCI ATA interfaces on bridge logic
 806  *      without the ATA interface being PCI visible. Where we have a matching PCI driver
 807  *      we must skip the relevant device here. If we don't know about it then the legacy
 808  *      driver is the right driver anyway.
 809  */
 810
 811 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
 812 {
 813         /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
 814         if (p->vendor == 0x1078 && p->device == 0x0000) {
 815                 *primary = *secondary = 1;
 816                 return;
 817         }
 818         /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
 819         if (p->vendor == 0x1078 && p->device == 0x0002) {
 820                 *primary = *secondary = 1;
 821                 return;
 822         }
 823         /* Intel MPIIX - PIO ATA on non PCI side of bridge */
 824         if (p->vendor == 0x8086 && p->device == 0x1234) {
 825                 u16 r;
 826                 pci_read_config_word(p, 0x6C, &r);
 827                 if (r & 0x8000) {       /* ATA port enabled */
 828                         if (r & 0x4000)
 829                                 *secondary = 1;
 830                         else
 831                                 *primary = 1;
 832                 }
 833                 return;
 834         }
 835 }
 836
 837
 838 /**
 839  *      legacy_init             -       attach legacy interfaces
 840  *
 841  *      Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
 842  *      Right now we do not scan the ide0 and ide1 address but should do so
 843  *      for non PCI systems or systems with no PCI IDE legacy mode devices.
 844  *      If you fix that note there are special cases to consider like VLB
 845  *      drivers and CS5510/20.
 846  */
 847
 848 static __init int legacy_init(void)
 849 {
 850         int i;
 851         int ct = 0;
 852         int primary = 0;
 853         int secondary = 0;
 854         int last_port = NR_HOST;
 855
 856         struct pci_dev *p = NULL;
 857
 858         for_each_pci_dev(p) {
 859                 int r;
 860                 /* Check for any overlap of the system ATA mappings. Native mode controllers
 861                    stuck on these addresses or some devices in 'raid' mode won't be found by
 862                    the storage class test */
 863                 for (r = 0; r < 6; r++) {
 864                         if (pci_resource_start(p, r) == 0x1f0)
 865                                 primary = 1;
 866                         if (pci_resource_start(p, r) == 0x170)
 867                                 secondary = 1;
 868                 }
 869                 /* Check for special cases */
 870                 legacy_check_special_cases(p, &primary, &secondary);
 871
 872                 /* If PCI bus is present then don't probe for tertiary legacy ports */
 873                 if (probe_all == 0)
 874                         last_port = 2;
 875         }
 876
 877         /* If an OPTI 82C46X is present find out where the channels are */
 878         if (opti82c46x) {
 879                 static const char *optis[4] = {
 880                         "3/463MV", "5MV",
 881                         "5MVA", "5MVB"
 882                 };
 883                 u8 chans = 1;
 884                 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
 885
 886                 opti82c46x = 3; /* Assume master and slave first */
 887                 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
 888                 if (ctrl == 3)
 889                         chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
 890                 ctrl = opti_syscfg(0xAC);
 891                 /* Check enabled and this port is the 465MV port. On the
 892                    MVB we may have two channels */
 893                 if (ctrl & 8) {
 894                         if (ctrl & 4)
 895                                 opti82c46x = 2; /* Slave */
 896                         else
 897                                 opti82c46x = 1; /* Master */
 898                         if (chans == 2)
 899                                 opti82c46x = 3; /* Master and Slave */
 900                 }       /* Slave only */
 901                 else if (chans == 1)
 902                         opti82c46x = 1;
 903         }
 904
 905         for (i = 0; i < last_port; i++) {
 906                 /* Skip primary if we have seen a PCI one */
 907                 if (i == 0 && primary == 1)
 908                         continue;
 909                 /* Skip secondary if we have seen a PCI one */
 910                 if (i == 1 && secondary == 1)
 911                         continue;
 912                 if (legacy_init_one(i, legacy_port[i],
 913                                    legacy_port[i] + 0x0206,
 914                                    legacy_irq[i]) == 0)
 915                         ct++;
 916         }
 917         if (ct != 0)
 918                 return 0;
 919         return -ENODEV;
 920 }
 921
 922 static __exit void legacy_exit(void)
 923 {
 924         int i;
 925
 926         for (i = 0; i < nr_legacy_host; i++) {
 927                 struct legacy_data *ld = &legacy_data[i];
 928
 929                 ata_host_detach(legacy_host[i]);
 930                 platform_device_unregister(ld->platform_dev);
 931                 if (ld->timing)
 932                         release_region(ld->timing, 2);
 933         }
 934 }
 935
 936 MODULE_AUTHOR("Alan Cox");
 937 MODULE_DESCRIPTION("low-level driver for legacy ATA");
 938 MODULE_LICENSE("GPL");
 939 MODULE_VERSION(DRV_VERSION);
 940
 941 module_param(probe_all, int, 0);
 942 module_param(autospeed, int, 0);
 943 module_param(ht6560a, int, 0);
 944 module_param(ht6560b, int, 0);
 945 module_param(opti82c611a, int, 0);
 946 module_param(opti82c46x, int, 0);
 947 module_param(pio_mask, int, 0);
 948
 949 module_init(legacy_init);
 950 module_exit(legacy_exit);
 951