2 * pata_it821x.c - IT821x PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
11 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
13 * Copyright (C) 2004 Red Hat <alan@redhat.com>
15 * May be copied or modified under the terms of the GNU General Public License
16 * Based in part on the ITE vendor provided SCSI driver.
18 * Documentation available from
19 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
20 * Some other documents are NDA.
22 * The ITE8212 isn't exactly a standard IDE controller. It has two
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
26 * identify, none of the fancier commands apply. The IT8211 is identical
27 * in other respects but lacks the raid mode.
30 * o Rev 0x10 also requires master/slave hold the same DMA timings and
31 * cannot do ATAPI MWDMA.
32 * o The identify data for raid volumes lacks CHS info (technically ok)
33 * but also fails to set the LBA28 and other bits. We fix these in
34 * the IDE probe quirk code.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
36 * raid then the controller firmware dies
37 * o Smart mode without RAID doesn't clear all the necessary identify
38 * bits to reduce the command set to the one used
40 * This has a few impacts on the driver
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
43 * but we must watch the other limits and filter.
44 * - There are a few extra vendor commands that actually talk to the
45 * controller but only work PIO with no IRQ.
47 * Vendor areas of the identify block in smart mode are used for the
48 * timing and policy set up. Each HDD in raid mode also has a serial
49 * block on the disk. The hardware extra commands are get/set chip status,
50 * rebuild, get rebuild status.
52 * In Linux the driver supports pass through mode as if the device was
53 * just another IDE controller. If the smart mode is running then
54 * volumes are managed by the controller firmware and each IDE "disk"
55 * is a raid volume. Even more cute - the controller can do automated
56 * hotplug and rebuild.
58 * The pass through controller itself is a little demented. It has a
59 * flaw that it has a single set of PIO/MWDMA timings per channel so
60 * non UDMA devices restrict each others performance. It also has a
61 * single clock source per channel so mixed UDMA100/133 performance
62 * isn't perfect and we have to pick a clock. Thankfully none of this
63 * matters in smart mode. ATAPI DMA is not currently supported.
65 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
68 * - ATAPI and other speed filtering
69 * - RAID configuration ioctls
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/pci.h>
75 #include <linux/init.h>
76 #include <linux/blkdev.h>
77 #include <linux/delay.h>
78 #include <scsi/scsi_host.h>
79 #include <linux/libata.h>
82 #define DRV_NAME "pata_it821x"
83 #define DRV_VERSION "0.3.8"
87 unsigned int smart
:1, /* Are we in smart raid mode */
88 timing10
:1; /* Rev 0x10 */
89 u8 clock_mode
; /* 0, ATA_50 or ATA_66 */
90 u8 want
[2][2]; /* Mode/Pri log for master slave */
91 /* We need these for switching the clock when DMA goes on/off
92 The high byte is the 66Mhz timing */
93 u16 pio
[2]; /* Cached PIO values */
94 u16 mwdma
[2]; /* Cached MWDMA values */
95 u16 udma
[2]; /* Cached UDMA values (per drive) */
96 u16 last_device
; /* Master or slave loaded ? */
107 * We allow users to force the card into non raid mode without
108 * flashing the alternative BIOS. This is also necessary right now
109 * for embedded platforms that cannot run a PC BIOS but are using this
113 static int it8212_noraid
;
116 * it821x_program - program the PIO/MWDMA registers
118 * @adev: Device to program
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 * Program the PIO/MWDMA timing for this channel according to the
122 * current clock. These share the same register so are managed by
123 * the DMA start/stop sequence as with the old driver.
126 static void it821x_program(struct ata_port
*ap
, struct ata_device
*adev
, u16 timing
)
128 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
129 struct it821x_dev
*itdev
= ap
->private_data
;
130 int channel
= ap
->port_no
;
133 /* Program PIO/MWDMA timing bits */
134 if (itdev
->clock_mode
== ATA_66
)
137 conf
= timing
& 0xFF;
138 pci_write_config_byte(pdev
, 0x54 + 4 * channel
, conf
);
143 * it821x_program_udma - program the UDMA registers
145 * @adev: ATA device to update
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 * Program the UDMA timing for this drive according to the
149 * current clock. Handles the dual clocks and also knows about
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
151 * here and partly in start_dma.
154 static void it821x_program_udma(struct ata_port
*ap
, struct ata_device
*adev
, u16 timing
)
156 struct it821x_dev
*itdev
= ap
->private_data
;
157 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
158 int channel
= ap
->port_no
;
159 int unit
= adev
->devno
;
162 /* Program UDMA timing bits */
163 if (itdev
->clock_mode
== ATA_66
)
166 conf
= timing
& 0xFF;
167 if (itdev
->timing10
== 0)
168 pci_write_config_byte(pdev
, 0x56 + 4 * channel
+ unit
, conf
);
170 /* Early revision must be programmed for both together */
171 pci_write_config_byte(pdev
, 0x56 + 4 * channel
, conf
);
172 pci_write_config_byte(pdev
, 0x56 + 4 * channel
+ 1, conf
);
177 * it821x_clock_strategy
179 * @adev: ATA device being updated
181 * Select between the 50 and 66Mhz base clocks to get the best
182 * results for this interface.
185 static void it821x_clock_strategy(struct ata_port
*ap
, struct ata_device
*adev
)
187 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
188 struct it821x_dev
*itdev
= ap
->private_data
;
189 u8 unit
= adev
->devno
;
190 struct ata_device
*pair
= ata_dev_pair(adev
);
196 /* Look for the most wanted clocking */
197 if (itdev
->want
[0][0] > itdev
->want
[1][0]) {
198 clock
= itdev
->want
[0][1];
199 altclock
= itdev
->want
[1][1];
201 clock
= itdev
->want
[1][1];
202 altclock
= itdev
->want
[0][1];
205 /* Master doesn't care does the slave ? */
206 if (clock
== ATA_ANY
)
209 /* Nobody cares - keep the same clock */
210 if (clock
== ATA_ANY
)
213 if (clock
== itdev
->clock_mode
)
216 /* Load this into the controller */
218 itdev
->clock_mode
= ATA_66
;
220 itdev
->clock_mode
= ATA_50
;
223 pci_read_config_byte(pdev
, 0x50, &v
);
224 v
&= ~(1 << (1 + ap
->port_no
));
225 v
|= sel
<< (1 + ap
->port_no
);
226 pci_write_config_byte(pdev
, 0x50, v
);
229 * Reprogram the UDMA/PIO of the pair drive for the switch
230 * MWDMA will be dealt with by the dma switcher
232 if (pair
&& itdev
->udma
[1-unit
] != UDMA_OFF
) {
233 it821x_program_udma(ap
, pair
, itdev
->udma
[1-unit
]);
234 it821x_program(ap
, pair
, itdev
->pio
[1-unit
]);
237 * Reprogram the UDMA/PIO of our drive for the switch.
238 * MWDMA will be dealt with by the dma switcher
240 if (itdev
->udma
[unit
] != UDMA_OFF
) {
241 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
242 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
247 * it821x_passthru_set_piomode - set PIO mode data
251 * Configure for PIO mode. This is complicated as the register is
252 * shared by PIO and MWDMA and for both channels.
255 static void it821x_passthru_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
257 /* Spec says 89 ref driver uses 88 */
258 static const u16 pio
[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
259 static const u8 pio_want
[] = { ATA_66
, ATA_66
, ATA_66
, ATA_66
, ATA_ANY
};
261 struct it821x_dev
*itdev
= ap
->private_data
;
262 int unit
= adev
->devno
;
263 int mode_wanted
= adev
->pio_mode
- XFER_PIO_0
;
265 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
266 itdev
->want
[unit
][1] = pio_want
[mode_wanted
];
267 itdev
->want
[unit
][0] = 1; /* PIO is lowest priority */
268 itdev
->pio
[unit
] = pio
[mode_wanted
];
269 it821x_clock_strategy(ap
, adev
);
270 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
274 * it821x_passthru_set_dmamode - set initial DMA mode data
278 * Set up the DMA modes. The actions taken depend heavily on the mode
279 * to use. If UDMA is used as is hopefully the usual case then the
280 * timing register is private and we need only consider the clock. If
281 * we are using MWDMA then we have to manage the setting ourself as
282 * we switch devices and mode.
285 static void it821x_passthru_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
287 static const u16 dma
[] = { 0x8866, 0x3222, 0x3121 };
288 static const u8 mwdma_want
[] = { ATA_ANY
, ATA_66
, ATA_ANY
};
289 static const u16 udma
[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
290 static const u8 udma_want
[] = { ATA_ANY
, ATA_50
, ATA_ANY
, ATA_66
, ATA_66
, ATA_50
, ATA_66
};
292 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
293 struct it821x_dev
*itdev
= ap
->private_data
;
294 int channel
= ap
->port_no
;
295 int unit
= adev
->devno
;
298 if (adev
->dma_mode
>= XFER_UDMA_0
) {
299 int mode_wanted
= adev
->dma_mode
- XFER_UDMA_0
;
301 itdev
->want
[unit
][1] = udma_want
[mode_wanted
];
302 itdev
->want
[unit
][0] = 3; /* UDMA is high priority */
303 itdev
->mwdma
[unit
] = MWDMA_OFF
;
304 itdev
->udma
[unit
] = udma
[mode_wanted
];
305 if (mode_wanted
>= 5)
306 itdev
->udma
[unit
] |= 0x8080; /* UDMA 5/6 select on */
308 /* UDMA on. Again revision 0x10 must do the pair */
309 pci_read_config_byte(pdev
, 0x50, &conf
);
311 conf
&= channel
? 0x9F: 0xE7;
313 conf
&= ~ (1 << (3 + 2 * channel
+ unit
));
314 pci_write_config_byte(pdev
, 0x50, conf
);
315 it821x_clock_strategy(ap
, adev
);
316 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
318 int mode_wanted
= adev
->dma_mode
- XFER_MW_DMA_0
;
320 itdev
->want
[unit
][1] = mwdma_want
[mode_wanted
];
321 itdev
->want
[unit
][0] = 2; /* MWDMA is low priority */
322 itdev
->mwdma
[unit
] = dma
[mode_wanted
];
323 itdev
->udma
[unit
] = UDMA_OFF
;
325 /* UDMA bits off - Revision 0x10 do them in pairs */
326 pci_read_config_byte(pdev
, 0x50, &conf
);
328 conf
|= channel
? 0x60: 0x18;
330 conf
|= 1 << (3 + 2 * channel
+ unit
);
331 pci_write_config_byte(pdev
, 0x50, conf
);
332 it821x_clock_strategy(ap
, adev
);
337 * it821x_passthru_dma_start - DMA start callback
338 * @qc: Command in progress
340 * Usually drivers set the DMA timing at the point the set_dmamode call
341 * is made. IT821x however requires we load new timings on the
342 * transitions in some cases.
345 static void it821x_passthru_bmdma_start(struct ata_queued_cmd
*qc
)
347 struct ata_port
*ap
= qc
->ap
;
348 struct ata_device
*adev
= qc
->dev
;
349 struct it821x_dev
*itdev
= ap
->private_data
;
350 int unit
= adev
->devno
;
352 if (itdev
->mwdma
[unit
] != MWDMA_OFF
)
353 it821x_program(ap
, adev
, itdev
->mwdma
[unit
]);
354 else if (itdev
->udma
[unit
] != UDMA_OFF
&& itdev
->timing10
)
355 it821x_program_udma(ap
, adev
, itdev
->udma
[unit
]);
360 * it821x_passthru_dma_stop - DMA stop callback
363 * We loaded new timings in dma_start, as a result we need to restore
364 * the PIO timings in dma_stop so that the next command issue gets the
365 * right clock values.
368 static void it821x_passthru_bmdma_stop(struct ata_queued_cmd
*qc
)
370 struct ata_port
*ap
= qc
->ap
;
371 struct ata_device
*adev
= qc
->dev
;
372 struct it821x_dev
*itdev
= ap
->private_data
;
373 int unit
= adev
->devno
;
376 if (itdev
->mwdma
[unit
] != MWDMA_OFF
)
377 it821x_program(ap
, adev
, itdev
->pio
[unit
]);
382 * it821x_passthru_dev_select - Select master/slave
384 * @device: Device number (not pointer)
386 * Device selection hook. If necessary perform clock switching
389 static void it821x_passthru_dev_select(struct ata_port
*ap
,
392 struct it821x_dev
*itdev
= ap
->private_data
;
393 if (itdev
&& device
!= itdev
->last_device
) {
394 struct ata_device
*adev
= &ap
->link
.device
[device
];
395 it821x_program(ap
, adev
, itdev
->pio
[adev
->devno
]);
396 itdev
->last_device
= device
;
398 ata_std_dev_select(ap
, device
);
402 * it821x_smart_qc_issue_prot - wrap qc issue prot
405 * Wrap the command issue sequence for the IT821x. We need to
406 * perform out own device selection timing loads before the
407 * usual happenings kick off
410 static unsigned int it821x_smart_qc_issue_prot(struct ata_queued_cmd
*qc
)
412 switch(qc
->tf
.command
)
414 /* Commands the firmware supports */
416 case ATA_CMD_READ_EXT
:
418 case ATA_CMD_WRITE_EXT
:
419 case ATA_CMD_PIO_READ
:
420 case ATA_CMD_PIO_READ_EXT
:
421 case ATA_CMD_PIO_WRITE
:
422 case ATA_CMD_PIO_WRITE_EXT
:
423 case ATA_CMD_READ_MULTI
:
424 case ATA_CMD_READ_MULTI_EXT
:
425 case ATA_CMD_WRITE_MULTI
:
426 case ATA_CMD_WRITE_MULTI_EXT
:
428 /* Arguably should just no-op this one */
429 case ATA_CMD_SET_FEATURES
:
430 return ata_qc_issue_prot(qc
);
432 printk(KERN_DEBUG
"it821x: can't process command 0x%02X\n", qc
->tf
.command
);
437 * it821x_passthru_qc_issue_prot - wrap qc issue prot
440 * Wrap the command issue sequence for the IT821x. We need to
441 * perform out own device selection timing loads before the
442 * usual happenings kick off
445 static unsigned int it821x_passthru_qc_issue_prot(struct ata_queued_cmd
*qc
)
447 it821x_passthru_dev_select(qc
->ap
, qc
->dev
->devno
);
448 return ata_qc_issue_prot(qc
);
452 * it821x_smart_set_mode - mode setting
453 * @link: interface to set up
454 * @unused: device that failed (error only)
456 * Use a non standard set_mode function. We don't want to be tuned.
457 * The BIOS configured everything. Our job is not to fiddle. We
458 * read the dma enabled bits from the PCI configuration of the device
462 static int it821x_smart_set_mode(struct ata_link
*link
, struct ata_device
**unused
)
464 struct ata_device
*dev
;
466 ata_link_for_each_dev(dev
, link
) {
467 if (ata_dev_enabled(dev
)) {
468 /* We don't really care */
469 dev
->pio_mode
= XFER_PIO_0
;
470 dev
->dma_mode
= XFER_MW_DMA_0
;
471 /* We do need the right mode information for DMA or PIO
472 and this comes from the current configuration flags */
473 if (ata_id_has_dma(dev
->id
)) {
474 ata_dev_printk(dev
, KERN_INFO
, "configured for DMA\n");
475 dev
->xfer_mode
= XFER_MW_DMA_0
;
476 dev
->xfer_shift
= ATA_SHIFT_MWDMA
;
477 dev
->flags
&= ~ATA_DFLAG_PIO
;
479 ata_dev_printk(dev
, KERN_INFO
, "configured for PIO\n");
480 dev
->xfer_mode
= XFER_PIO_0
;
481 dev
->xfer_shift
= ATA_SHIFT_PIO
;
482 dev
->flags
|= ATA_DFLAG_PIO
;
490 * it821x_dev_config - Called each device identify
491 * @adev: Device that has just been identified
493 * Perform the initial setup needed for each device that is chip
494 * special. In our case we need to lock the sector count to avoid
495 * blowing the brains out of the firmware with large LBA48 requests
497 * FIXME: When FUA appears we need to block FUA too. And SMART and
498 * basically we need to filter commands for this chip.
501 static void it821x_dev_config(struct ata_device
*adev
)
503 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
505 ata_id_c_string(adev
->id
, model_num
, ATA_ID_PROD
, sizeof(model_num
));
507 if (adev
->max_sectors
> 255)
508 adev
->max_sectors
= 255;
510 if (strstr(model_num
, "Integrated Technology Express")) {
512 printk(KERN_INFO
"IT821x %sRAID%d volume",
513 adev
->id
[147]?"Bootable ":"",
515 if (adev
->id
[129] != 1)
516 printk("(%dK stripe)", adev
->id
[146]);
519 /* This is a controller firmware triggered funny, don't
520 report the drive faulty! */
521 adev
->horkage
&= ~ATA_HORKAGE_DIAGNOSTIC
;
525 * it821x_ident_hack - Hack identify data up
528 * Walk the devices on this firmware driven port and slightly
529 * mash the identify data to stop us and common tools trying to
530 * use features not firmware supported. The firmware itself does
531 * some masking (eg SMART) but not enough.
533 * This is a bit of an abuse of the cable method, but it is the
534 * only method called at the right time. We could modify the libata
535 * core specifically for ident hacking but while we have one offender
536 * it seems better to keep the fallout localised.
539 static int it821x_ident_hack(struct ata_port
*ap
)
541 struct ata_device
*adev
;
542 ata_link_for_each_dev(adev
, &ap
->link
) {
543 if (ata_dev_enabled(adev
)) {
544 adev
->id
[84] &= ~(1 << 6); /* No FUA */
545 adev
->id
[85] &= ~(1 << 10); /* No HPA */
546 adev
->id
[76] = 0; /* No NCQ/AN etc */
549 return ata_cable_unknown(ap
);
554 * it821x_check_atapi_dma - ATAPI DMA handler
555 * @qc: Command we are about to issue
557 * Decide if this ATAPI command can be issued by DMA on this
558 * controller. Return 0 if it can be.
561 static int it821x_check_atapi_dma(struct ata_queued_cmd
*qc
)
563 struct ata_port
*ap
= qc
->ap
;
564 struct it821x_dev
*itdev
= ap
->private_data
;
566 /* Only use dma for transfers to/from the media. */
567 if (ata_qc_raw_nbytes(qc
) < 2048)
570 /* No ATAPI DMA in smart mode */
573 /* No ATAPI DMA on rev 10 */
582 * it821x_port_start - port setup
583 * @ap: ATA port being set up
585 * The it821x needs to maintain private data structures and also to
586 * use the standard PCI interface which lacks support for this
587 * functionality. We instead set up the private data on the port
588 * start hook, and tear it down on port stop
591 static int it821x_port_start(struct ata_port
*ap
)
593 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
594 struct it821x_dev
*itdev
;
597 int ret
= ata_sff_port_start(ap
);
601 itdev
= devm_kzalloc(&pdev
->dev
, sizeof(struct it821x_dev
), GFP_KERNEL
);
604 ap
->private_data
= itdev
;
606 pci_read_config_byte(pdev
, 0x50, &conf
);
610 /* Long I/O's although allowed in LBA48 space cause the
611 onboard firmware to enter the twighlight zone */
612 /* No ATAPI DMA in this mode either */
614 /* Pull the current clocks from 0x50 */
615 if (conf
& (1 << (1 + ap
->port_no
)))
616 itdev
->clock_mode
= ATA_50
;
618 itdev
->clock_mode
= ATA_66
;
620 itdev
->want
[0][1] = ATA_ANY
;
621 itdev
->want
[1][1] = ATA_ANY
;
622 itdev
->last_device
= -1;
624 if (pdev
->revision
== 0x10) {
626 /* Need to disable ATAPI DMA for this case */
628 printk(KERN_WARNING DRV_NAME
": Revision 0x10, workarounds activated.\n");
634 static struct scsi_host_template it821x_sht
= {
635 ATA_BMDMA_SHT(DRV_NAME
),
638 static struct ata_port_operations it821x_smart_port_ops
= {
639 .inherits
= &ata_bmdma_port_ops
,
641 .check_atapi_dma
= it821x_check_atapi_dma
,
642 .qc_issue
= it821x_smart_qc_issue_prot
,
644 .cable_detect
= it821x_ident_hack
,
645 .set_mode
= it821x_smart_set_mode
,
646 .dev_config
= it821x_dev_config
,
648 .port_start
= it821x_port_start
,
651 static struct ata_port_operations it821x_passthru_port_ops
= {
652 .inherits
= &ata_bmdma_port_ops
,
654 .check_atapi_dma
= it821x_check_atapi_dma
,
655 .dev_select
= it821x_passthru_dev_select
,
656 .bmdma_start
= it821x_passthru_bmdma_start
,
657 .bmdma_stop
= it821x_passthru_bmdma_stop
,
658 .qc_issue
= it821x_passthru_qc_issue_prot
,
660 .cable_detect
= ata_cable_unknown
,
661 .set_piomode
= it821x_passthru_set_piomode
,
662 .set_dmamode
= it821x_passthru_set_dmamode
,
664 .port_start
= it821x_port_start
,
667 static void it821x_disable_raid(struct pci_dev
*pdev
)
669 /* Reset local CPU, and set BIOS not ready */
670 pci_write_config_byte(pdev
, 0x5E, 0x01);
672 /* Set to bypass mode, and reset PCI bus */
673 pci_write_config_byte(pdev
, 0x50, 0x00);
674 pci_write_config_word(pdev
, PCI_COMMAND
,
675 PCI_COMMAND_PARITY
| PCI_COMMAND_IO
|
676 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
677 pci_write_config_word(pdev
, 0x40, 0xA0F3);
679 pci_write_config_dword(pdev
,0x4C, 0x02040204);
680 pci_write_config_byte(pdev
, 0x42, 0x36);
681 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0x20);
685 static int it821x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
689 static const struct ata_port_info info_smart
= {
691 .flags
= ATA_FLAG_SLAVE_POSS
,
694 .port_ops
= &it821x_smart_port_ops
696 static const struct ata_port_info info_passthru
= {
698 .flags
= ATA_FLAG_SLAVE_POSS
,
701 .udma_mask
= ATA_UDMA6
,
702 .port_ops
= &it821x_passthru_port_ops
705 const struct ata_port_info
*ppi
[] = { NULL
, NULL
};
706 static char *mode
[2] = { "pass through", "smart" };
709 rc
= pcim_enable_device(pdev
);
713 /* Force the card into bypass mode if so requested */
715 printk(KERN_INFO DRV_NAME
": forcing bypass mode.\n");
716 it821x_disable_raid(pdev
);
718 pci_read_config_byte(pdev
, 0x50, &conf
);
721 printk(KERN_INFO DRV_NAME
": controller in %s mode.\n", mode
[conf
]);
723 ppi
[0] = &info_passthru
;
725 ppi
[0] = &info_smart
;
727 return ata_pci_init_one(pdev
, ppi
);
731 static int it821x_reinit_one(struct pci_dev
*pdev
)
733 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
736 rc
= ata_pci_device_do_resume(pdev
);
739 /* Resume - turn raid back off if need be */
741 it821x_disable_raid(pdev
);
742 ata_host_resume(host
);
747 static const struct pci_device_id it821x
[] = {
748 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8211
), },
749 { PCI_VDEVICE(ITE
, PCI_DEVICE_ID_ITE_8212
), },
754 static struct pci_driver it821x_pci_driver
= {
757 .probe
= it821x_init_one
,
758 .remove
= ata_pci_remove_one
,
760 .suspend
= ata_pci_device_suspend
,
761 .resume
= it821x_reinit_one
,
765 static int __init
it821x_init(void)
767 return pci_register_driver(&it821x_pci_driver
);
770 static void __exit
it821x_exit(void)
772 pci_unregister_driver(&it821x_pci_driver
);
775 MODULE_AUTHOR("Alan Cox");
776 MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
777 MODULE_LICENSE("GPL");
778 MODULE_DEVICE_TABLE(pci
, it821x
);
779 MODULE_VERSION(DRV_VERSION
);
782 module_param_named(noraid
, it8212_noraid
, int, S_IRUGO
);
783 MODULE_PARM_DESC(noraid
, "Force card into bypass mode");
785 module_init(it821x_init
);
786 module_exit(it821x_exit
);