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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
128 PIIX_AHCI_DEVICE = 6,
129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
132 };
133
134 enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
142 ich5_sata,
143 ich6_sata,
144 ich6m_sata,
145 ich8_sata,
146 ich8_2port_sata,
147 ich8m_apple_sata, /* locks up on second port enable */
148 tolapai_sata,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150 };
151
152 struct piix_map_db {
153 const u32 mask;
154 const u16 port_enable;
155 const int map[][4];
156 };
157
158 struct piix_host_priv {
159 const int *map;
160 u32 saved_iocfg;
161 void __iomem *sidpr;
162 };
163
164 static int piix_init_one(struct pci_dev *pdev,
165 const struct pci_device_id *ent);
166 static void piix_remove_one(struct pci_dev *pdev);
167 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
168 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
169 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
171 static int ich_pata_cable_detect(struct ata_port *ap);
172 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
173 static int piix_sidpr_scr_read(struct ata_link *link,
174 unsigned int reg, u32 *val);
175 static int piix_sidpr_scr_write(struct ata_link *link,
176 unsigned int reg, u32 val);
177 static bool piix_irq_check(struct ata_port *ap);
178 #ifdef CONFIG_PM
179 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
180 static int piix_pci_device_resume(struct pci_dev *pdev);
181 #endif
182
183 static unsigned int in_module_init = 1;
184
185 static const struct pci_device_id piix_pci_tbl[] = {
186 /* Intel PIIX3 for the 430HX etc */
187 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
188 /* VMware ICH4 */
189 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
190 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
191 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
192 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX4 */
194 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel PIIX4 */
196 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
197 /* Intel PIIX */
198 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
199 /* Intel ICH (i810, i815, i840) UDMA 66*/
200 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
201 /* Intel ICH0 : UDMA 33*/
202 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
203 /* Intel ICH2M */
204 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
206 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH3M */
208 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* Intel ICH3 (E7500/1) UDMA 100 */
210 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
212 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* Intel ICH5 */
215 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* C-ICH (i810E2) */
217 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
219 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 /* ICH6 (and 6) (i915) UDMA 100 */
221 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* ICH7/7-R (i945, i975) UDMA 100*/
223 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
224 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
225 /* ICH8 Mobile PATA Controller */
226 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
227
228 /* SATA ports */
229
230 /* 82801EB (ICH5) */
231 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 82801EB (ICH5) */
233 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 6300ESB (ICH5 variant with broken PCS present bits) */
235 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 6300ESB pretending RAID */
237 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
238 /* 82801FB/FW (ICH6/ICH6W) */
239 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
240 /* 82801FR/FRW (ICH6R/ICH6RW) */
241 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
242 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
243 * Attach iff the controller is in IDE mode. */
244 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
245 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
246 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
247 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
249 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
250 /* Enterprise Southbridge 2 (631xESB/632xESB) */
251 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
252 /* SATA Controller 1 IDE (ICH8) */
253 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* SATA Controller 2 IDE (ICH8) */
255 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* Mobile SATA Controller IDE (ICH8M), Apple */
257 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
258 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
259 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
260 /* Mobile SATA Controller IDE (ICH8M) */
261 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (ICH9) */
265 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9) */
267 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (ICH9M) */
271 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
272 /* SATA Controller IDE (ICH9M) */
273 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (Tolapai) */
275 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (ICH10) */
283 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
296 /* SATA Controller IDE (CPT) */
297 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
298 /* SATA Controller IDE (CPT) */
299 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (CPT) */
301 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (CPT) */
303 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 { } /* terminate list */
305 };
306
307 static struct pci_driver piix_pci_driver = {
308 .name = DRV_NAME,
309 .id_table = piix_pci_tbl,
310 .probe = piix_init_one,
311 .remove = piix_remove_one,
312 #ifdef CONFIG_PM
313 .suspend = piix_pci_device_suspend,
314 .resume = piix_pci_device_resume,
315 #endif
316 };
317
318 static struct scsi_host_template piix_sht = {
319 ATA_BMDMA_SHT(DRV_NAME),
320 };
321
322 static struct ata_port_operations piix_sata_ops = {
323 .inherits = &ata_bmdma32_port_ops,
324 .sff_irq_check = piix_irq_check,
325 };
326
327 static struct ata_port_operations piix_pata_ops = {
328 .inherits = &piix_sata_ops,
329 .cable_detect = ata_cable_40wire,
330 .set_piomode = piix_set_piomode,
331 .set_dmamode = piix_set_dmamode,
332 .prereset = piix_pata_prereset,
333 };
334
335 static struct ata_port_operations piix_vmw_ops = {
336 .inherits = &piix_pata_ops,
337 .bmdma_status = piix_vmw_bmdma_status,
338 };
339
340 static struct ata_port_operations ich_pata_ops = {
341 .inherits = &piix_pata_ops,
342 .cable_detect = ich_pata_cable_detect,
343 .set_dmamode = ich_set_dmamode,
344 };
345
346 static struct ata_port_operations piix_sidpr_sata_ops = {
347 .inherits = &piix_sata_ops,
348 .hardreset = sata_std_hardreset,
349 .scr_read = piix_sidpr_scr_read,
350 .scr_write = piix_sidpr_scr_write,
351 };
352
353 static const struct piix_map_db ich5_map_db = {
354 .mask = 0x7,
355 .port_enable = 0x3,
356 .map = {
357 /* PM PS SM SS MAP */
358 { P0, NA, P1, NA }, /* 000b */
359 { P1, NA, P0, NA }, /* 001b */
360 { RV, RV, RV, RV },
361 { RV, RV, RV, RV },
362 { P0, P1, IDE, IDE }, /* 100b */
363 { P1, P0, IDE, IDE }, /* 101b */
364 { IDE, IDE, P0, P1 }, /* 110b */
365 { IDE, IDE, P1, P0 }, /* 111b */
366 },
367 };
368
369 static const struct piix_map_db ich6_map_db = {
370 .mask = 0x3,
371 .port_enable = 0xf,
372 .map = {
373 /* PM PS SM SS MAP */
374 { P0, P2, P1, P3 }, /* 00b */
375 { IDE, IDE, P1, P3 }, /* 01b */
376 { P0, P2, IDE, IDE }, /* 10b */
377 { RV, RV, RV, RV },
378 },
379 };
380
381 static const struct piix_map_db ich6m_map_db = {
382 .mask = 0x3,
383 .port_enable = 0x5,
384
385 /* Map 01b isn't specified in the doc but some notebooks use
386 * it anyway. MAP 01b have been spotted on both ICH6M and
387 * ICH7M.
388 */
389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, P2, NA, NA }, /* 00b */
392 { IDE, IDE, P1, P3 }, /* 01b */
393 { P0, P2, IDE, IDE }, /* 10b */
394 { RV, RV, RV, RV },
395 },
396 };
397
398 static const struct piix_map_db ich8_map_db = {
399 .mask = 0x3,
400 .port_enable = 0xf,
401 .map = {
402 /* PM PS SM SS MAP */
403 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
404 { RV, RV, RV, RV },
405 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
406 { RV, RV, RV, RV },
407 },
408 };
409
410 static const struct piix_map_db ich8_2port_map_db = {
411 .mask = 0x3,
412 .port_enable = 0x3,
413 .map = {
414 /* PM PS SM SS MAP */
415 { P0, NA, P1, NA }, /* 00b */
416 { RV, RV, RV, RV }, /* 01b */
417 { RV, RV, RV, RV }, /* 10b */
418 { RV, RV, RV, RV },
419 },
420 };
421
422 static const struct piix_map_db ich8m_apple_map_db = {
423 .mask = 0x3,
424 .port_enable = 0x1,
425 .map = {
426 /* PM PS SM SS MAP */
427 { P0, NA, NA, NA }, /* 00b */
428 { RV, RV, RV, RV },
429 { P0, P2, IDE, IDE }, /* 10b */
430 { RV, RV, RV, RV },
431 },
432 };
433
434 static const struct piix_map_db tolapai_map_db = {
435 .mask = 0x3,
436 .port_enable = 0x3,
437 .map = {
438 /* PM PS SM SS MAP */
439 { P0, NA, P1, NA }, /* 00b */
440 { RV, RV, RV, RV }, /* 01b */
441 { RV, RV, RV, RV }, /* 10b */
442 { RV, RV, RV, RV },
443 },
444 };
445
446 static const struct piix_map_db *piix_map_db_table[] = {
447 [ich5_sata] = &ich5_map_db,
448 [ich6_sata] = &ich6_map_db,
449 [ich6m_sata] = &ich6m_map_db,
450 [ich8_sata] = &ich8_map_db,
451 [ich8_2port_sata] = &ich8_2port_map_db,
452 [ich8m_apple_sata] = &ich8m_apple_map_db,
453 [tolapai_sata] = &tolapai_map_db,
454 };
455
456 static struct ata_port_info piix_port_info[] = {
457 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
458 {
459 .flags = PIIX_PATA_FLAGS,
460 .pio_mask = ATA_PIO4,
461 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
462 .port_ops = &piix_pata_ops,
463 },
464
465 [piix_pata_33] = /* PIIX4 at 33MHz */
466 {
467 .flags = PIIX_PATA_FLAGS,
468 .pio_mask = ATA_PIO4,
469 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
470 .udma_mask = ATA_UDMA2,
471 .port_ops = &piix_pata_ops,
472 },
473
474 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
475 {
476 .flags = PIIX_PATA_FLAGS,
477 .pio_mask = ATA_PIO4,
478 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
479 .udma_mask = ATA_UDMA2,
480 .port_ops = &ich_pata_ops,
481 },
482
483 [ich_pata_66] = /* ICH controllers up to 66MHz */
484 {
485 .flags = PIIX_PATA_FLAGS,
486 .pio_mask = ATA_PIO4,
487 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
488 .udma_mask = ATA_UDMA4,
489 .port_ops = &ich_pata_ops,
490 },
491
492 [ich_pata_100] =
493 {
494 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
495 .pio_mask = ATA_PIO4,
496 .mwdma_mask = ATA_MWDMA12_ONLY,
497 .udma_mask = ATA_UDMA5,
498 .port_ops = &ich_pata_ops,
499 },
500
501 [ich_pata_100_nomwdma1] =
502 {
503 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
504 .pio_mask = ATA_PIO4,
505 .mwdma_mask = ATA_MWDMA2_ONLY,
506 .udma_mask = ATA_UDMA5,
507 .port_ops = &ich_pata_ops,
508 },
509
510 [ich5_sata] =
511 {
512 .flags = PIIX_SATA_FLAGS,
513 .pio_mask = ATA_PIO4,
514 .mwdma_mask = ATA_MWDMA2,
515 .udma_mask = ATA_UDMA6,
516 .port_ops = &piix_sata_ops,
517 },
518
519 [ich6_sata] =
520 {
521 .flags = PIIX_SATA_FLAGS,
522 .pio_mask = ATA_PIO4,
523 .mwdma_mask = ATA_MWDMA2,
524 .udma_mask = ATA_UDMA6,
525 .port_ops = &piix_sata_ops,
526 },
527
528 [ich6m_sata] =
529 {
530 .flags = PIIX_SATA_FLAGS,
531 .pio_mask = ATA_PIO4,
532 .mwdma_mask = ATA_MWDMA2,
533 .udma_mask = ATA_UDMA6,
534 .port_ops = &piix_sata_ops,
535 },
536
537 [ich8_sata] =
538 {
539 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
540 .pio_mask = ATA_PIO4,
541 .mwdma_mask = ATA_MWDMA2,
542 .udma_mask = ATA_UDMA6,
543 .port_ops = &piix_sata_ops,
544 },
545
546 [ich8_2port_sata] =
547 {
548 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
549 .pio_mask = ATA_PIO4,
550 .mwdma_mask = ATA_MWDMA2,
551 .udma_mask = ATA_UDMA6,
552 .port_ops = &piix_sata_ops,
553 },
554
555 [tolapai_sata] =
556 {
557 .flags = PIIX_SATA_FLAGS,
558 .pio_mask = ATA_PIO4,
559 .mwdma_mask = ATA_MWDMA2,
560 .udma_mask = ATA_UDMA6,
561 .port_ops = &piix_sata_ops,
562 },
563
564 [ich8m_apple_sata] =
565 {
566 .flags = PIIX_SATA_FLAGS,
567 .pio_mask = ATA_PIO4,
568 .mwdma_mask = ATA_MWDMA2,
569 .udma_mask = ATA_UDMA6,
570 .port_ops = &piix_sata_ops,
571 },
572
573 [piix_pata_vmw] =
574 {
575 .flags = PIIX_PATA_FLAGS,
576 .pio_mask = ATA_PIO4,
577 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
578 .udma_mask = ATA_UDMA2,
579 .port_ops = &piix_vmw_ops,
580 },
581
582 };
583
584 static struct pci_bits piix_enable_bits[] = {
585 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
586 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
587 };
588
589 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
590 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
591 MODULE_LICENSE("GPL");
592 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
593 MODULE_VERSION(DRV_VERSION);
594
595 struct ich_laptop {
596 u16 device;
597 u16 subvendor;
598 u16 subdevice;
599 };
600
601 /*
602 * List of laptops that use short cables rather than 80 wire
603 */
604
605 static const struct ich_laptop ich_laptop[] = {
606 /* devid, subvendor, subdev */
607 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
608 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
609 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
610 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
611 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
612 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
613 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
614 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
615 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
616 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
617 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
618 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
619 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
620 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
621 /* end marker */
622 { 0, }
623 };
624
625 /**
626 * ich_pata_cable_detect - Probe host controller cable detect info
627 * @ap: Port for which cable detect info is desired
628 *
629 * Read 80c cable indicator from ATA PCI device's PCI config
630 * register. This register is normally set by firmware (BIOS).
631 *
632 * LOCKING:
633 * None (inherited from caller).
634 */
635
636 static int ich_pata_cable_detect(struct ata_port *ap)
637 {
638 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
639 struct piix_host_priv *hpriv = ap->host->private_data;
640 const struct ich_laptop *lap = &ich_laptop[0];
641 u8 mask;
642
643 /* Check for specials - Acer Aspire 5602WLMi */
644 while (lap->device) {
645 if (lap->device == pdev->device &&
646 lap->subvendor == pdev->subsystem_vendor &&
647 lap->subdevice == pdev->subsystem_device)
648 return ATA_CBL_PATA40_SHORT;
649
650 lap++;
651 }
652
653 /* check BIOS cable detect results */
654 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
655 if ((hpriv->saved_iocfg & mask) == 0)
656 return ATA_CBL_PATA40;
657 return ATA_CBL_PATA80;
658 }
659
660 /**
661 * piix_pata_prereset - prereset for PATA host controller
662 * @link: Target link
663 * @deadline: deadline jiffies for the operation
664 *
665 * LOCKING:
666 * None (inherited from caller).
667 */
668 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
669 {
670 struct ata_port *ap = link->ap;
671 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
672
673 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
674 return -ENOENT;
675 return ata_sff_prereset(link, deadline);
676 }
677
678 static DEFINE_SPINLOCK(piix_lock);
679
680 /**
681 * piix_set_piomode - Initialize host controller PATA PIO timings
682 * @ap: Port whose timings we are configuring
683 * @adev: um
684 *
685 * Set PIO mode for device, in host controller PCI config space.
686 *
687 * LOCKING:
688 * None (inherited from caller).
689 */
690
691 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
692 {
693 struct pci_dev *dev = to_pci_dev(ap->host->dev);
694 unsigned long flags;
695 unsigned int pio = adev->pio_mode - XFER_PIO_0;
696 unsigned int is_slave = (adev->devno != 0);
697 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
698 unsigned int slave_port = 0x44;
699 u16 master_data;
700 u8 slave_data;
701 u8 udma_enable;
702 int control = 0;
703
704 /*
705 * See Intel Document 298600-004 for the timing programing rules
706 * for ICH controllers.
707 */
708
709 static const /* ISP RTC */
710 u8 timings[][2] = { { 0, 0 },
711 { 0, 0 },
712 { 1, 0 },
713 { 2, 1 },
714 { 2, 3 }, };
715
716 if (pio >= 2)
717 control |= 1; /* TIME1 enable */
718 if (ata_pio_need_iordy(adev))
719 control |= 2; /* IE enable */
720
721 /* Intel specifies that the PPE functionality is for disk only */
722 if (adev->class == ATA_DEV_ATA)
723 control |= 4; /* PPE enable */
724
725 spin_lock_irqsave(&piix_lock, flags);
726
727 /* PIO configuration clears DTE unconditionally. It will be
728 * programmed in set_dmamode which is guaranteed to be called
729 * after set_piomode if any DMA mode is available.
730 */
731 pci_read_config_word(dev, master_port, &master_data);
732 if (is_slave) {
733 /* clear TIME1|IE1|PPE1|DTE1 */
734 master_data &= 0xff0f;
735 /* Enable SITRE (separate slave timing register) */
736 master_data |= 0x4000;
737 /* enable PPE1, IE1 and TIME1 as needed */
738 master_data |= (control << 4);
739 pci_read_config_byte(dev, slave_port, &slave_data);
740 slave_data &= (ap->port_no ? 0x0f : 0xf0);
741 /* Load the timing nibble for this slave */
742 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
743 << (ap->port_no ? 4 : 0);
744 } else {
745 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
746 master_data &= 0xccf0;
747 /* Enable PPE, IE and TIME as appropriate */
748 master_data |= control;
749 /* load ISP and RCT */
750 master_data |=
751 (timings[pio][0] << 12) |
752 (timings[pio][1] << 8);
753 }
754 pci_write_config_word(dev, master_port, master_data);
755 if (is_slave)
756 pci_write_config_byte(dev, slave_port, slave_data);
757
758 /* Ensure the UDMA bit is off - it will be turned back on if
759 UDMA is selected */
760
761 if (ap->udma_mask) {
762 pci_read_config_byte(dev, 0x48, &udma_enable);
763 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
764 pci_write_config_byte(dev, 0x48, udma_enable);
765 }
766
767 spin_unlock_irqrestore(&piix_lock, flags);
768 }
769
770 /**
771 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
772 * @ap: Port whose timings we are configuring
773 * @adev: Drive in question
774 * @isich: set if the chip is an ICH device
775 *
776 * Set UDMA mode for device, in host controller PCI config space.
777 *
778 * LOCKING:
779 * None (inherited from caller).
780 */
781
782 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
783 {
784 struct pci_dev *dev = to_pci_dev(ap->host->dev);
785 unsigned long flags;
786 u8 master_port = ap->port_no ? 0x42 : 0x40;
787 u16 master_data;
788 u8 speed = adev->dma_mode;
789 int devid = adev->devno + 2 * ap->port_no;
790 u8 udma_enable = 0;
791
792 static const /* ISP RTC */
793 u8 timings[][2] = { { 0, 0 },
794 { 0, 0 },
795 { 1, 0 },
796 { 2, 1 },
797 { 2, 3 }, };
798
799 spin_lock_irqsave(&piix_lock, flags);
800
801 pci_read_config_word(dev, master_port, &master_data);
802 if (ap->udma_mask)
803 pci_read_config_byte(dev, 0x48, &udma_enable);
804
805 if (speed >= XFER_UDMA_0) {
806 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
807 u16 udma_timing;
808 u16 ideconf;
809 int u_clock, u_speed;
810
811 /*
812 * UDMA is handled by a combination of clock switching and
813 * selection of dividers
814 *
815 * Handy rule: Odd modes are UDMATIMx 01, even are 02
816 * except UDMA0 which is 00
817 */
818 u_speed = min(2 - (udma & 1), udma);
819 if (udma == 5)
820 u_clock = 0x1000; /* 100Mhz */
821 else if (udma > 2)
822 u_clock = 1; /* 66Mhz */
823 else
824 u_clock = 0; /* 33Mhz */
825
826 udma_enable |= (1 << devid);
827
828 /* Load the CT/RP selection */
829 pci_read_config_word(dev, 0x4A, &udma_timing);
830 udma_timing &= ~(3 << (4 * devid));
831 udma_timing |= u_speed << (4 * devid);
832 pci_write_config_word(dev, 0x4A, udma_timing);
833
834 if (isich) {
835 /* Select a 33/66/100Mhz clock */
836 pci_read_config_word(dev, 0x54, &ideconf);
837 ideconf &= ~(0x1001 << devid);
838 ideconf |= u_clock << devid;
839 /* For ICH or later we should set bit 10 for better
840 performance (WR_PingPong_En) */
841 pci_write_config_word(dev, 0x54, ideconf);
842 }
843 } else {
844 /*
845 * MWDMA is driven by the PIO timings. We must also enable
846 * IORDY unconditionally along with TIME1. PPE has already
847 * been set when the PIO timing was set.
848 */
849 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
850 unsigned int control;
851 u8 slave_data;
852 const unsigned int needed_pio[3] = {
853 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
854 };
855 int pio = needed_pio[mwdma] - XFER_PIO_0;
856
857 control = 3; /* IORDY|TIME1 */
858
859 /* If the drive MWDMA is faster than it can do PIO then
860 we must force PIO into PIO0 */
861
862 if (adev->pio_mode < needed_pio[mwdma])
863 /* Enable DMA timing only */
864 control |= 8; /* PIO cycles in PIO0 */
865
866 if (adev->devno) { /* Slave */
867 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
868 master_data |= control << 4;
869 pci_read_config_byte(dev, 0x44, &slave_data);
870 slave_data &= (ap->port_no ? 0x0f : 0xf0);
871 /* Load the matching timing */
872 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
873 pci_write_config_byte(dev, 0x44, slave_data);
874 } else { /* Master */
875 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
876 and master timing bits */
877 master_data |= control;
878 master_data |=
879 (timings[pio][0] << 12) |
880 (timings[pio][1] << 8);
881 }
882
883 if (ap->udma_mask)
884 udma_enable &= ~(1 << devid);
885
886 pci_write_config_word(dev, master_port, master_data);
887 }
888 /* Don't scribble on 0x48 if the controller does not support UDMA */
889 if (ap->udma_mask)
890 pci_write_config_byte(dev, 0x48, udma_enable);
891
892 spin_unlock_irqrestore(&piix_lock, flags);
893 }
894
895 /**
896 * piix_set_dmamode - Initialize host controller PATA DMA timings
897 * @ap: Port whose timings we are configuring
898 * @adev: um
899 *
900 * Set MW/UDMA mode for device, in host controller PCI config space.
901 *
902 * LOCKING:
903 * None (inherited from caller).
904 */
905
906 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
907 {
908 do_pata_set_dmamode(ap, adev, 0);
909 }
910
911 /**
912 * ich_set_dmamode - Initialize host controller PATA DMA timings
913 * @ap: Port whose timings we are configuring
914 * @adev: um
915 *
916 * Set MW/UDMA mode for device, in host controller PCI config space.
917 *
918 * LOCKING:
919 * None (inherited from caller).
920 */
921
922 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
923 {
924 do_pata_set_dmamode(ap, adev, 1);
925 }
926
927 /*
928 * Serial ATA Index/Data Pair Superset Registers access
929 *
930 * Beginning from ICH8, there's a sane way to access SCRs using index
931 * and data register pair located at BAR5 which means that we have
932 * separate SCRs for master and slave. This is handled using libata
933 * slave_link facility.
934 */
935 static const int piix_sidx_map[] = {
936 [SCR_STATUS] = 0,
937 [SCR_ERROR] = 2,
938 [SCR_CONTROL] = 1,
939 };
940
941 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
942 {
943 struct ata_port *ap = link->ap;
944 struct piix_host_priv *hpriv = ap->host->private_data;
945
946 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
947 hpriv->sidpr + PIIX_SIDPR_IDX);
948 }
949
950 static int piix_sidpr_scr_read(struct ata_link *link,
951 unsigned int reg, u32 *val)
952 {
953 struct piix_host_priv *hpriv = link->ap->host->private_data;
954
955 if (reg >= ARRAY_SIZE(piix_sidx_map))
956 return -EINVAL;
957
958 piix_sidpr_sel(link, reg);
959 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
960 return 0;
961 }
962
963 static int piix_sidpr_scr_write(struct ata_link *link,
964 unsigned int reg, u32 val)
965 {
966 struct piix_host_priv *hpriv = link->ap->host->private_data;
967
968 if (reg >= ARRAY_SIZE(piix_sidx_map))
969 return -EINVAL;
970
971 piix_sidpr_sel(link, reg);
972 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
973 return 0;
974 }
975
976 static bool piix_irq_check(struct ata_port *ap)
977 {
978 if (unlikely(!ap->ioaddr.bmdma_addr))
979 return false;
980
981 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
982 }
983
984 #ifdef CONFIG_PM
985 static int piix_broken_suspend(void)
986 {
987 static const struct dmi_system_id sysids[] = {
988 {
989 .ident = "TECRA M3",
990 .matches = {
991 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
993 },
994 },
995 {
996 .ident = "TECRA M3",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1000 },
1001 },
1002 {
1003 .ident = "TECRA M4",
1004 .matches = {
1005 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1006 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1007 },
1008 },
1009 {
1010 .ident = "TECRA M4",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1014 },
1015 },
1016 {
1017 .ident = "TECRA M5",
1018 .matches = {
1019 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1020 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1021 },
1022 },
1023 {
1024 .ident = "TECRA M6",
1025 .matches = {
1026 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1027 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1028 },
1029 },
1030 {
1031 .ident = "TECRA M7",
1032 .matches = {
1033 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1034 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1035 },
1036 },
1037 {
1038 .ident = "TECRA A8",
1039 .matches = {
1040 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1041 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1042 },
1043 },
1044 {
1045 .ident = "Satellite R20",
1046 .matches = {
1047 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1048 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1049 },
1050 },
1051 {
1052 .ident = "Satellite R25",
1053 .matches = {
1054 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1055 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1056 },
1057 },
1058 {
1059 .ident = "Satellite U200",
1060 .matches = {
1061 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1062 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1063 },
1064 },
1065 {
1066 .ident = "Satellite U200",
1067 .matches = {
1068 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1069 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1070 },
1071 },
1072 {
1073 .ident = "Satellite Pro U200",
1074 .matches = {
1075 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1076 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1077 },
1078 },
1079 {
1080 .ident = "Satellite U205",
1081 .matches = {
1082 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1083 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1084 },
1085 },
1086 {
1087 .ident = "SATELLITE U205",
1088 .matches = {
1089 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1090 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1091 },
1092 },
1093 {
1094 .ident = "Portege M500",
1095 .matches = {
1096 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1097 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1098 },
1099 },
1100 {
1101 .ident = "VGN-BX297XP",
1102 .matches = {
1103 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1104 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1105 },
1106 },
1107
1108 { } /* terminate list */
1109 };
1110 static const char *oemstrs[] = {
1111 "Tecra M3,",
1112 };
1113 int i;
1114
1115 if (dmi_check_system(sysids))
1116 return 1;
1117
1118 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1119 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1120 return 1;
1121
1122 /* TECRA M4 sometimes forgets its identify and reports bogus
1123 * DMI information. As the bogus information is a bit
1124 * generic, match as many entries as possible. This manual
1125 * matching is necessary because dmi_system_id.matches is
1126 * limited to four entries.
1127 */
1128 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1129 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1130 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1131 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1132 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1133 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1134 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1135 return 1;
1136
1137 return 0;
1138 }
1139
1140 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1141 {
1142 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1143 unsigned long flags;
1144 int rc = 0;
1145
1146 rc = ata_host_suspend(host, mesg);
1147 if (rc)
1148 return rc;
1149
1150 /* Some braindamaged ACPI suspend implementations expect the
1151 * controller to be awake on entry; otherwise, it burns cpu
1152 * cycles and power trying to do something to the sleeping
1153 * beauty.
1154 */
1155 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1156 pci_save_state(pdev);
1157
1158 /* mark its power state as "unknown", since we don't
1159 * know if e.g. the BIOS will change its device state
1160 * when we suspend.
1161 */
1162 if (pdev->current_state == PCI_D0)
1163 pdev->current_state = PCI_UNKNOWN;
1164
1165 /* tell resume that it's waking up from broken suspend */
1166 spin_lock_irqsave(&host->lock, flags);
1167 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1168 spin_unlock_irqrestore(&host->lock, flags);
1169 } else
1170 ata_pci_device_do_suspend(pdev, mesg);
1171
1172 return 0;
1173 }
1174
1175 static int piix_pci_device_resume(struct pci_dev *pdev)
1176 {
1177 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1178 unsigned long flags;
1179 int rc;
1180
1181 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1182 spin_lock_irqsave(&host->lock, flags);
1183 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1184 spin_unlock_irqrestore(&host->lock, flags);
1185
1186 pci_set_power_state(pdev, PCI_D0);
1187 pci_restore_state(pdev);
1188
1189 /* PCI device wasn't disabled during suspend. Use
1190 * pci_reenable_device() to avoid affecting the enable
1191 * count.
1192 */
1193 rc = pci_reenable_device(pdev);
1194 if (rc)
1195 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1196 "device after resume (%d)\n", rc);
1197 } else
1198 rc = ata_pci_device_do_resume(pdev);
1199
1200 if (rc == 0)
1201 ata_host_resume(host);
1202
1203 return rc;
1204 }
1205 #endif
1206
1207 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1208 {
1209 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1210 }
1211
1212 #define AHCI_PCI_BAR 5
1213 #define AHCI_GLOBAL_CTL 0x04
1214 #define AHCI_ENABLE (1 << 31)
1215 static int piix_disable_ahci(struct pci_dev *pdev)
1216 {
1217 void __iomem *mmio;
1218 u32 tmp;
1219 int rc = 0;
1220
1221 /* BUG: pci_enable_device has not yet been called. This
1222 * works because this device is usually set up by BIOS.
1223 */
1224
1225 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1226 !pci_resource_len(pdev, AHCI_PCI_BAR))
1227 return 0;
1228
1229 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1230 if (!mmio)
1231 return -ENOMEM;
1232
1233 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1234 if (tmp & AHCI_ENABLE) {
1235 tmp &= ~AHCI_ENABLE;
1236 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1237
1238 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1239 if (tmp & AHCI_ENABLE)
1240 rc = -EIO;
1241 }
1242
1243 pci_iounmap(pdev, mmio);
1244 return rc;
1245 }
1246
1247 /**
1248 * piix_check_450nx_errata - Check for problem 450NX setup
1249 * @ata_dev: the PCI device to check
1250 *
1251 * Check for the present of 450NX errata #19 and errata #25. If
1252 * they are found return an error code so we can turn off DMA
1253 */
1254
1255 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1256 {
1257 struct pci_dev *pdev = NULL;
1258 u16 cfg;
1259 int no_piix_dma = 0;
1260
1261 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1262 /* Look for 450NX PXB. Check for problem configurations
1263 A PCI quirk checks bit 6 already */
1264 pci_read_config_word(pdev, 0x41, &cfg);
1265 /* Only on the original revision: IDE DMA can hang */
1266 if (pdev->revision == 0x00)
1267 no_piix_dma = 1;
1268 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1269 else if (cfg & (1<<14) && pdev->revision < 5)
1270 no_piix_dma = 2;
1271 }
1272 if (no_piix_dma)
1273 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1274 if (no_piix_dma == 2)
1275 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1276 return no_piix_dma;
1277 }
1278
1279 static void __devinit piix_init_pcs(struct ata_host *host,
1280 const struct piix_map_db *map_db)
1281 {
1282 struct pci_dev *pdev = to_pci_dev(host->dev);
1283 u16 pcs, new_pcs;
1284
1285 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1286
1287 new_pcs = pcs | map_db->port_enable;
1288
1289 if (new_pcs != pcs) {
1290 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1291 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1292 msleep(150);
1293 }
1294 }
1295
1296 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1297 struct ata_port_info *pinfo,
1298 const struct piix_map_db *map_db)
1299 {
1300 const int *map;
1301 int i, invalid_map = 0;
1302 u8 map_value;
1303
1304 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1305
1306 map = map_db->map[map_value & map_db->mask];
1307
1308 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1309 for (i = 0; i < 4; i++) {
1310 switch (map[i]) {
1311 case RV:
1312 invalid_map = 1;
1313 printk(" XX");
1314 break;
1315
1316 case NA:
1317 printk(" --");
1318 break;
1319
1320 case IDE:
1321 WARN_ON((i & 1) || map[i + 1] != IDE);
1322 pinfo[i / 2] = piix_port_info[ich_pata_100];
1323 i++;
1324 printk(" IDE IDE");
1325 break;
1326
1327 default:
1328 printk(" P%d", map[i]);
1329 if (i & 1)
1330 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1331 break;
1332 }
1333 }
1334 printk(" ]\n");
1335
1336 if (invalid_map)
1337 dev_printk(KERN_ERR, &pdev->dev,
1338 "invalid MAP value %u\n", map_value);
1339
1340 return map;
1341 }
1342
1343 static bool piix_no_sidpr(struct ata_host *host)
1344 {
1345 struct pci_dev *pdev = to_pci_dev(host->dev);
1346
1347 /*
1348 * Samsung DB-P70 only has three ATA ports exposed and
1349 * curiously the unconnected first port reports link online
1350 * while not responding to SRST protocol causing excessive
1351 * detection delay.
1352 *
1353 * Unfortunately, the system doesn't carry enough DMI
1354 * information to identify the machine but does have subsystem
1355 * vendor and device set. As it's unclear whether the
1356 * subsystem vendor/device is used only for this specific
1357 * board, the port can't be disabled solely with the
1358 * information; however, turning off SIDPR access works around
1359 * the problem. Turn it off.
1360 *
1361 * This problem is reported in bnc#441240.
1362 *
1363 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1364 */
1365 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1366 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1367 pdev->subsystem_device == 0xb049) {
1368 dev_printk(KERN_WARNING, host->dev,
1369 "Samsung DB-P70 detected, disabling SIDPR\n");
1370 return true;
1371 }
1372
1373 return false;
1374 }
1375
1376 static int __devinit piix_init_sidpr(struct ata_host *host)
1377 {
1378 struct pci_dev *pdev = to_pci_dev(host->dev);
1379 struct piix_host_priv *hpriv = host->private_data;
1380 struct ata_link *link0 = &host->ports[0]->link;
1381 u32 scontrol;
1382 int i, rc;
1383
1384 /* check for availability */
1385 for (i = 0; i < 4; i++)
1386 if (hpriv->map[i] == IDE)
1387 return 0;
1388
1389 /* is it blacklisted? */
1390 if (piix_no_sidpr(host))
1391 return 0;
1392
1393 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1394 return 0;
1395
1396 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1397 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1398 return 0;
1399
1400 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1401 return 0;
1402
1403 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1404
1405 /* SCR access via SIDPR doesn't work on some configurations.
1406 * Give it a test drive by inhibiting power save modes which
1407 * we'll do anyway.
1408 */
1409 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1410
1411 /* if IPM is already 3, SCR access is probably working. Don't
1412 * un-inhibit power save modes as BIOS might have inhibited
1413 * them for a reason.
1414 */
1415 if ((scontrol & 0xf00) != 0x300) {
1416 scontrol |= 0x300;
1417 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1418 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1419
1420 if ((scontrol & 0xf00) != 0x300) {
1421 dev_printk(KERN_INFO, host->dev, "SCR access via "
1422 "SIDPR is available but doesn't work\n");
1423 return 0;
1424 }
1425 }
1426
1427 /* okay, SCRs available, set ops and ask libata for slave_link */
1428 for (i = 0; i < 2; i++) {
1429 struct ata_port *ap = host->ports[i];
1430
1431 ap->ops = &piix_sidpr_sata_ops;
1432
1433 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1434 rc = ata_slave_link_init(ap);
1435 if (rc)
1436 return rc;
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
1443 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1444 {
1445 static const struct dmi_system_id sysids[] = {
1446 {
1447 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1448 * isn't used to boot the system which
1449 * disables the channel.
1450 */
1451 .ident = "M570U",
1452 .matches = {
1453 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1454 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1455 },
1456 },
1457
1458 { } /* terminate list */
1459 };
1460 struct pci_dev *pdev = to_pci_dev(host->dev);
1461 struct piix_host_priv *hpriv = host->private_data;
1462
1463 if (!dmi_check_system(sysids))
1464 return;
1465
1466 /* The datasheet says that bit 18 is NOOP but certain systems
1467 * seem to use it to disable a channel. Clear the bit on the
1468 * affected systems.
1469 */
1470 if (hpriv->saved_iocfg & (1 << 18)) {
1471 dev_printk(KERN_INFO, &pdev->dev,
1472 "applying IOCFG bit18 quirk\n");
1473 pci_write_config_dword(pdev, PIIX_IOCFG,
1474 hpriv->saved_iocfg & ~(1 << 18));
1475 }
1476 }
1477
1478 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1479 {
1480 static const struct dmi_system_id broken_systems[] = {
1481 {
1482 .ident = "HP Compaq 2510p",
1483 .matches = {
1484 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1485 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1486 },
1487 /* PCI slot number of the controller */
1488 .driver_data = (void *)0x1FUL,
1489 },
1490 {
1491 .ident = "HP Compaq nc6000",
1492 .matches = {
1493 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1494 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1495 },
1496 /* PCI slot number of the controller */
1497 .driver_data = (void *)0x1FUL,
1498 },
1499
1500 { } /* terminate list */
1501 };
1502 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1503
1504 if (dmi) {
1505 unsigned long slot = (unsigned long)dmi->driver_data;
1506 /* apply the quirk only to on-board controllers */
1507 return slot == PCI_SLOT(pdev->devfn);
1508 }
1509
1510 return false;
1511 }
1512
1513 /**
1514 * piix_init_one - Register PIIX ATA PCI device with kernel services
1515 * @pdev: PCI device to register
1516 * @ent: Entry in piix_pci_tbl matching with @pdev
1517 *
1518 * Called from kernel PCI layer. We probe for combined mode (sigh),
1519 * and then hand over control to libata, for it to do the rest.
1520 *
1521 * LOCKING:
1522 * Inherited from PCI layer (may sleep).
1523 *
1524 * RETURNS:
1525 * Zero on success, or -ERRNO value.
1526 */
1527
1528 static int __devinit piix_init_one(struct pci_dev *pdev,
1529 const struct pci_device_id *ent)
1530 {
1531 static int printed_version;
1532 struct device *dev = &pdev->dev;
1533 struct ata_port_info port_info[2];
1534 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1535 unsigned long port_flags;
1536 struct ata_host *host;
1537 struct piix_host_priv *hpriv;
1538 int rc;
1539
1540 if (!printed_version++)
1541 dev_printk(KERN_DEBUG, &pdev->dev,
1542 "version " DRV_VERSION "\n");
1543
1544 /* no hotplugging support for later devices (FIXME) */
1545 if (!in_module_init && ent->driver_data >= ich5_sata)
1546 return -ENODEV;
1547
1548 if (piix_broken_system_poweroff(pdev)) {
1549 piix_port_info[ent->driver_data].flags |=
1550 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1551 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1552 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1553 "on poweroff and hibernation\n");
1554 }
1555
1556 port_info[0] = piix_port_info[ent->driver_data];
1557 port_info[1] = piix_port_info[ent->driver_data];
1558
1559 port_flags = port_info[0].flags;
1560
1561 /* enable device and prepare host */
1562 rc = pcim_enable_device(pdev);
1563 if (rc)
1564 return rc;
1565
1566 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1567 if (!hpriv)
1568 return -ENOMEM;
1569
1570 /* Save IOCFG, this will be used for cable detection, quirk
1571 * detection and restoration on detach. This is necessary
1572 * because some ACPI implementations mess up cable related
1573 * bits on _STM. Reported on kernel bz#11879.
1574 */
1575 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1576
1577 /* ICH6R may be driven by either ata_piix or ahci driver
1578 * regardless of BIOS configuration. Make sure AHCI mode is
1579 * off.
1580 */
1581 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1582 rc = piix_disable_ahci(pdev);
1583 if (rc)
1584 return rc;
1585 }
1586
1587 /* SATA map init can change port_info, do it before prepping host */
1588 if (port_flags & ATA_FLAG_SATA)
1589 hpriv->map = piix_init_sata_map(pdev, port_info,
1590 piix_map_db_table[ent->driver_data]);
1591
1592 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1593 if (rc)
1594 return rc;
1595 host->private_data = hpriv;
1596
1597 /* initialize controller */
1598 if (port_flags & ATA_FLAG_SATA) {
1599 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1600 rc = piix_init_sidpr(host);
1601 if (rc)
1602 return rc;
1603 }
1604
1605 /* apply IOCFG bit18 quirk */
1606 piix_iocfg_bit18_quirk(host);
1607
1608 /* On ICH5, some BIOSen disable the interrupt using the
1609 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1610 * On ICH6, this bit has the same effect, but only when
1611 * MSI is disabled (and it is disabled, as we don't use
1612 * message-signalled interrupts currently).
1613 */
1614 if (port_flags & PIIX_FLAG_CHECKINTR)
1615 pci_intx(pdev, 1);
1616
1617 if (piix_check_450nx_errata(pdev)) {
1618 /* This writes into the master table but it does not
1619 really matter for this errata as we will apply it to
1620 all the PIIX devices on the board */
1621 host->ports[0]->mwdma_mask = 0;
1622 host->ports[0]->udma_mask = 0;
1623 host->ports[1]->mwdma_mask = 0;
1624 host->ports[1]->udma_mask = 0;
1625 }
1626 host->flags |= ATA_HOST_PARALLEL_SCAN;
1627
1628 pci_set_master(pdev);
1629 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1630 }
1631
1632 static void piix_remove_one(struct pci_dev *pdev)
1633 {
1634 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1635 struct piix_host_priv *hpriv = host->private_data;
1636
1637 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1638
1639 ata_pci_remove_one(pdev);
1640 }
1641
1642 static int __init piix_init(void)
1643 {
1644 int rc;
1645
1646 DPRINTK("pci_register_driver\n");
1647 rc = pci_register_driver(&piix_pci_driver);
1648 if (rc)
1649 return rc;
1650
1651 in_module_init = 0;
1652
1653 DPRINTK("done\n");
1654 return 0;
1655 }
1656
1657 static void __exit piix_exit(void)
1658 {
1659 pci_unregister_driver(&piix_pci_driver);
1660 }
1661
1662 module_init(piix_init);
1663 module_exit(piix_exit);
kernel source for telekom puls (alcatel/mediatek)