projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:


8385387c49cd4b8fcc7c5aa7093721d4e172cb9a
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac6"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
111 */
112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* controller IDs */
119 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
120 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
121 ich_pata_66 = 2, /* ICH up to 66 Mhz */
122 ich_pata_100 = 3, /* ICH up to UDMA 100 */
123 ich_pata_133 = 4, /* ICH up to UDMA 133 */
124 ich5_sata = 5,
125 esb_sata = 6,
126 ich6_sata = 7,
127 ich6_sata_ahci = 8,
128 ich6m_sata_ahci = 9,
129 ich8_sata_ahci = 10,
130
131 /* constants for mapping table */
132 P0 = 0, /* port 0 */
133 P1 = 1, /* port 1 */
134 P2 = 2, /* port 2 */
135 P3 = 3, /* port 3 */
136 IDE = -1, /* IDE */
137 NA = -2, /* not avaliable */
138 RV = -3, /* reserved */
139
140 PIIX_AHCI_DEVICE = 6,
141 };
142
143 struct piix_map_db {
144 const u32 mask;
145 const u16 port_enable;
146 const int present_shift;
147 const int map[][4];
148 };
149
150 struct piix_host_priv {
151 const int *map;
152 const struct piix_map_db *map_db;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_host_stop(struct ata_host *host);
158 static void piix_pata_error_handler(struct ata_port *ap);
159 static void ich_pata_error_handler(struct ata_port *ap);
160 static void piix_sata_error_handler(struct ata_port *ap);
161 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
162 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
163 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
164
165 static unsigned int in_module_init = 1;
166
167 static const struct pci_device_id piix_pci_tbl[] = {
168 #ifdef ATA_ENABLE_PATA
169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7110, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
172 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
173 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
174 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
175 /* Intel PIIX4 */
176 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel PIIX4 */
178 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX */
180 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel ICH (i810, i815, i840) UDMA 66*/
182 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
183 /* Intel ICH0 : UDMA 33*/
184 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
185 /* Intel ICH2M */
186 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
188 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH3M */
190 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH3 (E7500/1) UDMA 100 */
192 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
194 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH5 */
197 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
198 /* C-ICH (i810E2) */
199 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
201 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* ICH6 (and 6) (i915) UDMA 100 */
203 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* ICH7/7-R (i945, i975) UDMA 100*/
205 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
206 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 #endif
208
209 /* NOTE: The following PCI ids must be kept in sync with the
210 * list in drivers/pci/quirks.c.
211 */
212
213 /* 82801EB (ICH5) */
214 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
215 /* 82801EB (ICH5) */
216 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
217 /* 6300ESB (ICH5 variant with broken PCS present bits) */
218 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
219 /* 6300ESB pretending RAID */
220 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
221 /* 82801FB/FW (ICH6/ICH6W) */
222 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
223 /* 82801FR/FRW (ICH6R/ICH6RW) */
224 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
225 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
226 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
227 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
228 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
229 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
230 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
231 /* Enterprise Southbridge 2 (where's the datasheet?) */
232 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
233 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
234 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
235 /* SATA Controller 2 IDE (ICH8, ditto) */
236 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
237 /* Mobile SATA Controller IDE (ICH8M, ditto) */
238 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
239
240 { } /* terminate list */
241 };
242
243 static struct pci_driver piix_pci_driver = {
244 .name = DRV_NAME,
245 .id_table = piix_pci_tbl,
246 .probe = piix_init_one,
247 .remove = ata_pci_remove_one,
248 .suspend = ata_pci_device_suspend,
249 .resume = ata_pci_device_resume,
250 };
251
252 static struct scsi_host_template piix_sht = {
253 .module = THIS_MODULE,
254 .name = DRV_NAME,
255 .ioctl = ata_scsi_ioctl,
256 .queuecommand = ata_scsi_queuecmd,
257 .can_queue = ATA_DEF_QUEUE,
258 .this_id = ATA_SHT_THIS_ID,
259 .sg_tablesize = LIBATA_MAX_PRD,
260 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
261 .emulated = ATA_SHT_EMULATED,
262 .use_clustering = ATA_SHT_USE_CLUSTERING,
263 .proc_name = DRV_NAME,
264 .dma_boundary = ATA_DMA_BOUNDARY,
265 .slave_configure = ata_scsi_slave_config,
266 .slave_destroy = ata_scsi_slave_destroy,
267 .bios_param = ata_std_bios_param,
268 .resume = ata_scsi_device_resume,
269 .suspend = ata_scsi_device_suspend,
270 };
271
272 static const struct ata_port_operations piix_pata_ops = {
273 .port_disable = ata_port_disable,
274 .set_piomode = piix_set_piomode,
275 .set_dmamode = piix_set_dmamode,
276 .mode_filter = ata_pci_default_filter,
277
278 .tf_load = ata_tf_load,
279 .tf_read = ata_tf_read,
280 .check_status = ata_check_status,
281 .exec_command = ata_exec_command,
282 .dev_select = ata_std_dev_select,
283
284 .bmdma_setup = ata_bmdma_setup,
285 .bmdma_start = ata_bmdma_start,
286 .bmdma_stop = ata_bmdma_stop,
287 .bmdma_status = ata_bmdma_status,
288 .qc_prep = ata_qc_prep,
289 .qc_issue = ata_qc_issue_prot,
290 .data_xfer = ata_pio_data_xfer,
291
292 .freeze = ata_bmdma_freeze,
293 .thaw = ata_bmdma_thaw,
294 .error_handler = piix_pata_error_handler,
295 .post_internal_cmd = ata_bmdma_post_internal_cmd,
296
297 .irq_handler = ata_interrupt,
298 .irq_clear = ata_bmdma_irq_clear,
299
300 .port_start = ata_port_start,
301 .port_stop = ata_port_stop,
302 .host_stop = piix_host_stop,
303 };
304
305 static const struct ata_port_operations ich_pata_ops = {
306 .port_disable = ata_port_disable,
307 .set_piomode = piix_set_piomode,
308 .set_dmamode = ich_set_dmamode,
309 .mode_filter = ata_pci_default_filter,
310
311 .tf_load = ata_tf_load,
312 .tf_read = ata_tf_read,
313 .check_status = ata_check_status,
314 .exec_command = ata_exec_command,
315 .dev_select = ata_std_dev_select,
316
317 .bmdma_setup = ata_bmdma_setup,
318 .bmdma_start = ata_bmdma_start,
319 .bmdma_stop = ata_bmdma_stop,
320 .bmdma_status = ata_bmdma_status,
321 .qc_prep = ata_qc_prep,
322 .qc_issue = ata_qc_issue_prot,
323 .data_xfer = ata_pio_data_xfer,
324
325 .freeze = ata_bmdma_freeze,
326 .thaw = ata_bmdma_thaw,
327 .error_handler = ich_pata_error_handler,
328 .post_internal_cmd = ata_bmdma_post_internal_cmd,
329
330 .irq_handler = ata_interrupt,
331 .irq_clear = ata_bmdma_irq_clear,
332
333 .port_start = ata_port_start,
334 .port_stop = ata_port_stop,
335 .host_stop = ata_host_stop,
336 };
337
338 static const struct ata_port_operations piix_sata_ops = {
339 .port_disable = ata_port_disable,
340
341 .tf_load = ata_tf_load,
342 .tf_read = ata_tf_read,
343 .check_status = ata_check_status,
344 .exec_command = ata_exec_command,
345 .dev_select = ata_std_dev_select,
346
347 .bmdma_setup = ata_bmdma_setup,
348 .bmdma_start = ata_bmdma_start,
349 .bmdma_stop = ata_bmdma_stop,
350 .bmdma_status = ata_bmdma_status,
351 .qc_prep = ata_qc_prep,
352 .qc_issue = ata_qc_issue_prot,
353 .data_xfer = ata_pio_data_xfer,
354
355 .freeze = ata_bmdma_freeze,
356 .thaw = ata_bmdma_thaw,
357 .error_handler = piix_sata_error_handler,
358 .post_internal_cmd = ata_bmdma_post_internal_cmd,
359
360 .irq_handler = ata_interrupt,
361 .irq_clear = ata_bmdma_irq_clear,
362
363 .port_start = ata_port_start,
364 .port_stop = ata_port_stop,
365 .host_stop = piix_host_stop,
366 };
367
368 static const struct piix_map_db ich5_map_db = {
369 .mask = 0x7,
370 .port_enable = 0x3,
371 .present_shift = 4,
372 .map = {
373 /* PM PS SM SS MAP */
374 { P0, NA, P1, NA }, /* 000b */
375 { P1, NA, P0, NA }, /* 001b */
376 { RV, RV, RV, RV },
377 { RV, RV, RV, RV },
378 { P0, P1, IDE, IDE }, /* 100b */
379 { P1, P0, IDE, IDE }, /* 101b */
380 { IDE, IDE, P0, P1 }, /* 110b */
381 { IDE, IDE, P1, P0 }, /* 111b */
382 },
383 };
384
385 static const struct piix_map_db ich6_map_db = {
386 .mask = 0x3,
387 .port_enable = 0xf,
388 .present_shift = 4,
389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, P2, P1, P3 }, /* 00b */
392 { IDE, IDE, P1, P3 }, /* 01b */
393 { P0, P2, IDE, IDE }, /* 10b */
394 { RV, RV, RV, RV },
395 },
396 };
397
398 static const struct piix_map_db ich6m_map_db = {
399 .mask = 0x3,
400 .port_enable = 0x5,
401 .present_shift = 4,
402
403 /* Map 01b isn't specified in the doc but some notebooks use
404 * it anyway. MAP 01b have been spotted on both ICH6M and
405 * ICH7M.
406 */
407 .map = {
408 /* PM PS SM SS MAP */
409 { P0, P2, RV, RV }, /* 00b */
410 { IDE, IDE, P1, P3 }, /* 01b */
411 { P0, P2, IDE, IDE }, /* 10b */
412 { RV, RV, RV, RV },
413 },
414 };
415
416 static const struct piix_map_db ich8_map_db = {
417 .mask = 0x3,
418 .port_enable = 0x3,
419 .present_shift = 8,
420 .map = {
421 /* PM PS SM SS MAP */
422 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
423 { RV, RV, RV, RV },
424 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
425 { RV, RV, RV, RV },
426 },
427 };
428
429 static const struct piix_map_db *piix_map_db_table[] = {
430 [ich5_sata] = &ich5_map_db,
431 [esb_sata] = &ich5_map_db,
432 [ich6_sata] = &ich6_map_db,
433 [ich6_sata_ahci] = &ich6_map_db,
434 [ich6m_sata_ahci] = &ich6m_map_db,
435 [ich8_sata_ahci] = &ich8_map_db,
436 };
437
438 static struct ata_port_info piix_port_info[] = {
439 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
440 {
441 .sht = &piix_sht,
442 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
445 .udma_mask = ATA_UDMA_MASK_40C,
446 .port_ops = &piix_pata_ops,
447 },
448
449 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
450 {
451 .sht = &piix_sht,
452 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
453 .pio_mask = 0x1f, /* pio 0-4 */
454 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
455 .udma_mask = ATA_UDMA2, /* UDMA33 */
456 .port_ops = &ich_pata_ops,
457 },
458 /* ich_pata_66: 2 ICH controllers up to 66MHz */
459 {
460 .sht = &piix_sht,
461 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
462 .pio_mask = 0x1f, /* pio 0-4 */
463 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
464 .udma_mask = ATA_UDMA4,
465 .port_ops = &ich_pata_ops,
466 },
467
468 /* ich_pata_100: 3 */
469 {
470 .sht = &piix_sht,
471 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
472 .pio_mask = 0x1f, /* pio0-4 */
473 .mwdma_mask = 0x06, /* mwdma1-2 */
474 .udma_mask = ATA_UDMA5, /* udma0-5 */
475 .port_ops = &ich_pata_ops,
476 },
477
478 /* ich_pata_133: 4 ICH with full UDMA6 */
479 {
480 .sht = &piix_sht,
481 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
482 .pio_mask = 0x1f, /* pio 0-4 */
483 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
484 .udma_mask = ATA_UDMA6, /* UDMA133 */
485 .port_ops = &ich_pata_ops,
486 },
487
488 /* ich5_sata: 5 */
489 {
490 .sht = &piix_sht,
491 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
492 PIIX_FLAG_IGNORE_PCS,
493 .pio_mask = 0x1f, /* pio0-4 */
494 .mwdma_mask = 0x07, /* mwdma0-2 */
495 .udma_mask = 0x7f, /* udma0-6 */
496 .port_ops = &piix_sata_ops,
497 },
498
499 /* i6300esb_sata: 6 */
500 {
501 .sht = &piix_sht,
502 .flags = ATA_FLAG_SATA |
503 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x07, /* mwdma0-2 */
506 .udma_mask = 0x7f, /* udma0-6 */
507 .port_ops = &piix_sata_ops,
508 },
509
510 /* ich6_sata: 7 */
511 {
512 .sht = &piix_sht,
513 .flags = ATA_FLAG_SATA |
514 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
515 .pio_mask = 0x1f, /* pio0-4 */
516 .mwdma_mask = 0x07, /* mwdma0-2 */
517 .udma_mask = 0x7f, /* udma0-6 */
518 .port_ops = &piix_sata_ops,
519 },
520
521 /* ich6_sata_ahci: 8 */
522 {
523 .sht = &piix_sht,
524 .flags = ATA_FLAG_SATA |
525 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
526 PIIX_FLAG_AHCI,
527 .pio_mask = 0x1f, /* pio0-4 */
528 .mwdma_mask = 0x07, /* mwdma0-2 */
529 .udma_mask = 0x7f, /* udma0-6 */
530 .port_ops = &piix_sata_ops,
531 },
532
533 /* ich6m_sata_ahci: 9 */
534 {
535 .sht = &piix_sht,
536 .flags = ATA_FLAG_SATA |
537 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
538 PIIX_FLAG_AHCI,
539 .pio_mask = 0x1f, /* pio0-4 */
540 .mwdma_mask = 0x07, /* mwdma0-2 */
541 .udma_mask = 0x7f, /* udma0-6 */
542 .port_ops = &piix_sata_ops,
543 },
544
545 /* ich8_sata_ahci: 10 */
546 {
547 .sht = &piix_sht,
548 .flags = ATA_FLAG_SATA |
549 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
550 PIIX_FLAG_AHCI,
551 .pio_mask = 0x1f, /* pio0-4 */
552 .mwdma_mask = 0x07, /* mwdma0-2 */
553 .udma_mask = 0x7f, /* udma0-6 */
554 .port_ops = &piix_sata_ops,
555 },
556
557 };
558
559 static struct pci_bits piix_enable_bits[] = {
560 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
561 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
562 };
563
564 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
565 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
566 MODULE_LICENSE("GPL");
567 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
568 MODULE_VERSION(DRV_VERSION);
569
570 static int force_pcs = 0;
571 module_param(force_pcs, int, 0444);
572 MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
573 "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)");
574
575 /**
576 * piix_pata_cbl_detect - Probe host controller cable detect info
577 * @ap: Port for which cable detect info is desired
578 *
579 * Read 80c cable indicator from ATA PCI device's PCI config
580 * register. This register is normally set by firmware (BIOS).
581 *
582 * LOCKING:
583 * None (inherited from caller).
584 */
585
586 static void ich_pata_cbl_detect(struct ata_port *ap)
587 {
588 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
589 u8 tmp, mask;
590
591 /* no 80c support in host controller? */
592 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
593 goto cbl40;
594
595 /* check BIOS cable detect results */
596 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
597 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
598 if ((tmp & mask) == 0)
599 goto cbl40;
600
601 ap->cbl = ATA_CBL_PATA80;
602 return;
603
604 cbl40:
605 ap->cbl = ATA_CBL_PATA40;
606 }
607
608 /**
609 * piix_pata_prereset - prereset for PATA host controller
610 * @ap: Target port
611 *
612 *
613 * LOCKING:
614 * None (inherited from caller).
615 */
616 static int piix_pata_prereset(struct ata_port *ap)
617 {
618 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
619
620 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
621 return -ENOENT;
622
623 ap->cbl = ATA_CBL_PATA40;
624 return ata_std_prereset(ap);
625 }
626
627 static void piix_pata_error_handler(struct ata_port *ap)
628 {
629 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
630 ata_std_postreset);
631 }
632
633
634 /**
635 * ich_pata_prereset - prereset for PATA host controller
636 * @ap: Target port
637 *
638 *
639 * LOCKING:
640 * None (inherited from caller).
641 */
642 static int ich_pata_prereset(struct ata_port *ap)
643 {
644 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
645
646 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
647 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
648 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
649 return 0;
650 }
651
652 ich_pata_cbl_detect(ap);
653
654 return ata_std_prereset(ap);
655 }
656
657 static void ich_pata_error_handler(struct ata_port *ap)
658 {
659 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
660 ata_std_postreset);
661 }
662
663 /**
664 * piix_sata_present_mask - determine present mask for SATA host controller
665 * @ap: Target port
666 *
667 * Reads SATA PCI device's PCI config register Port Configuration
668 * and Status (PCS) to determine port and device availability.
669 *
670 * LOCKING:
671 * None (inherited from caller).
672 *
673 * RETURNS:
674 * determined present_mask
675 */
676 static unsigned int piix_sata_present_mask(struct ata_port *ap)
677 {
678 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
679 struct piix_host_priv *hpriv = ap->host->private_data;
680 const unsigned int *map = hpriv->map;
681 int base = 2 * ap->port_no;
682 unsigned int present_mask = 0;
683 int port, i;
684 u16 pcs;
685
686 pci_read_config_word(pdev, ICH5_PCS, &pcs);
687 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
688
689 for (i = 0; i < 2; i++) {
690 port = map[base + i];
691 if (port < 0)
692 continue;
693 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
694 (pcs & 1 << (hpriv->map_db->present_shift + port)))
695 present_mask |= 1 << i;
696 }
697
698 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
699 ap->id, pcs, present_mask);
700
701 return present_mask;
702 }
703
704 /**
705 * piix_sata_softreset - reset SATA host port via ATA SRST
706 * @ap: port to reset
707 * @classes: resulting classes of attached devices
708 *
709 * Reset SATA host port via ATA SRST. On controllers with
710 * reliable PCS present bits, the bits are used to determine
711 * device presence.
712 *
713 * LOCKING:
714 * Kernel thread context (may sleep)
715 *
716 * RETURNS:
717 * 0 on success, -errno otherwise.
718 */
719 static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
720 {
721 unsigned int present_mask;
722 int i, rc;
723
724 present_mask = piix_sata_present_mask(ap);
725
726 rc = ata_std_softreset(ap, classes);
727 if (rc)
728 return rc;
729
730 for (i = 0; i < ATA_MAX_DEVICES; i++) {
731 if (!(present_mask & (1 << i)))
732 classes[i] = ATA_DEV_NONE;
733 }
734
735 return 0;
736 }
737
738 static void piix_sata_error_handler(struct ata_port *ap)
739 {
740 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
741 ata_std_postreset);
742 }
743
744 /**
745 * piix_set_piomode - Initialize host controller PATA PIO timings
746 * @ap: Port whose timings we are configuring
747 * @adev: um
748 *
749 * Set PIO mode for device, in host controller PCI config space.
750 *
751 * LOCKING:
752 * None (inherited from caller).
753 */
754
755 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
756 {
757 unsigned int pio = adev->pio_mode - XFER_PIO_0;
758 struct pci_dev *dev = to_pci_dev(ap->host->dev);
759 unsigned int is_slave = (adev->devno != 0);
760 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
761 unsigned int slave_port = 0x44;
762 u16 master_data;
763 u8 slave_data;
764 u8 udma_enable;
765 int control = 0;
766
767 /*
768 * See Intel Document 298600-004 for the timing programing rules
769 * for ICH controllers.
770 */
771
772 static const /* ISP RTC */
773 u8 timings[][2] = { { 0, 0 },
774 { 0, 0 },
775 { 1, 0 },
776 { 2, 1 },
777 { 2, 3 }, };
778
779 if (pio >= 2)
780 control |= 1; /* TIME1 enable */
781 if (ata_pio_need_iordy(adev))
782 control |= 2; /* IE enable */
783
784 /* Intel specifies that the PPE functionality is for disk only */
785 if (adev->class == ATA_DEV_ATA)
786 control |= 4; /* PPE enable */
787
788 pci_read_config_word(dev, master_port, &master_data);
789 if (is_slave) {
790 /* Enable SITRE (seperate slave timing register) */
791 master_data |= 0x4000;
792 /* enable PPE1, IE1 and TIME1 as needed */
793 master_data |= (control << 4);
794 pci_read_config_byte(dev, slave_port, &slave_data);
795 slave_data &= (ap->port_no ? 0x0f : 0xf0);
796 /* Load the timing nibble for this slave */
797 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
798 } else {
799 /* Master keeps the bits in a different format */
800 master_data &= 0xccf8;
801 /* Enable PPE, IE and TIME as appropriate */
802 master_data |= control;
803 master_data |=
804 (timings[pio][0] << 12) |
805 (timings[pio][1] << 8);
806 }
807 pci_write_config_word(dev, master_port, master_data);
808 if (is_slave)
809 pci_write_config_byte(dev, slave_port, slave_data);
810
811 /* Ensure the UDMA bit is off - it will be turned back on if
812 UDMA is selected */
813
814 if (ap->udma_mask) {
815 pci_read_config_byte(dev, 0x48, &udma_enable);
816 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
817 pci_write_config_byte(dev, 0x48, udma_enable);
818 }
819 }
820
821 /**
822 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
823 * @ap: Port whose timings we are configuring
824 * @adev: Drive in question
825 * @udma: udma mode, 0 - 6
826 * @isich: set if the chip is an ICH device
827 *
828 * Set UDMA mode for device, in host controller PCI config space.
829 *
830 * LOCKING:
831 * None (inherited from caller).
832 */
833
834 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
835 {
836 struct pci_dev *dev = to_pci_dev(ap->host->dev);
837 u8 master_port = ap->port_no ? 0x42 : 0x40;
838 u16 master_data;
839 u8 speed = adev->dma_mode;
840 int devid = adev->devno + 2 * ap->port_no;
841 u8 udma_enable;
842
843 static const /* ISP RTC */
844 u8 timings[][2] = { { 0, 0 },
845 { 0, 0 },
846 { 1, 0 },
847 { 2, 1 },
848 { 2, 3 }, };
849
850 pci_read_config_word(dev, master_port, &master_data);
851 pci_read_config_byte(dev, 0x48, &udma_enable);
852
853 if (speed >= XFER_UDMA_0) {
854 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
855 u16 udma_timing;
856 u16 ideconf;
857 int u_clock, u_speed;
858
859 /*
860 * UDMA is handled by a combination of clock switching and
861 * selection of dividers
862 *
863 * Handy rule: Odd modes are UDMATIMx 01, even are 02
864 * except UDMA0 which is 00
865 */
866 u_speed = min(2 - (udma & 1), udma);
867 if (udma == 5)
868 u_clock = 0x1000; /* 100Mhz */
869 else if (udma > 2)
870 u_clock = 1; /* 66Mhz */
871 else
872 u_clock = 0; /* 33Mhz */
873
874 udma_enable |= (1 << devid);
875
876 /* Load the CT/RP selection */
877 pci_read_config_word(dev, 0x4A, &udma_timing);
878 udma_timing &= ~(3 << (4 * devid));
879 udma_timing |= u_speed << (4 * devid);
880 pci_write_config_word(dev, 0x4A, udma_timing);
881
882 if (isich) {
883 /* Select a 33/66/100Mhz clock */
884 pci_read_config_word(dev, 0x54, &ideconf);
885 ideconf &= ~(0x1001 << devid);
886 ideconf |= u_clock << devid;
887 /* For ICH or later we should set bit 10 for better
888 performance (WR_PingPong_En) */
889 pci_write_config_word(dev, 0x54, ideconf);
890 }
891 } else {
892 /*
893 * MWDMA is driven by the PIO timings. We must also enable
894 * IORDY unconditionally along with TIME1. PPE has already
895 * been set when the PIO timing was set.
896 */
897 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
898 unsigned int control;
899 u8 slave_data;
900 const unsigned int needed_pio[3] = {
901 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
902 };
903 int pio = needed_pio[mwdma] - XFER_PIO_0;
904
905 control = 3; /* IORDY|TIME1 */
906
907 /* If the drive MWDMA is faster than it can do PIO then
908 we must force PIO into PIO0 */
909
910 if (adev->pio_mode < needed_pio[mwdma])
911 /* Enable DMA timing only */
912 control |= 8; /* PIO cycles in PIO0 */
913
914 if (adev->devno) { /* Slave */
915 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
916 master_data |= control << 4;
917 pci_read_config_byte(dev, 0x44, &slave_data);
918 slave_data &= (0x0F + 0xE1 * ap->port_no);
919 /* Load the matching timing */
920 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
921 pci_write_config_byte(dev, 0x44, slave_data);
922 } else { /* Master */
923 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
924 and master timing bits */
925 master_data |= control;
926 master_data |=
927 (timings[pio][0] << 12) |
928 (timings[pio][1] << 8);
929 }
930 udma_enable &= ~(1 << devid);
931 pci_write_config_word(dev, master_port, master_data);
932 }
933 /* Don't scribble on 0x48 if the controller does not support UDMA */
934 if (ap->udma_mask)
935 pci_write_config_byte(dev, 0x48, udma_enable);
936 }
937
938 /**
939 * piix_set_dmamode - Initialize host controller PATA DMA timings
940 * @ap: Port whose timings we are configuring
941 * @adev: um
942 *
943 * Set MW/UDMA mode for device, in host controller PCI config space.
944 *
945 * LOCKING:
946 * None (inherited from caller).
947 */
948
949 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
950 {
951 do_pata_set_dmamode(ap, adev, 0);
952 }
953
954 /**
955 * ich_set_dmamode - Initialize host controller PATA DMA timings
956 * @ap: Port whose timings we are configuring
957 * @adev: um
958 *
959 * Set MW/UDMA mode for device, in host controller PCI config space.
960 *
961 * LOCKING:
962 * None (inherited from caller).
963 */
964
965 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
966 {
967 do_pata_set_dmamode(ap, adev, 1);
968 }
969
970 #define AHCI_PCI_BAR 5
971 #define AHCI_GLOBAL_CTL 0x04
972 #define AHCI_ENABLE (1 << 31)
973 static int piix_disable_ahci(struct pci_dev *pdev)
974 {
975 void __iomem *mmio;
976 u32 tmp;
977 int rc = 0;
978
979 /* BUG: pci_enable_device has not yet been called. This
980 * works because this device is usually set up by BIOS.
981 */
982
983 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
984 !pci_resource_len(pdev, AHCI_PCI_BAR))
985 return 0;
986
987 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
988 if (!mmio)
989 return -ENOMEM;
990
991 tmp = readl(mmio + AHCI_GLOBAL_CTL);
992 if (tmp & AHCI_ENABLE) {
993 tmp &= ~AHCI_ENABLE;
994 writel(tmp, mmio + AHCI_GLOBAL_CTL);
995
996 tmp = readl(mmio + AHCI_GLOBAL_CTL);
997 if (tmp & AHCI_ENABLE)
998 rc = -EIO;
999 }
1000
1001 pci_iounmap(pdev, mmio);
1002 return rc;
1003 }
1004
1005 /**
1006 * piix_check_450nx_errata - Check for problem 450NX setup
1007 * @ata_dev: the PCI device to check
1008 *
1009 * Check for the present of 450NX errata #19 and errata #25. If
1010 * they are found return an error code so we can turn off DMA
1011 */
1012
1013 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1014 {
1015 struct pci_dev *pdev = NULL;
1016 u16 cfg;
1017 u8 rev;
1018 int no_piix_dma = 0;
1019
1020 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1021 {
1022 /* Look for 450NX PXB. Check for problem configurations
1023 A PCI quirk checks bit 6 already */
1024 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
1025 pci_read_config_word(pdev, 0x41, &cfg);
1026 /* Only on the original revision: IDE DMA can hang */
1027 if (rev == 0x00)
1028 no_piix_dma = 1;
1029 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1030 else if (cfg & (1<<14) && rev < 5)
1031 no_piix_dma = 2;
1032 }
1033 if (no_piix_dma)
1034 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1035 if (no_piix_dma == 2)
1036 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1037 return no_piix_dma;
1038 }
1039
1040 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1041 struct ata_port_info *pinfo,
1042 const struct piix_map_db *map_db)
1043 {
1044 u16 pcs, new_pcs;
1045
1046 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1047
1048 new_pcs = pcs | map_db->port_enable;
1049
1050 if (new_pcs != pcs) {
1051 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1052 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1053 msleep(150);
1054 }
1055
1056 if (force_pcs == 1) {
1057 dev_printk(KERN_INFO, &pdev->dev,
1058 "force ignoring PCS (0x%x)\n", new_pcs);
1059 pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS;
1060 pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS;
1061 } else if (force_pcs == 2) {
1062 dev_printk(KERN_INFO, &pdev->dev,
1063 "force honoring PCS (0x%x)\n", new_pcs);
1064 pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS;
1065 pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS;
1066 }
1067 }
1068
1069 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1070 struct ata_port_info *pinfo,
1071 const struct piix_map_db *map_db)
1072 {
1073 struct piix_host_priv *hpriv = pinfo[0].private_data;
1074 const unsigned int *map;
1075 int i, invalid_map = 0;
1076 u8 map_value;
1077
1078 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1079
1080 map = map_db->map[map_value & map_db->mask];
1081
1082 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1083 for (i = 0; i < 4; i++) {
1084 switch (map[i]) {
1085 case RV:
1086 invalid_map = 1;
1087 printk(" XX");
1088 break;
1089
1090 case NA:
1091 printk(" --");
1092 break;
1093
1094 case IDE:
1095 WARN_ON((i & 1) || map[i + 1] != IDE);
1096 pinfo[i / 2] = piix_port_info[ich_pata_100];
1097 pinfo[i / 2].private_data = hpriv;
1098 i++;
1099 printk(" IDE IDE");
1100 break;
1101
1102 default:
1103 printk(" P%d", map[i]);
1104 if (i & 1)
1105 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1106 break;
1107 }
1108 }
1109 printk(" ]\n");
1110
1111 if (invalid_map)
1112 dev_printk(KERN_ERR, &pdev->dev,
1113 "invalid MAP value %u\n", map_value);
1114
1115 hpriv->map = map;
1116 hpriv->map_db = map_db;
1117 }
1118
1119 /**
1120 * piix_init_one - Register PIIX ATA PCI device with kernel services
1121 * @pdev: PCI device to register
1122 * @ent: Entry in piix_pci_tbl matching with @pdev
1123 *
1124 * Called from kernel PCI layer. We probe for combined mode (sigh),
1125 * and then hand over control to libata, for it to do the rest.
1126 *
1127 * LOCKING:
1128 * Inherited from PCI layer (may sleep).
1129 *
1130 * RETURNS:
1131 * Zero on success, or -ERRNO value.
1132 */
1133
1134 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1135 {
1136 static int printed_version;
1137 struct ata_port_info port_info[2];
1138 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1139 struct piix_host_priv *hpriv;
1140 unsigned long port_flags;
1141
1142 if (!printed_version++)
1143 dev_printk(KERN_DEBUG, &pdev->dev,
1144 "version " DRV_VERSION "\n");
1145
1146 /* no hotplugging support (FIXME) */
1147 if (!in_module_init)
1148 return -ENODEV;
1149
1150 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1151 if (!hpriv)
1152 return -ENOMEM;
1153
1154 port_info[0] = piix_port_info[ent->driver_data];
1155 port_info[1] = piix_port_info[ent->driver_data];
1156 port_info[0].private_data = hpriv;
1157 port_info[1].private_data = hpriv;
1158
1159 port_flags = port_info[0].flags;
1160
1161 if (port_flags & PIIX_FLAG_AHCI) {
1162 u8 tmp;
1163 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1164 if (tmp == PIIX_AHCI_DEVICE) {
1165 int rc = piix_disable_ahci(pdev);
1166 if (rc)
1167 return rc;
1168 }
1169 }
1170
1171 /* Initialize SATA map */
1172 if (port_flags & ATA_FLAG_SATA) {
1173 piix_init_sata_map(pdev, port_info,
1174 piix_map_db_table[ent->driver_data]);
1175 piix_init_pcs(pdev, port_info,
1176 piix_map_db_table[ent->driver_data]);
1177 }
1178
1179 /* On ICH5, some BIOSen disable the interrupt using the
1180 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1181 * On ICH6, this bit has the same effect, but only when
1182 * MSI is disabled (and it is disabled, as we don't use
1183 * message-signalled interrupts currently).
1184 */
1185 if (port_flags & PIIX_FLAG_CHECKINTR)
1186 pci_intx(pdev, 1);
1187
1188 if (piix_check_450nx_errata(pdev)) {
1189 /* This writes into the master table but it does not
1190 really matter for this errata as we will apply it to
1191 all the PIIX devices on the board */
1192 port_info[0].mwdma_mask = 0;
1193 port_info[0].udma_mask = 0;
1194 port_info[1].mwdma_mask = 0;
1195 port_info[1].udma_mask = 0;
1196 }
1197 return ata_pci_init_one(pdev, ppinfo, 2);
1198 }
1199
1200 static void piix_host_stop(struct ata_host *host)
1201 {
1202 struct piix_host_priv *hpriv = host->private_data;
1203
1204 ata_host_stop(host);
1205
1206 kfree(hpriv);
1207 }
1208
1209 static int __init piix_init(void)
1210 {
1211 int rc;
1212
1213 DPRINTK("pci_register_driver\n");
1214 rc = pci_register_driver(&piix_pci_driver);
1215 if (rc)
1216 return rc;
1217
1218 in_module_init = 0;
1219
1220 DPRINTK("done\n");
1221 return 0;
1222 }
1223
1224 static void __exit piix_exit(void)
1225 {
1226 pci_unregister_driver(&piix_pci_driver);
1227 }
1228
1229 module_init(piix_init);
1230 module_exit(piix_exit);
kernel source for telekom puls (alcatel/mediatek)